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lastdragon
2026-09-06 12:53:21 -06:00
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linux-7.2.3/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek AUDSYS controller
maintainers:
- Eugen Hristev <eugen.hristev@collabora.com>
description:
The MediaTek AUDSYS controller provides various clocks to the system.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-audsys
- mediatek,mt6765-audsys
- mediatek,mt6779-audsys
- mediatek,mt7622-audsys
- mediatek,mt8167-audsys
- mediatek,mt8173-audsys
- mediatek,mt8183-audiosys
- mediatek,mt8183-audsys
- mediatek,mt8186-audsys
- mediatek,mt8192-audsys
- mediatek,mt8516-audsys
- const: syscon
- items:
# Special case for mt7623 for backward compatibility
- const: mediatek,mt7623-audsys
- const: mediatek,mt2701-audsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
audio-controller:
type: object
required:
- compatible
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-audsys
- mediatek,mt7622-audsys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt8183-audiosys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt8192-audsys
then:
properties:
audio-controller:
$ref: /schemas/sound/mt8192-afe-pcm.yaml#
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/clock/mt2701-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
compatible = "mediatek,mt2701-audio";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&audsys CLK_AUD_I2SO1>,
<&audsys CLK_AUD_I2SO2>,
<&audsys CLK_AUD_I2SO3>,
<&audsys CLK_AUD_I2SO4>,
<&audsys CLK_AUD_I2SIN1>,
<&audsys CLK_AUD_I2SIN2>,
<&audsys CLK_AUD_I2SIN3>,
<&audsys CLK_AUD_I2SIN4>,
<&audsys CLK_AUD_ASRCO1>,
<&audsys CLK_AUD_ASRCO2>,
<&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>;
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
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MediaTek g3dsys controller
============================
The MediaTek g3dsys controller provides various clocks and reset controller to
the GPU.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-g3dsys", "syscon":
for MT2701 SoC
- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
for MT7623 SoC
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The g3dsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
g3dsys: clock-controller@13000000 {
compatible = "mediatek,mt7623-g3dsys",
"mediatek,mt2701-g3dsys",
"syscon";
reg = <0 0x13000000 0 0x200>;
#clock-cells = <1>;
#reset-cells = <1>;
};
linux-7.2.3/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek mmsys controller
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
The MediaTek mmsys system controller provides clock control, routing control,
and miscellaneous control in mmsys partition.
properties:
$nodename:
pattern: "^syscon@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-mmsys
- mediatek,mt2712-mmsys
- mediatek,mt6765-mmsys
- mediatek,mt6779-mmsys
- mediatek,mt6795-mmsys
- mediatek,mt6797-mmsys
- mediatek,mt8167-mmsys
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
- mediatek,mt8188-vdosys1
- mediatek,mt8188-vppsys0
- mediatek,mt8188-vppsys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
- mediatek,mt8195-vppsys1
- mediatek,mt8365-mmsys
- const: syscon
- description: vdosys0 and vdosys1 are 2 display HW pipelines,
so mt8195 binding should be deprecated.
deprecated: true
items:
- const: mediatek,mt8195-mmsys
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
- const: mediatek,mt2701-mmsys
- const: syscon
- items:
- const: mediatek,mt8195-vdosys0
- const: mediatek,mt8195-mmsys
- const: syscon
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier as defined by bindings
of the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
mboxes:
description:
Using mailbox to communicate with GCE, it should have this
property and list of phandle, mailbox specifiers. See
Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
for details.
$ref: /schemas/types.yaml#/definitions/phandle-array
mediatek,gce-client-reg:
description:
The register of client driver can be configured by gce with 4 arguments
defined in this property, such as phandle of gce, subsys id,
register offset and size.
Each subsys id is mapping to a base address of display function blocks
register which is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h.
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
"#clock-cells":
const: 1
'#reset-cells':
const: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port connects the MMSYS/VDOSYS output to
the first component of one display pipeline, for example one of
the available OVL or RDMA blocks.
Some MediaTek SoCs support multiple display outputs per MMSYS.
properties:
endpoint@0:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Output to the primary display pipeline
endpoint@1:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Output to the secondary display pipeline
endpoint@2:
$ref: /schemas/graph.yaml#/properties/endpoint
description: Output to the tertiary display pipeline
anyOf:
- required:
- endpoint@0
- required:
- endpoint@1
- required:
- endpoint@2
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
#reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
linux-7.2.3/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE Mirror Controller for MT7622
maintainers:
- Lorenzo Bianconi <lorenzo@kernel.org>
- Felix Fietkau <nbd@nbd.name>
description:
The mediatek PCIE mirror provides a configuration interface for PCIE
controller on MT7622 soc.
properties:
compatible:
items:
- enum:
- mediatek,mt7622-pcie-mirror
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie_mirror: pcie-mirror@10000400 {
compatible = "mediatek,mt7622-pcie-mirror", "syscon";
reg = <0 0x10000400 0 0x10>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
maintainers:
- Lorenzo Bianconi <lorenzo@kernel.org>
- Felix Fietkau <nbd@nbd.name>
description:
The mediatek wireless ethernet dispatch controller can be configured to
intercept and handle access to the WLAN DMA queues and PCIe interrupts
and implement hardware flow offloading from ethernet to WLAN.
properties:
compatible:
items:
- enum:
- mediatek,mt7622-wed
- mediatek,mt7981-wed
- mediatek,mt7986-wed
- mediatek,mt7988-wed
- const: syscon
reg:
maxItems: 1
interrupts:
maxItems: 1
memory-region:
items:
- description: firmware EMI region
- description: firmware ILM region
- description: firmware DLM region
- description: firmware CPU DATA region
- description: firmware BOOT region
memory-region-names:
items:
- const: wo-emi
- const: wo-ilm
- const: wo-dlm
- const: wo-data
- const: wo-boot
mediatek,wo-ccif:
$ref: /schemas/types.yaml#/definitions/phandle
description: mediatek wed-wo controller interface.
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt7622-wed
then:
properties:
memory-region-names: false
memory-region: false
mediatek,wo-ccif: false
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
wed0: wed@1020a000 {
compatible = "mediatek,mt7622-wed","syscon";
reg = <0 0x1020a000 0 0x1000>;
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
wed@15010000 {
compatible = "mediatek,mt7986-wed", "syscon";
reg = <0 0x15010000 0 0x1000>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi>, <&wo_ilm>, <&wo_dlm>,
<&wo_data>, <&wo_boot>;
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
"wo-data", "wo-boot";
mediatek,wo-ccif = <&wo_ccif0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE WED Controller for MT7986
maintainers:
- Lorenzo Bianconi <lorenzo@kernel.org>
- Felix Fietkau <nbd@nbd.name>
description:
The mediatek WED PCIE provides a configuration interface for PCIE
controller on MT7986 soc.
properties:
compatible:
items:
- enum:
- mediatek,mt7986-wed-pcie
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
wed_pcie: wed-pcie@10003000 {
compatible = "mediatek,mt7986-wed-pcie",
"syscon";
reg = <0 0x10003000 0 0x10>;
};
};