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linux-7.2.3/Documentation/devicetree/bindings/ata/ahci-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ahci-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Serial ATA AHCI controllers
maintainers:
- Hans de Goede <hdegoede@redhat.com>
- Damien Le Moal <dlemoal@kernel.org>
description:
This document defines device tree properties for a common AHCI SATA
controller implementation. It's hardware interface is supposed to
conform to the technical standard defined by Intel (see Serial ATA
Advanced Host Controller Interface specification for details). The
document doesn't constitute a DT-node binding by itself but merely
defines a set of common properties for the AHCI-compatible devices.
select: false
allOf:
- $ref: sata-common.yaml#
properties:
reg:
description:
Generic AHCI registers space conforming to the Serial ATA AHCI
specification.
reg-names:
description: CSR space IDs
contains:
const: ahci
interrupts:
description:
Generic AHCI state change interrupt. Can be implemented either as a
single line attached to the controller or as a set of the signals
indicating the particular port events.
minItems: 1
maxItems: 32
ahci-supply:
description: Power regulator for AHCI controller
target-supply:
description: Power regulator for SATA target device
phy-supply:
description: Power regulator for SATA PHY
phys:
description: Reference to the SATA PHY node
maxItems: 1
phy-names:
const: sata-phy
hba-cap:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA generic platform capabilities like Staggered
Spin-up or Mechanical Presence Switch support. It can be used to
appropriately initialize the HWinit fields of the HBA CAP register
in case if the system firmware hasn't done it.
ports-implemented:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mask that indicates which ports the HBA supports. Useful if PI is not
programmed by the BIOS, which is true for some embedded SoC's.
patternProperties:
"^sata-port@[0-9a-f]+$":
$ref: '#/$defs/ahci-port'
description:
It is optionally possible to describe the ports as sub-nodes so
to enable each port independently when dealing with multiple PHYs.
required:
- reg
- interrupts
additionalProperties: true
$defs:
ahci-port:
$ref: /schemas/ata/sata-common.yaml#/$defs/sata-port
properties:
reg:
description:
AHCI SATA port identifier. By design AHCI controller can't have
more than 32 ports due to the CAP.NP fields and PI register size
constraints.
minimum: 0
maximum: 31
phys:
description: Individual AHCI SATA port PHY
maxItems: 1
phy-names:
description: AHCI SATA port PHY ID
const: sata-phy
target-supply:
description: Power regulator for SATA port target device
hba-port-cap:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA port-specific platform capabilities like Hot
plugging, eSATA, FIS-based Switching, etc (see AHCI specification
for details). It can be used to initialize the HWinit fields of
the PxCMD register in case if the system firmware hasn't done it.
required:
- reg
...
linux-7.2.3/Documentation/devicetree/bindings/ata/ahci-platform.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AHCI SATA Controller
description: |
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
It is possible, but not required, to represent each port as a sub-node.
It allows to enable each port independently when dealing with multiple
PHYs.
maintainers:
- Hans de Goede <hdegoede@redhat.com>
- Jens Axboe <axboe@kernel.dk>
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,iproc-ahci
- marvell,armada-8k-ahci
- marvell,berlin2-ahci
- marvell,berlin2q-ahci
- qcom,apq8064-ahci
- qcom,ipq806x-ahci
- socionext,uniphier-pro4-ahci
- socionext,uniphier-pxs2-ahci
- socionext,uniphier-pxs3-ahci
- const: generic-ahci
- enum:
- cavium,octeon-7130-ahci
- hisilicon,hisi-ahci
- ibm,476gtr-ahci
- marvell,armada-3700-ahci
reg:
minItems: 1
maxItems: 2
reg-names:
maxItems: 1
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
interrupts:
maxItems: 1
power-domains:
maxItems: 1
resets:
minItems: 1
maxItems: 3
iommus:
maxItems: 1
patternProperties:
"^sata-port@[0-9a-f]+$":
$ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
anyOf:
- required: [ phys ]
- required: [ target-supply ]
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
allOf:
- $ref: ahci-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,apq8064-ahci
- qcom,ipq806x-ahci
then:
properties:
clocks:
minItems: 5
clock-names:
items:
- const: slave_iface
- const: iface
- const: core
- const: rxoob
- const: pmalive
required:
- phys
- phy-names
- clocks
- clock-names
- if:
properties:
compatible:
contains:
const: socionext,uniphier-pro4-ahci
then:
properties:
resets:
items:
- description: reset line for the parent
- description: reset line for the glue logic
- description: reset line for the controller
required:
- resets
else:
if:
properties:
compatible:
contains:
enum:
- socionext,uniphier-pxs2-ahci
- socionext,uniphier-pxs3-ahci
then:
properties:
resets:
items:
- description: reset for the glue logic
- description: reset for the controller
required:
- resets
else:
properties:
resets:
maxItems: 1
unevaluatedProperties: false
examples:
- |
sata@ffe08000 {
compatible = "snps,spear-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/ata/ahci.h>
sata@f7e90000 {
compatible = "marvell,berlin2q-ahci", "generic-ahci";
reg = <0xf7e90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
hba-cap = <HBA_SMPS>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
target-supply = <&reg_sata0>;
hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
target-supply = <&reg_sata1>;
hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 AHCI SATA Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
const: allwinner,sun4i-a10-ahci
reg:
maxItems: 1
clocks:
items:
- description: AHCI Bus Clock
- description: AHCI Module Clock
interrupts:
maxItems: 1
target-supply:
description: Regulator for SATA target power
required:
- compatible
- reg
- clocks
- interrupts
additionalProperties: false
examples:
- |
ahci: sata@1c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
clocks = <&pll6 0>, <&ahb_gates 25>;
target-supply = <&reg_ahci_5v>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/allwinner,sun8i-r40-ahci.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner R40 AHCI SATA Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
const: allwinner,sun8i-r40-ahci
reg:
maxItems: 1
clocks:
items:
- description: AHCI Bus Clock
- description: AHCI Module Clock
interrupts:
maxItems: 1
resets:
maxItems: 1
reset-names:
const: ahci
ahci-supply:
description: Regulator for the AHCI controller
phy-supply:
description: Regulator for the SATA PHY power
required:
- compatible
- reg
- clocks
- interrupts
- resets
- reset-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
ahci: sata@1c18000 {
compatible = "allwinner,sun8i-r40-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
resets = <&ccu RST_BUS_SATA>;
reset-names = "ahci";
ahci-supply = <&reg_dldo4>;
phy-supply = <&reg_eldo3>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/apm,xgene-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene 6.0 Gb/s SATA host controller
maintainers:
- Rob Herring <robh@kernel.org>
properties:
compatible:
enum:
- apm,xgene-ahci
- apm,xgene-ahci-v2
reg:
minItems: 4
items:
- description: AHCI memory resource
- description: Host controller core
- description: Host controller diagnostic
- description: Host controller AXI
- description: Host controller MUX
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
unevaluatedProperties: false
allOf:
- $ref: ahci-common.yaml#
- if:
properties:
compatible:
contains:
const: apm,xgene-ahci
then:
required:
- clocks
- phys
- phy-names
examples:
- |
sata@1a400000 {
compatible = "apm,xgene-ahci";
reg = <0x1a400000 0x1000>,
<0x1f220000 0x1000>,
<0x1f22d000 0x1000>,
<0x1f22e000 0x1000>,
<0x1f227000 0x1000>;
clocks = <&sataclk 0>;
dma-coherent;
interrupts = <0x0 0x87 0x4>;
phys = <&phy2 0>;
phy-names = "sata-phy";
};
linux-7.2.3/Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/arasan,cf-spear1340.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arasan PATA Compact Flash Controller
maintainers:
- Viresh Kumar <viresh.kumar@linaro.org>
properties:
compatible:
const: arasan,cf-spear1340
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
arasan,broken-udma:
description: UDMA mode is unusable
type: boolean
arasan,broken-mwdma:
description: MWDMA mode is unusable
type: boolean
arasan,broken-pio:
description: PIO mode is unusable
type: boolean
dmas:
maxItems: 1
dma-names:
items:
- const: data
required:
- compatible
- reg
- interrupts
additionalProperties: false
allOf:
- if:
not:
required:
- arasan,broken-udma
- arasan,broken-mwdma
then:
required:
- dmas
- dma-names
examples:
- |
cf@fc000000 {
compatible = "arasan,cf-spear1340";
reg = <0xfc000000 0x1000>;
interrupts = <12>;
dmas = <&dma 23>;
dma-names = "data";
};
linux-7.2.3/Documentation/devicetree/bindings/ata/ata-generic.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ata-generic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic Parallel ATA Controller
maintainers:
- Linus Walleij <linusw@kernel.org>
description:
Generic Parallel ATA controllers supporting PIO modes only.
properties:
compatible:
items:
- enum:
- arm,vexpress-cf
- fsl,mpc8349emitx-pata
- const: ata-generic
reg:
items:
- description: Command interface registers
- description: Control interface registers
reg-shift:
enum: [ 1, 2 ]
interrupts:
maxItems: 1
ata-generic,use16bit:
type: boolean
description: Use 16-bit accesses instead of 32-bit for data transfers
pio-mode:
description: Maximum ATA PIO transfer mode
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 6
default: 0
required:
- compatible
- reg
additionalProperties: false
examples:
- |
compact-flash@1a000 {
compatible = "arm,vexpress-cf", "ata-generic";
reg = <0x1a000 0x100>,
<0x1a100 0xf00>;
reg-shift = <2>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom SATA3 AHCI Controller
description:
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
allOf:
- $ref: ahci-common.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,bcm7216-ahci
- brcm,bcm7445-ahci
- brcm,bcm7425-ahci
- brcm,bcm63138-ahci
- const: brcm,sata3-ahci
- items:
- const: brcm,bcm-nsp-ahci
reg:
maxItems: 2
reg-names:
items:
- const: ahci
- const: top-ctrl
interrupts:
maxItems: 1
if:
properties:
compatible:
contains:
enum:
- brcm,bcm7216-ahci
- brcm,bcm63138-ahci
then:
properties:
resets:
maxItems: 1
reset-names:
enum:
- rescal
- ahci
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
sata@f045a000 {
compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
reg-names = "ahci", "top-ctrl";
interrupts = <0 30 0>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/ata/cavium,ebt3000-compact-flash.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/cavium,ebt3000-compact-flash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cavium Compact Flash
maintainers:
- Rob Herring <robh@kernel.org>
description:
The Cavium Compact Flash device is connected to the Octeon Boot Bus, and is
thus a child of the Boot Bus device. It can read and write industry standard
compact flash devices.
properties:
compatible:
const: cavium,ebt3000-compact-flash
reg:
description: The base address of the CF chip select banks.
items:
- description: CF chip select bank 0
- description: CF chip select bank 1
cavium,bus-width:
description: The width of the connection to the CF devices.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
cavium,true-ide:
description: True IDE mode when present.
type: boolean
cavium,dma-engine-handle:
description: A phandle for the DMA Engine connected to this device.
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- reg
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <1>;
compact-flash@5,0 {
compatible = "cavium,ebt3000-compact-flash";
reg = <5 0 0x10000>, <6 0 0x10000>;
cavium,bus-width = <16>;
cavium,true-ide;
cavium,dma-engine-handle = <&dma0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some
special extensions to add functionality, is a high-performance dual-port
SATA host controller with an AHCI compliant command layer which supports
advanced features such as native command queuing and frame information
structure (FIS) based switching for systems employing port multipliers.
properties:
compatible:
const: ceva,ahci-1v84
reg:
maxItems: 1
clocks:
maxItems: 1
dma-coherent: true
interrupts:
maxItems: 1
iommus:
maxItems: 4
power-domains:
maxItems: 1
ceva,p0-cominit-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMINIT parameter for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
items:
- description: CINMP - COMINIT Negate Minimum Period.
- description: CIBGN - COMINIT Burst Gap Nominal.
- description: CIBGMX - COMINIT Burst Gap Maximum.
- description: CIBGMN - COMINIT Burst Gap Minimum.
ceva,p0-comwake-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMWAKE parameter for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
items:
- description: CWBGMN - COMWAKE Burst Gap Minimum.
- description: CWBGMX - COMWAKE Burst Gap Maximum.
- description: CWBGN - COMWAKE Burst Gap Nominal.
- description: CWNMP - COMWAKE Negate Minimum Period.
ceva,p0-burst-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
Burst timing value for COM parameter for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
items:
- description: BMX - COM Burst Maximum.
- description: BNM - COM Burst Nominal.
- description: SFD - Signal Failure Detection value.
- description: PTST - Partial to Slumber timer value.
ceva,p0-retry-params:
$ref: /schemas/types.yaml#/definitions/uint16-array
description: |
Retry interval timing value for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-retry-params = /bits/ 16 <RIT RCT>;
items:
- description: RIT - Retry Interval Timer.
- description: RCT - Rate Change Timer.
ceva,p1-cominit-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMINIT parameter for port 1.
The fields for the above parameter must be as shown below:-
ceva,p1-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
items:
- description: CINMP - COMINIT Negate Minimum Period.
- description: CIBGN - COMINIT Burst Gap Nominal.
- description: CIBGMX - COMINIT Burst Gap Maximum.
- description: CIBGMN - COMINIT Burst Gap Minimum.
ceva,p1-comwake-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMWAKE parameter for port 1.
The fields for the above parameter must be as shown below:-
ceva,p1-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
items:
- description: CWBGMN - COMWAKE Burst Gap Minimum.
- description: CWBGMX - COMWAKE Burst Gap Maximum.
- description: CWBGN - COMWAKE Burst Gap Nominal.
- description: CWNMP - COMWAKE Negate Minimum Period.
ceva,p1-burst-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
Burst timing value for COM parameter for port 1.
The fields for the above parameter must be as shown below:-
ceva,p1-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
items:
- description: BMX - COM Burst Maximum.
- description: BNM - COM Burst Nominal.
- description: SFD - Signal Failure Detection value.
- description: PTST - Partial to Slumber timer value.
ceva,p1-retry-params:
$ref: /schemas/types.yaml#/definitions/uint16-array
description: |
Retry interval timing value for port 1.
The fields for the above parameter must be as shown below:-
ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
items:
- description: RIT - Retry Interval Timer.
- description: RCT - Rate Change Timer.
ceva,broken-gen2:
$ref: /schemas/types.yaml#/definitions/flag
description: |
limit to gen1 speed instead of gen2.
phys:
maxItems: 1
phy-names:
items:
- const: sata-phy
resets:
maxItems: 1
required:
- compatible
- reg
- clocks
- interrupts
- ceva,p0-cominit-params
- ceva,p0-comwake-params
- ceva,p0-burst-params
- ceva,p0-retry-params
- ceva,p1-cominit-params
- ceva,p1-comwake-params
- ceva,p1-burst-params
- ceva,p1-retry-params
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
#include <dt-bindings/phy/phy.h>
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
reg = <0xfd0c0000 0x200>;
interrupt-parent = <&gic>;
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 22>;
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
phys = <&psgtr 1 PHY_TYPE_SATA 1 1>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic EP9312 PATA controller
maintainers:
- Damien Le Moal <dlemoal@kernel.org>
properties:
compatible:
oneOf:
- const: cirrus,ep9312-pata
- items:
- const: cirrus,ep9315-pata
- const: cirrus,ep9312-pata
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
ide@800a0000 {
compatible = "cirrus,ep9312-pata";
reg = <0x800a0000 0x38>;
interrupt-parent = <&vic1>;
interrupts = <8>;
pinctrl-names = "default";
pinctrl-0 = <&ide_default_pins>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina Systems Gemini SATA Bridge
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
takes two Faraday Technology FTIDE010 PATA controllers and bridges
them in different configurations to two SATA ports.
properties:
compatible:
const: cortina,gemini-sata-bridge
reg:
maxItems: 1
resets:
maxItems: 2
description: phandles to the reset lines for both SATA bridges
reset-names:
items:
- const: sata0
- const: sata1
clocks:
maxItems: 2
description: phandles to the compulsory peripheral clocks
clock-names:
items:
- const: SATA0_PCLK
- const: SATA1_PCLK
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the global Gemini system controller
cortina,gemini-ata-muxmode:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0
- 1
- 2
- 3
description: |
Tell the desired multiplexing mode for the ATA controller and SATA
bridges.
Mode 0: ata0 master <-> sata0
ata1 master <-> sata1
ata0 slave interface brought out on IDE pads
Mode 1: ata0 master <-> sata0
ata1 master <-> sata1
ata1 slave interface brought out on IDE pads
Mode 2: ata1 master <-> sata1
ata1 slave <-> sata0
ata0 master and slave interfaces brought out on IDE pads
Mode 3: ata0 master <-> sata0
ata0 slave <-> sata1
ata1 master and slave interfaces brought out on IDE pads
cortina,gemini-enable-ide-pins:
type: boolean
description: Enables the PATA to IDE connection.
The muxmode setting decides whether ATA0 or ATA1 is brought out,
and whether master, slave or both interfaces get brought out.
cortina,gemini-enable-sata-bridge:
type: boolean
description: Enables the PATA to SATA bridge inside the Gemnini SoC.
The Muxmode decides what PATA blocks will be muxed out and how.
required:
- clocks
- clock-names
- cortina,gemini-ata-muxmode
- resets
- reset-names
- compatible
- reg
- syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/cortina,gemini-clock.h>
sata@46000000 {
compatible = "cortina,gemini-sata-bridge";
reg = <0x46000000 0x100>;
resets = <&rcon 26>, <&rcon 27>;
reset-names = "sata0", "sata1";
clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
<&gcc GEMINI_CLK_GATE_SATA1>;
clock-names = "SATA0_PCLK", "SATA1_PCLK";
syscon = <&syscon>;
cortina,gemini-ata-muxmode = <3>;
cortina,gemini-enable-ide-pins;
cortina,gemini-enable-sata-bridge;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Eswin EIC7700 SoC SATA Controller
maintainers:
- Yulin Lu <luyulin@eswincomputing.com>
- Huan He <hehuan1@eswincomputing.com>
description:
AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI
SATA v5.00a IP core.
select:
properties:
compatible:
const: eswin,eic7700-ahci
required:
- compatible
allOf:
- $ref: snps,dwc-ahci-common.yaml#
properties:
compatible:
items:
- const: eswin,eic7700-ahci
- const: snps,dwc-ahci
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pclk
- const: aclk
resets:
maxItems: 1
reset-names:
const: arst
ports-implemented:
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- phys
- phy-names
- ports-implemented
unevaluatedProperties: false
examples:
- |
sata@50420000 {
compatible = "eswin,eic7700-ahci", "snps,dwc-ahci";
reg = <0x50420000 0x10000>;
interrupt-parent = <&plic>;
interrupts = <58>;
clocks = <&clock 171>, <&clock 186>;
clock-names = "pclk", "aclk";
phys = <&sata_phy>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
resets = <&reset 96>;
reset-names = "arst";
};
linux-7.2.3/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTIDE010 PATA controller
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
This controller is the first Faraday IDE interface block, used in the
StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini
platform. The controller can do PIO modes 0 through 4, Multi-word DMA
(MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6.
On the Gemini platform, this PATA block is accompanied by a PATA to
SATA bridge in order to support SATA. This is why a phandle to that
controller is compulsory on that platform.
The timing properties are unique per-SoC, not per-board.
properties:
compatible:
oneOf:
- const: faraday,ftide010
- items:
- const: cortina,gemini-pata
- const: faraday,ftide010
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
clock-names:
const: PCLK
sata:
description:
phandle to the Gemini PATA to SATA bridge, if available
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- reg
- interrupts
allOf:
- $ref: pata-common.yaml#
- if:
properties:
compatible:
contains:
const: cortina,gemini-pata
then:
required:
- sata
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/cortina,gemini-clock.h>
ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x100>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
clocks = <&gcc GEMINI_CLK_GATE_IDE>;
clock-names = "PCLK";
sata = <&sata>;
#address-cells = <1>;
#size-cells = <0>;
ide-port@0 {
reg = <0>;
};
ide-port@1 {
reg = <1>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/fsl,ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/fsl,ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QorIQ AHCI SATA Controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- description: SATA controller for ls1012a
items:
- const: fsl,ls1012a-ahci
- const: fsl,ls1043a-ahci
- enum:
- fsl,ls1021a-ahci
- fsl,ls1028a-ahci
- fsl,ls1043a-ahci
- fsl,ls1046a-ahci
- fsl,ls1088a-ahci
- fsl,ls2080a-ahci
- fsl,lx2160a-ahci
reg:
minItems: 1
maxItems: 2
reg-names:
items:
- const: ahci
- const: sata-ecc
minItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
dma-coherent: true
required:
- compatible
- reg
- clocks
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
sata@3200000 {
compatible = "fsl,ls1021a-ahci";
reg = <0x3200000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
dma-coherent;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/fsl,imx-pata.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/fsl,imx-pata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX PATA Controller
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,imx31-pata
- fsl,imx51-pata
- const: fsl,imx27-pata
- const: fsl,imx27-pata
reg:
maxItems: 1
interrupts:
items:
- description: PATA Controller interrupts
clocks:
items:
- description: PATA Controller clocks
additionalProperties: false
examples:
- |
pata: pata@83fe0000 {
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 161>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/fsl,pq-sata.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale 8xxx/3.0 Gb/s SATA nodes
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,mpc8377-sata
- fsl,mpc8536-sata
- fsl,mpc8315-sata
- fsl,mpc8379-sata
- const: fsl,pq-sata
- const: fsl,pq-sata-v2
reg:
maxItems: 1
interrupts:
maxItems: 1
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4]
description: |
1 for controller @ 0x18000
2 for controller @ 0x19000
3 for controller @ 0x1a000
4 for controller @ 0x1b000
required:
- compatible
- interrupts
- cell-index
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
sata@18000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/imx-sata.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX AHCI SATA Controller
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The Freescale i.MX SATA controller mostly conforms to the AHCI interface
with some special extensions at integration level.
properties:
compatible:
enum:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
- fsl,imx8qm-ahci
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
items:
- description: sata clock
- description: sata reference clock
- description: ahb clock
clock-names:
minItems: 2
items:
- const: sata
- const: sata_ref
- const: ahb
fsl,transmit-level-mV:
$ref: /schemas/types.yaml#/definitions/uint32
description: transmit voltage level, in millivolts.
fsl,transmit-boost-mdB:
$ref: /schemas/types.yaml#/definitions/uint32
description: transmit boost level, in milli-decibels.
fsl,transmit-atten-16ths:
$ref: /schemas/types.yaml#/definitions/uint32
description: transmit attenuation, in 16ths.
fsl,receive-eq-mdB:
$ref: /schemas/types.yaml#/definitions/uint32
description: receive equalisation, in milli-decibels.
fsl,no-spread-spectrum:
$ref: /schemas/types.yaml#/definitions/flag
description: if present, disable spread-spectrum clocking on the SATA link.
phys:
items:
- description: phandle to SATA PHY.
Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
calibration result will be stored, passed through second lane, and
shared with all three lanes PHY. The first two lanes PHY are used as
calibration PHYs, although only the third lane PHY is used by SATA.
- description: phandle to the first lane PHY of i.MX8QM.
- description: phandle to the second lane PHY of i.MX8QM.
phy-names:
items:
- const: sata-phy
- const: cali-phy0
- const: cali-phy1
power-domains:
maxItems: 1
target-supply:
description: Power regulator for the SATA target device.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
then:
properties:
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-ahci
then:
properties:
clock-names:
minItems: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
sata@2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SATA>,
<&clks IMX6QDL_CLK_SATA_REF_100M>,
<&clks IMX6QDL_CLK_AHB>;
clock-names = "sata", "sata_ref", "ahb";
};
linux-7.2.3/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx CompactFlash Card Controller
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
The IXP4xx network processors have a CompactFlash interface that presents
a CompactFlash card to the system as a true IDE (parallel ATA) device. The
device is always connected to the expansion bus of the IXP4xx SoCs using one
or two chip select areas and address translating logic on the board. The
node must be placed inside a chip select node on the IXP4xx expansion bus.
properties:
compatible:
const: intel,ixp4xx-compact-flash
reg:
items:
- description: Command interface registers
- description: Control interface registers
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
allOf:
- $ref: pata-common.yaml#
- $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
bus@c4000000 {
compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x1000>;
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
ide@1,0 {
compatible = "intel,ixp4xx-compact-flash";
reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
interrupt-parent = <&gpio0>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/marvell,orion-sata.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/marvell,orion-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Orion SATA
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
allOf:
- $ref: sata-common.yaml#
properties:
compatible:
enum:
- marvell,orion-sata
- marvell,armada-370-sata
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 8
clock-names:
minItems: 1
items:
- const: '0'
- const: '1'
- const: '2'
- const: '3'
- const: '4'
- const: '5'
- const: '6'
- const: '7'
interrupts:
maxItems: 1
nr-ports:
description:
Number of SATA ports in use.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 8
phys:
minItems: 1
maxItems: 8
phy-names:
minItems: 1
items:
- const: port0
- const: port1
- const: port2
- const: port3
- const: port4
- const: port5
- const: port6
- const: port7
required:
- compatible
- reg
- interrupts
- nr-ports
unevaluatedProperties: false
examples:
- |
sata@80000 {
compatible = "marvell,orion-sata";
reg = <0x80000 0x5000>;
interrupts = <21>;
phys = <&sata_phy0>, <&sata_phy1>;
phy-names = "port0", "port1";
nr-ports = <2>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/mediatek,mtk-ahci.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Serial ATA controller
maintainers:
- Ryder Lee <ryder.lee@mediatek.com>
allOf:
- $ref: ahci-common.yaml#
properties:
compatible:
items:
- enum:
- mediatek,mt7622-ahci
- const: mediatek,mtk-ahci
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-names:
const: hostc
clocks:
maxItems: 5
clock-names:
items:
- const: ahb
- const: axi
- const: asic
- const: rbc
- const: pm
power-domains:
maxItems: 1
resets:
maxItems: 3
reset-names:
items:
- const: axi
- const: sw
- const: reg
mediatek,phy-mode:
description: System controller phandle, used to enable SATA function
$ref: /schemas/types.yaml#/definitions/phandle
required:
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- phys
- phy-names
- ports-implemented
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/reset/mt7622-reset.h>
sata@1a200000 {
compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
reg = <0x1a200000 0x1100>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
clocks = <&pciesys CLK_SATA_AHB_EN>,
<&pciesys CLK_SATA_AXI_EN>,
<&pciesys CLK_SATA_ASIC_EN>,
<&pciesys CLK_SATA_RBC_EN>,
<&pciesys CLK_SATA_PM_EN>;
clock-names = "ahb", "axi", "asic", "rbc", "pm";
phys = <&u3port1 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
<&pciesys MT7622_SATA_PHY_SW_RST>,
<&pciesys MT7622_SATA_PHY_REG_RST>;
reset-names = "axi", "sw", "reg";
mediatek,phy-mode = <&pciesys>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra AHCI SATA Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra124-ahci
- nvidia,tegra132-ahci
- nvidia,tegra210-ahci
- nvidia,tegra186-ahci
reg:
minItems: 2
items:
- description: AHCI registers
- description: SATA configuration and IPFS registers
- description: SATA AUX registers
interrupts:
maxItems: 1
clock-names:
items:
- const: sata
- const: sata-oob
clocks:
maxItems: 2
reset-names:
minItems: 2
items:
- const: sata
- const: sata-cold
- const: sata-oob
resets:
minItems: 2
maxItems: 3
iommus:
maxItems: 1
interconnect-names:
items:
- const: dma-mem
- const: write
interconnects:
maxItems: 2
power-domains:
items:
- description: SAX power-domain
phy-names:
items:
- const: sata-0
phys:
maxItems: 1
hvdd-supply:
description: SATA HVDD regulator supply.
vddio-supply:
description: SATA VDDIO regulator supply.
avdd-supply:
description: SATA AVDD regulator supply.
target-5v-supply:
description: SATA 5V power regulator supply.
target-12v-supply:
description: SATA 12V power regulator supply.
required:
- compatible
- reg
- interrupts
- clock-names
- clocks
- reset-names
- resets
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-ahci
- nvidia,tegra132-ahci
then:
properties:
reg:
maxItems: 2
reset-names:
minItems: 3
resets:
minItems: 3
required:
- phys
- phy-names
- hvdd-supply
- vddio-supply
- avdd-supply
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra210-ahci
then:
properties:
reg:
minItems: 3
reset-names:
minItems: 3
resets:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-ahci
then:
properties:
reg:
minItems: 3
reset-names:
maxItems: 2
resets:
maxItems: 2
required:
- iommus
- interconnect-names
- interconnects
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
sata@70020000 {
compatible = "nvidia,tegra210-ahci";
reg = <0x70027000 0x00002000>, /* AHCI */
<0x70020000 0x00007000>, /* SATA */
<0x70001100 0x00010000>; /* SATA AUX */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SATA>,
<&tegra_car TEGRA210_CLK_SATA_OOB>;
clock-names = "sata", "sata-oob";
resets = <&tegra_car 124>,
<&tegra_car 129>,
<&tegra_car 123>;
reset-names = "sata", "sata-cold", "sata-oob";
};
linux-7.2.3/Documentation/devicetree/bindings/ata/pata-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/pata-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Parallel AT attachment (PATA) controllers
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
This document defines device tree properties common to most Parallel
ATA (PATA, also known as IDE) AT attachment storage devices.
It doesn't constitute a device tree binding specification by itself but is
meant to be referenced by device tree bindings.
The PATA (IDE) controller-specific device tree bindings are responsible for
defining whether each property is required or optional.
properties:
$nodename:
pattern: "^ide(@.*)?$"
description:
Specifies the host controller node. PATA host controller nodes are named
"ide".
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^ide-port@[0-1]$":
description: |
DT nodes for ports connected on the PATA host. The master drive will have
ID number 0 and the slave drive will have ID number 1. The PATA port
nodes will be named "ide-port".
type: object
additionalProperties: false
properties:
reg:
minimum: 0
maximum: 1
description:
The ID number of the drive port, 0 for the master port and 1 for the
slave port.
additionalProperties: true
...
linux-7.2.3/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Serial-ATA Interface
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,sata-r8a7779 # R-Car H1
- items:
- enum:
- renesas,sata-r8a7742 # RZ/G1H
- renesas,sata-r8a7790-es1 # R-Car H2 ES1
- renesas,sata-r8a7790 # R-Car H2 other than ES1
- renesas,sata-r8a7791 # R-Car M2-W
- renesas,sata-r8a7793 # R-Car M2-N
- const: renesas,rcar-gen2-sata # generic R-Car Gen2
- items:
- enum:
- renesas,sata-r8a774b1 # RZ/G2N
- renesas,sata-r8a774e1 # RZ/G2H
- renesas,sata-r8a7795 # R-Car H3
- renesas,sata-r8a77965 # R-Car M3-N
- const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- power-domains
if:
not:
properties:
compatible:
contains:
const: renesas,sata-r8a7779
then:
required:
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7791-sysc.h>
sata@ee300000 {
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0xee300000 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 815>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DWC AHCI SATA controller for Rockchip devices
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description:
This document defines device tree bindings for the Synopsys DWC
implementation of the AHCI SATA controller found in Rockchip
devices.
select:
properties:
compatible:
contains:
enum:
- rockchip,rk3568-dwc-ahci
- rockchip,rk3576-dwc-ahci
- rockchip,rk3588-dwc-ahci
required:
- compatible
properties:
compatible:
items:
- enum:
- rockchip,rk3568-dwc-ahci
- rockchip,rk3576-dwc-ahci
- rockchip,rk3588-dwc-ahci
- const: snps,dwc-ahci
ports-implemented:
const: 1
power-domains:
maxItems: 1
sata-port@0:
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
properties:
reg:
const: 0
unevaluatedProperties: false
patternProperties:
"^sata-port@[1-9a-e]$": false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- ports-implemented
allOf:
- $ref: snps,dwc-ahci-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3588-dwc-ahci
then:
properties:
clocks:
maxItems: 5
clock-names:
items:
- const: sata
- const: pmalive
- const: rxoob
- const: ref
- const: asic
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3568-dwc-ahci
- rockchip,rk3576-dwc-ahci
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: sata
- const: pmalive
- const: rxoob
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/ata/ahci.h>
#include <dt-bindings/phy/phy.h>
sata@fe210000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0xfe210000 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/sata-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/sata-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Serial AT attachment (SATA) controllers
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
This document defines device tree properties common to most Serial
AT attachment (SATA) storage devices. It doesn't constitute a device tree
binding specification by itself but is meant to be referenced by device
tree bindings.
The SATA controller-specific device tree bindings are responsible for
defining whether each property is required or optional.
properties:
$nodename:
pattern: "^sata(@.*)?$"
description:
Specifies the host controller node. SATA host controller nodes are named
"sata"
"#address-cells":
const: 1
"#size-cells":
const: 0
dma-coherent: true
patternProperties:
"^sata-port@[0-9a-e]$":
$ref: '#/$defs/sata-port'
description: |
DT nodes for ports connected on the SATA host. The SATA port
nodes will be named "sata-port".
additionalProperties: true
$defs:
sata-port:
type: object
properties:
reg:
minimum: 0
description:
The ID number of the SATA port. Aside with being directly used,
each port can have a Port Multiplier attached thus allowing to
access more than one drive by means of a single SATA port.
port:
$ref: /schemas/graph.yaml#/properties/port
...
linux-7.2.3/Documentation/devicetree/bindings/ata/sata_highbank.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda AHCI SATA Controller
description: |
The Calxeda SATA controller mostly conforms to the AHCI interface
with some special extensions to add functionality, to map GPIOs for
activity LEDs and for mapping the ComboPHYs.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: calxeda,hb-ahci
reg:
maxItems: 1
interrupts:
maxItems: 1
dma-coherent: true
calxeda,pre-clocks:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Indicates the number of additional clock cycles to transmit before
sending an SGPIO pattern.
calxeda,post-clocks:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Indicates the number of additional clock cycles to transmit after
sending an SGPIO pattern.
calxeda,led-order:
description: Maps port numbers to offsets within the SGPIO bitstream.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
calxeda,port-phys:
description: |
phandle-combophy and lane assignment, which maps each SATA port to a
combophy and a lane within that combophy
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
items:
maxItems: 2
calxeda,tx-atten:
description: |
Contains TX attenuation override codes, one per port.
The upper 24 bits of each entry are always 0 and thus ignored.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
calxeda,sgpio-gpio:
maxItems: 3
description: |
phandle-gpio bank, bit offset, and default on or off, which indicates
that the driver supports SGPIO indicator lights using the indicated
GPIOs.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
sata@ffe08000 {
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
dma-coherent;
calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
<&combophy0 2>, <&combophy0 3>;
calxeda,sgpio-gpio = <&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
calxeda,pre-clocks = <10>;
calxeda,post-clocks = <0>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DWC AHCI SATA controller properties
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description:
This document defines device tree schema for the generic Synopsys DWC
AHCI controller properties.
select: false
allOf:
- $ref: ahci-common.yaml#
properties:
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description:
Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
clock, etc.
minItems: 1
maxItems: 6
clock-names:
minItems: 1
maxItems: 6
items:
oneOf:
- description: Application APB/AHB/AXI BIU clock
enum:
- pclk
- aclk
- hclk
- sata
- description: Power Module keep-alive clock
const: pmalive
- description: RxOOB detection clock
const: rxoob
- description: PHY Transmit Clock
const: asic
- description: PHY Receive Clock
const: rbc
- description: SATA Ports reference clock
const: ref
resets:
description:
At least basic application and reference clock domains resets are
normally supported by the DWC AHCI SATA controller.
minItems: 1
maxItems: 4
reset-names:
minItems: 1
maxItems: 4
items:
oneOf:
- description: Application AHB/AXI BIU clock domain reset control
enum:
- arst
- hrst
- description: Power Module keep-alive clock domain reset control
const: pmalive
- description: RxOOB detection clock domain reset control
const: rxoob
- description: Reference clock domain reset control
const: ref
patternProperties:
"^sata-port@[0-9a-e]$":
$ref: '#/$defs/dwc-ahci-port'
additionalProperties: true
$defs:
dwc-ahci-port:
$ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
properties:
reg:
minimum: 0
maximum: 7
snps,tx-ts-max:
$ref: /schemas/types.yaml#/definitions/uint32
description: Maximal size of Tx DMA transactions in FIFO words
enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
snps,rx-ts-max:
$ref: /schemas/types.yaml#/definitions/uint32
description: Maximal size of Rx DMA transactions in FIFO words
enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
...
linux-7.2.3/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DWC AHCI SATA controller
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description:
This document defines device tree bindings for the generic Synopsys DWC
implementation of the AHCI SATA controller.
select:
properties:
compatible:
enum:
- snps,dwc-ahci
- snps,spear-ahci
required:
- compatible
allOf:
- $ref: snps,dwc-ahci-common.yaml#
properties:
compatible:
oneOf:
- description: Synopsys AHCI SATA-compatible devices
const: snps,dwc-ahci
- description: SPEAr1340 AHCI SATA device
const: snps,spear-ahci
iommus:
minItems: 1
maxItems: 3
patternProperties:
"^sata-port@[0-9a-e]$":
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/ata/ahci.h>
sata@122f0000 {
compatible = "snps,dwc-ahci";
reg = <0x122F0000 0x1ff>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock1>, <&clock2>;
clock-names = "aclk", "ref";
phys = <&sata_phy>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
snps,tx-ts-max = <512>;
snps,rx-ts-max = <512>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/ata/st,ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/st,ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STi SATA controller
maintainers:
- Patrice Chotard <patrice.chotard@foss.st.com>
allOf:
- $ref: ahci-common.yaml#
properties:
compatible:
const: st,ahci
interrupt-names:
items:
- const: hostc
clocks:
maxItems: 1
clock-names:
items:
- const: ahci_clk
resets:
items:
- description: Power-down line
- description: Soft-reset line
- description: Power-reset line
reset-names:
items:
- const: pwr-dwn
- const: sw-rst
- const: pwr-rst
required:
- compatible
- interrupt-names
- phys
- phy-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/stih407-resets.h>
#include <dt-bindings/clock/stih407-clks.h>
sata@9b20000 {
compatible = "st,ahci";
reg = <0x9b20000 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
interrupt-names = "hostc";
phys = <&phy_port0 PHY_TYPE_SATA>;
phy-names = "sata-phy";
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
<&softreset STIH407_SATA0_SOFTRESET>,
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
clock-names = "ahci_clk";
};
linux-7.2.3/Documentation/devicetree/bindings/ata/ti,da850-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ti,da850-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DA850 AHCI SATA Controller
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
properties:
compatible:
const: ti,da850-ahci
reg:
items:
- description: Address and size of the register map as defined by the AHCI 1.1 standard.
- description:
Address and size of Power Down Control Register (PWRDN) for enabling/disabling the SATA clock
receiver.
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
sata@218000 {
compatible = "ti,da850-ahci";
reg = <0x218000 0x2000>, <0x22c018 0x4>;
interrupts = <67>;
};
linux-7.2.3/Documentation/devicetree/bindings/ata/ti,dm816-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ti,dm816-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DM816 AHCI SATA Controller
maintainers:
- Bartosz Golaszewski <brgl@bgdev.pl>
allOf:
- $ref: ahci-common.yaml#
properties:
compatible:
const: ti,dm816-ahci
reg:
maxItems: 1
clocks:
items:
- description: functional clock
- description: external reference clock
ti,hwmods:
const: sata
required:
- compatible
- clocks
unevaluatedProperties: false
examples:
- |
sata@4a140000 {
compatible = "ti,dm816-ahci";
reg = <0x4a140000 0x10000>;
interrupts = <16>;
clocks = <&sysclk5_ck>, <&sata_refclk>;
};