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linux-7.2.3/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2023 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andestech AX45MP L2 Cache Controller
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
A level-2 cache (L2C) is used to improve the system performance by providing
a large amount of cache line entries and reasonable access delays. The L2C
is shared between cores, and a non-inclusive non-exclusive policy is used.
select:
properties:
compatible:
contains:
enum:
- andestech,ax45mp-cache
required:
- compatible
properties:
compatible:
items:
- enum:
- andestech,qilai-ax45mp-cache
- renesas,r9a07g043f-ax45mp-cache
- const: andestech,ax45mp-cache
- const: cache
reg:
maxItems: 1
interrupts:
maxItems: 1
cache-line-size:
const: 64
cache-level:
const: 2
cache-sets:
enum: [1024, 2048]
cache-size:
enum: [131072, 262144, 524288, 1048576, 2097152]
cache-unified: true
next-level-cache: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- cache-line-size
- cache-level
- cache-sets
- cache-size
- cache-unified
allOf:
- if:
properties:
compatible:
contains:
const: andestech,qilai-ax45mp-cache
then:
properties:
cache-sets:
const: 2048
cache-size:
const: 2097152
else:
properties:
cache-sets:
const: 1024
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
cache-controller@13400000 {
compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
"cache";
reg = <0x13400000 0x100000>;
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
cache-line-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <262144>;
cache-unified;
};
linux-7.2.3/Documentation/devicetree/bindings/cache/freescale-l2cache.txt
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Freescale L2 Cache Controller
L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
The cache bindings explained below are Devicetree Specification compliant
Required Properties:
- compatible : Should include one of the following:
"fsl,b4420-l2-cache-controller"
"fsl,b4860-l2-cache-controller"
"fsl,bsc9131-l2-cache-controller"
"fsl,bsc9132-l2-cache-controller"
"fsl,c293-l2-cache-controller"
"fsl,mpc8536-l2-cache-controller"
"fsl,mpc8540-l2-cache-controller"
"fsl,mpc8541-l2-cache-controller"
"fsl,mpc8544-l2-cache-controller"
"fsl,mpc8548-l2-cache-controller"
"fsl,mpc8555-l2-cache-controller"
"fsl,mpc8560-l2-cache-controller"
"fsl,mpc8568-l2-cache-controller"
"fsl,mpc8569-l2-cache-controller"
"fsl,mpc8572-l2-cache-controller"
"fsl,p1010-l2-cache-controller"
"fsl,p1011-l2-cache-controller"
"fsl,p1012-l2-cache-controller"
"fsl,p1013-l2-cache-controller"
"fsl,p1014-l2-cache-controller"
"fsl,p1015-l2-cache-controller"
"fsl,p1016-l2-cache-controller"
"fsl,p1020-l2-cache-controller"
"fsl,p1021-l2-cache-controller"
"fsl,p1022-l2-cache-controller"
"fsl,p1023-l2-cache-controller"
"fsl,p1024-l2-cache-controller"
"fsl,p1025-l2-cache-controller"
"fsl,p2010-l2-cache-controller"
"fsl,p2020-l2-cache-controller"
"fsl,t2080-l2-cache-controller"
"fsl,t4240-l2-cache-controller"
and "cache".
- reg : Address and size of L2 cache controller registers
- cache-size : Size of the entire L2 cache
- interrupts : Error interrupt of L2 controller
- cache-line-size : Size of L2 cache lines
Example:
L2: l2-cache-controller@20000 {
compatible = "fsl,bsc9132-l2-cache-controller", "cache";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2,256K
interrupts = <16 2 1 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/cache/l2c2x0.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM L2 Cache Controller
maintainers:
- Rob Herring <robh@kernel.org>
description: |+
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
PL220/PL310 and variants) based level 2 cache controller. All these various
implementations of the L2 cache controller have compatible programming
models (Note 1). Some of the properties that are just prefixed "cache-*" are
taken from section 3.7.3 of the Devicetree Specification which can be found
at:
https://www.devicetree.org/specifications/
Note 1: The description in this document doesn't apply to integrated L2
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
integrated L2 controllers are assumed to be all preconfigured by
early secure boot code. Thus no need to deal with their configuration
in the kernel at all.
allOf:
- $ref: /schemas/cache-controller.yaml#
properties:
compatible:
oneOf:
- enum:
- arm,pl310-cache
- arm,l220-cache
- arm,l210-cache
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- bcm,bcm11351-a2-pl310-cache
# For Broadcom bcm11351 chipset where an
# offset needs to be added to the address before passing down to the L2
# cache controller
- brcm,bcm11351-a2-pl310-cache
# Marvell Controller designed to be
# compatible with the ARM one, with system cache mode (meaning
# maintenance operations on L1 are broadcasted to the L2 and L2
# performs the same operation).
- marvell,aurora-system-cache
# Marvell Controller designed to be
# compatible with the ARM one with outer cache mode.
- marvell,aurora-outer-cache
- items:
# Marvell Tauros3 cache controller, compatible
# with arm,pl310-cache controller.
- const: marvell,tauros3-cache
- const: arm,pl310-cache
cache-level:
const: 2
cache-unified: true
cache-size: true
cache-sets: true
cache-block-size: true
cache-line-size: true
reg:
maxItems: 1
power-domains:
maxItems: 1
arm,data-latency:
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
read, write and setup latencies. Minimum valid values are 1. Controllers
without setup latency control should use a value of 0.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 3
items:
minimum: 0
maximum: 8
arm,tag-latency:
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
read, write and setup latencies. Controllers without setup latency control
should use 0. Controllers without separate read and write Tag RAM latency
values should only use the first cell.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 3
items:
minimum: 0
maximum: 8
arm,dirty-latency:
description: Cycles of latency for Dirty RAMs. This is a single cell.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 8
arm,filter-ranges:
description: <start length> Starting address and length of window to
filter. Addresses in the filter window are directed to the M1 port. Other
addresses will go to the M0 port.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
arm,io-coherent:
description: indicates that the system is operating in an hardware
I/O coherent mode. Valid only when the arm,pl310-cache compatible
string is used.
type: boolean
interrupts:
# Either a single combined interrupt or up to 9 individual interrupts
minItems: 1
maxItems: 9
cache-id-part:
description: cache id part number to be used if it is not present
on hardware
$ref: /schemas/types.yaml#/definitions/uint32
wt-override:
description: If present then L2 is forced to Write through mode
type: boolean
arm,double-linefill:
description: Override double linefill enable setting. Enable if
non-zero, disable if zero.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,double-linefill-incr:
description: Override double linefill on INCR read. Enable
if non-zero, disable if zero.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,double-linefill-wrap:
description: Override double linefill on WRAP read. Enable
if non-zero, disable if zero.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,prefetch-drop:
description: Override prefetch drop enable setting. Enable if non-zero,
disable if zero.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,prefetch-offset:
description: Override prefetch offset value.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
arm,shared-override:
description: The default behavior of the L220 or PL310 cache
controllers with respect to the shareable attribute is to transform "normal
memory non-cacheable transactions" into "cacheable no allocate" (for reads)
or "write through no write allocate" (for writes).
On systems where this may cause DMA buffer corruption, this property must
be specified to indicate that such transforms are precluded.
type: boolean
arm,parity-enable:
description: enable parity checking on the L2 cache (L220 or PL310).
type: boolean
arm,parity-disable:
description: disable parity checking on the L2 cache (L220 or PL310).
type: boolean
marvell,ecc-enable:
description: enable ECC protection on the L2 cache
type: boolean
arm,outer-sync-disable:
description: disable the outer sync operation on the L2 cache.
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
will randomly hang unless outer sync operations are disabled.
type: boolean
prefetch-data:
description: |
Data prefetch. Value: <0> (forcibly disable), <1>
(forcibly enable), property absent (retain settings set by firmware)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
prefetch-instr:
description: |
Instruction prefetch. Value: <0> (forcibly disable),
<1> (forcibly enable), property absent (retain settings set by
firmware)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,dynamic-clock-gating:
description: |
L2 dynamic clock gating. Value: <0> (forcibly
disable), <1> (forcibly enable), property absent (OS specific behavior,
preferably retain firmware settings)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,standby-mode:
description: L2 standby mode enable. Value <0> (forcibly disable),
<1> (forcibly enable), property absent (OS specific behavior,
preferably retain firmware settings)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,early-bresp-disable:
description: Disable the CA9 optimization Early BRESP (PL310)
type: boolean
arm,full-line-zero-disable:
description: Disable the CA9 optimization Full line of zero
write (PL310)
type: boolean
required:
- compatible
- cache-unified
- reg
additionalProperties: false
examples:
- |
cache-controller@fff12000 {
compatible = "arm,pl310-cache";
reg = <0xfff12000 0x1000>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <2 2 2>;
arm,filter-ranges = <0x80000000 0x8000000>;
cache-unified;
cache-level = <2>;
interrupts = <45>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/marvell,kirkwood-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Feroceon/Kirkwood Cache
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
enum:
- marvell,feroceon-cache
- marvell,kirkwood-cache
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: marvell,kirkwood-cache
then:
required:
- reg
else:
properties:
reg: false
required:
- compatible
additionalProperties: false
examples:
- |
l2-cache@20128 {
compatible = "marvell,kirkwood-cache";
reg = <0x20128 0x4>;
};
linux-7.2.3/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/marvell,tauros2-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Tauros2 Cache
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
const: marvell,tauros2-cache
marvell,tauros2-cache-features:
description: >
Specify the features supported for the tauros2 cache. The features include:
- CACHE_TAUROS2_PREFETCH_ON (1 << 0)
- CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
The definition can be found at arch/arm/include/asm/hardware/cache-tauros2.h
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0x3
required:
- compatible
- marvell,tauros2-cache-features
additionalProperties: false
examples:
- |
l2-cache {
compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0x3>;
};
linux-7.2.3/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Last Level Cache Controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
that can be shared by multiple clients. Clients here are different cores in the
SoC, the idea is to minimize the local caches at the clients and migrate to
common pool of memory. Cache memory is divided into partitions called slices
which are assigned to clients. Clients can query the slice details, activate
and deactivate them.
properties:
compatible:
enum:
- qcom,eliza-llcc
- qcom,glymur-llcc
- qcom,hawi-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
- qcom,sa8775p-llcc
- qcom,sar1130p-llcc
- qcom,sar2130p-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,sdm670-llcc
- qcom,sdm845-llcc
- qcom,shikra-llcc
- qcom,sm6350-llcc
- qcom,sm7150-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
- qcom,sm8750-llcc
- qcom,x1e80100-llcc
reg:
minItems: 1
maxItems: 14
reg-names:
minItems: 1
maxItems: 14
interrupts:
maxItems: 1
memory-region:
maxItems: 1
description: handle to a reserved-memory node used for firmware-populated
SLC/SCT shared memory.
nvmem-cells:
items:
- description: Reference to an nvmem node for multi channel DDR
nvmem-cell-names:
items:
- const: multi-chan-ddr
required:
- compatible
- reg
- reg-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq5424-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
reg-names:
items:
- const: llcc0_base
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC4 base register region
- description: LLCC5 base register region
- description: LLCC6 base register region
- description: LLCC7 base register region
- description: LLCC8 base register region
- description: LLCC9 base register region
- description: LLCC10 base register region
- description: LLCC11 base register region
- description: LLCC broadcast base register region
- description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc4_base
- const: llcc5_base
- const: llcc6_base
- const: llcc7_base
- const: llcc8_base
- const: llcc9_base
- const: llcc10_base
- const: llcc11_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
- if:
properties:
compatible:
contains:
enum:
- qcom,sar1130p-llcc
- qcom,sar2130p-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC broadcast OR register region
- description: LLCC broadcast AND register region
- description: LLCC scratchpad broadcast OR register region
- description: LLCC scratchpad broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
- const: llcc_scratchpad_broadcast_base
- const: llcc_scratchpad_broadcast_and_base
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs615-llcc
- qcom,sc7180-llcc
- qcom,sm6350-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc_broadcast_base
- if:
properties:
compatible:
contains:
enum:
- qcom,sa8775p-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC4 base register region
- description: LLCC5 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc4_base
- const: llcc5_base
- const: llcc_broadcast_base
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-llcc
- qcom,sdm670-llcc
- qcom,shikra-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc_broadcast_base
- if:
properties:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC4 base register region
- description: LLCC5 base register region
- description: LLCC6 base register region
- description: LLCC7 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc4_base
- const: llcc5_base
- const: llcc6_base
- const: llcc7_base
- const: llcc_broadcast_base
- if:
properties:
compatible:
contains:
enum:
- qcom,x1e80100-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC4 base register region
- description: LLCC5 base register region
- description: LLCC6 base register region
- description: LLCC7 base register region
- description: LLCC broadcast base register region
- description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc4_base
- const: llcc5_base
- const: llcc6_base
- const: llcc7_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs8300-llcc
- qcom,sdm845-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc_broadcast_base
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-llcc
- qcom,hawi-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
- qcom,sm8750-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC broadcast OR register region
- description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
- if:
properties:
compatible:
contains:
enum:
- qcom,hawi-llcc
then:
required:
- memory-region
else:
properties:
memory-region: false
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC2 base register region
- description: LLCC broadcast OR register region
- description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc2_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
<0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
<0 0x01300000 0 0x50000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
description:
The SiFive Composable Cache Controller is used to provide access to fast copies
of memory for masters in a Core Complex. The Composable Cache Controller also
acts as directory-based coherency manager.
All the properties in ePAPR/DeviceTree specification applies for this platform.
select:
properties:
compatible:
contains:
enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
required:
- compatible
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
- items:
- enum:
- eswin,eic7700-l3-cache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
- items:
- const: microchip,pic64gx-ccache
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
cache-block-size:
const: 64
cache-level:
enum: [2, 3]
cache-sets:
enum: [1024, 2048, 4096]
cache-size:
enum: [2097152, 4194304]
cache-unified: true
interrupts:
minItems: 3
items:
- description: DirError interrupt
- description: DataError interrupt
- description: DataFail interrupt
- description: DirFail interrupt
reg:
maxItems: 1
next-level-cache: true
memory-region:
maxItems: 1
description: |
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
allOf:
- $ref: /schemas/cache-controller.yaml#
- if:
properties:
compatible:
contains:
enum:
- eswin,eic7700-l3-cache
- sifive,fu740-c000-ccache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
then:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
else:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
- if:
properties:
compatible:
contains:
const: eswin,eic7700-l3-cache
then:
properties:
cache-size:
const: 4194304
else:
properties:
cache-size:
const: 2097152
- if:
properties:
compatible:
contains:
enum:
- sifive,fu740-c000-ccache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
properties:
cache-sets:
const: 2048
- if:
properties:
compatible:
contains:
enum:
- microchip,mpfs-ccache
- sifive,fu540-c000-ccache
then:
properties:
cache-sets:
const: 1024
- if:
properties:
compatible:
contains:
enum:
- eswin,eic7700-l3-cache
then:
properties:
cache-sets:
const: 4096
- if:
properties:
compatible:
contains:
const: sifive,ccache0
then:
properties:
cache-level:
enum: [2, 3]
else:
properties:
cache-level:
const: 2
additionalProperties: false
required:
- compatible
- cache-block-size
- cache-level
- cache-sets
- cache-size
- cache-unified
- interrupts
- reg
examples:
- |
cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
reg = <0x2010000 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <1>,
<2>,
<3>;
next-level-cache = <&L25>;
memory-region = <&l2_lim>;
};
linux-7.2.3/Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier outer cache controller
description: |
UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
controller system. All of them have a level 2 cache controller, and some
have a level 3 cache controller as well.
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
const: socionext,uniphier-system-cache
reg:
description: |
should contain 3 regions: control register, revision register,
operation register, in this order.
maxItems: 3
interrupts:
description: |
Interrupts can be used to notify the completion of cache operations.
The number of interrupts should match to the number of CPU cores.
The specified interrupts correspond to CPU0, CPU1, ... in this order.
minItems: 1
maxItems: 4
cache-unified: true
cache-size: true
cache-sets: true
cache-line-size: true
cache-level:
minimum: 2
maximum: 3
next-level-cache: true
allOf:
- $ref: /schemas/cache-controller.yaml#
additionalProperties: false
required:
- compatible
- reg
- interrupts
- cache-unified
- cache-size
- cache-sets
- cache-line-size
- cache-level
examples:
- |
// System with L2.
cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
cache-unified;
cache-size = <0x140000>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
};
- |
// System with L2 and L3.
// L2 should specify the next level cache by 'next-level-cache'.
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
interrupts = <0 190 4>, <0 191 4>;
cache-unified;
cache-size = <0x200000>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
next-level-cache = <&l3>;
};
l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <0x200000>;
cache-sets = <512>;
cache-line-size = <256>;
cache-level = <3>;
};
linux-7.2.3/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive StarLink Cache Controller
maintainers:
- Joshua Yeong <joshua.yeong@starfivetech.com>
description:
StarFive's StarLink Cache Controller manages the L3 cache shared between
clusters of CPU cores. The cache driver enables RISC-V non-standard cache
management as an alternative to instructions in the RISC-V Zicbom extension.
allOf:
- $ref: /schemas/cache-controller.yaml#
# We need a select here so we don't match all nodes with 'cache'
select:
properties:
compatible:
contains:
enum:
- starfive,jh8100-starlink-cache
required:
- compatible
properties:
compatible:
items:
- const: starfive,jh8100-starlink-cache
- const: cache
reg:
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- reg
- cache-block-size
- cache-level
- cache-sets
- cache-size
- cache-unified
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
cache-controller@15000000 {
compatible = "starfive,jh8100-starlink-cache", "cache";
reg = <0x0 0x15000000 0x0 0x278>;
cache-block-size = <64>;
cache-level = <3>;
cache-sets = <8192>;
cache-size = <0x400000>;
cache-unified;
};
};