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lastdragon
2026-09-06 12:53:21 -06:00
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linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-display-subsystem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX DRM master device
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
The freescale i.MX DRM master device is a virtual device needed to list all
IPU or other display interface nodes that comprise the graphics subsystem.
properties:
compatible:
const: fsl,imx-display-subsystem
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Should contain a list of phandles pointing to camera
sensor interface ports of IPU devices.
required:
- compatible
additionalProperties: false
examples:
- |
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx-lcdc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27
maintainers:
- Sascha Hauer <s.hauer@pengutronix.de>
- Pengutronix Kernel Team <kernel@pengutronix.de>
properties:
compatible:
oneOf:
- enum:
- fsl,imx1-fb
- fsl,imx21-fb
- items:
- enum:
- fsl,imx25-fb
- fsl,imx27-fb
- const: fsl,imx21-fb
- items:
- const: fsl,imx25-lcdc
- const: fsl,imx21-lcdc
clocks:
maxItems: 3
clock-names:
items:
- const: ipg
- const: ahb
- const: per
port:
$ref: /schemas/graph.yaml#/properties/port
display:
$ref: /schemas/types.yaml#/definitions/phandle
interrupts:
maxItems: 1
reg:
maxItems: 1
lcd-supply:
description:
Regulator for LCD supply voltage.
fsl,dmacr:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Override value for DMA Control Register
fsl,lpccr:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Contrast Control Register value.
fsl,lscr1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
LCDC Sharp Configuration Register value.
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx1-lcdc
- fsl,imx21-lcdc
then:
properties:
display: false
fsl,dmacr: false
fsl,lpccr: false
fsl,lscr1: false
required:
- port
else:
properties:
port: false
required:
- display
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
additionalProperties: false
examples:
- |
lcdc@53fbc000 {
compatible = "fsl,imx25-lcdc", "fsl,imx21-lcdc";
reg = <0x53fbc000 0x4000>;
interrupts = <39>;
clocks = <&clks 103>, <&clks 66>, <&clks 49>;
clock-names = "ipg", "ahb", "per";
port {
parallel_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
- |
imxfb: fb@10021000 {
compatible = "fsl,imx21-fb";
interrupts = <61>;
reg = <0x10021000 0x1000>;
display = <&display0>;
clocks = <&clks 103>, <&clks 49>, <&clks 66>;
clock-names = "ipg", "ahb", "per";
};
display0: display0 {
model = "Primeview-PD050VL1";
bits-per-pixel = <16>;
fsl,pcr = <0xf0c88080>; /* non-standard but required */
display-timings {
native-mode = <&timing_disp0>;
timing_disp0: timing0 {
hactive = <640>;
vactive = <480>;
hback-porch = <112>;
hfront-porch = <36>;
hsync-len = <32>;
vback-porch = <33>;
vfront-porch = <33>;
vsync-len = <2>;
clock-frequency = <25000000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Parallel display support
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx-parallel-display
interface-pix-fmt:
$ref: /schemas/types.yaml#/definitions/string
enum:
- rgb24
- rgb565
- bgr666
- lvds666
ddc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle describing the i2c bus handling the display data channel
'#address-cells':
const: 1
'#size-cells':
const: 0
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: input port connected to the IPU display interface
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: output port connected to a panel
port:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
deprecated: true
description: input port connected to the IPU display interface, see port@0
display-timings:
$ref: /schemas/display/panel/display-timings.yaml#
unevaluatedProperties: false
deprecated: true
required:
- compatible
additionalProperties: false
examples:
- |
display {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&panel_in>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx53-tve.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX53 Television Encoder (TVE)
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
The Television Encoder (TVE) is a hardware block in the i.MX53 SoC that
converts digital video data into analog TV signals (NTSC/PAL).
properties:
compatible:
const: fsl,imx53-tve
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: TVE gate clock
- description: Display interface selector clock
clock-names:
items:
- const: tve
- const: di_sel
ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the I2C bus used for DDC (Display Data Channel) communication
to read EDID information from the connected display.
dac-supply:
description:
Regulator supply for the TVE DAC (Digital-to-Analog Converter).
fsl,tve-mode:
$ref: /schemas/types.yaml#/definitions/string
description:
TVE output mode selection.
enum:
- ntsc
- pal
- vga
fsl,hsync-pin:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Pin number for horizontal sync signal in VGA mode.
minimum: 0
maximum: 8
fsl,vsync-pin:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Pin number for vertical sync signal in VGA mode.
minimum: 0
maximum: 8
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Port node with one endpoint connected to the IPU display interface.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- fsl,tve-mode
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
tve@63ff0000 {
compatible = "fsl,imx53-tve";
reg = <0x63ff0000 0x1000>;
interrupts = <92>;
clocks = <&clks IMX5_CLK_TVE_GATE>,
<&clks IMX5_CLK_IPU_DI1_SEL>;
clock-names = "tve", "di_sel";
fsl,tve-mode = "vga";
port {
endpoint {
remote-endpoint = <&ipu_di1_tve>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX6 DWC HDMI TX Encoder
maintainers:
- Philipp Zabel <p.zabel@pengutronix.de>
description: |
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with a companion PHY IP.
allOf:
- $ref: ../bridge/synopsys,dw-hdmi.yaml#
properties:
compatible:
enum:
- fsl,imx6dl-hdmi
- fsl,imx6q-hdmi
reg-io-width:
const: 1
clocks:
maxItems: 2
clock-names:
maxItems: 2
gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the iomuxc-gpr region containing the HDMI multiplexer control
register.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
This device has four video ports, corresponding to the four inputs of the
HDMI multiplexer. Each port shall have a single endpoint.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: First input of the HDMI multiplexer
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Second input of the HDMI multiplexer
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: Third input of the HDMI multiplexer
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: Fourth input of the HDMI multiplexer
anyOf:
- required:
- port@0
- required:
- port@1
- required:
- port@2
- required:
- port@3
required:
- compatible
- reg
- clocks
- clock-names
- gpr
- interrupts
- ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
hdmi: hdmi@120000 {
reg = <0x00120000 0x9000>;
interrupts = <0 115 0x04>;
gpr = <&gpr>;
clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
<&clks IMX6QDL_CLK_HDMI_ISFR>;
clock-names = "iahb", "isfr";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_hdmi>;
};
};
port@1 {
reg = <1>;
hdmi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_hdmi>;
};
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX IPUv3
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx51-ipu
- fsl,imx53-ipu
- fsl,imx6q-ipu
- items:
- const: fsl,imx6qp-ipu
- const: fsl,imx6q-ipu
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
clocks:
maxItems: 3
clock-names:
items:
- const: bus
- const: di0
- const: di1
resets:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
fsl,prg:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to prg node associated with this IPU instance
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI0
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI1
port@2:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: DI0
port@3:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: DI1
required:
- compatible
- reg
- interrupts
- resets
additionalProperties: false
examples:
- |
display-controller@18000000 {
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11 10>;
resets = <&src 2>;
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&display_in>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale LVDS Display Bridge (ldb)
description:
The LVDS Display Bridge device tree node contains up to two lvds-channel
nodes describing each of the two LVDS encoder channels of the bridge.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx53-ldb
- items:
- enum:
- fsl,imx6q-ldb
- const: fsl,imx53-ldb
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle points to the iomuxc-gpr region containing the LVDS
control register.
clocks:
minItems: 6
maxItems: 8
clock-names:
oneOf:
- items:
- const: di0_pll
- const: di1_pll
- const: di0_sel
- const: di1_sel
- const: di0
- const: di1
- items:
- const: di0_pll
- const: di1_pll
- const: di0_sel
- const: di1_sel
- const: di2_sel
- const: di3_sel
- const: di0
- const: di1
fsl,dual-channel:
$ref: /schemas/types.yaml#/definitions/flag
description:
if it exists, only LVDS channel 0 should
be configured - one input will be distributed on both outputs in dual
channel mode
patternProperties:
'^lvds-channel@[0-1]$':
type: object
description:
Each LVDS Channel has to contain either an of graph link to a panel device node
or a display-timings node that describes the video timings for the connected
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
properties:
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
display-timings:
$ref: /schemas/display/panel/display-timings.yaml#
fsl,data-mapping:
enum:
- spwg
- jeida
fsl,data-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: should be <18> or <24>
enum:
- 18
- 24
fsl,panel:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to lcd panel
patternProperties:
'^port@[0-4]$':
$ref: /schemas/graph.yaml#/properties/port
description:
On i.MX5, the internal two-input-multiplexer is used. Due to hardware
limitations, only one input port (port@[0,1]) can be used for each channel
(lvds-channel@[0,1], respectively).
On i.MX6, there should be four input ports (port@[0-3]) that correspond
to the four LVDS multiplexer inputs.
A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
to a panel input port. Optionally, the output port can be left out if
display-timings are used instead.
additionalProperties: false
required:
- compatible
- gpr
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
ldb@53fa8008 {
compatible = "fsl,imx53-ldb";
reg = <0x53fa8008 0x4>;
#address-cells = <1>;
#size-cells = <0>;
gpr = <&gpr>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
<&clks IMX5_CLK_LDB_DI1_SEL>,
<&clks IMX5_CLK_IPU_DI0_SEL>,
<&clks IMX5_CLK_IPU_DI1_SEL>,
<&clks IMX5_CLK_LDB_DI0_GATE>,
<&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
/* Using an of-graph endpoint link to connect the panel */
lvds-channel@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&panel_in>;
};
};
};
/* Using display-timings and fsl,data-mapping/width instead */
lvds-channel@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {/* ... */
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&ipu_di1_lvds1>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-pre.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX PRE (Prefetch Resolve Engine)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx6qp-pre
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: axi
fsl,iram:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle pointing to the mmio-sram device node, that should be
used for the PRE SRAM double buffer.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE0>;
clock-names = "axi";
fsl,iram = <&ocram2>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-prg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX PRG (Prefetch Resolve Gasket)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx6qp-prg
reg:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: ipg
- const: axi
fsl,pres:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
phandles to the PRE units attached to this PRG, with the fixed
PRE as the first entry and the muxable PREs following.
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
prg@21cc000 {
compatible = "fsl,imx6qp-prg";
reg = <0x021cc000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pai.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pai.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8MP HDMI Parallel Audio Interface
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
description:
The HDMI TX Parallel Audio Interface (HTX_PAI) is a bridge between the
Audio Subsystem to the HDMI TX Controller.
properties:
compatible:
const: fsl,imx8mp-hdmi-pai
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: apb
power-domains:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description: Output to the HDMI TX controller.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
audio-bridge@32fc4800 {
compatible = "fsl,imx8mp-hdmi-pai";
reg = <0x32fc4800 0x800>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <14>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>;
clock-names = "apb";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>;
port {
pai_to_hdmi_tx: endpoint {
remote-endpoint = <&hdmi_tx_from_pai>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8MP HDMI Parallel Video Interface
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
description:
The HDMI parallel video interface is a timing and sync generator block in the
i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
properties:
compatible:
const: fsl,imx8mp-hdmi-pvi
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input from the LCDIF controller.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output to the HDMI TX controller.
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- power-domains
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/imx8mp-power.h>
display-bridge@32fc4000 {
compatible = "fsl,imx8mp-hdmi-pvi";
reg = <0x32fc4000 0x44>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pvi_from_lcdif3: endpoint {
remote-endpoint = <&lcdif3_to_pvi>;
};
};
port@1 {
reg = <1>;
pvi_to_hdmi_tx: endpoint {
remote-endpoint = <&hdmi_tx_from_pvi>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller AXI Performance Counter
description: |
Performance counters are provided to allow measurement of average bandwidth
and latency during operation. The following features are supported:
* Manual and timer controlled measurement mode.
* Measurement counters:
- GLOBAL_COUNTER for overall measurement time
- BUSY_COUNTER for number of data bus busy cycles
- DATA_COUNTER for number of data transfer cycles
- TRANSFER_COUNTER for number of transfers
- ADDRBUSY_COUNTER for number of address bus busy cycles
- LATENCY_COUNTER for average latency
* Counter overflow detection.
* Outstanding Transfer Counters (OTC) which are used for latency measurement
have to run immediately after reset, but can be disabled by software when
there is no need for latency measurement.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-axi-performance-counter
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
pmu@5618f000 {
compatible = "fsl,imx8qxp-dc-axi-performance-counter";
reg = <0x5618f000 0x90>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blit-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Blit Engine
description: |
A blit operation (block based image transfer) reads up to 3 source images
from memory and computes one destination image from it, which is written
back to memory. The following basic operations are supported:
* Buffer Fill
Fills a buffer with constant color
* Buffer Copy
Copies one source to a destination buffer.
* Image Blend
Combines two source images by a blending equation and writes result to
destination (which can be one of the sources).
* Image Rop2/3
Combines up to three source images by a logical equation (raster operation)
and writes result to destination (which can be one of the sources).
* Image Flip
Mirrors the source image in horizontal and/or vertical direction.
* Format Convert
Convert between the supported color and buffer formats.
* Color Transform
Modify colors by linear or non-linear transformations.
* Image Scale
Changes size of the source image.
* Image Rotate
Rotates the source image by any angle.
* Image Filter
Performs an FIR filter operation on the source image.
* Image Warp
Performs a re-sampling of the source image with any pattern. The sample
point positions are read from a compressed coordinate buffer.
* Buffer Pack
Writes an image with color components stored in up to three different
buffers (planar formats) into a single buffer (packed format).
* Chroma Resample
Converts between different YUV formats that differ in chroma sampling rate
(4:4:4, 4:2:2, 4:2:0).
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-blit-engine
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^blitblend@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-blitblend
"^clut@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-clut
"^fetchdecode@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchdecode
"^fetcheco@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetcheco
"^fetchwarp@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchwarp
"^filter@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-filter
"^hscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-hscaler
"^matrix@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
"^rop@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-rop
"^store@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-store
"^vscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-vscaler
required:
- compatible
- reg
- reg-names
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
blit-engine@56180820 {
compatible = "fsl,imx8qxp-dc-blit-engine";
reg = <0x56180820 0x13c>, <0x56181000 0x3400>;
reg-names = "pec", "cfg";
#address-cells = <1>;
#size-cells = <1>;
ranges;
fetchdecode@56180820 {
compatible = "fsl,imx8qxp-dc-fetchdecode";
reg = <0x56180820 0x10>, <0x56181000 0x404>;
reg-names = "pec", "cfg";
};
store@56180940 {
compatible = "fsl,imx8qxp-dc-store";
reg = <0x56180940 0x1c>, <0x56184000 0x5c>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <0>, <1>, <2>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blitblend.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blitblend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Blit Blend Unit
description:
Combines two input frames to a single output frame, all frames having the
same dimension.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-blitblend
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
blitblend@56180920 {
compatible = "fsl,imx8qxp-dc-blitblend";
reg = <0x56180920 0x10>, <0x56183c00 0x3c>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-clut.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-clut.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Color Lookup Table
description: |
The unit implements 3 look-up tables with 256 x 10 bit entries each. These
can be used for different kinds of applications. From 10-bit input values
only upper 8 bits are used.
The unit supports color lookup, index lookup, dithering and alpha masking.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-clut
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
clut@56180880 {
compatible = "fsl,imx8qxp-dc-clut";
reg = <0x56180880 0x10>, <0x56182400 0x404>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Command Sequencer
description: |
The Command Sequencer is designed to autonomously process command lists.
By that it can load setups into the DC configuration and synchronize to
hardware events. This releases a system's CPU from workload, because it
does not need to wait for certain events. Also it simplifies SW architecture,
because no interrupt handlers are required. Setups are read via AXI bus,
while write access to configuration registers occurs directly via an internal
bus. This saves bandwidth for the AXI interconnect and improves the system
architecture in terms of safety aspects.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-command-sequencer
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 5
interrupt-names:
items:
- const: error
- const: sw0
- const: sw1
- const: sw2
- const: sw3
sram:
maxItems: 1
description: phandle pointing to the mmio-sram device node
required:
- compatible
- reg
- clocks
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
command-sequencer@56180400 {
compatible = "fsl,imx8qxp-dc-command-sequencer";
reg = <0x56180400 0x1a4>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
interrupt-parent = <&dc0_intc>;
interrupts = <36>, <37>, <38>, <39>, <40>;
interrupt-names = "error", "sw0", "sw1", "sw2", "sw3";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-constframe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Constant Frame
description: |
The Constant Frame unit is used instead of a Fetch unit where generation of
constant color frames only is sufficient. This is the case for the background
planes of content and safety streams in a Display Controller.
The color can be setup to any RGBA value.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-constframe
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
constframe@56180960 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x56180960 0xc>, <0x56184400 0x20>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Display Engine
description:
All Processing Units that operate in a display clock domain. Pixel pipeline
is driven by a video timing and cannot be stalled. Implements all display
specific processing.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-display-engine
reg:
maxItems: 2
reg-names:
items:
- const: top
- const: cfg
resets:
maxItems: 1
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: framecomplete
- const: seqcomplete
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^dither@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-dither
"^framegen@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-framegen
"^gammacor@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-gammacor
"^matrix@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
"^signature@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-signature
"^tcon@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-tcon
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
display-engine@5618b400 {
compatible = "fsl,imx8qxp-dc-display-engine";
reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
reg-names = "top", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <15>, <16>, <17>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
framegen@5618b800 {
compatible = "fsl,imx8qxp-dc-framegen";
reg = <0x5618b800 0x98>;
clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
interrupt-parent = <&dc0_intc>;
interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
interrupt-names = "int0", "int1", "int2", "int3",
"primsync_on", "primsync_off",
"secsync_on", "secsync_off";
};
tcon@5618c800 {
compatible = "fsl,imx8qxp-dc-tcon";
reg = <0x5618c800 0x588>;
port {
dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-dither.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-dither.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Dither Unit
description: |
The unit can increase the physical color resolution of a display from 5, 6, 7
or 8 bits per RGB channel to a virtual resolution of 10 bits. The physical
resolution can be set individually for each channel.
The resolution is increased by mixing the two physical colors that are nearest
to the virtual color code in a variable ratio either by time (temporal
dithering) or by position (spatial dithering).
An optimized algorithm for temporal dithering minimizes noise artifacts on the
output image.
The dither operation can be individually enabled or disabled for each pixel
using the alpha input bit.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-dither
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
dither@5618c400 {
compatible = "fsl,imx8qxp-dc-dither";
reg = <0x5618c400 0x14>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller External Destination Interface
description: |
The External Destination unit is the interface between the internal pixel
processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha,
and a Display Engine.
It comprises the following built-in Gamma apply function.
+------X-----------------------+
| | ExtDst Unit |
| V |
| +-------+ |
| | Gamma | |
| +-------+ |
| | |
| V +
+------X-----------------------+
The output format is 24-bit RGB plus 1-bit Alpha. Conversion from 10 to 8
bits is done by LSBit truncation. Alpha output bit is 1 for input 255, 0
otherwise.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-extdst
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: framecomplete
- const: seqcomplete
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
extdst@56180980 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180980 0x1c>, <0x56184800 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <3>, <4>, <5>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchunit.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Fetch Unit
description: |
The Fetch Unit is the interface between the AXI bus for source buffer access
and the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit
Alpha.
It is used to generate foreground planes in Display Controllers and source
planes in Blit Engines, and comprises the following built-in functions to
convert a wide range of frame buffer types.
+---------X-----------------------------------------+
| | Fetch Unit |
| V |
| +---------+ |
| | | |
| | Decode | Decompression [Decode] |
| | | |
| +---------+ |
| | |
| V |
| +---------+ |
| | Clip & | Clip Window [All] |
| | Overlay | Plane composition [Layer, Warp] |
| | | |
| +---------+ |
| | |
| V |
| +---------+ |
| | Re- | Flip/Rotate/Repl./Drop [All] |
X--> | sample | Perspective/Affine warping [Persp] |
| | | | Arbitrary warping [Warp, Persp] |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | |
| | | Palette | Color Palette [Layer, Decode] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | Extract | Raw to RGBA/YUV [All] |
| | | & | Bit width expansion [All] |
| | | Expand | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | Planar to packed |
| |->| Combine | [Decode, Warp, Persp] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | YUV422 to YUV444 |
| | | Chroma | [Decode, Persp] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | YUV to RGB |
| | | Color | [Warp, Persp, Decode, Layer] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | Gamma removal |
| | | Gamma | [Warp, Persp, Decode, Layer] |
| | | | |
| | +---------+ |
| | | |
| | V |
| | +---------+ |
| | | | Alpla multiply, RGB pre-multiply |
| ->| Multiply| [Warp, Persp, Decode, Layer] |
| | | |
| --------- |
| | |
| V |
| +---------+ |
| | | Bilinear filter |
| | Filter | [Warp, Persp] |
| | | |
| +---------+ |
| | |
| V |
+---------X-----------------------------------------+
Note that different derivatives of the Fetch Unit exist. Each implements a
specific subset only of the pipeline stages shown above. Restrictions for the
units are specified in [square brackets].
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
enum:
- fsl,imx8qxp-dc-fetchdecode
- fsl,imx8qxp-dc-fetcheco
- fsl,imx8qxp-dc-fetchlayer
- fsl,imx8qxp-dc-fetchwarp
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
fsl,prg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Optional Prefetch Resolve Gasket associated with the Fetch Unit.
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
fetchlayer@56180ac0 {
compatible = "fsl,imx8qxp-dc-fetchlayer";
reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-filter.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-filter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Filter Unit
description: |
5x5 FIR filter with 25 programmable coefficients.
Typical applications are image blurring, sharpening or support for edge
detection algorithms.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-filter
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
filter@56180900 {
compatible = "fsl,imx8qxp-dc-filter";
reg = <0x56180900 0x10>, <0x56183800 0x30>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-framegen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Frame Generator
description:
The Frame Generator (FrameGen) module generates a programmable video timing
and optionally allows to synchronize the generated video timing to external
synchronization signals.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-framegen
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 8
interrupt-names:
items:
- const: int0
- const: int1
- const: int2
- const: int3
- const: primsync_on
- const: primsync_off
- const: secsync_on
- const: secsync_off
required:
- compatible
- reg
- clocks
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
framegen@5618b800 {
compatible = "fsl,imx8qxp-dc-framegen";
reg = <0x5618b800 0x98>;
clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
interrupt-parent = <&dc0_intc>;
interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
interrupt-names = "int0", "int1", "int2", "int3",
"primsync_on", "primsync_off",
"secsync_on", "secsync_off";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-gammacor.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-gammacor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Gamma Correction Unit
description: The unit supports non-linear color transformation.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-gammacor
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
gammacor@5618c000 {
compatible = "fsl,imx8qxp-dc-gammacor";
reg = <0x5618c000 0x20>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-layerblend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Layer Blend Unit
description: Combines two input frames to a single output frame.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-layerblend
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
layerblend@56180ba0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-matrix.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-matrix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Color Matrix
description:
The unit supports linear color transformation, alpha pre-multiply and
alpha masking.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
reg:
minItems: 1
maxItems: 2
reg-names:
oneOf:
- const: cfg # matrix in display engine
- items: # matrix in pixel engine
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
matrix@5618bc00 {
compatible = "fsl,imx8qxp-dc-matrix";
reg = <0x5618bc00 0x3c>;
reg-names = "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Pixel Engine
description:
All Processing Units that operate in the AXI bus clock domain. Pixel
pipelines have the ability to stall when a destination is busy. Implements
all communication to memory resources and most of the image processing
functions. Interconnection of Processing Units is re-configurable.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-pixel-engine
reg:
maxItems: 1
clocks:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^blit-engine@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-blit-engine
"^constframe@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-constframe
"^extdst@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-extdst
"^fetchdecode@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchdecode
"^fetcheco@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetcheco
"^fetchlayer@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchlayer
"^fetchwarp@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-fetchwarp
"^hscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-hscaler
"^layerblend@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-layerblend
"^matrix@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-matrix
"^safety@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-safety
"^vscaler@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-vscaler
required:
- compatible
- reg
- clocks
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
pixel-engine@56180800 {
compatible = "fsl,imx8qxp-dc-pixel-engine";
reg = <0x56180800 0xac00>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
constframe@56180960 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x56180960 0xc>, <0x56184400 0x20>;
reg-names = "pec", "cfg";
};
extdst@56180980 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180980 0x1c>, <0x56184800 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <3>, <4>, <5>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
constframe@561809a0 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x561809a0 0xc>, <0x56184c00 0x20>;
reg-names = "pec", "cfg";
};
extdst@561809c0 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x561809c0 0x1c>, <0x56185000 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <6>, <7>, <8>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
constframe@561809e0 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x561809e0 0xc>, <0x56185400 0x20>;
reg-names = "pec", "cfg";
};
extdst@56180a00 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180a00 0x1c>, <0x56185800 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <9>, <10>, <11>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
constframe@56180a20 {
compatible = "fsl,imx8qxp-dc-constframe";
reg = <0x56180a20 0xc>, <0x56185c00 0x20>;
reg-names = "pec", "cfg";
};
extdst@56180a40 {
compatible = "fsl,imx8qxp-dc-extdst";
reg = <0x56180a40 0x1c>, <0x56186000 0x28>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <12>, <13>, <14>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
fetchwarp@56180a60 {
compatible = "fsl,imx8qxp-dc-fetchwarp";
reg = <0x56180a60 0x10>, <0x56186400 0x190>;
reg-names = "pec", "cfg";
};
fetchlayer@56180ac0 {
compatible = "fsl,imx8qxp-dc-fetchlayer";
reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
reg-names = "pec", "cfg";
};
layerblend@56180ba0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
reg-names = "pec", "cfg";
};
layerblend@56180bc0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180bc0 0x10>, <0x5618a800 0x20>;
reg-names = "pec", "cfg";
};
layerblend@56180be0 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180be0 0x10>, <0x5618ac00 0x20>;
reg-names = "pec", "cfg";
};
layerblend@56180c00 {
compatible = "fsl,imx8qxp-dc-layerblend";
reg = <0x56180c00 0x10>, <0x5618b000 0x20>;
reg-names = "pec", "cfg";
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-rop.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-rop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Raster Operation Unit
description: |
The unit can combine up to three input frames to a single output frame, all
having the same dimension.
The unit supports logic operations, arithmetic operations and packing.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-rop
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
rop@56180860 {
compatible = "fsl,imx8qxp-dc-rop";
reg = <0x56180860 0x10>, <0x56182000 0x20>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-safety.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-safety.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Safety Unit
description:
The unit allows corresponding processing units to be configured in a path
leading to multiple endpoints.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-safety
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
safety@56180800 {
compatible = "fsl,imx8qxp-dc-safety";
reg = <0x56180800 0x1c>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Scaling Engine
description: |
The unit can change the dimension of the input frame by nearest or linear
re-sampling with 1/32 sub pixel precision.
Internally it consist of two independent blocks for horizontal and vertical
scaling. The sequence of both operations is arbitrary.
Any frame dimensions between 1 and 16384 pixels in width and height are
supported, except that the vertical scaler has a frame width maximum
depending of the system's functional limitations.
In general all scale factors are supported inside the supported frame
dimensions. In range of scale factors 1/16..16 the filtered output colors
are LSBit precise (e.g. DC ripple free).
+-----------+
| Line |
| Buffer |
+-----------+
^
|
V
|\ +-----------+
------+ | | |
| | +-->| Vertical |----
| ----+ | | Scaler | |
| | |/ +-----------+ |
| | |
| | |
| | | |\
| ------------- -------------+-----+ |
Input --+ X | +--> Output
| ------------- -------------+-----+ |
| | | |/
| | |
| | |\ +-----------+ |
| ----+ | | | |
| | +-->| Horizontal|----
------+ | | Scaler |
|/ +-----------+
The unit supports downscaling, upscaling, sub pixel translation and bob
de-interlacing.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
enum:
- fsl,imx8qxp-dc-hscaler
- fsl,imx8qxp-dc-vscaler
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
hscaler@561808c0 {
compatible = "fsl,imx8qxp-dc-hscaler";
reg = <0x561808c0 0x10>, <0x56183000 0x18>;
reg-names = "pec", "cfg";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-signature.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-signature.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Signature Unit
description: |
In order to control the correctness of display output, signature values can
be computed for each frame and compared against reference values. In case of
a mismatch (signature violation) a HW event can be triggered, for example a
SW interrupt.
This unit supports signature computation, reference check, evaluation windows,
alpha masking and panic modes.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-signature
reg:
maxItems: 1
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: valid
- const: error
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
signature@5618d000 {
compatible = "fsl,imx8qxp-dc-signature";
reg = <0x5618d000 0x140>;
interrupt-parent = <&dc0_intc>;
interrupts = <22>, <23>, <24>;
interrupt-names = "shdload", "valid", "error";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-store.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-store.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Store Unit
description: |
The Store unit is the interface between the internal pixel processing
pipeline, which is 30-bit RGB plus 8-bit Alpha, and the AXI bus for
destination buffer access. It is used for the destination of Blit Engines.
It comprises a set of built-in functions to generate a wide range of buffer
formats. Note, that these are exactly inverse to corresponding functions in
the Fetch Unit.
+------X-------------------------+
| | Store Unit |
| V |
| +-------+ |
| | Gamma | Gamma apply |
| +-------+ |
| | |
| V |
| +-------+ |
| | Color | RGB to YUV |
| +-------+ |
| | |
| V |
| +-------+ |
| | Chroma| YUV444 to 422 |
| +-------+ |
| | |
| V |
| +-------+ |
| | Reduce| Bit width reduction |
| | | dithering |
| +-------+ |
| | |
| V |
| +-------+ |
| | Pack | RGBA/YUV to RAW |
| | Encode| or Compression |
| +-------+ |
| | |
| V |
+------X-------------------------+
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-store
reg:
maxItems: 2
reg-names:
items:
- const: pec
- const: cfg
interrupts:
maxItems: 3
interrupt-names:
items:
- const: shdload
- const: framecomplete
- const: seqcomplete
fsl,lts:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Optional Linear Tile Store associated with the Store Unit.
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
store@56180940 {
compatible = "fsl,imx8qxp-dc-store";
reg = <0x56180940 0x1c>, <0x56184000 0x5c>;
reg-names = "pec", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <0>, <1>, <2>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-tcon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller Timing Controller
description:
The TCon can generate a wide range of customized synchronization signals and
does the mapping of the color bits to the output.
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc-tcon
reg:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description: video output
required:
- compatible
- reg
- port
additionalProperties: false
examples:
- |
tcon@5618c800 {
compatible = "fsl,imx8qxp-dc-tcon";
reg = <0x5618c800 0x588>;
port {
dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Display Controller
description: |
The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
components that include a blit engine for 2D graphics accelerations, display
controller for display output processing, as well as a command sequencer.
Display buffers Source buffers
(AXI read master) (AXI read master)
| .......... | | | |
+---------------------------+------------+------------------+-+-+------+
| Display Controller (DC) | .......... | | | | |
| | | | | | |
| @@@@@@@@@@@ +----------+------------+------------+ | | | |
A | | Command | | V V | | | | |
X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
I | | (AXI CLK) | | | | | @@@@@@@@@@ |
| @@@@@@@@@@@ | | Pixel Engine | | | | |
| | | | (AXI CLK) | | | | |
| V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | |
A | *********** | | | | | | | Blit | |
H <-+->| Configure | | V V V V | | Engine | |
B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| |
| *********** | | Display | | Display | | | | |
| | | Engine | | Engine | | | | |
| | | (Disp CLK)| | (Disp CLK)| | | | |
| @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ |
I | | Common | | | | | | |
R <-+--| Control | | | Display | | | |
Q | | (AXI CLK) | | | Controller | | | |
| @@@@@@@@@@@ +------------------------------------+ | |
| | | ^ | |
+--------------------------+----------------+-------+---------+--------+
^ | | | |
| V V | V
Clocks & Resets Display Display Panic Destination
Output0 Output1 Control buffer
(AXI write master)
maintainers:
- Liu Ying <victor.liu@nxp.com>
properties:
compatible:
const: fsl,imx8qxp-dc
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 2
reset-names:
items:
- const: axi
- const: cfg
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^command-sequencer@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-command-sequencer
"^display-engine@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-display-engine
"^interrupt-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-intc
"^pixel-engine@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-pixel-engine
"^pmu@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: fsl,imx8qxp-dc-axi-performance-counter
required:
- compatible
- reg
- clocks
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
display-controller@56180000 {
compatible = "fsl,imx8qxp-dc";
reg = <0x56180000 0x40000>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_4>;
power-domains = <&pd IMX_SC_R_DC_0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller@56180040 {
compatible = "fsl,imx8qxp-dc-intc";
reg = <0x56180040 0x60>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
interrupt-controller;
interrupt-parent = <&dc0_irqsteer>;
#interrupt-cells = <1>;
interrupts = <448>, <449>, <450>, <64>,
<65>, <66>, <67>, <68>,
<69>, <70>, <193>, <194>,
<195>, <196>, <197>, <72>,
<73>, <74>, <75>, <76>,
<77>, <78>, <79>, <80>,
<81>, <199>, <200>, <201>,
<202>, <203>, <204>, <205>,
<206>, <207>, <208>, <5>,
<0>, <1>, <2>, <3>,
<4>, <82>, <83>, <84>,
<85>, <209>, <210>, <211>,
<212>;
interrupt-names = "store9_shdload",
"store9_framecomplete",
"store9_seqcomplete",
"extdst0_shdload",
"extdst0_framecomplete",
"extdst0_seqcomplete",
"extdst4_shdload",
"extdst4_framecomplete",
"extdst4_seqcomplete",
"extdst1_shdload",
"extdst1_framecomplete",
"extdst1_seqcomplete",
"extdst5_shdload",
"extdst5_framecomplete",
"extdst5_seqcomplete",
"disengcfg_shdload0",
"disengcfg_framecomplete0",
"disengcfg_seqcomplete0",
"framegen0_int0",
"framegen0_int1",
"framegen0_int2",
"framegen0_int3",
"sig0_shdload",
"sig0_valid",
"sig0_error",
"disengcfg_shdload1",
"disengcfg_framecomplete1",
"disengcfg_seqcomplete1",
"framegen1_int0",
"framegen1_int1",
"framegen1_int2",
"framegen1_int3",
"sig1_shdload",
"sig1_valid",
"sig1_error",
"reserved",
"cmdseq_error",
"comctrl_sw0",
"comctrl_sw1",
"comctrl_sw2",
"comctrl_sw3",
"framegen0_primsync_on",
"framegen0_primsync_off",
"framegen0_secsync_on",
"framegen0_secsync_off",
"framegen1_primsync_on",
"framegen1_primsync_off",
"framegen1_secsync_on",
"framegen1_secsync_off";
};
pixel-engine@56180800 {
compatible = "fsl,imx8qxp-dc-pixel-engine";
reg = <0x56180800 0xac00>;
clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
display-engine@5618b400 {
compatible = "fsl,imx8qxp-dc-display-engine";
reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
reg-names = "top", "cfg";
interrupt-parent = <&dc0_intc>;
interrupts = <15>, <16>, <17>;
interrupt-names = "shdload", "framecomplete", "seqcomplete";
power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
+107
View File
@@ -0,0 +1,107 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: iMX8MQ Display Controller Subsystem (DCSS)
maintainers:
- Laurentiu Palcu <laurentiu.palcu@nxp.com>
description:
The DCSS (display controller sub system) is used to source up to three
display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
image processing capabilities are included to provide a solution capable of
driving next generation high dynamic range displays.
properties:
compatible:
const: nxp,imx8mq-dcss
reg:
items:
- description: DCSS base address and size, up to IRQ steer start
- description: DCSS BLKCTL base address and size
interrupts:
items:
- description: Context loader completion and error interrupt
- description: DTG interrupt used to signal context loader trigger time
- description: DTG interrupt for Vblank
interrupt-names:
items:
- const: ctxld
- const: ctxld_kick
- const: vblank
clocks:
items:
- description: Display APB clock for all peripheral PIO access interfaces
- description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
- description: RTRAM clock
- description: Pixel clock, can be driven either by HDMI phy clock or MIPI
- description: DTRC clock, needed by video decompressor
clock-names:
items:
- const: apb
- const: axi
- const: rtrm
- const: pix
- const: dtrc
assigned-clocks:
items:
- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
- description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
IMX8MQ_VIDEO_PLL1_REF_SEL
assigned-clock-parents:
items:
- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
- description: Phandle and clock specifier of IMX8MQ_CLK_27M
assigned-clock-rates:
items:
- description: Must be 800 MHz
- description: Must be 400 MHz
port:
$ref: /schemas/graph.yaml#/properties/port
description:
A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
dcss: display-controller@32e00000 {
compatible = "nxp,imx8mq-dcss";
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
interrupts = <6>, <8>, <9>;
interrupt-names = "ctxld", "ctxld_kick", "vblank";
interrupt-parent = <&irqsteer>;
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
<&clk IMX8MQ_CLK_DISP_DTRC>;
clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_27M>;
assigned-clock-rates = <800000000>,
<400000000>;
port {
dcss_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};