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lastdragon
2026-09-06 12:53:21 -06:00
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linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra MIPI pad calibration controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^mipi@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra114-mipi
- nvidia,tegra124-mipi
- nvidia,tegra132-mipi
- nvidia,tegra210-mipi
- nvidia,tegra186-mipi
reg:
maxItems: 1
clocks:
items:
- description: module clock
clock-names:
items:
- const: mipi-cal
power-domains:
maxItems: 1
"#nvidia,mipi-calibrate-cells":
description: The number of cells in a MIPI calibration specifier.
Should be 1. The single cell specifies a bitmask of the pads that
need to be calibrated for a given device.
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
additionalProperties: false
required:
- compatible
- reg
- clocks
- "#nvidia,mipi-calibrate-cells"
examples:
- |
#include <dt-bindings/clock/tegra114-car.h>
mipi@700e3000 {
compatible = "nvidia,tegra114-mipi";
reg = <0x700e3000 0x100>;
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
#nvidia,mipi-calibrate-cells = <1>;
};
dsia: dsi@54300000 {
compatible = "nvidia,tegra114-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_DSIA>,
<&tegra_car TEGRA114_CLK_DSIALP>,
<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Security co-processor
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
- Thierry Reding <thierry.reding@gmail.com>
description: Tegra Security co-processor, an embedded security processor used
mainly to manage the HDCP encryption and keys on the HDMI link.
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra114-tsec
- nvidia,tegra124-tsec
- nvidia,tegra210-tsec
- items:
- const: nvidia,tegra132-tsec
- const: nvidia,tegra124-tsec
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
iommus:
maxItems: 1
operating-points-v2: true
power-domains:
maxItems: 1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- resets
examples:
- |
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
tsec@54500000 {
compatible = "nvidia,tegra114-tsec";
reg = <0x54500000 0x00040000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
resets = <&tegra_car TEGRA114_CLK_TSEC>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra DisplayPort AUX Interface
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
pins which can be assigned to either the DPAUX channel or to an I2C
controller.
When configured for DisplayPort AUX operation, the DPAUX controller
can also be used to communicate with a DisplayPort device using the
AUX channel.
properties:
$nodename:
pattern: "^dpaux@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-dpaux
- nvidia,tegra210-dpaux
- nvidia,tegra186-dpaux
- nvidia,tegra194-dpaux
- items:
- const: nvidia,tegra132-dpaux
- const: nvidia,tegra124-dpaux
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: clock input for the DPAUX hardware
- description: reference clock
clock-names:
items:
- const: dpaux
- const: parent
resets:
items:
- description: module reset
reset-names:
items:
- const: dpaux
power-domains:
maxItems: 1
i2c-bus:
description: Subnode where I2C slave devices are listed. This
subnode must be always present. If there are no I2C slave
devices, an empty node should be added. See ../../i2c/i2c.yaml
for more information.
type: object
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
vdd-supply:
description: phandle of a supply that powers the DisplayPort
link
patternProperties:
"^pinmux-[a-z0-9]+$":
description:
Since only three configurations are possible, only three child
nodes are needed to describe the pin mux'ing options for the
DPAUX pads. Furthermore, given that the pad functions are only
applicable to a single set of pads, the child nodes only need
to describe the pad group the functions are being applied to
rather than the individual pads.
type: object
properties:
groups:
const: dpaux-io
function:
enum:
- aux
- i2c
- off
additionalProperties: false
required:
- groups
- function
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dpaux: dpaux@545c0000 {
compatible = "nvidia,tegra210-dpaux";
reg = <0x545c0000 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "dpaux", "parent";
resets = <&tegra_car 181>;
reset-names = "dpaux";
power-domains = <&pd_sor>;
state_dpaux_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra SOR Output Encoder
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
and DP outputs.
properties:
$nodename:
pattern: "^sor@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-sor
- nvidia,tegra210-sor
- nvidia,tegra210-sor1
- nvidia,tegra186-sor
- nvidia,tegra186-sor1
- nvidia,tegra194-sor
- items:
- const: nvidia,tegra132-sor
- const: nvidia,tegra124-sor
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 5
maxItems: 6
clock-names:
minItems: 5
maxItems: 6
resets:
items:
- description: module reset
reset-names:
items:
- const: sor
power-domains:
maxItems: 1
avdd-io-hdmi-dp-supply:
description: I/O supply for HDMI/DP
vdd-hdmi-dp-pll-supply:
description: PLL supply for HDMI/DP
hdmi-supply:
description: +5.0V HDMI connector supply, required for HDMI
# Tegra186 and later
nvidia,interface:
description: index of the SOR interface
$ref: /schemas/types.yaml#/definitions/uint32
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
$ref: /schemas/types.yaml#/definitions/phandle
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
description: supplies a binary EDID blob
$ref: /schemas/types.yaml#/definitions/uint8-array
nvidia,panel:
description: phandle of a display panel, required for eDP
$ref: /schemas/types.yaml#/definitions/phandle
nvidia,xbar-cfg:
description: 5 cells containing the crossbar configuration.
Each lane of the SOR, identified by the cell's index, is
mapped via the crossbar to the pad specified by the cell's
value.
$ref: /schemas/types.yaml#/definitions/uint32-array
# optional when driving an eDP output
nvidia,dpaux:
description: phandle to a DisplayPort AUX interface
$ref: /schemas/types.yaml#/definitions/phandle
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-sor
- nvidia,tegra194-sor
then:
properties:
clocks:
items:
- description: clock input for the SOR hardware
- description: SOR output clock
- description: input for the pixel clock
- description: reference clock for the SOR clock
- description: safe reference clock for the SOR clock
during power up
- description: SOR pad output clock
clock-names:
items:
- const: sor
- enum:
- source # deprecated
- out
- const: parent
- const: dp
- const: safe
- const: pad
else:
properties:
clocks:
items:
- description: clock input for the SOR hardware
- description: SOR output clock
- description: input for the pixel clock
- description: reference clock for the SOR clock
- description: safe reference clock for the SOR clock
during power up
clock-names:
items:
- const: sor
- enum:
- source # deprecated
- out
- const: parent
- const: dp
- const: safe
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- avdd-io-hdmi-dp-supply
- vdd-hdmi-dp-pll-supply
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
sor0: sor@54540000 {
compatible = "nvidia,tegra210-sor";
reg = <0x54540000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR0_OUT>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "out", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux_aux>;
pinctrl-1 = <&state_dpaux_i2c>;
pinctrl-2 = <&state_dpaux_off>;
pinctrl-names = "aux", "i2c", "off";
power-domains = <&pd_sor>;
avdd-io-hdmi-dp-supply = <&avdd_1v05>;
vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Image Composer
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^vic@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-vic
- nvidia,tegra210-vic
- nvidia,tegra186-vic
- nvidia,tegra194-vic
- nvidia,tegra234-vic
- items:
- const: nvidia,tegra132-vic
- const: nvidia,tegra124-vic
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: clock input for the VIC hardware
clock-names:
items:
- const: vic
resets:
items:
- description: module reset
reset-names:
items:
- const: vic
power-domains:
maxItems: 1
iommus:
maxItems: 1
interconnects:
description: Description of the interconnect paths for the VIC;
see ../interconnect/interconnect.txt for details.
items:
- description: memory read client for VIC
- description: memory write client for VIC
interconnect-names:
items:
- const: dma-mem # read
- const: write
dma-coherent: true
additionalProperties: false
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) Display Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^display@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra186-dc
- nvidia,tegra194-dc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: display controller pixel clock
clock-names:
items:
- const: dc
resets:
items:
- description: display controller reset
reset-names:
items:
- const: dc
power-domains:
maxItems: 1
iommus:
maxItems: 1
interconnects:
description: Description of the interconnect paths for the
display controller; see ../interconnect/interconnect.txt
for details.
interconnect-names:
items:
- const: dma-mem # read-0
- const: read-1
nvidia,outputs:
description: A list of phandles of outputs that this display
controller can drive.
$ref: /schemas/types.yaml#/definitions/phandle-array
nvidia,head:
description: The number of the display controller head. This
is used to setup the various types of output to receive
video data from the given head.
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- power-domains
- nvidia,outputs
- nvidia,head
# see nvidia,tegra186-display.yaml for examples
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) Display Hub
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^display-hub@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra186-display
- nvidia,tegra194-display
'#address-cells':
enum: [ 1, 2 ]
'#size-cells':
enum: [ 1, 2 ]
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
resets:
items:
- description: display hub reset
- description: window group 0 reset
- description: window group 1 reset
- description: window group 2 reset
- description: window group 3 reset
- description: window group 4 reset
- description: window group 5 reset
reset-names:
items:
- const: misc
- const: wgrp0
- const: wgrp1
- const: wgrp2
- const: wgrp3
- const: wgrp4
- const: wgrp5
power-domains:
maxItems: 1
ranges:
maxItems: 1
patternProperties:
"^display@[0-9a-f]+$":
type: object
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra186-display
then:
properties:
clocks:
items:
- description: display core clock
- description: display stream compression clock
- description: display hub clock
clock-names:
items:
- const: disp
- const: dsc
- const: hub
else:
properties:
clocks:
items:
- description: display core clock
- description: display hub clock
clock-names:
items:
- const: disp
- const: hub
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
display-hub@15200000 {
compatible = "nvidia,tegra186-display";
reg = <0x15200000 0x00040000>;
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
"wgrp3", "wgrp4", "wgrp5";
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
clock-names = "disp", "dsc", "hub";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x15200000 0x15200000 0x40000>;
display@15200000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15200000 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <0>;
};
display@15210000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15210000 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <1>;
};
display@15220000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15220000 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1>;
nvidia,head = <2>;
};
};
- |
#include <dt-bindings/clock/tegra194-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra194-mc.h>
#include <dt-bindings/power/tegra194-powergate.h>
#include <dt-bindings/reset/tegra194-reset.h>
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
reg = <0x15200000 0x00040000>;
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
"wgrp3", "wgrp4", "wgrp5";
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
clock-names = "disp", "hub";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x15200000 0x15200000 0x40000>;
display@15200000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15200000 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <0>;
};
display@15210000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15210000 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <1>;
};
display@15220000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15220000 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <2>;
};
display@15230000 {
compatible = "nvidia,tegra194-dc";
reg = <0x15230000 0x10000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
clock-names = "dc";
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <3>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra MIPI DSI pad controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^padctl@[0-9a-f]+$"
compatible:
const: nvidia,tegra186-dsi-padctl
reg:
maxItems: 1
resets:
items:
- description: module reset
reset-names:
items:
- const: dsi
allOf:
- $ref: /schemas/reset/reset.yaml
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/tegra186-reset.h>
padctl@15880000 {
compatible = "nvidia,tegra186-dsi-padctl";
reg = <0x15880000 0x10000>;
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 CSI controller
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
properties:
compatible:
enum:
- nvidia,tegra20-csi
- nvidia,tegra30-csi
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: module clock
- description: PAD A clock
- description: PAD B clock
clock-names:
items:
- const: csi
- const: csia-pad
- const: csib-pad
avdd-dsi-csi-supply:
description: DSI/CSI power supply. Must supply 1.2 V.
power-domains:
maxItems: 1
"#nvidia,mipi-calibrate-cells":
description:
The number of cells in a MIPI calibration specifier. Should be 1.
The single cell specifies an id of the pad that need to be
calibrated for a given device. Valid pad ids for receiver would be
0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B.
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^channel@[0-1]$":
type: object
description: channel 0 represents CSI-A and 1 represents CSI-B
additionalProperties: false
properties:
reg:
maximum: 1
nvidia,mipi-calibrate:
description: Should contain a phandle and a specifier specifying
which pad is used by this CSI channel and needs to be calibrated.
$ref: /schemas/types.yaml#/definitions/phandle-array
"#address-cells":
const: 1
"#size-cells":
const: 0
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: port receiving the video stream from the sensor
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: port sending the video stream to the VI
required:
- reg
- "#address-cells"
- "#size-cells"
- port@0
- port@1
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-csi
then:
properties:
clocks:
maxItems: 1
clock-names: false
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra30-csi
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
additionalProperties: false
required:
- compatible
- reg
- clocks
- power-domains
- "#address-cells"
- "#size-cells"
# see nvidia,tegra20-vi.yaml for an example
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Display Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^dc@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-dc
- nvidia,tegra30-dc
- nvidia,tegra114-dc
- nvidia,tegra124-dc
- nvidia,tegra210-dc
- items:
- const: nvidia,tegra124-dc
- const: nvidia,tegra132-dc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: display controller pixel clock
- description: parent clock # optional
clock-names:
minItems: 1
items:
- const: dc
- const: parent # optional
resets:
items:
- description: module reset
reset-names:
items:
- const: dc
interconnect-names: true
interconnects: true
iommus:
maxItems: 1
operating-points-v2: true
power-domains:
items:
- description: phandle to the core power domain
memory-region: true
nvidia,head:
$ref: /schemas/types.yaml#/definitions/uint32
description: The number of the display controller head. This is used to setup the various
types of output to receive video data from the given head.
nvidia,outputs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: A list of phandles of outputs that this display controller can drive.
rgb:
type: object
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-dc
- nvidia,tegra30-dc
- nvidia,tegra114-dc
then:
properties:
interconnects:
items:
- description: window A memory client
- description: window B memory client
- description: window B memory client (vertical filter)
- description: window C memory client
- description: cursor memory client
interconnect-names:
items:
- const: wina
- const: winb
- const: winb-vfilter
- const: winc
- const: cursor
rgb:
description: Each display controller node has a child node, named "rgb", that represents
the RGB output associated with the controller.
type: object
properties:
nvidia,ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle of an I2C controller used for DDC EDID probing
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: supplies a binary EDID blob
nvidia,panel:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle of a display panel
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-dc
then:
properties:
interconnects:
minItems: 4
items:
- description: window A memory client
- description: window B memory client
- description: window C memory client
- description: cursor memory client
- description: window D memory client
- description: window T memory client
interconnect-names:
minItems: 4
items:
- const: wina
- const: winb
- const: winc
- const: cursor
- const: wind
- const: wint
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Display Serial Interface
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-dsi
- nvidia,tegra30-dsi
- nvidia,tegra114-dsi
- nvidia,tegra124-dsi
- nvidia,tegra210-dsi
- nvidia,tegra186-dsi
- items:
- const: nvidia,tegra132-dsi
- const: nvidia,tegra124-dsi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
resets:
items:
- description: module reset
reset-names:
items:
- const: dsi
operating-points-v2: true
power-domains:
maxItems: 1
avdd-dsi-csi-supply:
description: phandle of a supply that powers the DSI controller
nvidia,mipi-calibrate:
description: Should contain a phandle and a specifier specifying
which pads are used by this DSI output and need to be
calibrated. See nvidia,tegra114-mipi.yaml for details.
$ref: /schemas/types.yaml#/definitions/phandle-array
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
$ref: /schemas/types.yaml#/definitions/phandle
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
description: supplies a binary EDID blob
$ref: /schemas/types.yaml#/definitions/uint8-array
nvidia,panel:
description: phandle of a display panel
$ref: /schemas/types.yaml#/definitions/phandle
nvidia,ganged-mode:
description: contains a phandle to a second DSI controller to
gang up with in order to support up to 8 data lanes
$ref: /schemas/types.yaml#/definitions/phandle
allOf:
- $ref: ../dsi-controller.yaml#
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-dsi
- nvidia,tegra30-dsi
then:
properties:
clocks:
items:
- description: DSI module clock
- description: input for the pixel clock
clock-names:
items:
- const: dsi
- const: parent
else:
properties:
clocks:
items:
- description: DSI module clock
- description: low-power module clock
- description: input for the pixel clock
clock-names:
items:
- const: dsi
- const: lp
- const: parent
- if:
properties:
compatible:
contains:
const: nvidia,tegra186-dsi
then:
required:
- interrupts
unevaluatedProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
dsi@15300000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15300000 0x10000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSI>,
<&bpmp TEGRA186_CLK_DSIA_LP>,
<&bpmp TEGRA186_CLK_PLLD>;
clock-names = "dsi", "lp", "parent";
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Encoder Pre-Processor
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^epp@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-epp
- nvidia,tegra30-epp
- nvidia,tegra114-epp
- nvidia,tegra124-epp
- items:
- const: nvidia,tegra132-epp
- const: nvidia,tegra124-epp
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
items:
- description: module reset
reset-names:
items:
- const: epp
iommus:
maxItems: 1
interconnects:
maxItems: 4
interconnect-names:
maxItems: 4
operating-points-v2: true
power-domains:
items:
- description: phandle to the core power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
epp@540c0000 {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA 2D graphics engine
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^gr2d@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-gr2d
- nvidia,tegra30-gr2d
- nvidia,tegra114-gr2d
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
items:
- const: 2d
- const: mc
iommus:
maxItems: 1
interconnects:
maxItems: 4
interconnect-names:
maxItems: 4
operating-points-v2: true
power-domains:
items:
- description: phandle to the HEG or core power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra20-mc.h>
gr2d@54140000 {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
reset-names = "2d", "mc";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA 3D graphics engine
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^gr3d@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-gr3d
- nvidia,tegra30-gr3d
- nvidia,tegra114-gr3d
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
resets:
minItems: 2
maxItems: 4
reset-names:
minItems: 2
maxItems: 4
iommus:
minItems: 1
maxItems: 2
interconnects:
minItems: 4
maxItems: 10
interconnect-names:
minItems: 4
maxItems: 10
operating-points-v2: true
power-domains:
minItems: 1
maxItems: 2
power-domain-names:
maxItems: 2
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra20-gr2d
then:
properties:
clocks:
items:
- description: module clock
clock-names:
items:
- const: 3d
resets:
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
items:
- const: 3d
- const: mc
iommus:
maxItems: 1
interconnects:
minItems: 4
maxItems: 4
interconnect-names:
minItems: 4
maxItems: 4
power-domains:
items:
- description: phandle to the TD power domain
- if:
properties:
compatible:
contains:
const: nvidia,tegra30-gr3d
then:
properties:
clocks:
items:
- description: primary module clock
- description: secondary module clock
clock-names:
items:
- const: 3d
- const: 3d2
resets:
items:
- description: primary module reset
- description: secondary module reset
- description: primary memory client hotflush reset
- description: secondary memory client hotflush reset
reset-names:
items:
- const: 3d
- const: 3d2
- const: mc
- const: mc2
iommus:
minItems: 2
maxItems: 2
interconnects:
minItems: 8
maxItems: 8
interconnect-names:
minItems: 8
maxItems: 8
power-domains:
items:
- description: phandle to the TD power domain
- description: phandle to the TD2 power domain
power-domain-names:
items:
- const: 3d0
- const: 3d1
dependencies:
power-domains: [ power-domain-names ]
- if:
properties:
compatible:
contains:
const: nvidia,tegra114-gr2d
then:
properties:
clocks:
items:
- description: module clock
clock-names:
items:
- const: 3d
resets:
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
items:
- const: 3d
- const: mc
iommus:
maxItems: 1
interconnects:
minItems: 10
maxItems: 10
interconnect-names:
minItems: 10
maxItems: 10
power-domains:
items:
- description: phandle to the TD power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/memory/tegra20-mc.h>
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
reset-names = "3d", "mc";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra HDMI Output Encoder
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^hdmi@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-hdmi
- nvidia,tegra30-hdmi
- nvidia,tegra114-hdmi
- nvidia,tegra124-hdmi
- items:
- const: nvidia,tegra132-hdmi
- const: nvidia,tegra124-hdmi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
- description: parent clock
clock-names:
items:
- const: hdmi
- const: parent
resets:
items:
- description: module reset
reset-names:
items:
- const: hdmi
operating-points-v2: true
power-domains:
items:
- description: phandle to the core power domain
hdmi-supply:
description: supply for the +5V HDMI connector pin
vdd-supply:
description: regulator for supply voltage
pll-supply:
description: regulator for PLL
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
$ref: /schemas/types.yaml#/definitions/phandle
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
maxItems: 1
nvidia,edid:
description: supplies a binary EDID blob
$ref: /schemas/types.yaml#/definitions/uint8-array
nvidia,panel:
description: phandle of a display panel
$ref: /schemas/types.yaml#/definitions/phandle
port:
description: HDMI output port for connection to HDMI connector or bridge
$ref: /schemas/graph.yaml#/properties/port
"#sound-dai-cells":
const: 0
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- pll-supply
- vdd-supply
anyOf:
- required:
- nvidia,ddc-i2c-bus
- nvidia,hpd-gpio
- required:
- port
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/tegra-gpio.h>
hdmi@54280000 {
compatible = "nvidia,tegra124-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_HDMI>,
<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
hdmi-supply = <&vdd_5v0_hdmi>;
pll-supply = <&vdd_hdmi_pll>;
vdd-supply = <&vdd_3v3_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra host1x controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: The host1x top-level node defines a number of children, each
representing one of the host1x client modules defined in this binding.
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-host1x
- nvidia,tegra30-host1x
- nvidia,tegra114-host1x
- nvidia,tegra124-host1x
- nvidia,tegra210-host1x
- nvidia,tegra186-host1x
- nvidia,tegra194-host1x
- nvidia,tegra234-host1x
- items:
- const: nvidia,tegra132-host1x
- const: nvidia,tegra124-host1x
reg:
minItems: 1
maxItems: 3
reg-names:
minItems: 1
maxItems: 3
interrupts:
minItems: 1
maxItems: 9
interrupt-names:
minItems: 1
maxItems: 9
'#address-cells':
description: The number of cells used to represent physical base addresses
in the host1x address space.
enum: [1, 2]
'#size-cells':
description: The number of cells used to represent the size of an address
range in the host1x address space.
enum: [1, 2]
ranges:
maxItems: 1
clocks:
description: Must contain one entry, for the module clock. See
../clocks/clock-bindings.txt for details.
clock-names:
items:
- const: host1x
resets:
minItems: 1 # MC reset is optional on Tegra186 and later
items:
- description: module reset
- description: memory client hotflush reset
reset-names:
minItems: 1 # MC reset is optional on Tegra186 and later
items:
- const: host1x
- const: mc
iommus:
maxItems: 1
interconnects:
items:
- description: memory read client for host1x
interconnect-names:
items:
- const: dma-mem # read
operating-points-v2: true
power-domains:
items:
- description: phandle to the HEG or core power domain
required:
- compatible
- interrupts
- interrupt-names
- '#address-cells'
- '#size-cells'
- ranges
- reg
- clocks
- clock-names
unevaluatedProperties:
type: object
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-host1x
- nvidia,tegra30-host1x
- nvidia,tegra114-host1x
- nvidia,tegra124-host1x
- nvidia,tegra210-host1x
then:
properties:
interrupts:
items:
- description: host1x syncpoint interrupt
- description: host1x general interrupt
interrupt-names:
items:
- const: syncpt
- const: host1x
required:
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-host1x
- nvidia,tegra194-host1x
then:
properties:
reg-names:
items:
- const: hypervisor
- const: vm
reg:
items:
- description: region used by the hypervisor
- description: region assigned to the virtual machine
resets:
maxItems: 1
reset-names:
maxItems: 1
interrupts:
items:
- description: host1x syncpoint interrupt
- description: host1x general interrupt
interrupt-names:
items:
- const: syncpt
- const: host1x
iommu-map:
description: Specification of stream IDs available for memory context device
use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
usable stream IDs.
required:
- reg-names
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra194-host1x
then:
properties:
dma-coherent: true
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra234-host1x
then:
properties:
reg-names:
items:
- const: common
- const: hypervisor
- const: vm
reg:
items:
- description: region used by host1x server
- description: region used by the hypervisor
- description: region assigned to the virtual machine
interrupts:
items:
- description: host1x syncpoint interrupt 0
- description: host1x syncpoint interrupt 1
- description: host1x syncpoint interrupt 2
- description: host1x syncpoint interrupt 3
- description: host1x syncpoint interrupt 4
- description: host1x syncpoint interrupt 5
- description: host1x syncpoint interrupt 6
- description: host1x syncpoint interrupt 7
- description: host1x general interrupt
interrupt-names:
items:
- const: syncpt0
- const: syncpt1
- const: syncpt2
- const: syncpt3
- const: syncpt4
- const: syncpt5
- const: syncpt6
- const: syncpt7
- const: host1x
iommu-map:
description: Specification of stream IDs available for memory context device
use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
usable stream IDs.
dma-coherent: true
required:
- reg-names
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra20-mc.h>
host1x@50000000 {
compatible = "nvidia,tegra20-host1x";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04>, /* mpcore syncpt */
<0 67 0x04>; /* mpcore general */
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
reset-names = "host1x", "mc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x04000000>;
mpe@54040000 {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
};
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 100>;
reset-names = "vi";
};
epp@540c0000 {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
};
isp@54100000 {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
};
gr2d@54140000 {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
reset-names = "2d", "mc";
};
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
reset-names = "3d", "mc";
};
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
rgb {
};
};
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP2>;
clock-names = "dc";
resets = <&tegra_car 26>;
reset-names = "dc";
rgb {
};
};
hdmi@54280000 {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
hdmi-supply = <&vdd_5v0_hdmi>;
pll-supply = <&vdd_hdmi_pll>;
vdd-supply = <&vdd_3v3_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
};
dsi@54300000 {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
};
};
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra210-mc.h>
host1x@50000000 {
compatible = "nvidia,tegra210-host1x";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x01000000>;
iommus = <&mc TEGRA_SWGROUP_HC>;
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x54080000 0x00000700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
clocks = <&tegra_car TEGRA210_CLK_VI>;
power-domains = <&pd_venc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54080000 0x2000>;
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <102000000>,
<102000000>,
<102000000>,
<972000000>;
clocks = <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra ISP processor
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-isp
- nvidia,tegra30-isp
- nvidia,tegra114-isp
- nvidia,tegra124-isp
- nvidia,tegra210-isp
- items:
- const: nvidia,tegra132-isp
- const: nvidia,tegra124-isp
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: isp
iommus:
maxItems: 1
interconnects:
items:
- description: memory write client
interconnect-names:
items:
- const: dma-mem # write
power-domains:
items:
- description: phandle to the VENC or core power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
isp@54100000 {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Encoder
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
oneOf:
- pattern: "^mpe@[0-9a-f]+$"
- pattern: "^msenc@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-mpe
- nvidia,tegra30-mpe
- nvidia,tegra114-msenc
- nvidia,tegra124-msenc
- items:
- const: nvidia,tegra132-msenc
- const: nvidia,tegra124-msenc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: mpe
iommus:
maxItems: 1
interconnects:
maxItems: 6
interconnect-names:
maxItems: 6
operating-points-v2: true
power-domains:
items:
- description: phandle to the MPE power domain
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mpe@54040000 {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra TV Encoder Output
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^tvo@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-tvo
- nvidia,tegra30-tvo
- nvidia,tegra114-tvo
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
operating-points-v2: true
power-domains:
items:
- description: phandle to the core power domain
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Input controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^vi@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra20-vi
- nvidia,tegra114-vi
- nvidia,tegra124-vi
- nvidia,tegra210-vi
- nvidia,tegra186-vi
- nvidia,tegra194-vi
- items:
- const: nvidia,tegra30-vi
- const: nvidia,tegra20-vi
- items:
- const: nvidia,tegra132-vi
- const: nvidia,tegra124-vi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
items:
- description: module reset
reset-names:
items:
- const: vi
iommus:
maxItems: 1
interconnects:
minItems: 4
maxItems: 5
interconnect-names:
minItems: 4
maxItems: 5
operating-points-v2: true
power-domains:
items:
- description: phandle to the VENC power domain
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
maxItems: 1
vip:
$ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Input from the VIP (parallel input capture) module
patternProperties:
"^csi@[0-9a-f]+$":
type: object
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-vi
- nvidia,tegra30-vi
- nvidia,tegra114-vi
- nvidia,tegra124-vi
then:
required:
- resets
- reset-names
else:
required:
- power-domains
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
camera@48 {
compatible = "aptina,mt9v111";
reg = <0x48>;
clocks = <&camera_clk>;
port {
mt9v111_out: endpoint {
remote-endpoint = <&vi_vip_in>;
};
};
};
};
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 100>;
reset-names = "vi";
vip {
compatible = "nvidia,tegra20-vip";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vi_vip_in: endpoint {
remote-endpoint = <&mt9v111_out>;
};
};
port@1 {
reg = <1>;
vi_vip_out: endpoint {
remote-endpoint = <&vi_in>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vi_in: endpoint {
remote-endpoint = <&vi_vip_out>;
};
};
};
};
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x54080000 0x00000700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
clocks = <&tegra_car TEGRA210_CLK_VI>;
power-domains = <&pd_venc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54080000 0x2000>;
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <102000000>,
<102000000>,
<102000000>,
<972000000>;
clocks = <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra VIP (parallel video capture) controller
maintainers:
- Luca Ceresoli <luca.ceresoli@bootlin.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-vip
- items:
- const: nvidia,tegra30-vip
- const: nvidia,tegra20-vip
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Port receiving the video stream from the sensor
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Port sending the video stream to the VI
required:
- port@0
- port@1
unevaluatedProperties: false
required:
- compatible
- ports
# see nvidia,tegra20-vi.yaml for an example
linux-7.2.3/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra CSI controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^csi@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra210-csi
reg:
maxItems: 1
clocks:
items:
- description: module clock
- description: A/B lanes clock
- description: C/D lanes clock
- description: E lane clock
- description: test pattern generator clock
clock-names:
items:
- const: csi
- const: cilab
- const: cilcd
- const: cile
- const: csi_tpg
avdd-dsi-csi-supply:
description: DSI/CSI power supply. Must supply 1.2 V.
power-domains:
maxItems: 1
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
# see nvidia,tegra20-vi.yaml for an example