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linux-7.2.3/Documentation/devicetree/bindings/gpu/apple,agx.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/apple,agx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SoC GPU
maintainers:
- Sasha Finkelstein <k@chaosmail.tech>
properties:
compatible:
oneOf:
- enum:
- apple,agx-g13g
- apple,agx-g13s
- apple,agx-g14g
- apple,agx-g14s
- items:
- enum:
- apple,agx-g13c
- apple,agx-g13d
- const: apple,agx-g13s
- items:
- enum:
- apple,agx-g14c
- apple,agx-g14d
- const: apple,agx-g14s
reg:
items:
- description: GPU coprocessor control registers
- description: GPU block MMIO registers
reg-names:
items:
- const: asc
- const: sgx
power-domains:
maxItems: 1
mboxes:
maxItems: 1
memory-region:
items:
- description: Region containing GPU MMU TTBs
- description: Region containing GPU MMU page tables
- description:
Region containing a shared handoff structure for VM
management coordination
- description: Calibration blob. Mostly power-related configuration
- description: Calibration blob. Mostly GPU-related configuration
- description: Shared global variables with GPU firmware
memory-region-names:
items:
- const: ttbs
- const: pagetables
- const: handoff
- const: hw-cal-a
- const: hw-cal-b
- const: globals
apple,firmware-abi:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
description:
macOS version the current firmware is paired with, used to pick
the version of firmware ABI to be used.
Bootloader will overwrite this
required:
- compatible
- reg
- mboxes
- memory-region
- apple,firmware-abi
additionalProperties: false
examples:
- |
gpu@6400000 {
compatible = "apple,agx-g13g";
reg = <0x6400000 0x40000>,
<0x4000000 0x1000000>;
reg-names = "asc", "sgx";
mboxes = <&agx_mbox>;
power-domains = <&ps_gfx>;
memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>,
<&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>;
memory-region-names = "ttbs", "pagetables", "handoff",
"hw-cal-a", "hw-cal-b", "globals";
apple,firmware-abi = <0 0 0>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Bifrost GPU
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- allwinner,sun50i-h616-mali
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- mediatek,mt8183b-mali
- mediatek,mt8186-mali
- mediatek,mt8365-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a08g046-mali
- renesas,r9a09g047-mali
- renesas,r9a09g056-mali
- renesas,r9a09g057-mali
- rockchip,px30-mali
- rockchip,rk3562-mali
- rockchip,rk3568-mali
- rockchip,rk3576-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
- items:
- enum:
- mediatek,mt8195-mali
- const: mediatek,mt8192-mali
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
- items:
- enum:
- allwinner,sun55i-a523-mali
- mediatek,mt8188-mali
- mediatek,mt8192-mali
- mediatek,mt8370-mali
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
reg:
maxItems: 1
interrupts:
minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interrupt
interrupt-names:
minItems: 3
items:
- const: job
- const: mmu
- const: gpu
- const: event
clocks:
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
sram-supply: true
operating-points-v2: true
power-domains:
minItems: 1
maxItems: 5
power-domain-names:
minItems: 2
maxItems: 5
resets:
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells":
const: 2
dynamic-power-coefficient:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
dma-coherent: true
nvmem-cell-names:
items:
- const: speed-bin
nvmem-cells:
maxItems: 1
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: amlogic,meson-g12a-mali
then:
properties:
power-domains:
maxItems: 1
power-domain-names: false
required:
- resets
- if:
properties:
compatible:
contains:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a08g046-mali
- renesas,r9a09g047-mali
- renesas,r9a09g056-mali
- renesas,r9a09g057-mali
then:
properties:
interrupts:
minItems: 4
interrupt-names:
minItems: 4
clocks:
minItems: 3
clock-names:
items:
- const: gpu
- const: bus
- const: bus_ace
power-domains:
maxItems: 1
power-domain-names: false
resets:
minItems: 3
reset-names:
items:
- const: rst
- const: axi_rst
- const: ace_rst
required:
- clock-names
- power-domains
- resets
- reset-names
- if:
properties:
compatible:
contains:
const: mediatek,mt8183-mali
then:
properties:
power-domains:
minItems: 3
maxItems: 3
power-domain-names:
items:
- const: core0
- const: core1
- const: core2
required:
- sram-supply
- power-domains
- power-domain-names
else:
properties:
sram-supply: false
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8183b-mali
- mediatek,mt8188-mali
then:
properties:
power-domains:
minItems: 3
maxItems: 3
power-domain-names:
items:
- const: core0
- const: core1
- const: core2
required:
- power-domains
- power-domain-names
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8186-mali
- mediatek,mt8370-mali
then:
properties:
power-domains:
minItems: 2
maxItems: 2
power-domain-names:
items:
- const: core0
- const: core1
required:
- power-domains
- power-domain-names
- if:
properties:
compatible:
contains:
const: mediatek,mt8192-mali
then:
properties:
power-domains:
minItems: 5
power-domain-names:
items:
- const: core0
- const: core1
- const: core2
- const: core3
- const: core4
required:
- power-domains
- power-domain-names
- if:
properties:
compatible:
contains:
const: rockchip,rk3568-mali
then:
properties:
clocks:
minItems: 2
clock-names:
items:
- const: gpu
- const: bus
power-domains:
maxItems: 1
power-domain-names: false
required:
- clock-names
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@ffe40000 {
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
reg = <0xffe40000 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&clk 1>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
resets = <&reset 0>, <&reset 1>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp-266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Midgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- samsung,exynos5250-mali
- const: arm,mali-t604
- items:
- enum:
- samsung,exynos5420-mali
- const: arm,mali-t628
- items:
- enum:
- allwinner,sun50i-h6-mali
- const: arm,mali-t720
- items:
- enum:
- amlogic,meson-gxm-mali
- realtek,rtd1295-mali
- const: arm,mali-t820
- items:
- enum:
- arm,juno-mali
- const: arm,mali-t624
- items:
- enum:
- rockchip,rk3288-mali
- samsung,exynos5433-mali
- const: arm,mali-t760
- items:
- enum:
- samsung,exynos7-mali
- const: samsung,exynos5433-mali
- const: arm,mali-t760
- items:
- enum:
- samsung,exynos7870-mali
- const: arm,mali-t830
- items:
- enum:
- rockchip,rk3399-mali
- const: arm,mali-t860
- items:
- enum:
- samsung,exynos8890-mali
- const: arm,mali-t880
reg:
maxItems: 1
interrupts:
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
interrupt-names:
items:
- const: job
- const: mmu
- const: gpu
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: bus
mali-supply: true
opp-table:
type: object
power-domains:
maxItems: 1
resets:
minItems: 1
maxItems: 2
operating-points-v2: true
"#cooling-cells":
const: 2
dma-coherent: true
dynamic-power-coefficient:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: allwinner,sun50i-h6-mali
then:
properties:
clocks:
minItems: 2
required:
- clock-names
- resets
- if:
properties:
compatible:
contains:
const: amlogic,meson-gxm-mali
then:
properties:
resets:
minItems: 2
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru 0>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power 0>;
#cooling-cells = <2>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp-266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Utgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
- Maxime Ripard <mripard@kernel.org>
- Heiko Stuebner <heiko@sntech.de>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- const: allwinner,sun8i-a23-mali
- const: allwinner,sun7i-a20-mali
- const: arm,mali-400
- items:
- enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-h3-mali
- allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
- rockchip,rk3128-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- samsung,exynos4210-mali
- st,stih410-mali
- stericsson,db8500-mali
- xlnx,zynqmp-mali
- const: arm,mali-400
- items:
- enum:
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
- amlogic,meson8b-mali
- amlogic,meson-gxbb-mali
- amlogic,meson-gxl-mali
- hisilicon,hi6220-mali
- mediatek,mt7623-mali
- rockchip,rk3328-mali
- rockchip,rk3528-mali
- const: arm,mali-450
# "arm,mali-300"
reg:
maxItems: 1
interrupts:
minItems: 4
maxItems: 20
interrupt-names:
allOf:
- additionalItems: true
minItems: 4
maxItems: 20
items:
# At least enforce the first 2 interrupts
- const: gp
- const: gpmmu
- items:
# Not ideal as any order and combination are allowed
enum:
- gp # Geometry Processor interrupt
- gpmmu # Geometry Processor MMU interrupt
- pp # Pixel Processor broadcast interrupt (mali-450 only)
- pp0 # Pixel Processor X interrupt (X from 0 to 7)
- ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
- pp1
- ppmmu1
- pp2
- ppmmu2
- pp3
- ppmmu3
- pp4
- ppmmu4
- pp5
- ppmmu5
- pp6
- ppmmu6
- pp7
- ppmmu7
- pmu # Power Management Unit interrupt (optional)
- combined # stericsson,db8500-mali only
clocks:
maxItems: 2
clock-names:
items:
- const: bus
- const: core
memory-region: true
mali-supply: true
opp-table:
type: object
power-domains:
maxItems: 1
resets:
maxItems: 1
operating-points-v2: true
"#cooling-cells":
const: 2
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
- amlogic,meson8b-mali
- hisilicon,hi6220-mali
- mediatek,mt7623-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- rockchip,rk3328-mali
- rockchip,rk3528-mali
then:
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mali: gpu@1c40000 {
compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pmu";
clocks = <&ccu 1>, <&ccu 2>;
clock-names = "bus", "core";
resets = <&ccu 1>;
#cooling-cells = <2>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Valhall GPU
maintainers:
- Liviu Dudau <liviu.dudau@arm.com>
- Boris Brezillon <boris.brezillon@collabora.com>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- mediatek,mt8196-mali
- nxp,imx95-mali # G310
- rockchip,rk3588-mali
- const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
reg:
maxItems: 1
interrupts:
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
interrupt-names:
items:
- const: job
- const: mmu
- const: gpu
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
items:
- const: core
- enum:
- coregroup
- stacks
- const: stacks
nvmem-cells:
items:
- description: bitmask of functional shader cores
nvmem-cell-names:
items:
- const: shader-present
mali-supply: true
operating-points-v2: true
opp-table:
type: object
power-domains:
minItems: 1
maxItems: 5
power-domain-names:
minItems: 1
maxItems: 5
sram-supply: true
"#cooling-cells":
const: 2
dynamic-power-coefficient:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
dma-coherent: true
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,rk3588-mali
then:
properties:
clocks:
minItems: 3
nvmem-cells: false
nvmem-cell-names: false
power-domains:
maxItems: 1
power-domain-names: false
required:
- mali-supply
- if:
properties:
compatible:
contains:
const: mediatek,mt8196-mali
then:
properties:
mali-supply: false
sram-supply: false
operating-points-v2: false
power-domains:
maxItems: 1
power-domain-names: false
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: stacks
required:
- nvmem-cells
- nvmem-cell-names
- power-domains
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3588-power.h>
gpu: gpu@fb000000 {
compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
reg = <0xfb000000 0x200000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
clock-names = "core", "coregroup", "stacks";
clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
<&cru CLK_GPU_STACKS>;
power-domains = <&power RK3588_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <675000 675000 850000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <675000 675000 850000>;
};
};
};
- |
gpu@48000000 {
compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
reg = <0x48000000 0x480000>;
clocks = <&gpufreq 0>, <&gpufreq 1>;
clock-names = "core", "stacks";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
nvmem-cells = <&shader_present>;
nvmem-cell-names = "shader-present";
power-domains = <&gpufreq>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/aspeed,ast2400-gfx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED GFX Display Controller
maintainers:
- Joel Stanley <joel@jms.id.au>
properties:
compatible:
items:
- enum:
- aspeed,ast2400-gfx
- aspeed,ast2500-gfx
- aspeed,ast2600-gfx
- const: syscon
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
memory-region:
maxItems: 1
description:
a reserved-memory region to use for the framebuffer.
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to SCU
required:
- compatible
- reg
- interrupts
- clocks
- resets
- memory-region
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
resets = <&syscon ASPEED_RESET_CRT1>;
interrupts = <0x19>;
memory-region = <&gfx_memory>;
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/brcm,bcm-v3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom V3D GPU
maintainers:
- Maíra Canal <mcanal@igalia.com>
- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
enum:
- brcm,2711-v3d
- brcm,2712-v3d
- brcm,7268-v3d
- brcm,7278-v3d
reg:
minItems: 2
maxItems: 4
reg-names:
minItems: 2
maxItems: 4
interrupts:
items:
- description: hub interrupt (required)
- description: core interrupts (if it doesn't share the hub's interrupt)
minItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- reg-names
- interrupts
allOf:
- if:
properties:
compatible:
contains:
const: brcm,2711-v3d
then:
properties:
reg:
items:
- description: hub register
- description: core0 register
reg-names:
items:
- const: hub
- const: core0
- if:
properties:
compatible:
contains:
const: brcm,2712-v3d
then:
properties:
reg:
items:
- description: hub register
- description: core0 register
- description: SMS state manager register
reg-names:
items:
- const: hub
- const: core0
- const: sms
- if:
properties:
compatible:
contains:
const: brcm,7268-v3d
then:
properties:
reg:
items:
- description: hub register
- description: core0 register
- description: GCA cache controller register
- description: bridge register
reg-names:
items:
- const: hub
- const: core0
- const: gca
- const: bridge
- if:
properties:
compatible:
contains:
const: brcm,7278-v3d
then:
properties:
reg:
items:
- description: hub register
- description: core0 register
- description: bridge register
reg-names:
items:
- const: hub
- const: core0
- const: bridge
additionalProperties: false
examples:
- |
gpu@f1200000 {
compatible = "brcm,7268-v3d";
reg = <0xf1200000 0x4000>,
<0xf1208000 0x4000>,
<0xf1204100 0x100>,
<0xf1204000 0x100>;
reg-names = "hub", "core0", "gca", "bridge";
interrupts = <0 78 4>,
<0 77 4>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVDEC
description: |
NVDEC is the hardware video decoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvdec@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvdec
- nvidia,tegra186-nvdec
- nvidia,tegra194-nvdec
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvdec
resets:
maxItems: 1
reset-names:
items:
- const: nvdec
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA read 2 memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: read-1
- const: write
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
when programming the engine through Host1x channels or when
configuring engine-specific behavior in Host1x.
default: 0xf0
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvdec@15480000 {
compatible = "nvidia,tegra186-nvdec";
reg = <0x15480000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
clock-names = "nvdec";
resets = <&bpmp TEGRA186_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "read-1", "write";
iommus = <&smmu TEGRA186_SID_NVDEC>;
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVENC
description: |
NVENC is the hardware video encoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvenc@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvenc
- nvidia,tegra186-nvenc
- nvidia,tegra194-nvenc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvenc
resets:
maxItems: 1
reset-names:
items:
- const: nvenc
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
minItems: 2
maxItems: 3
interconnect-names:
minItems: 2
maxItems: 3
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
when programming the engine through Host1x channels or when
configuring engine-specific behavior in Host1x.
default: 0x21
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
allOf:
- if:
properties:
compatible:
enum:
- nvidia,tegra210-nvenc
- nvidia,tegra186-nvenc
then:
properties:
interconnects:
items:
- description: DMA read memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: write
- if:
properties:
compatible:
enum:
- nvidia,tegra194-nvenc
then:
properties:
interconnects:
items:
- description: DMA read memory client
- description: DMA read 2 memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: read-1
- const: write
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvenc@154c0000 {
compatible = "nvidia,tegra186-nvenc";
reg = <0x154c0000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA186_RESET_NVENC>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVENC>;
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVJPG
description: |
NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically programmed
through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvjpg@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvjpg
- nvidia,tegra186-nvjpg
- nvidia,tegra194-nvjpg
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvjpg
resets:
maxItems: 1
reset-names:
items:
- const: nvjpg
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: write
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvjpg@15380000 {
compatible = "nvidia,tegra186-nvjpg";
reg = <0x15380000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA186_RESET_NVJPG>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVJPG>;
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra234 NVDEC
description: |
NVDEC is the hardware video decoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvdec@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra234-nvdec
reg:
maxItems: 1
clocks:
maxItems: 3
clock-names:
items:
- const: nvdec
- const: fuse
- const: tsec_pka
resets:
maxItems: 1
reset-names:
items:
- const: nvdec
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: write
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the memory controller for determining information for the NVDEC
firmware secure carveout. This carveout is configured by the bootloader and
not accessible to CPU.
nvidia,bl-manifest-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to bootloader manifest from beginning of firmware that was configured by
the bootloader.
nvidia,bl-code-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to bootloader code section from beginning of firmware that was configured by
the bootloader.
nvidia,bl-data-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to bootloader data section from beginning of firmware that was configured by
the bootloader.
nvidia,os-manifest-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to operating system manifest from beginning of firmware that was configured by
the bootloader.
nvidia,os-code-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to operating system code section from beginning of firmware that was configured by
the bootloader.
nvidia,os-data-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset to operating system data section from beginning of firmware that was configured
by the bootloader.
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
- nvidia,memory-controller
- nvidia,bl-manifest-offset
- nvidia,bl-code-offset
- nvidia,bl-data-offset
- nvidia,os-manifest-offset
- nvidia,os-code-offset
- nvidia,os-data-offset
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
nvdec@15480000 {
compatible = "nvidia,tegra234-nvdec";
reg = <0x15480000 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVDEC>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_TSEC_PKA>;
clock-names = "nvdec", "fuse", "tsec_pka";
resets = <&bpmp TEGRA234_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
dma-coherent;
nvidia,memory-controller = <&mc>;
/* Placeholder values, to be replaced with values from overlay */
nvidia,bl-manifest-offset = <0>;
nvidia,bl-data-offset = <0>;
nvidia,bl-code-offset = <0>;
nvidia,os-manifest-offset = <0>;
nvidia,os-data-offset = <0>;
nvidia,os-code-offset = <0>;
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2023 Imagination Technologies Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies PowerVR and IMG Rogue GPUs
maintainers:
- Frank Binns <frank.binns@imgtec.com>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r8a7796-gpu
- renesas,r8a77961-gpu
- const: img,img-gx6250
- const: img,img-rogue
- items:
- enum:
- renesas,r8a77965-gpu
- renesas,r8a779a0-gpu
- const: img,img-ge7800
- const: img,img-rogue
- items:
- enum:
- ti,am62-gpu
- const: img,img-axe-1-16m
# This deprecated element must be kept around to allow old kernels to
# work with newer dts.
- const: img,img-axe
- const: img,img-rogue
- items:
- enum:
- thead,th1520-gpu
- const: img,img-bxm-4-64
- const: img,img-rogue
- items:
- enum:
- ti,am62p-gpu
- ti,j721s2-gpu
- const: img,img-bxs-4-64
- const: img,img-rogue
# This legacy combination of compatible strings was introduced early on
# before the more specific GPU identifiers were used.
- items:
- enum:
- ti,am62-gpu
- const: img,img-axe
deprecated: true
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
items:
- const: core
- const: mem
- const: sys
minItems: 1
interrupts:
maxItems: 1
power-domains:
minItems: 1
maxItems: 2
power-domain-names:
items:
- const: a
- const: b
minItems: 1
dma-coherent: true
resets:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- ti,am62-gpu
- ti,am62p-gpu
- ti,j721s2-gpu
then:
properties:
clocks:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- img,img-ge7800
- img,img-gx6250
- thead,th1520-gpu
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
const: img,img-axe-1-16m
then:
properties:
power-domains:
maxItems: 1
power-domain-names:
maxItems: 1
required:
- power-domains
- power-domain-names
- if:
properties:
compatible:
contains:
enum:
- img,img-bxs-4-64
- img,img-ge7800
- img,img-gx6250
then:
properties:
power-domains:
minItems: 2
power-domain-names:
minItems: 2
required:
- power-domains
- power-domain-names
- if:
properties:
compatible:
contains:
const: thead,th1520-gpu
then:
properties:
power-domains:
items:
- description: The single, unified power domain for the GPU on the
TH1520 SoC, integrating all internal IP power domains.
power-domain-names: false
required:
- power-domains
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
gpu@fd00000 {
compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe",
"img,img-rogue";
reg = <0x0fd00000 0x20000>;
clocks = <&k3_clks 187 0>;
clock-names = "core";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
power-domain-names = "a";
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2023 Imagination Technologies Ltd.
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies PowerVR SGX GPUs
maintainers:
- Frank Binns <frank.binns@imgtec.com>
properties:
compatible:
oneOf:
- items:
- enum:
- ti,omap3430-gpu # Rev 121
- ti,omap3630-gpu # Rev 125
- const: img,powervr-sgx530
- items:
- enum:
- ingenic,jz4780-gpu # Rev 130
- ti,omap4430-gpu # Rev 120
- const: img,powervr-sgx540
- items:
- enum:
- allwinner,sun6i-a31-gpu # MP2 Rev 115
- ti,omap4470-gpu # MP1 Rev 112
- ti,omap5432-gpu # MP2 Rev 105
- ti,am5728-gpu # MP2 Rev 116
- ti,am6548-gpu # MP1 Rev 117
- const: img,powervr-sgx544
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
items:
- const: core
- const: mem
- const: sys
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
allOf:
- if:
properties:
compatible:
contains:
const: ti,am6548-gpu
then:
required:
- power-domains
else:
properties:
power-domains: false
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun6i-a31-gpu
- ingenic,jz4780-gpu
then:
required:
- clocks
- clock-names
else:
properties:
clocks: false
clock-names: false
- if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-gpu
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
const: ingenic,jz4780-gpu
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
gpu@7000000 {
compatible = "ti,am6548-gpu", "img,powervr-sgx544";
reg = <0x7000000 0x10000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu: gpu@1c40000 {
compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 1>, <&ccu 2>;
clock-names = "core", "mem";
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Graphics Processing Units
maintainers:
- Alexandre Courbot <acourbot@nvidia.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <treding@nvidia.com>
properties:
compatible:
enum:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
- nvidia,gv11b
reg:
items:
- description: Bar0 register window
- description: Bar1 register window
interrupts:
items:
- description: Stall interrupt
- description: Nonstall interrupt
interrupt-names:
items:
- const: stall
- const: nonstall
vdd-supply:
description:
Regulator for GPU supply voltage
clocks:
minItems: 2
items:
- description: GPU clock
- description: Power clock
- description: Reference or fuse clock
clock-names:
minItems: 2
items:
- const: gpu
- const: pwr
- enum: [ ref, fuse ]
resets:
maxItems: 1
reset-names:
items:
- const: gpu
power-domains:
maxItems: 1
interconnects:
minItems: 4
maxItems: 12
interconnect-names:
minItems: 4
maxItems: 12
iommus:
maxItems: 1
dma-coherent: true
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- resets
- reset-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,gp10b
- nvidia,gv11b
then:
required:
- power-domains
else:
properties:
interconnects: false
interconnect-names: false
required:
- vdd-supply
- if:
properties:
compatible:
contains:
enum:
- nvidia,gp10b
then:
properties:
interconnects:
maxItems: 4
interconnect-names:
items:
- const: dma-mem
- const: write-0
- const: read-1
- const: write-1
- if:
properties:
compatible:
contains:
enum:
- nvidia,gv11b
then:
properties:
interconnects:
minItems: 12
interconnect-names:
items:
- const: dma-mem
- const: read-0-hp
- const: write-0
- const: read-1
- const: read-1-hp
- const: write-1
- const: read-2
- const: read-2-hp
- const: write-2
- const: read-3
- const: read-3-hp
- const: write-3
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/tegra124-car-common.h>
#include <dt-bindings/memory/tegra124-mc.h>
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x57000000 0x01000000>,
<0x58000000 0x01000000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
vdd-supply = <&vdd_gpu>;
clocks = <&tegra_car TEGRA124_CLK_GPU>,
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
clock-names = "gpu", "pwr";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/samsung-g2d.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-g2d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung SoC 2D Graphics Accelerator
maintainers:
- Inki Dae <inki.dae@samsung.com>
properties:
compatible:
enum:
- samsung,s5pv210-g2d # in S5PV210 & Exynos4210 SoC
- samsung,exynos4212-g2d # in Exynos4x12 SoCs
- samsung,exynos5250-g2d
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
iommus:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5250-g2d
then:
properties:
clocks:
items:
- description: fimg2d clock
clock-names:
items:
- const: fimg2d
else:
properties:
clocks:
items:
- description: sclk_fimg2d clock
- description: fimg2d clock
clock-names:
items:
- const: sclk_fimg2d
- const: fimg2d
additionalProperties: false
examples:
- |
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-rotator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung SoC Image Rotator
maintainers:
- Inki Dae <inki.dae@samsung.com>
properties:
compatible:
enum:
- samsung,s5pv210-rotator
- samsung,exynos4210-rotator
- samsung,exynos4212-rotator
- samsung,exynos5250-rotator
reg:
maxItems: 1
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: rotator
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
rotator@12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x1000>;
interrupts = <0 83 0>;
clocks = <&clock 278>;
clock-names = "rotator";
};
linux-7.2.3/Documentation/devicetree/bindings/gpu/samsung-scaler.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-scaler.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Image Scaler
maintainers:
- Inki Dae <inki.dae@samsung.com>
properties:
compatible:
enum:
- samsung,exynos5420-scaler
- samsung,exynos5433-scaler
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
iommus:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5420-scaler
then:
properties:
clocks:
items:
- description: mscl clock
clock-names:
items:
- const: mscl
iommus:
minItems: 2
else:
properties:
clocks:
items:
- description: pclk clock
- description: aclk clock
- description: aclk_xiu clock
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
iommus:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
scaler@12800000 {
compatible = "samsung,exynos5420-scaler";
reg = <0x12800000 0x1294>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MSCL0>;
clock-names = "mscl";
};
...
linux-7.2.3/Documentation/devicetree/bindings/gpu/vivante,gc.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Vivante GPU
description: Vivante GPU core devices
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
properties:
compatible:
const: vivante,gc
reg:
maxItems: 1
interrupts:
maxItems: 1
'#cooling-cells':
const: 2
assigned-clock-parents: true
assigned-clock-rates: true
assigned-clocks: true
clocks:
items:
- description: AXI/master interface clock
- description: GPU core clock
- description: Shader clock (only required if GPU has feature PIPE_3D)
- description: AHB/slave interface clock (only required if GPU can gate
slave interface independently)
minItems: 1
clock-names:
items:
enum: [ bus, core, shader, reg ]
minItems: 1
maxItems: 4
resets:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&gpc 1>;
};
...