lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml
+60
View File
@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed Coprocessor Vectored Interrupt Controller
maintainers:
- Andrew Jeffery <andrew@codeconstruct.com.au>
description:
The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts
to the ColdFire coprocessor. It's not a normal interrupt controller and it
would be rather inconvenient to create an interrupt tree for it, as it
somewhat shares some of the same sources as the main ARM interrupt controller
but with different numbers.
The AST2500 also supports a software generated interrupt.
properties:
compatible:
items:
- enum:
- aspeed,ast2400-cvic
- aspeed,ast2500-cvic
- const: aspeed,cvic
reg:
maxItems: 1
valid-sources:
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description:
A bitmap of supported sources for the implementation.
copro-sw-interrupts:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
A list of interrupt numbers that can be used as software interrupts from
the ARM to the coprocessor.
required:
- compatible
- reg
- valid-sources
additionalProperties: false
examples:
- |
interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic", "aspeed,cvic";
reg = <0x1e6c2000 0x80>;
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml
+26
View File
@@ -0,0 +1,26 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/fsl,dpaa2-console.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DPAA2 console support
maintainers:
- Laurentiu Tudor <laurentiu.tudor@nxp.com>
properties:
compatible:
const: fsl,dpaa2-console
reg:
maxItems: 1
description: A standard property. Specifies the region where the MCFBA
(MC firmware base address) register can be found.
required:
- compatible
- reg
additionalProperties: false
linux-7.2.3/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml
+187
View File
@@ -0,0 +1,187 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Management Complex
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
The Freescale Management Complex (fsl-mc) is a hardware resource
manager that manages specialized hardware objects used in
network-oriented packet processing applications. After the fsl-mc
block is enabled, pools of hardware resources are available, such as
queues, buffer pools, I/O interfaces. These resources are building
blocks that can be used to create functional hardware objects/devices
such as network interfaces, crypto accelerator instances, L2 switches,
etc.
For an overview of the DPAA2 architecture and fsl-mc bus see:
Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst
As described in the above overview, all DPAA2 objects in a DPRC share the
same hardware "isolation context" and a 10-bit value called an ICID
(isolation context id) is expressed by the hardware to identify
the requester.
The generic 'iommus' property is insufficient to describe the relationship
between ICIDs and IOMMUs, so an iommu-map property is used to define
the set of possible ICIDs under a root DPRC and how they map to
an IOMMU.
For generic IOMMU bindings, see
Documentation/devicetree/bindings/iommu/iommu.txt.
For arm-smmu binding, see:
Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
The MSI writes are accompanied by sideband data which is derived from the ICID.
The msi-map property is used to associate the devices with both the ITS
controller and the sideband data which accompanies the writes.
For generic MSI bindings, see
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
For GICv3 and GIC ITS bindings, see:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
properties:
compatible:
enum:
- fsl,qoriq-mc
description:
Must be "fsl,qoriq-mc". A Freescale Management Complex
compatible with this binding must have Block Revision
Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
the MC control register region.
reg:
items:
- description:
the first region is the command portal for the
this machine and must always be present
- description:
the second region is the MC control registers. This
region may not be present in some scenarios, such
as in the device tree presented to a virtual machine.
ranges:
description: |
A standard property. Defines the mapping between the child
MC address space and the parent system address space.
The MC address space is defined by 3 components:
<region type> <offset hi> <offset lo>
Valid values for region type are
0x0 - MC portals
0x1 - QBMAN portals
"#address-cells":
const: 3
"#size-cells":
const: 1
iommu-map:
description: |
Maps an ICID to an IOMMU and associated iommu-specifier
data.
The property is an arbitrary number of tuples of
(icid-base,iommu,iommu-base,length).
Any ICID i in the interval [icid-base, icid-base + length) is
associated with the listed IOMMU, with the iommu-specifier
(i - icid-base + iommu-base).
msi-map:
description: |
Maps an ICID to a GIC ITS and associated msi-specifier
data.
The property is an arbitrary number of tuples of
(icid-base,gic-its,msi-base,length).
Any ICID in the interval [icid-base, icid-base + length) is
associated with the listed GIC ITS, with the msi-specifier
(i - icid-base + msi-base).
msi-parent:
deprecated: true
maxItems: 1
description:
Describes the MSI controller node handling message
interrupts for the MC. When there is no translation
between the ICID and deviceID this property can be used
to describe the MSI controller used by the devices on the
mc-bus.
The use of this property for mc-bus is deprecated. Please
use msi-map.
dma-coherent: true
dpmacs:
type: object
description:
The fsl-mc node may optionally have dpmac sub-nodes that describe
the relationship between the Ethernet MACs which belong to the MC
and the Ethernet PHYs on the system board.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
'^ethernet@[a-f0-9]+$':
$ref: /schemas/net/fsl,qoriq-mc-dpmac.yaml
additionalProperties: false
required:
- compatible
- reg
- ranges
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x0c000000 0x40>, /* MC portal base */
<0x08340000 0x40000>; /* MC control reg */
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x8 0x18000000 0x8000000>;
/* define map for ICIDs 23-64 */
iommu-map = <23 &smmu 23 41>;
/* define msi map for ICIDs 23-64 */
msi-map = <23 &its 23 41>;
#address-cells = <3>;
#size-cells = <1>;
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <1>;
phy-handle = <&mdio0_phy0>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/ge-achc.yaml
+65
View File
@@ -0,0 +1,65 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
# Copyright (C) 2021 GE Inc.
# Copyright (C) 2021 Collabora Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ge-achc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GE Healthcare USB Management Controller
description: |
A device which handles data acquisition from compatible USB based peripherals.
SPI is used for device management.
Note: This device does not expose the peripherals as USB devices.
maintainers:
- Sebastian Reichel <sre@kernel.org>
properties:
compatible:
items:
- const: ge,achc
- const: nxp,kinetis-k20
clocks:
maxItems: 1
vdd-supply:
description: Digital power supply regulator on VDD pin
vdda-supply:
description: Analog power supply regulator on VDDA pin
reg:
items:
- description: Control interface
- description: Firmware programming interface
reset-gpios:
description: GPIO used for hardware reset.
maxItems: 1
required:
- compatible
- clocks
- reg
- reset-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
spi@1 {
compatible = "ge,achc", "nxp,kinetis-k20";
reg = <1>, <0>;
clocks = <&achc_24M>;
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/google,android-pipe.yaml
+38
View File
@@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/google,android-pipe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Android Goldfish QEMU Pipe
maintainers:
- Kuan-Wei Chiu <visitorckw@gmail.com>
description:
Android QEMU pipe virtual device generated by Android emulator.
properties:
compatible:
const: google,android-pipe
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
pipe@ff018000 {
compatible = "google,android-pipe";
reg = <0xff018000 0x2000>;
interrupts = <18>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/idt,89hpesx.yaml
+72
View File
@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/idt,89hpesx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
select:
properties:
compatible:
contains:
pattern: '^idt,89hpes'
required:
- compatible
properties:
compatible:
oneOf:
- pattern: '^idt,89hpes(8nt2|12nt3|12n3a?|24n3a?|(12|24)t3g2|4t4g2|10t4g2|[56]t5|8t5a?)$'
- pattern: '^idt,89hpes(6t6g2|16t7|(24t6|32t8|48t12|16t4a?)(g2)?)$'
- pattern: '^idt,89hpes(24nt6a|32nt8[ab]|12nt12|16nt16|24nt24|32nt24[ab])g2$'
- pattern: '^idt,89hpes((32h8|48h12a?|22h16|34h16|64h16a?)(g2)?|16h16)$'
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^eeprom@':
$ref: /schemas/eeprom/at24.yaml#
unevaluatedProperties: false
properties:
compatible:
description: Only a subset of devices are supported
pattern: ',24c(32|64|128|256|512)$'
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
idt@74 {
compatible = "idt,89hpes32nt8ag2";
reg = <0x74>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
read-only;
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/misc/ifm-csi.txt
+41
View File
@@ -0,0 +1,41 @@
IFM camera sensor interface on mpc5200 LocalPlus bus
Required properties:
- compatible: "ifm,o2d-csi"
- reg: specifies sensor chip select number and associated address range
- interrupts: external interrupt line number and interrupt sense mode
of the interrupt line signaling frame valid events
- gpios: three gpio-specifiers for "capture", "reset" and "master enable"
GPIOs (strictly in this order).
- ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
clock generator. This node is usually a general purpose timer controller.
- ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
- ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
- ifm,csi-wait-cycles: sensor bus wait cycles
Optional properties:
- ifm,csi-byte-swap: if this property is present, the byte swapping on
the bus will be enabled.
Example:
csi@3,0 {
compatible = "ifm,o2d-csi";
reg = <3 0 0x00100000>; /* CS 3, 1 MiB range */
interrupts = <1 1 2>; /* IRQ1, edge falling */
ifm,csi-clk-handle = <&timer7>;
gpios = <&gpio_simple 23 0 /* image_capture */
&gpio_simple 26 0 /* image_reset */
&gpio_simple 29 0>; /* image_master_en */
ifm,csi-addr-bus-width = <24>;
ifm,csi-data-bus-width = <8>;
ifm,csi-wait-cycles = <0>;
};
The base address of the used chip select is specified in the
ranges property of the parent localbus node, for example:
ranges = <0 0 0xff000000 0x01000000
3 0 0xe3000000 0x00100000>;
linux-7.2.3/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx AHB Queue Manager
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
The IXP4xx AHB Queue Manager maintains queues as circular buffers in
an 8KB embedded SRAM along with hardware pointers. It is used by both
the XScale processor and the NPEs (Network Processing Units) in the
IXP4xx for accelerating queues, especially for networking. Clients pick
queues from the queue manager with foo-queue = <&qmgr N> where the
&qmgr is a phandle to the queue manager and N is the queue resource
number. The queue resources available and their specific purpose
on a certain IXP4xx system will vary.
properties:
compatible:
items:
- const: intel,ixp4xx-ahb-queue-manager
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for queues 0-31
- description: Interrupt for queues 32-63
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/lwn,bk4-spi.yaml
+54
View File
@@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/lwn,bk4-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Liebherr's BK4 external SPI controller
maintainers:
- Lukasz Majewski <lukma@denx.de>
description: |
Liebherr's BK4 external SPI controller is a device which handles data
acquisition from compatible industrial peripherals.
The SPI is used for data and management purposes in both master and
slave modes.
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
const: lwn,bk4-spi
reg:
maxItems: 1
spi-max-frequency:
maximum: 30000000
fsl,spi-cs-sck-delay: true
fsl,spi-sck-cs-delay: true
required:
- compatible
- spi-max-frequency
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "lwn,bk4-spi";
reg = <0>;
spi-max-frequency = <30000000>;
fsl,spi-cs-sck-delay = <200>;
fsl,spi-sck-cs-delay = <400>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
+44
View File
@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) MISC register block
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: The MISC register block found on Tegra186 and later SoCs contains
registers that can be used to identify a given chip and various strapping
options.
properties:
compatible:
enum:
- nvidia,tegra186-misc
- nvidia,tegra194-misc
- nvidia,tegra234-misc
- nvidia,tegra264-misc
reg:
items:
- description: physical address and length of the registers which
contain revision and debug features
- description: physical address and length of the registers which
indicate strapping options
additionalProperties: false
required:
- compatible
- reg
examples:
- |
misc@100000 {
compatible = "nvidia,tegra186-misc";
reg = <0x00100000 0xf000>,
<0x0010f000 0x1000>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra APBMISC block
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- items:
- enum:
- nvidia,tegra210-apbmisc
- nvidia,tegra124-apbmisc
- nvidia,tegra114-apbmisc
- nvidia,tegra30-apbmisc
- const: nvidia,tegra20-apbmisc
- items:
- const: nvidia,tegra20-apbmisc
reg:
items:
- description: physical address and length of the registers which
contain revision and debug features
- description: physical address and length of the registers which
indicate strapping options
nvidia,long-ram-code:
description: If present, the RAM code is long (4 bit). If not, short
(2 bit).
type: boolean
additionalProperties: false
required:
- compatible
- reg
examples:
- |
apbmisc@70000800 {
compatible = "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64>, /* Chip revision */
<0x70000008 0x04>; /* Strapping options */
};
linux-7.2.3/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml
+56
View File
@@ -0,0 +1,56 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OLPC XO-1.75 Embedded Controller
description: |
This binding describes the Embedded Controller acting as a SPI bus master
on a OLPC XO-1.75 laptop computer.
The embedded controller requires the SPI controller driver to signal
readiness to receive a transfer (that is, when TX FIFO contains the
response data) by strobing the ACK pin with the ready signal. See the
"ready-gpios" property of the SSP binding as documented in:
<Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
compatible:
const: olpc,xo1.75-ec
cmd-gpios:
description: GPIO uspecifier of the CMD pin
maxItems: 1
spi-cpha: true
required:
- compatible
- cmd-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
spi-slave;
#address-cells = <0>;
#size-cells = <0>;
ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/misc/pci1de4,1.yaml
+143
View File
@@ -0,0 +1,143 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/pci1de4,1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RaspberryPi RP1 MFD PCI device
maintainers:
- A. della Porta <andrea.porta@suse.com>
description:
The RaspberryPi RP1 is a PCI multi function device containing
peripherals ranging from Ethernet to USB controller, I2C, SPI
and others.
The peripherals are accessed by addressing the PCI BAR1 region.
allOf:
- $ref: /schemas/pci/pci-ep-bus.yaml
properties:
compatible:
additionalItems: true
maxItems: 3
items:
- const: pci1de4,1
reg:
maxItems: 1
description: The PCI Bus-Device-Function address.
'#interrupt-cells':
const: 2
description: |
Specifies respectively the interrupt number and flags as defined
in include/dt-bindings/interrupt-controller/irq.h.
Since all interrupts are active high, only IRQ_TYPE_LEVEL_HIGH
and IRQ_TYPE_EDGE_RISING can be specified as type flags.
The supported values for the interrupt number are:
- IO BANK0: 0
- IO BANK1: 1
- IO BANK2: 2
- AUDIO IN: 3
- AUDIO OUT: 4
- PWM0: 5
- ETH: 6
- I2C0: 7
- I2C1: 8
- I2C2: 9
- I2C3: 10
- I2C4: 11
- I2C5: 12
- I2C6: 13
- I2S0: 14
- I2S1: 15
- I2S2: 16
- SDIO0: 17
- SDIO1: 18
- SPI0: 19
- SPI1: 20
- SPI2: 21
- SPI3: 22
- SPI4: 23
- SPI5: 24
- UART0: 25
- TIMER0: 26
- TIMER1: 27
- TIMER2: 28
- TIMER3: 29
- USB HOST0: 30
- USB HOST0-0: 31
- USB HOST0-1: 32
- USB HOST0-2: 33
- USB HOST0-3: 34
- USB HOST1: 35
- USB HOST1-0: 36
- USB HOST1-1: 37
- USB HOST1-2: 38
- USB HOST1-3: 39
- DMA: 40
- PWM1: 41
- UART1: 42
- UART2: 43
- UART3: 44
- UART4: 45
- UART5: 46
- MIPI0: 47
- MIPI1: 48
- VIDEO OUT: 49
- PIO0: 50
- PIO1: 51
- ADC FIFO: 52
- PCIE OUT: 53
- SPI6: 54
- SPI7: 55
- SPI8: 56
- PROC MISC: 57
- SYSCFG: 58
- CLOCKS DEFAULT: 59
- VBUSCTRL: 60
interrupt-controller: true
unevaluatedProperties: false
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- pci-ep-bus@1
examples:
- |
pci {
#address-cells = <3>;
#size-cells = <2>;
dev@0,0 {
compatible = "pci1de4,1";
reg = <0x10000 0x0 0x0 0x0 0x0>;
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
pci_ep_bus: pci-ep-bus@1 {
compatible = "simple-bus";
ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>;
dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>;
#address-cells = <2>;
#size-cells = <2>;
rp1_clocks: clocks@40018000 {
compatible = "raspberrypi,rp1-clocks";
reg = <0x00 0x40018000 0x0 0x10038>;
#clock-cells = <1>;
clocks = <&clk_rp1_xosc>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/pvpanic-mmio.txt
+29
View File
@@ -0,0 +1,29 @@
* QEMU PVPANIC MMIO Configuration bindings
QEMU's emulation / virtualization targets provide the following PVPANIC
MMIO Configuration interface on the "virt" machine.
type:
- a read-write, 16-bit wide data register.
QEMU exposes the data register to guests as memory mapped registers.
Required properties:
- compatible: "qemu,pvpanic-mmio".
- reg: the MMIO region used by the device.
* Bytes 0x0 Write panic event to the reg when guest OS panics.
* Bytes 0x1 Reserved.
Example:
/ {
#size-cells = <0x2>;
#address-cells = <0x2>;
pvpanic-mmio@9060000 {
compatible = "qemu,pvpanic-mmio";
reg = <0x0 0x9060000 0x0 0x2>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml
+157
View File
@@ -0,0 +1,157 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qcom,fastrpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm FastRPC Driver
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
The FastRPC implements an IPC (Inter-Processor Communication)
mechanism that allows for clients to transparently make remote method
invocations across DSP and APPS boundaries. This enables developers
to offload tasks to the DSP and free up the application processor for
other tasks.
properties:
compatible:
oneOf:
- enum:
- qcom,kaanapali-fastrpc
- qcom,fastrpc
- items:
- enum:
- qcom,glymur-fastrpc
- qcom,hawi-fastrpc
- const: qcom,kaanapali-fastrpc
label:
enum:
- adsp
- mdsp
- sdsp
- cdsp
- cdsp1
- gdsp0
- gdsp1
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for remote heap CMA.
qcom,glink-channels:
description:
A list of channels tied to this function, used for matching
the function to a set of virtual channels.
$ref: /schemas/types.yaml#/definitions/string-array
items:
- const: fastrpcglink-apps-dsp
qcom,non-secure-domain:
description:
Used to mark the current domain as non-secure.
type: boolean
qcom,smd-channels:
description:
Channel name used for the RPM communication
$ref: /schemas/types.yaml#/definitions/string-array
items:
- const: fastrpcsmd-apps-dsp
qcom,vmids:
description:
Virtual machine IDs for remote processor.
$ref: /schemas/types.yaml#/definitions/uint32-array
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"(compute-)?cb@[0-9]*$":
type: object
description: >
Each subnode of the Fastrpc represents compute context banks available on the dsp.
properties:
compatible:
const: qcom,fastrpc-compute-cb
reg:
maxItems: 1
dma-coherent: true
iommus:
minItems: 1
maxItems: 10
qcom,nsessions:
$ref: /schemas/types.yaml#/definitions/uint32
default: 1
description: >
A value indicating how many sessions can share this context bank.
required:
- compatible
- reg
additionalProperties: false
required:
- compatible
- label
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "sdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x0541 0x0>;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x0542 0x0>;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x0543 0x0>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/qemu,vcpu-stall-detector.yaml
+57
View File
@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qemu,vcpu-stall-detector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: VCPU stall detector
description:
This binding describes a CPU stall detector mechanism for virtual CPUs
which is accessed through MMIO.
maintainers:
- Sebastian Ene <sebastianene@google.com>
properties:
compatible:
enum:
- qemu,vcpu-stall-detector
reg:
maxItems: 1
clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The internal clock of the stall detector peripheral measure in Hz used
to decrement its internal counter register on each tick.
Defaults to 10 if unset.
default: 10
interrupts:
maxItems: 1
timeout-sec:
description: |
The stall detector expiration timeout measured in seconds.
Defaults to 8 if unset. Please note that it also takes into account the
time spent while the VCPU is not running.
default: 8
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
vmwdt@9030000 {
compatible = "qemu,vcpu-stall-detector";
reg = <0x9030000 0x10000>;
clock-frequency = <10>;
timeout-sec = <8>;
interrupts = <GIC_PPI 15 IRQ_TYPE_EDGE_RISING>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/ti,fpc202.yaml
+115
View File
@@ -0,0 +1,115 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ti,fpc202.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI FPC202 dual port controller with expanded IOs
maintainers:
- Romain Gantois <romain.gantois@bootlin.com>
allOf:
- $ref: /schemas/i2c/i2c-atr.yaml#
properties:
compatible:
const: ti,fpc202
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
enable-gpios:
description:
Specifier for the GPIO connected to the EN pin.
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^i2c@[0-1]$":
$ref: /schemas/i2c/i2c-controller.yaml#
description: Downstream device ports 0 and 1
properties:
reg:
maxItems: 1
description:
Downstream port ID
required:
- "#address-cells"
- "#size-cells"
- reg
unevaluatedProperties: false
"^led@1[4-b]$":
$ref: /schemas/leds/common.yaml#
description: Output GPIO line with advanced LED features enabled.
properties:
reg:
minimum: 0x14
maximum: 0x1b
description:
GPIO line ID
required:
- reg
unevaluatedProperties: false
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
i2c-atr@f {
compatible = "ti,fpc202";
reg = <0xf>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
led@14 {
reg = <0x14>;
label = "phy0:green:indicator";
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml
+53
View File
@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 ESM
maintainers:
- Neha Malcom Francis <n-francis@ti.com>
description:
The ESM (Error Signaling Module) is an IP block on TI K3 devices
that allows handling of safety events somewhat similar to what interrupt
controller would do. The safety signals have their separate paths within
the SoC, and they are handled by the ESM, which routes them to the proper
destination, which can be system reset, interrupt controller, etc. In the
simplest configuration the signals are just routed to reset the SoC.
properties:
compatible:
const: ti,j721e-esm
reg:
maxItems: 1
ti,esm-pins:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
integer array of ESM interrupt pins to route to external event pin
which can be used to reset the SoC.
minItems: 1
maxItems: 255
required:
- compatible
- reg
- ti,esm-pins
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
+140
View File
@@ -0,0 +1,140 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SDFEC(16nm) IP
maintainers:
- Cvetic, Dragan <dragan.cvetic@amd.com>
- Erim, Salih <salih.erim@amd.com>
description:
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
which provides high-throughput LDPC and Turbo Code implementations.
The LDPC decode & encode functionality is capable of covering a range of
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
principally covers codes used by LTE. The FEC Engine offers significant
power and area savings versus implementations done in the FPGA fabric.
properties:
compatible:
const: xlnx,sd-fec-1.1
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 8
additionalItems: true
items:
- description: Main processing clock for processing core
- description: AXI4-Lite memory-mapped slave interface clock
- description: Control input AXI4-Stream Slave interface clock
- description: DIN AXI4-Stream Slave interface clock
- description: Status output AXI4-Stream Master interface clock
- description: DOUT AXI4-Stream Master interface clock
- description: DIN_WORDS AXI4-Stream Slave interface clock
- description: DOUT_WORDS AXI4-Stream Master interface clock
clock-names:
allOf:
- minItems: 2
maxItems: 8
additionalItems: true
items:
- const: core_clk
- const: s_axi_aclk
- items:
enum:
- core_clk
- s_axi_aclk
- s_axis_ctrl_aclk
- s_axis_din_aclk
- m_axis_status_aclk
- m_axis_dout_aclk
- s_axis_din_words_aclk
- m_axis_dout_words_aclk
interrupts:
maxItems: 1
xlnx,sdfec-code:
description:
The SD-FEC integrated block supports Low Density Parity Check (LDPC)
decoding and encoding and Turbo code decoding. The LDPC codes used are
highly configurable, and the specific code used can be specified on
a codeword-by-codeword basis. The Turbo code decoding is required by LTE
standard.
$ref: /schemas/types.yaml#/definitions/string
items:
enum: [ ldpc, turbo ]
xlnx,sdfec-din-width:
description:
Configures the DIN AXI stream where a value of 1
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
of "4x128b".
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 4 ]
xlnx,sdfec-din-words:
description:
A value 0 indicates that the DIN_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DIN_WORDS to be block based, while a value of 2 configures the
DIN_WORDS input to be supplied for each AXI transaction.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2 ]
xlnx,sdfec-dout-width:
description:
Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b",
2 a width of "2x128b" and 4 configures a width of "4x128b".
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 4 ]
xlnx,sdfec-dout-words:
description:
A value 0 indicates that the DOUT_WORDS interface is
driven with a fixed value and is not present on the device, a value of 1
configures the DOUT_WORDS to be block based, while a value of 2 configures the
DOUT_WORDS input to be supplied for each AXI transaction.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2 ]
required:
- compatible
- reg
- clocks
- clock-names
- xlnx,sdfec-code
- xlnx,sdfec-din-width
- xlnx,sdfec-din-words
- xlnx,sdfec-dout-width
- xlnx,sdfec-dout-words
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
sd-fec@a0040000 {
compatible = "xlnx,sd-fec-1.1";
reg = <0xa0040000 0x40000>;
clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>,
<&misc_clk_1>, <&misc_clk_1>;
clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
"s_axis_din_aclk", "m_axis_status_aclk",
"m_axis_dout_aclk";
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
xlnx,sdfec-code = "ldpc";
xlnx,sdfec-din-width = <2>;
xlnx,sdfec-din-words = <0>;
xlnx,sdfec-dout-width = <1>;
xlnx,sdfec-dout-words = <0>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
+47
View File
@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Triple Modular Redundancy(TMR) Inject IP
maintainers:
- Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
description: |
The Triple Modular Redundancy(TMR) Inject core provides functional fault
injection by changing selected MicroBlaze instructions, which provides the
possibility to verify that the TMR subsystem error detection and fault
recovery logic is working properly.
properties:
compatible:
enum:
- xlnx,tmr-inject-1.0
reg:
maxItems: 1
xlnx,magic:
minimum: 0
maximum: 255
description: |
Magic number, When configured it allows the controller to perform
recovery.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- xlnx,magic
additionalProperties: false
examples:
- |
fault-inject@44a30000 {
compatible = "xlnx,tmr-inject-1.0";
reg = <0x44a10000 0x10000>;
xlnx,magic = <0x46>;
};
linux-7.2.3/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
+47
View File
@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Triple Modular Redundancy(TMR) Manager IP
maintainers:
- Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
description: |
The Triple Modular Redundancy(TMR) Manager is responsible for handling the
TMR subsystem state, including fault detection and error recovery. The core
is triplicated in each of the sub-blocks in the TMR subsystem, and provides
majority voting of its internal state.
properties:
compatible:
enum:
- xlnx,tmr-manager-1.0
reg:
maxItems: 1
xlnx,magic1:
minimum: 0
maximum: 255
description:
Magic byte 1, When configured it allows the controller to perform
recovery.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- xlnx,magic1
additionalProperties: false
examples:
- |
tmr-manager@44a10000 {
compatible = "xlnx,tmr-manager-1.0";
reg = <0x44a10000 0x10000>;
xlnx,magic1 = <0x46>;
};