lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
+146
View File
@@ -0,0 +1,146 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 NAND Controller
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- allwinner,sun4i-a10-nand
- allwinner,sun8i-a23-nand-controller
- allwinner,sun50i-h616-nand-controller
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
items:
- description: Bus Clock
- description: Module Clock
- description: ECC Clock
- description: MBus Clock
clock-names:
minItems: 2
items:
- const: ahb
- const: mod
- const: ecc
- const: mbus
resets:
maxItems: 1
reset-names:
const: ahb
dmas:
maxItems: 1
dma-names:
const: rxtx
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 7
nand-ecc-algo:
const: bch
nand-ecc-step-size:
enum: [ 512, 1024 ]
nand-ecc-strength:
maximum: 80
allwinner,rb:
description:
Contains the native Ready/Busy IDs.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 2
items:
minimum: 0
maximum: 1
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
allOf:
- $ref: nand-controller.yaml
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun4i-a10-nand
- allwinner,sun8i-a23-nand-controller
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun50i-h616-nand-controller
then:
properties:
clocks:
minItems: 4
clock-names:
minItems: 4
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
nand-controller@1c03000 {
compatible = "allwinner,sun8i-a23-nand-controller";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
dmas = <&dma 5>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
#address-cells = <1>;
#size-cells = <0>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
+124
View File
@@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
allOf:
- $ref: nand-controller.yaml
maintainers:
- liang.yang@amlogic.com
properties:
compatible:
enum:
- amlogic,meson-gxl-nfc
- amlogic,meson-axg-nfc
reg:
maxItems: 2
reg-names:
items:
- const: nfc
- const: emmc
interrupts:
maxItems: 1
clocks:
minItems: 2
clock-names:
items:
- const: core
- const: device
patternProperties:
"^nand@[0-7]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 1
nand-ecc-mode:
const: hw
nand-ecc-step-size:
enum: [512, 1024]
nand-ecc-strength:
enum: [8, 16, 24, 30, 40, 50, 60]
description: |
The ECC configurations that can be supported are as follows.
meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60
meson-axg-nfc 8
nand-rb:
maxItems: 1
items:
maximum: 0
amlogic,boot-pages:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of pages starting from offset 0, where a special ECC
configuration must be used because it is accessed by the ROM
code. This ECC configuration uses 384 bytes data blocks.
Also scrambling mode is enabled for such pages.
amlogic,boot-page-step:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Interval between pages, accessed by the ROM code. For example
we have 8 pages [0, 7]. Pages 0,2,4,6 are accessed by the
ROM code, so this field will be 2 (e.g. every 2nd page). Rest
of pages - 1,3,5,7 are read/written without this mode.
unevaluatedProperties: false
dependencies:
nand-ecc-strength: [nand-ecc-step-size]
nand-ecc-step-size: [nand-ecc-strength]
amlogic,boot-pages: [nand-is-boot-medium, "amlogic,boot-page-step"]
amlogic,boot-page-step: [nand-is-boot-medium, "amlogic,boot-pages"]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
nand-controller@ffe07800 {
compatible = "amlogic,meson-axg-nfc";
reg = <0xffe07800 0x100>, <0xffe07000 0x800>;
reg-names = "nfc", "emmc";
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "device";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-rb = <0>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml
+58
View File
@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arasan NAND Flash Controller with ONFI 3.1 support
allOf:
- $ref: nand-controller.yaml
maintainers:
- Michal Simek <michal.simek@amd.com>
properties:
compatible:
items:
- enum:
- xlnx,zynqmp-nand-controller
- const: arasan,nfc-v3p10
reg:
maxItems: 1
clocks:
items:
- description: Controller clock
- description: NAND bus clock
clock-names:
items:
- const: controller
- const: bus
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
unevaluatedProperties: false
examples:
- |
nfc: nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
reg = <0xff100000 0x1000>;
clock-names = "controller", "bus";
clocks = <&clk200>, <&clk100>;
interrupt-parent = <&gic>;
interrupts = <0 14 4>;
#address-cells = <1>;
#size-cells = <0>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
+52
View File
@@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PL353 NAND Controller
allOf:
- $ref: nand-controller.yaml
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
properties:
compatible:
items:
- const: arm,pl353-nand-r2p1
reg:
items:
- items:
- description: CS with regard to the parent ranges property
- description: Offset of the memory region requested by the device
- description: Length of the memory region requested by the device
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
smcc: memory-controller@e000e000 {
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
reg = <0xe000e000 0x0001000>;
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
#address-cells = <2>;
#size-cells = <1>;
nfc0: nand-controller@0,0 {
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/atmel,dataflash.yaml
+55
View File
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/atmel,dataflash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel DataFlash
maintainers:
- Nayab Sayed <nayabbasha.sayed@microchip.com>
description:
The Atmel DataFlash is a low pin-count serial interface sequential access
Flash memory, compatible with SPI standard. The device tree may optionally
contain sub-nodes describing partitions of the address space.
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at45db321d
- atmel,at45db041e
- atmel,at45db642d
- atmel,at45db021d
- const: atmel,at45
- const: atmel,dataflash
- items:
- const: atmel,at45
- const: atmel,dataflash
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- $ref: mtd.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
flash@1 {
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
reg = <1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+227
View File
@@ -0,0 +1,227 @@
Atmel NAND flash controller bindings
The NAND flash controller node should be defined under the EBI bus (see
Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
One or several NAND devices can be defined under this NAND controller.
The NAND controller might be connected to an ECC engine.
* NAND controller bindings:
Required properties:
- compatible: should be one of the following
"atmel,at91rm9200-nand-controller"
"atmel,at91sam9260-nand-controller"
"atmel,at91sam9261-nand-controller"
"atmel,at91sam9g45-nand-controller"
"atmel,sama5d3-nand-controller"
"microchip,sam9x60-nand-controller"
- ranges: empty ranges property to forward EBI ranges definitions.
- #address-cells: should be set to 2.
- #size-cells: should be set to 1.
- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
controllers.
- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
controllers.
Optional properties:
- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
a PMECC engine.
* NAND device/chip bindings:
Required properties:
- reg: describes the CS lines assigned to the NAND device. If the NAND device
exposes multiple CS lines (multi-dies chips), your reg property will
contain X tuples of 3 entries.
1st entry: the CS line this NAND chip is connected to
2nd entry: the base offset of the memory region assigned to this
device (always 0)
3rd entry: the memory region size (always 0x800000)
Optional properties:
- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
- cs-gpios: the GPIO(s) used to control the CS line.
- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
on sama5 SoCs.
All generic properties are described in the generic yaml files under
Documentation/devicetree/bindings/mtd/.
* ECC engine (PMECC) bindings:
Required properties:
- compatible: should be one of the following
"atmel,at91sam9g45-pmecc"
"atmel,sama5d4-pmecc"
"atmel,sama5d2-pmecc"
"microchip,sam9x60-pmecc"
"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
block, and the second one to the PMECC_ERRLOC block.
Example:
nfc_io: nfc-io@70000000 {
compatible = "atmel,sama5d3-nfc-io", "syscon";
reg = <0x70000000 0x8000000>;
};
pmecc: ecc-engine@ffffc070 {
compatible = "atmel,at91sam9g45-pmecc";
reg = <0xffffc070 0x490>,
<0xffffc500 0x100>;
};
ebi: ebi@10000000 {
compatible = "atmel,sama5d3-ebi";
#address-cells = <2>;
#size-cells = <1>;
atmel,smc = <&hsmc>;
reg = <0x10000000 0x10000000
0x40000000 0x30000000>;
ranges = <0x0 0x0 0x10000000 0x10000000
0x1 0x0 0x40000000 0x10000000
0x2 0x0 0x50000000 0x10000000
0x3 0x0 0x60000000 0x10000000>;
clocks = <&mck>;
nand_controller: nand-controller {
compatible = "atmel,sama5d3-nand-controller";
atmel,nfc-sram = <&nfc_sram>;
atmel,nfc-io = <&nfc_io>;
ecc-engine = <&pmecc>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
nand@3 {
reg = <0x3 0x0 0x800000>;
atmel,rb = <0>;
/*
* Put generic NAND/MTD properties and
* subnodes here.
*/
};
};
};
-----------------------------------------------------------------------
Deprecated bindings (should not be used in new device trees):
Required properties:
- compatible: The possible values are:
"atmel,at91rm9200-nand"
"atmel,sama5d2-nand"
"atmel,sama5d4-nand"
- reg : should specify localbus address and size used for the chip,
and hardware ECC controller if available.
If the hardware ECC is PMECC, it should contain address and size for
PMECC and PMECC Error Location controller.
The PMECC lookup table address and size in ROM is optional. If not
specified, driver will build it in runtime.
- atmel,nand-addr-offset : offset for the address latch.
- atmel,nand-cmd-offset : offset for the command latch.
- #address-cells, #size-cells : Must be present if the device has sub-nodes
representing partitions.
- gpios : specifies the gpio pins to control the NAND device. detect is an
optional gpio and may be set to 0 if not present.
Optional properties:
- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
"soft_bch".
- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
capable of BCH encoding and decoding, on devices where it is present.
- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
is "atmel,sama5d2-nand", 32 is also valid.
- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
are: 512, 1024.
- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
for different sector size. First one is for sector size 512, the next is for
sector size 1024. If not specified, driver will build the table in runtime.
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
Nand Flash Controller(NFC) is an optional sub-node
Required properties:
- compatible : "atmel,sama5d3-nfc".
- reg : should specify the address and size used for NFC command registers,
NFC registers and NFC SRAM. NFC SRAM address and size can be absent
if don't want to use it.
- clocks: phandle to the peripheral clock
Optional properties:
- atmel,write-by-sram: boolean to enable NFC write by SRAM.
Examples:
nand0: nand@40000000,0 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe800 0x200
>;
atmel,nand-addr-offset = <21>; /* ale */
atmel,nand-cmd-offset = <22>; /* cle */
nand-on-flash-bbt;
nand-ecc-mode = "soft";
gpios = <&pioC 13 0 /* rdy */
&pioC 14 0 /* nce */
0 /* cd */
>;
partition@0 {
...
};
};
/* for PMECC supported chips */
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x40000000 0x10000000 /* bus addr & size */
0xffffe000 0x00000600 /* PMECC addr & size */
0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
0x00100000 0x00100000 /* ROM addr & size */
>;
atmel,nand-addr-offset = <21>; /* ale */
atmel,nand-cmd-offset = <22>; /* cle */
nand-on-flash-bbt;
nand-ecc-mode = "hw";
atmel,has-pmecc; /* enable PMECC */
atmel,pmecc-cap = <2>;
atmel,pmecc-sector-size = <512>;
atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
gpios = <&pioD 5 0 /* rdy */
&pioD 4 0 /* nce */
0 /* cd */
>;
partition@0 {
...
};
};
/* for NFC supported chips */
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
ranges;
...
nfc@70000000 {
compatible = "atmel,sama5d3-nfc";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&hsmc_clk>
reg = <
0x70000000 0x10000000 /* NFC Command Registers */
0xffffc000 0x00000070 /* NFC HSMC regs */
0x00200000 0x00100000 /* NFC SRAM banks */
>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml
+278
View File
@@ -0,0 +1,278 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom STB NAND Controller
maintainers:
- Brian Norris <computersforpeace@gmail.com>
- Kamal Dasu <kdasu.kdev@gmail.com>
- William Zhang <william.zhang@broadcom.com>
description: |
The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
flash chips. It has a memory-mapped register interface for both control
registers and for its data input/output buffer. On some SoCs, this controller
is paired with a custom DMA engine (inventively named "Flash DMA") which
supports basic PROGRAM and READ functions, among other features.
This controller was originally designed for STB SoCs (BCM7xxx) but is now
available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
Its history includes several similar (but not fully register compatible)
versions.
-- Additional SoC-specific NAND controller properties --
The NAND controller is integrated differently on the variety of SoCs on which
it is found. Part of this integration involves providing status and enable
bits with which to control the 8 exposed NAND interrupts, as well as hardware
for configuring the endianness of the data bus. On some SoCs, these features
are handled via standard, modular components (e.g., their interrupts look like
a normal IRQ chip), but on others, they are controlled in unique and
interesting ways, sometimes with registers that lump multiple NAND-related
functions together. The former case can be described simply by the standard
interrupts properties in the main controller node. But for the latter
exceptional cases, we define additional 'compatible' properties and associated
register resources within the NAND controller node above.
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,brcmnand-v2.1
- brcm,brcmnand-v2.2
- brcm,brcmnand-v4.0
- brcm,brcmnand-v5.0
- brcm,brcmnand-v6.0
- brcm,brcmnand-v6.1
- brcm,brcmnand-v6.2
- brcm,brcmnand-v7.0
- brcm,brcmnand-v7.1
- brcm,brcmnand-v7.2
- brcm,brcmnand-v7.3
- const: brcm,brcmnand
- description: BCMBCA SoC-specific NAND controller
items:
- const: brcm,nand-bcm63138
- enum:
- brcm,brcmnand-v7.0
- brcm,brcmnand-v7.1
- const: brcm,brcmnand
- description: iProc SoC-specific NAND controller
items:
- const: brcm,nand-iproc
- const: brcm,brcmnand-v6.1
- description: BCM63168 SoC-specific NAND controller
items:
- const: brcm,nand-bcm63168
- const: brcm,nand-bcm6368
- const: brcm,brcmnand-v4.0
- const: brcm,brcmnand
reg:
minItems: 1
maxItems: 6
reg-names:
minItems: 1
maxItems: 6
items:
enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
interrupts:
minItems: 1
items:
- description: NAND CTLRDY interrupt
- description: FLASH_DMA_DONE (if flash DMA is available) or FLASH_EDU_DONE (if EDU is available)
interrupt-names:
minItems: 1
items:
- const: nand_ctlrdy
- enum:
- flash_dma_done
- flash_edu_done
clocks:
maxItems: 1
description: reference to the clock for the NAND controller
clock-names:
const: nand
brcm,nand-has-wp:
description: >
Some versions of this IP include a write-protect
(WP) control bit. It is always available on >=
v7.0. Use this property to describe the rare
earlier versions of this core that include WP
type: boolean
brcm,wp-not-connected:
description:
Use this property when WP pin is not physically wired to the NAND chip.
Write protection feature cannot be used. By default, controller assumes
the pin is connected and feature is used.
$ref: /schemas/types.yaml#/definitions/flag
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
compatible:
const: brcm,nandcs
nand-ecc-step-size:
enum: [ 512, 1024 ]
brcm,nand-oob-sector-size:
description: |
integer, to denote the spare area sector size
expected for the ECC layout in use. This size, in
addition to the strength and step-size,
determines how the hardware BCH engine will lay
out the parity bytes it stores on the flash.
This property can be automatically determined by
the flash geometry (particularly the NAND page
and OOB size) in many cases, but when booting
from NAND, the boot controller has only a limited
number of available options for its default ECC
layout.
$ref: /schemas/types.yaml#/definitions/uint32
brcm,nand-ecc-use-strap:
description:
This property requires the host system to get the ECC related
settings from the SoC NAND boot strap configuration instead of
the generic NAND ECC settings. This is a common hardware design
on BCMBCA based boards. This strap ECC option and generic NAND
ECC option can not be specified at the same time.
$ref: /schemas/types.yaml#/definitions/flag
unevaluatedProperties: false
allOf:
- $ref: nand-controller.yaml#
- if:
properties:
compatible:
contains:
const: brcm,nand-bcm63138
then:
properties:
reg-names:
items:
- const: nand
- const: nand-int-base
- if:
properties:
compatible:
contains:
const: brcm,nand-bcm6368
then:
properties:
reg-names:
items:
- const: nand
- const: nand-int-base
- const: nand-cache
- if:
properties:
compatible:
contains:
const: brcm,nand-iproc
then:
properties:
reg-names:
items:
- const: nand
- const: iproc-idm
- const: iproc-ext
- if:
required:
- interrupts
properties:
interrupts:
minItems: 2
then:
required:
- interrupt-names
- if:
patternProperties:
"^nand@[a-f0-9]$":
required:
- brcm,nand-ecc-use-strap
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-strength: false
nand-ecc-step-size: false
nand-ecc-maximize: false
nand-ecc-algo: false
brcm,nand-oob-sector-size: false
unevaluatedProperties: false
required:
- reg
- reg-names
examples:
- |
nand-controller@f0442800 {
compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
reg = <0xf0442800 0x600>,
<0xf0443000 0x100>;
reg-names = "nand", "flash-dma";
interrupt-parent = <&hif_intr2_intc>;
interrupts = <24>, <4>;
interrupt-names = "nand_ctlrdy", "flash_dma_done";
#address-cells = <1>;
#size-cells = <0>;
nand@1 {
compatible = "brcm,nandcs";
reg = <1>; // Chip select 1
nand-on-flash-bbt;
nand-ecc-strength = <12>;
nand-ecc-step-size = <512>;
#address-cells = <1>;
#size-cells = <1>;
};
};
- |
nand-controller@10000200 {
compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
"brcm,brcmnand-v4.0", "brcm,brcmnand";
reg = <0x10000200 0x180>,
<0x100000b0 0x10>,
<0x10000600 0x200>;
reg-names = "nand", "nand-int-base", "nand-cache";
interrupt-parent = <&periph_intc>;
interrupts = <50>;
clocks = <&periph_clk 20>;
clock-names = "nand";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
#address-cells = <1>;
#size-cells = <1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+86
View File
@@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence NAND controller
maintainers:
- Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
allOf:
- $ref: nand-controller.yaml
properties:
compatible:
items:
- const: cdns,hp-nfc
reg:
items:
- description: Controller register set
- description: Slave DMA data port register set
reg-names:
items:
- const: reg
- const: sdma
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nf_clk
dmas:
maxItems: 1
dma-coherent: true
iommus:
maxItems: 1
cdns,board-delay-ps:
description: |
Estimated Board delay. The value includes the total round trip
delay for the signals and is used for deciding on values associated
with data read capture. The example formula for SDR mode is the
following.
board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+ DQ PAD delay
required:
- compatible
- reg
- reg-names
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
nand-controller@10b80000 {
compatible = "cdns,hp-nfc";
reg = <0x10b80000 0x10000>,
<0x10840000 0x10000>;
reg-names = "reg", "sdma";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk>;
clock-names = "nf_clk";
cdns,board-delay-ps = <4830>;
nand@0 {
reg = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/denali,nand.yaml
+153
View File
@@ -0,0 +1,153 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Denali NAND controller
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
enum:
- altr,socfpga-denali-nand
- socionext,uniphier-denali-nand-v5a
- socionext,uniphier-denali-nand-v5b
reg-names:
description: |
There are two register regions:
nand_data: host data/command interface
denali_reg: register interface
items:
- const: nand_data
- const: denali_reg
reg:
minItems: 2
maxItems: 2
interrupts:
maxItems: 1
clock-names:
description: |
There are three clocks:
nand: controller core clock
nand_x: bus interface clock
ecc: ECC circuit clock
items:
- const: nand
- const: nand_x
- const: ecc
clocks:
minItems: 3
maxItems: 3
reset-names:
description: |
There are two optional resets:
nand: controller core reset
reg: register reset
oneOf:
- items:
- const: nand
- const: reg
- const: nand
- const: reg
resets:
minItems: 1
maxItems: 2
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
unevaluatedProperties: false
allOf:
- $ref: nand-controller.yaml
- if:
properties:
compatible:
contains:
const: altr,socfpga-denali-nand
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-strength:
enum:
- 8
- 15
nand-ecc-step-size:
enum:
- 512
- if:
properties:
compatible:
contains:
const: socionext,uniphier-denali-nand-v5a
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-strength:
enum:
- 8
- 16
- 24
nand-ecc-step-size:
enum:
- 1024
- if:
properties:
compatible:
contains:
const: socionext,uniphier-denali-nand-v5b
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-strength:
enum:
- 8
- 16
nand-ecc-step-size:
enum:
- 1024
required:
- compatible
- reg
- interrupts
- clock-names
- clocks
unevaluatedProperties: false
examples:
- |
nand-controller@ff900000 {
compatible = "altr,socfpga-denali-nand";
reg-names = "nand_data", "denali_reg";
reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
interrupts = <0 144 4>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
reset-names = "nand", "reg";
resets = <&nand_rst>, <&nand_reg_rst>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/diskonchip.txt
+15
View File
@@ -0,0 +1,15 @@
M-Systems and Sandisk DiskOnChip devices
M-System DiskOnChip G3
======================
The Sandisk (formerly M-Systems) docg3 is a nand device of 64M to 256MB.
Required properties:
- compatible: should be "m-systems,diskonchip-g3"
- reg: register base and size
Example:
docg3: flash@0 {
compatible = "m-systems,diskonchip-g3";
reg = <0x0 0x2000>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/flctl-nand.txt
+49
View File
@@ -0,0 +1,49 @@
FLCTL NAND controller
Required properties:
- compatible : "renesas,shmobile-flctl-sh7372"
- reg : Address range of the FLCTL
- interrupts : flste IRQ number
- nand-bus-width : bus width to NAND chip
Optional properties:
- dmas: DMA specifier(s)
- dma-names: name for each DMA specifier. Valid names are
"data_tx", "data_rx", "ecc_tx", "ecc_rx"
The DMA fields are not used yet in the driver but are listed here for
completing the bindings.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See mtd.yaml for more detail.
Example:
flctl@e6a30000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "renesas,shmobile-flctl-sh7372";
reg = <0xe6a30000 0x100>;
interrupts = <0x0d80>;
nand-bus-width = <16>;
dmas = <&dmac 1 /* data_tx */
&dmac 2;> /* data_rx */
dma-names = "data_tx", "data_rx";
system@0 {
label = "system";
reg = <0x0 0x8000000>;
};
userdata@8000000 {
label = "userdata";
reg = <0x8000000 0x10000000>;
};
cache@18000000 {
label = "cache";
reg = <0x18000000 0x8000000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/fsl,vf610-nfc.yaml
+89
View File
@@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/fsl,vf610-nfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale's NAND flash controller (NFC)
description:
This variant of the Freescale NAND flash controller (NFC) can be found on
Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
enum:
- fsl,vf610-nfc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nfc
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
compatible:
const: fsl,vf610-nfc-nandcs
reg:
const: 0
nand-ecc-strength:
enum: [24, 32]
nand-ecc-step-size:
const: 2048
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
allOf:
- $ref: nand-controller.yaml
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/vf610-clock.h>
nand-controller@400e0000 {
compatible = "fsl,vf610-nfc";
reg = <0x400e0000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_NFC>;
clock-names = "nfc";
assigned-clocks = <&clks VF610_CLK_NFC>;
assigned-clock-rates = <33000000>;
nand@0 {
compatible = "fsl,vf610-nfc-nandcs";
reg = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <32>;
nand-ecc-step-size = <2048>;
nand-on-flash-bbt;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+67
View File
@@ -0,0 +1,67 @@
Freescale Localbus UPM programmed to work with NAND flash
Required properties:
- compatible : "fsl,upm-nand".
- reg : should specify localbus chip select and size used for the chip.
- fsl,upm-addr-offset : UPM pattern offset for the address latch.
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
Optional properties:
- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
The corresponding address lines are used to select the chip.
- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
(R/B#). For multi-chip devices, "n" GPIO definitions are required
according to the number of chips.
Deprecated properties:
- fsl,upm-wait-flags : add chip-dependent short delays after running the
UPM pattern (0x1), after writing a data byte (0x2) or after
writing out a buffer (0x4).
- chip-delay : chip dependent delay for transferring data from array to
read registers (tR). Required if property "gpios" is not used
(R/B# pins not connected).
Each flash chip described may optionally contain additional sub-nodes
describing partitions of the address space. See mtd.yaml for more
detail.
Examples:
upm@1,0 {
compatible = "fsl,upm-nand";
reg = <1 0 1>;
fsl,upm-addr-offset = <16>;
fsl,upm-cmd-offset = <8>;
gpios = <&qe_pio_e 18 0>;
flash {
#address-cells = <1>;
#size-cells = <1>;
compatible = "...";
partition@0 {
...
};
};
};
upm@3,0 {
#address-cells = <0>;
#size-cells = <0>;
compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
reg = <3 0x0 0x800>;
fsl,upm-addr-offset = <0x10>;
fsl,upm-cmd-offset = <0x08>;
/* Multi-chip NAND device */
fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
nand@0 {
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "fs";
reg = <0x00000000 0x10000000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+60
View File
@@ -0,0 +1,60 @@
ST Microelectronics Flexible Static Memory Controller (FSMC)
NAND Interface
Required properties:
- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
- reg : Address range of the mtd chip
- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
Optional properties:
- bank-width : Width (in bytes) of the device. If not present, the width
defaults to 1 byte
- nand-skip-bbtscan: Indicates the BBT scanning should be skipped
- timings: array of 6 bytes for NAND timings. The meanings of these bytes
are:
byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
are valid. Zero means one clockcycle, 15 means 16 clock
cycles.
byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
byte 2 THIZ : number of HCLK clock cycles during which the data bus is
kept in Hi-Z (tristate) after the start of a write access.
Only valid for write transactions. Zero means zero cycles,
255 means 255 cycles.
byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
when writing) after the command deassertation. Zero means
one cycle, 255 means 256 cycles.
byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
NAND flash in response to SMWAITn. Zero means 1 cycle,
255 means 256 cycles.
byte 5 TSET : number of HCLK clock cycles to assert the address before the
command is asserted. Zero means one cycle, 255 means 256
cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default).
- nand-ecc-mode : see nand-controller.yaml
- nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : see nand-controller.yaml
Can support 1-bit HW ECC (default) or if stronger correction is required,
software-based BCH.
Example:
fsmc: flash@d1800000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd1800000 0x1000 /* FSMC Register */
0xd2000000 0x0010 /* NAND Base DATA */
0xd2020000 0x0010 /* NAND Base ADDR */
0xd2010000 0x0010>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
bank-width = <1>;
nand-skip-bbtscan;
timings = /bits/ 8 <0 0 0 2 3 0>;
bank = <1>;
partition@0 {
...
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
+47
View File
@@ -0,0 +1,47 @@
GPIO assisted NAND flash
The GPIO assisted NAND flash uses a memory mapped interface to
read/write the NAND commands and data and GPIO pins for the control
signals.
Required properties:
- compatible : "gpio-control-nand"
- reg : should specify localbus chip select and size used for the chip. The
resource describes the data bus connected to the NAND flash and all accesses
are made in native endianness.
- #address-cells, #size-cells : Must be present if the device has sub-nodes
representing partitions.
- gpios : Specifies the GPIO pins to control the NAND device. The order of
GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
Optional properties:
- bank-width : Width (in bytes) of the device. If not present, the width
defaults to 1 byte.
- chip-delay : chip dependent delay for transferring data from array to
read registers (tR). If not present then a default of 20us is used.
- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
location used to guard against bus reordering with regards to accesses to
the GPIO's and the NAND flash data bus. If present, then after changing
GPIO state and before and after command byte writes, this register will be
read to ensure that the GPIO accesses have completed.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See mtd.yaml for more detail.
Examples:
gpio-nand@1,0 {
compatible = "gpio-control-nand";
reg = <1 0x0000 0x2>;
#address-cells = <1>;
#size-cells = <1>;
gpios = <&banka 1 0>, /* RDY */
<0>, /* nCE */
<&banka 3 0>, /* ALE */
<&banka 4 0>, /* CLE */
<0>; /* nWP */
partition@0 {
...
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
+197
View File
@@ -0,0 +1,197 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale General-Purpose Media Interface (GPMI)
maintainers:
- Han Xu <han.xu@nxp.com>
description: |
The GPMI nand controller provides an interface to control the NAND
flash chips. The device tree may optionally contain sub-nodes
describing partitions of the address space. See mtd.yaml for
more detail.
properties:
compatible:
oneOf:
- enum:
- fsl,imx23-gpmi-nand
- fsl,imx28-gpmi-nand
- fsl,imx6q-gpmi-nand
- fsl,imx6sx-gpmi-nand
- fsl,imx7d-gpmi-nand
- fsl,imx8qxp-gpmi-nand
- items:
- enum:
- fsl,imx8mm-gpmi-nand
- fsl,imx8mn-gpmi-nand
- fsl,imx8mp-gpmi-nand
- fsl,imx8mq-gpmi-nand
- const: fsl,imx7d-gpmi-nand
- items:
- enum:
- fsl,imx8dxl-gpmi-nand
- fsl,imx8qm-gpmi-nand
- const: fsl,imx8qxp-gpmi-nand
reg:
items:
- description: Address and length of gpmi block.
- description: Address and length of bch block.
reg-names:
items:
- const: gpmi-nand
- const: bch
interrupts:
maxItems: 1
interrupt-names:
const: bch
dmas:
maxItems: 1
dma-names:
const: rx-tx
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
fsl,use-minimum-ecc:
type: boolean
description: |
Protect this NAND flash with the minimum ECC strength required.
The required ECC strength is automatically discoverable for some
flash (e.g., according to the ONFI standard). However, note that
if this strength is not discoverable or this property is not enabled,
the software may chooses an implementation-defined ECC scheme.
fsl,no-blockmark-swap:
type: boolean
description: |
Don't swap the bad block marker from the OOB area with the byte in
the data area but rely on the flash based BBT for identifying bad blocks.
NOTE: this is only valid in conjunction with 'nand-on-flash-bbt'.
WARNING: on i.MX28 blockmark swapping cannot be disabled for the BootROM
in the FCB. Thus, partitions written from Linux with this feature turned
on may not be accessible by the BootROM code.
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
- dmas
- dma-names
unevaluatedProperties: false
allOf:
- $ref: nand-controller-legacy.yaml
- if:
properties:
compatible:
contains:
enum:
- fsl,imx23-gpmi-nand
- fsl,imx28-gpmi-nand
then:
properties:
clocks:
items:
- description: SoC gpmi io clock
clock-names:
items:
- const: gpmi_io
- if:
properties:
compatible:
contains:
enum:
- fsl,imx6q-gpmi-nand
- fsl,imx6sx-gpmi-nand
then:
properties:
clocks:
items:
- description: SoC gpmi io clock
- description: SoC gpmi apb clock
- description: SoC gpmi bch clock
- description: SoC gpmi bch apb clock
- description: SoC per1 bch clock
clock-names:
items:
- const: gpmi_io
- const: gpmi_apb
- const: gpmi_bch
- const: gpmi_bch_apb
- const: per1_bch
- if:
properties:
compatible:
contains:
const: fsl,imx7d-gpmi-nand
then:
properties:
clocks:
items:
- description: SoC gpmi io clock
- description: SoC gpmi bch apb clock
clock-names:
items:
- const: gpmi_io
- const: gpmi_bch_apb
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-gpmi-nand
then:
properties:
clocks:
items:
- description: SoC gpmi io clock
- description: SoC gpmi apb clock
- description: SoC gpmi bch clock
- description: SoC gpmi bch apb clock
clock-names:
items:
- const: gpmi_io
- const: gpmi_apb
- const: gpmi_bch
- const: gpmi_bch_apb
examples:
- |
nand-controller@8000c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-gpmi-nand";
reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <41>;
interrupt-names = "bch";
clocks = <&clks 50>;
clock-names = "gpmi_io";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/hisi504-nand.txt
+47
View File
@@ -0,0 +1,47 @@
Hisilicon Hip04 Soc NAND controller DT binding
Required properties:
- compatible: Should be "hisilicon,504-nfc".
- reg: The first contains base physical address and size of
NAND controller's registers. The second contains base
physical address and size of NAND controller's buffer.
- interrupts: Interrupt number for nfc.
- nand-bus-width: See nand-controller.yaml.
- nand-ecc-mode: Support none and hw ecc mode.
- #address-cells: Partition address, should be set 1.
- #size-cells: Partition size, should be set 1.
Optional properties:
- nand-ecc-strength: Number of bits to correct per ECC step.
- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
Flash chip may optionally contain additional sub-nodes describing partitions of
the address space. See mtd.yaml for more detail.
Example:
nand: nand@4020000 {
compatible = "hisilicon,504-nfc";
reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
interrupts = <0 379 4>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <16>;
nand-ecc-step-size = <1024>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nand_text";
reg = <0x00000000 0x00400000>;
};
...
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt
+24
View File
@@ -0,0 +1,24 @@
HiSilicon SPI-NOR Flash Controller
Required properties:
- compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
"hisilicon,hi3519-spi-nor"
- address-cells : Should be 1.
- size-cells : Should be 0.
- reg : Offset and length of the register set for the controller device.
- reg-names : Must include the following two entries: "control", "memory".
- clocks : handle to spi-nor flash controller clock.
Example:
spi-nor-controller@10000000 {
compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
reg-names = "control", "memory";
clocks = <&clock HI3519_FMC_CLK>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ibm,ndfc.txt
+39
View File
@@ -0,0 +1,39 @@
AMCC NDFC (NanD Flash Controller)
Required properties:
- compatible : "ibm,ndfc".
- reg : should specify chip select and size used for the chip (0x2000).
Optional properties:
- ccr : NDFC config and control register value (default 0).
- bank-settings : NDFC bank configuration register value (default 0).
Notes:
- partition(s) - follows the OF MTD standard for partitions
Example:
ndfc@1,0 {
compatible = "ibm,ndfc";
reg = <0x00000001 0x00000000 0x00002000>;
ccr = <0x00001000>;
bank-settings = <0x80002222>;
#address-cells = <1>;
#size-cells = <1>;
nand {
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x00200000>;
};
partition@200000 {
label = "root";
reg = <0x00200000 0x03E00000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
+139
View File
@@ -0,0 +1,139 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs NAND controller
maintainers:
- Paul Cercueil <paul@crapouillou.net>
allOf:
- $ref: nand-controller.yaml#
- $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
properties:
compatible:
enum:
- ingenic,jz4740-nand
- ingenic,jz4725b-nand
- ingenic,jz4780-nand
reg:
items:
- description: Bank number, offset and size of first attached NAND chip
- description: Bank number, offset and size of second attached NAND chip
- description: Bank number, offset and size of third attached NAND chip
- description: Bank number, offset and size of fourth attached NAND chip
minItems: 1
ecc-engine: true
partitions:
type: object
deprecated: true
description:
Node containing description of fixed partitions.
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
rb-gpios:
description: GPIO specifier for the busy pin.
maxItems: 1
wp-gpios:
description: GPIO specifier for the write-protect pin.
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
memory-controller@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000>,
<2 0 0x1a000000 0x1000000>,
<3 0 0x19000000 0x1000000>,
<4 0 0x18000000 0x1000000>,
<5 0 0x17000000 0x1000000>,
<6 0 0x16000000 0x1000000>;
clocks = <&cgu JZ4780_CLK_NEMC>;
nand-controller@1 {
compatible = "ingenic,jz4780-nand";
reg = <1 0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
ecc-engine = <&bch>;
ingenic,nemc-tAS = <10>;
ingenic,nemc-tAH = <5>;
ingenic,nemc-tBP = <10>;
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc>;
nand@1 {
reg = <1>;
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc_cs1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <2>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x0 0x0 0x800000>;
};
partition@800000 {
label = "u-boot";
reg = <0x0 0x800000 0x0 0x200000>;
};
partition@a00000 {
label = "u-boot-env";
reg = <0x0 0xa00000 0x0 0x200000>;
};
partition@c00000 {
label = "boot";
reg = <0x0 0xc00000 0x0 0x4000000>;
};
partition@4c00000 {
label = "system";
reg = <0x0 0x4c00000 0x1 0xfb400000>;
};
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml
+90
View File
@@ -0,0 +1,90 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel LGM SoC NAND Controller
allOf:
- $ref: nand-controller.yaml
maintainers:
- Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
properties:
compatible:
const: intel,lgm-ebunand
reg:
maxItems: 6
reg-names:
items:
- const: ebunand
- const: hsnand
- const: nand_cs0
- const: nand_cs1
- const: addr_sel0
- const: addr_sel1
clocks:
maxItems: 1
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 1
nand-ecc-algo:
const: hw
unevaluatedProperties: false
required:
- compatible
- reg
- reg-names
- clocks
- dmas
- dma-names
unevaluatedProperties: false
examples:
- |
nand-controller@e0f00000 {
compatible = "intel,lgm-ebunand";
reg = <0xe0f00000 0x100>,
<0xe1000000 0x300>,
<0xe1400000 0x8000>,
<0xe1c00000 0x1000>,
<0x17400000 0x4>,
<0x17c00000 0x4>;
reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
"addr_sel0", "addr_sel1";
clocks = <&cgu0 125>;
dmas = <&dma0 8>, <&dma0 9>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+127
View File
@@ -0,0 +1,127 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
maintainers:
- Rob Herring <robh@kernel.org>
allOf:
- $ref: mtd.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
oneOf:
- items:
- pattern: "^((((micron|spansion|st),)?\
(m25p(40|80|16|32|64|128)|\
n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
atmel,at(25|26)df(321a|641|081a)|\
everspin,mr25h(10|40|128|256)|\
(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
(mxicy|macronix),mx25u(4033|4035)|\
(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
(sst|microchip),sst25vf(016b|032b|040b)|\
(sst,)?sst26wf016b|\
(sst,)?sst25wf(040b|080)|\
winbond,w25x(80|32)|\
(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
- const: jedec,spi-nor
- items:
- enum:
- issi,is25lp016d
- micron,mt25qu02g
- mxicy,mx25r1635f
- mxicy,mx25u6435f
- mxicy,mx25v8035f
- spansion,s25sl12801
- spansion,s25fs512s
- const: jedec,spi-nor
- const: jedec,spi-nor
description:
SPI NOR flashes compatible with the JEDEC SFDP standard or which may be
identified with the READ ID opcode (0x9F) do not deserve a specific
compatible. They should instead only be matched against the generic
"jedec,spi-nor" compatible.
reg:
minItems: 1
maxItems: 2
interrupts:
maxItems: 1
m25p,fast-read:
type: boolean
description:
Use the "fast read" opcode to read data from the chip instead of the usual
"read" opcode. This opcode is not supported by all chips and support for
it can not be detected at runtime. Refer to your chips' datasheet to check
if this is supported by your chip.
broken-flash-reset:
type: boolean
description:
Some flash devices utilize stateful addressing modes (e.g., for 32-bit
addressing) which need to be managed carefully by a system. Because these
sorts of flash don't have a standardized software reset command, and
because some systems don't toggle the flash RESET# pin upon system reset
(if the pin even exists at all), there are systems which cannot reboot
properly if the flash is left in the "wrong" state. This boolean flag can
be used on such systems, to denote the absence of a reliable reset
mechanism.
no-wp:
type: boolean
description:
The status register write disable (SRWD) bit in status register, combined
with the WP# signal, provides hardware data protection for the device. When
the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
strapped to LOW, the status register nonvolatile bits become read-only and
the WRITE STATUS REGISTER operation will not execute. The only way to exit
this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the
flash device is not connected or is wrongly tied to GND (that includes internal
pull-downs) then status register permanently becomes read-only as the SRWD bit
cannot be reset. This boolean flag can be used on such systems to avoid setting
the SRWD bit while writing the status register. WP# signal hard strapped to GND
can be a valid use case.
reset-gpios:
description:
A GPIO line connected to the RESET (active low) signal of the device.
If "broken-flash-reset" is present then having this property does not
make any difference.
vcc-supply:
description:
Supply for the SPI NOR power.
spi-cpol: true
spi-cpha: true
dependencies:
spi-cpol: [ spi-cpha ]
spi-cpha: [ spi-cpol ]
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
m25p,fast-read;
reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml
+122
View File
@@ -0,0 +1,122 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson NAND Controller
maintainers:
- Keguang Zhang <keguang.zhang@gmail.com>
- Binbin Zhou <zhoubinbin@loongson.cn>
description:
The Loongson NAND controller abstracts all supported operations,
meaning it does not support low-level access to raw NAND flash chips.
Moreover, the controller is paired with the DMA engine to perform
READ and PROGRAM functions.
allOf:
- $ref: nand-controller.yaml
properties:
compatible:
oneOf:
- enum:
- loongson,ls1b-nand-controller
- loongson,ls1c-nand-controller
- loongson,ls2k0500-nand-controller
- loongson,ls2k1000-nand-controller
- items:
- enum:
- loongson,ls1a-nand-controller
- const: loongson,ls1b-nand-controller
reg:
minItems: 2
maxItems: 3
reg-names:
minItems: 2
items:
- const: nand
- const: nand-dma
- const: dma-config
dmas:
maxItems: 1
dma-names:
const: rxtx
required:
- compatible
- reg
- reg-names
- dmas
- dma-names
unevaluatedProperties: false
if:
properties:
compatible:
contains:
enum:
- loongson,ls2k1000-nand-controller
then:
properties:
reg:
minItems: 3
reg-names:
minItems: 3
else:
properties:
reg:
maxItems: 2
reg-names:
maxItems: 2
examples:
- |
nand-controller@1fe78000 {
compatible = "loongson,ls1b-nand-controller";
reg = <0x1fe78000 0x24>, <0x1fe78040 0x4>;
reg-names = "nand", "nand-dma";
dmas = <&dma 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
label = "ls1x-nand";
nand-use-soft-ecc-engine;
nand-ecc-algo = "hamming";
};
};
- |
nand-controller@1fe26000 {
compatible = "loongson,ls2k1000-nand-controller";
reg = <0x1fe26000 0x24>,
<0x1fe26040 0x4>,
<0x1fe00438 0x8>;
reg-names = "nand", "nand-dma", "dma-config";
dmas = <&apbdma0 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
label = "ls2k1000-nand";
nand-use-soft-ecc-engine;
nand-ecc-algo = "bch";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt
+50
View File
@@ -0,0 +1,50 @@
NXP LPC32xx SoC NAND MLC controller
Required properties:
- compatible: "nxp,lpc3220-mlc"
- reg: Address and size of the controller
- interrupts: The NAND interrupt specification
- gpios: GPIO specification for NAND write protect
The following required properties are very controller specific. See the LPC32xx
User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
Hz, to make them independent of actual clock speed and to provide for good
accuracy:)
- nxp,tcea_delay: TCEA_DELAY
- nxp,busy_delay: BUSY_DELAY
- nxp,nand_ta: NAND_TA
- nxp,rd_high: RD_HIGH
- nxp,rd_low: RD_LOW
- nxp,wr_high: WR_HIGH
- nxp,wr_low: WR_LOW
Optional subnodes:
- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
Example:
mlc: flash@200a8000 {
compatible = "nxp,lpc3220-mlc";
reg = <0x200A8000 0x11000>;
interrupts = <11 0>;
#address-cells = <1>;
#size-cells = <1>;
nxp,tcea-delay = <333333333>;
nxp,busy-delay = <10000000>;
nxp,nand-ta = <18181818>;
nxp,rd-high = <31250000>;
nxp,rd-low = <45454545>;
nxp,wr-high = <40000000>;
nxp,wr-low = <83333333>;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
mtd0@00000000 {
label = "boot";
reg = <0x00000000 0x00064000>;
read-only;
};
...
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
+52
View File
@@ -0,0 +1,52 @@
NXP LPC32xx SoC NAND SLC controller
Required properties:
- compatible: "nxp,lpc3220-slc"
- reg: Address and size of the controller
- nand-on-flash-bbt: Use bad block table on flash
- gpios: GPIO specification for NAND write protect
The following required properties are very controller specific. See the LPC32xx
User Manual:
- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
(The following values are specified in Hz, to make them independent of actual
clock speed:)
- nxp,wwidth: Write pulse width (W_WIDTH)
- nxp,whold: Write hold time (W_HOLD)
- nxp,wsetup: Write setup time (W_SETUP)
- nxp,rwidth: Read pulse width (R_WIDTH)
- nxp,rhold: Read hold time (R_HOLD)
- nxp,rsetup: Read setup time (R_SETUP)
Optional subnodes:
- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
Example:
slc: flash@20020000 {
compatible = "nxp,lpc3220-slc";
reg = <0x20020000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
nxp,wdr-clks = <14>;
nxp,wwidth = <40000000>;
nxp,whold = <100000000>;
nxp,wsetup = <100000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <40000000>;
nxp,rhold = <66666666>;
nxp,rsetup = <100000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
read-only;
};
...
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
+226
View File
@@ -0,0 +1,226 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell NAND Flash Controller (NFC)
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
properties:
compatible:
oneOf:
- items:
- const: marvell,armada-8k-nand-controller
- const: marvell,armada370-nand-controller
- enum:
- marvell,ac5-nand-controller
- marvell,armada370-nand-controller
- marvell,pxa3xx-nand-controller
- description: legacy bindings
deprecated: true
enum:
- marvell,armada-8k-nand
- marvell,armada370-nand
- marvell,pxa3xx-nand
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description:
Shall reference the NAND controller clocks, the second one is
is only needed for the Armada 7K/8K SoCs
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: reg
dmas:
maxItems: 1
dma-names:
items:
- const: data
marvell,system-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description: Syscon node that handles NAND controller related registers
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 3
nand-rb:
items:
- minimum: 0
maximum: 1
nand-ecc-step-size:
const: 512
nand-ecc-strength:
enum: [1, 4, 8, 12, 16]
nand-ecc-mode:
const: hw
marvell,nand-keep-config:
$ref: /schemas/types.yaml#/definitions/flag
description:
Orders the driver not to take the timings from the core and
leaving them completely untouched. Bootloader timings will then
be used.
marvell,nand-enable-arbiter:
$ref: /schemas/types.yaml#/definitions/flag
description:
To enable the arbiter, all boards blindly used it,
this bit was set by the bootloader for many boards and even if
it is marked reserved in several datasheets, it might be needed to set
it (otherwise it is harmless).
deprecated: true
required:
- reg
- nand-rb
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
allOf:
- $ref: nand-controller.yaml#
- if:
properties:
compatible:
contains:
const: marvell,pxa3xx-nand-controller
then:
required:
- dmas
- dma-names
- if:
properties:
compatible:
contains:
const: marvell,armada-8k-nand-controller
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
required:
- marvell,system-controller
else:
properties:
clocks:
minItems: 1
clock-names:
minItems: 1
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
nand_controller: nand-controller@d0000 {
compatible = "marvell,armada370-nand-controller";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
nand@0 {
reg = <0>;
label = "main-storage";
nand-rb = <0>;
nand-ecc-mode = "hw";
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Rootfs";
reg = <0x00000000 0x40000000>;
};
};
};
};
- |
cp0_nand_controller: nand-controller@720000 {
compatible = "marvell,armada-8k-nand-controller",
"marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&cp0_clk 1 2>,
<&cp0_clk 1 17>;
marvell,system-controller = <&cp0_syscon0>;
nand@0 {
reg = <0>;
label = "main-storage";
nand-rb = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
- |
nand-controller@43100000 {
compatible = "marvell,pxa3xx-nand-controller";
reg = <0x43100000 90>;
interrupts = <45>;
clocks = <&clks 1>;
clock-names = "core";
dmas = <&pdma 97 3>;
dma-names = "data";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-rb = <0>;
nand-ecc-mode = "hw";
marvell,nand-keep-config;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
+154
View File
@@ -0,0 +1,154 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
maintainers:
- Xiangsheng Hou <xiangsheng.hou@mediatek.com>
properties:
compatible:
enum:
- mediatek,mt2701-nfc
- mediatek,mt2712-nfc
- mediatek,mt7622-nfc
reg:
items:
- description: Base physical address and size of NFI.
interrupts:
items:
- description: NFI interrupt
clocks:
items:
- description: clock used for the controller
- description: clock used for the pad
clock-names:
items:
- const: nfi_clk
- const: pad_clk
ecc-engine:
description: device-tree node of the required ECC engine.
$ref: /schemas/types.yaml#/definitions/phandle
patternProperties:
"^nand@[a-f0-9]$":
$ref: raw-nand-chip.yaml#
unevaluatedProperties: false
properties:
reg:
maximum: 1
nand-ecc-mode:
const: hw
allOf:
- $ref: nand-controller.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt2701-nfc
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-step-size:
enum: [ 512, 1024 ]
nand-ecc-strength:
enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
40, 44, 48, 52, 56, 60]
- if:
properties:
compatible:
contains:
const: mediatek,mt2712-nfc
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-step-size:
enum: [ 512, 1024 ]
nand-ecc-strength:
enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
40, 44, 48, 52, 56, 60, 68, 72, 80]
- if:
properties:
compatible:
contains:
const: mediatek,mt7622-nfc
then:
patternProperties:
"^nand@[a-f0-9]$":
properties:
nand-ecc-step-size:
const: 512
nand-ecc-strength:
enum: [4, 6, 8, 10, 12]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- ecc-engine
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
nand-controller@1100d000 {
compatible = "mediatek,mt2701-nfc";
reg = <0 0x1100d000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFI>,
<&pericfg CLK_PERI_NFI_PAD>;
clock-names = "nfi_clk", "pad_clk";
ecc-engine = <&bch>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
preloader@0 {
label = "pl";
read-only;
reg = <0x0 0x400000>;
};
android@400000 {
label = "android";
reg = <0x400000 0x12c00000>;
};
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml
+63
View File
@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek(MTK) SoCs NAND ECC engine
maintainers:
- Xiangsheng Hou <xiangsheng.hou@mediatek.com>
description: |
MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
properties:
compatible:
enum:
- mediatek,mt2701-ecc
- mediatek,mt2712-ecc
- mediatek,mt7622-ecc
- mediatek,mt7986-ecc
reg:
items:
- description: Base physical address and size of ECC.
interrupts:
items:
- description: ECC interrupt
clocks:
maxItems: 1
clock-names:
const: nfiecc_clk
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
bch: ecc@1100e000 {
compatible = "mediatek,mt2701-ecc";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFI_ECC>;
clock-names = "nfiecc_clk";
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/microchip,mchp23k256.yaml
+49
View File
@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/microchip,mchp23k256.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip 23K256 SPI SRAM
maintainers:
- Richard Weinberger <richard@nod.at>
description:
The Microchip 23K256 is a 256 Kbit (32 Kbyte) serial SRAM with an
SPI interface,supporting clock frequencies up to 20 MHz. It features
a 32-byte page size for writes and supports byte, page, and
sequential access modes.
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
enum:
- microchip,mchp23k256
- microchip,mchp23lcv1024
reg:
maxItems: 1
required:
- reg
- compatible
- spi-max-frequency
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
sram@0 {
compatible = "microchip,mchp23k256";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml
+47
View File
@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip 48l640 (and similar) serial EERAM
maintainers:
- Heiko Schocher <hs@denx.de>
description: |
The Microchip 48l640 is a 8KByte EERAM connected via SPI.
datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/20006055B.pdf
properties:
compatible:
enum:
- fujitsu,mb85rs128ty
- microchip,48l640
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
eeram@0 {
compatible = "microchip,48l640";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
+236
View File
@@ -0,0 +1,236 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
maintainers:
- Rob Herring <robh@kernel.org>
description: |
Flash chips (Memory Technology Devices) are often used for solid state
file systems on embedded devices.
allOf:
- $ref: mtd.yaml#
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- amd,s29gl01gp
- amd,s29gl032a
- amd,s29gl256n
- amd,s29gl512n
- arm,versatile-flash
- arm,vexpress-flash
- cortina,gemini-flash
- cypress,hyperflash
- ge,imp3a-firmware-mirror
- ge,imp3a-paged-flash
- gef,ppc9a-firmware-mirror
- gef,ppc9a-paged-flash
- gef,sbc310-firmware-mirror
- gef,sbc310-paged-flash
- gef,sbc610-firmware-mirror
- gef,sbc610-paged-flash
- intel,28f128j3
- intel,dt28f160
- intel,ixp4xx-flash
- intel,JS28F128
- intel,JS28F640
- intel,PC28F640P30T85
- numonyx,js28f00a
- numonyx,js28f128
- sst,sst39vf320
- xlnx,xps-mch-emc-2.00.a
- enum:
- cfi-flash
- jedec-flash
- items:
- enum:
- cypress,cy7c1019dv33-10zsxi
- arm,vexpress-psram
- const: mtd-ram
- enum:
- cfi-flash
- jedec-flash
- mtd-ram
- mtd-rom
reg:
description: |
It's possible to (optionally) define multiple "reg" tuples so that
non-identical chips can be described in one node.
minItems: 1
maxItems: 8
clocks:
description: |
Chips may need clocks to be enabled for themselves or for transparent
bridges.
power-domains:
description: |
Chips may need power domains to be enabled for themselves or for
transparent bridges.
bank-width:
description: Width (in bytes) of the bank. Equal to the device width times
the number of interleaved chips.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 4 ]
device-width:
description:
Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2 ]
no-unaligned-direct-access:
type: boolean
description: |
Disables the default direct mapping of the flash.
On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
accesses as implemented in the JFFS2 code via memcpy(). By defining
"no-unaligned-direct-access", the flash will not be exposed directly to
the MTD users (e.g. JFFS2) any more.
linux,mtd-name:
description:
Allows specifying the mtd name for retro capability with physmap-flash
drivers as boot loader pass the mtd partition via the old device name
physmap-flash.
$ref: /schemas/types.yaml#/definitions/string
use-advanced-sector-protection:
type: boolean
description: |
Enables support for the advanced sector protection (Spansion: PPB -
Persistent Protection Bits) locking.
erase-size:
description: The chip's physical erase block size in bytes.
$ref: /schemas/types.yaml#/definitions/uint32
addr-gpios:
description:
List of GPIO descriptors that will be used to address the MSBs address
lines. The order goes from LSB to MSB.
minItems: 1
maxItems: 8
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
big-endian: true
little-endian: true
required:
- compatible
- reg
if:
properties:
compatible:
contains:
const: cortina,gemini-flash
then:
properties:
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the syscon controller
required:
- syscon
unevaluatedProperties: false
examples:
- |
flash@ff000000 {
compatible = "cfi-flash";
reg = <0xff000000 0x01000000>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff000000 0x01000000>;
fs@0 {
label = "fs";
reg = <0 0xf80000>;
};
firmware@f80000 {
label = "firmware";
reg = <0xf80000 0x80000>;
read-only;
};
};
- |
/* An example with multiple "reg" tuples */
flash@0 {
compatible = "intel,PC28F640P30T85", "cfi-flash";
reg = <0x00000000 0x02000000>,
<0x02000000 0x02000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x04000000>;
partition@0 {
label = "test-part1";
reg = <0 0x04000000>;
};
};
- |
/* An example using SRAM */
bus {
#address-cells = <2>;
#size-cells = <1>;
sram@2,0 {
compatible = "mtd-ram";
reg = <2 0 0x00200000>;
bank-width = <2>;
};
};
- |
/* An example using addr-gpios */
#include <dt-bindings/gpio/gpio.h>
flash@20000000 {
compatible = "cfi-flash";
reg = <0x20000000 0x02000000>;
bank-width = <2>;
addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0x02000000>,
<1 0x02000000 0x02000000>;
partition@0 {
label = "test-part1";
reg = <0 0x04000000>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/mtd.yaml
+113
View File
@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mtd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MTD (Memory Technology Device)
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Richard Weinberger <richard@nod.at>
select: false
properties:
$nodename:
pattern: "^(flash|.*sram|nand)(@.*)?$"
label:
description:
User-defined MTD device name. Can be used to assign user friendly
names to MTD devices (instead of the flash model or flash controller
based name) in order to ease flash device identification and/or
describe what they are used for.
'#address-cells':
deprecated: true
'#size-cells':
deprecated: true
partitions:
type: object
required:
- compatible
patternProperties:
"(^partition)?@[0-9a-f]+$":
$ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node
deprecated: true
"^otp(-[0-9]+)?$":
type: object
allOf:
- $ref: /schemas/nvmem/nvmem.yaml#
- $ref: /schemas/nvmem/nvmem-deprecated-cells.yaml#
unevaluatedProperties: false
description: |
An OTP memory region. Some flashes provide a one-time-programmable
memory whose content can either be programmed by a user or is already
pre-programmed by the factory. Some flashes might provide both.
properties:
compatible:
enum:
- user-otp
- factory-otp
required:
- compatible
# This is a generic file other binding inherit from
additionalProperties: true
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
label = "System-firmware";
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
otp-1 {
compatible = "factory-otp";
#address-cells = <1>;
#size-cells = <1>;
electronic-serial-number@0 {
reg = <0 8>;
};
};
otp-2 {
compatible = "user-otp";
#address-cells = <1>;
#size-cells = <1>;
mac-address@0 {
reg = <0 6>;
};
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/mxc-nand.yaml
+65
View File
@@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mxc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale's mxc_nand
maintainers:
- Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
allOf:
- $ref: nand-controller-legacy.yaml
properties:
compatible:
oneOf:
- enum:
- fsl,imx25-nand
- fsl,imx27-nand
- fsl,imx51-nand
- fsl,imx53-nand
- items:
- enum:
- fsl,imx35-nand
- const: fsl,imx25-nand
- items:
- enum:
- fsl,imx31-nand
- const: fsl,imx27-nand
reg:
minItems: 1
items:
- description: IP register space
- description: Nand flash internal buffer space
interrupts:
maxItems: 1
clocks:
maxItems: 1
dmas:
maxItems: 1
dma-names:
items:
- const: rx-tx
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
nand-controller@d8000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-nand";
reg = <0xd8000000 0x1000>;
interrupts = <29>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/mxic,multi-itfc-v009-nand-controller.yaml
+78
View File
@@ -0,0 +1,78 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mxic,multi-itfc-v009-nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Macronix Raw NAND Controller
maintainers:
- Mason Yang <masonccyang@mxic.com.tw>
description:
The Macronix Multi-Interface Raw NAND Controller is a versatile flash
memory controller for embedding in SoCs, capable of interfacing with
various NAND devices. It requires dedicated clock inputs for core, data
transmit, and delayed transmit paths along with register space and an
interrupt line for operation.
allOf:
- $ref: nand-controller.yaml#
properties:
compatible:
const: mxic,multi-itfc-v009-nand-controller
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: ps
- const: send
- const: send_dly
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
nand-controller@43c30000 {
compatible = "mxic,multi-itfc-v009-nand-controller";
reg = <0x43c30000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
clock-names = "ps", "send", "send_dly";
nand@0 {
reg = <0>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/mxicy,nand-ecc-engine.yaml
+77
View File
@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Macronix NAND ECC engine
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
properties:
compatible:
const: mxicy,nand-ecc-engine-rev3
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
/* External configuration */
spi_controller0: spi@43c30000 {
compatible = "mxicy,mx25f0a-spi";
reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
reg-names = "regs", "dirmap";
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
clock-names = "send_clk", "send_dly_clk", "ps_clk";
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "spi-nand";
reg = <0>;
nand-ecc-engine = <&ecc_engine0>;
};
};
ecc_engine0: ecc@43c40000 {
compatible = "mxicy,nand-ecc-engine-rev3";
reg = <0x43c40000 0x10000>;
};
- |
/* Pipelined configuration */
spi_controller1: spi@43c30000 {
compatible = "mxicy,mx25f0a-spi";
reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
reg-names = "regs", "dirmap";
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
clock-names = "send_clk", "send_dly_clk", "ps_clk";
#address-cells = <1>;
#size-cells = <0>;
nand-ecc-engine = <&ecc_engine1>;
flash@0 {
compatible = "spi-nand";
reg = <0>;
nand-ecc-engine = <&spi_controller1>;
};
};
ecc_engine1: ecc@43c40000 {
compatible = "mxicy,nand-ecc-engine-rev3";
reg = <0x43c40000 0x10000>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/nand-chip.yaml
+39
View File
@@ -0,0 +1,39 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NAND Chip Common Properties
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
allOf:
- $ref: mtd.yaml#
- $ref: nand-property.yaml
description: |
This file covers the generic description of a NAND chip. It implies that the
bus interface should not be taken into account: both raw NAND devices and
SPI-NAND devices are concerned by this description.
properties:
reg:
description:
Contains the chip-select IDs.
nand-randomizer:
description: |
Control the data randomizer feature.
0: Disable randomizer.
1: Enable randomizer.
If absent, the current hardware state is left unchanged.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
required:
- reg
# This file can be referenced by more specific devices (like spi-nands)
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/mtd/nand-controller-legacy.yaml
+65
View File
@@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-controller-legacy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NAND Controller Common Properties
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Richard Weinberger <richard@nod.at>
description: >
The NAND controller should be represented with its own DT node, and
all NAND chips attached to this controller should be defined as
children nodes of the NAND controller. This representation should be
enforced even for simple controllers supporting only one chip.
This is only for legacy nand controller, new controller should use
nand-controller.yaml
properties:
"#address-cells":
const: 1
"#size-cells":
enum: [0, 1]
ranges: true
cs-gpios:
description:
Array of chip-select available to the controller. The first
entries are a 1:1 mapping of the available chip-select on the
NAND controller (even if they are not used). As many additional
chip-select as needed may follow and should be phandles of GPIO
lines. 'reg' entries of the NAND chip subnodes become indexes of
this array when this property is present.
minItems: 1
maxItems: 8
partitions:
type: object
required:
- compatible
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml#
"^partition@[0-9a-f]+$":
type: object
$ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node
deprecated: true
allOf:
- $ref: raw-nand-property.yaml#
- $ref: nand-property.yaml#
# This is a generic file other binding inherit from and extend
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+73
View File
@@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NAND Controller Common Properties
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Richard Weinberger <richard@nod.at>
description: |
The NAND controller should be represented with its own DT node, and
all NAND chips attached to this controller should be defined as
children nodes of the NAND controller. This representation should be
enforced even for simple controllers supporting only one chip.
select: false
properties:
$nodename:
pattern: "^nand-controller(@.*)?"
"#address-cells":
const: 1
"#size-cells":
const: 0
ranges: true
cs-gpios:
description:
Array of chip-select available to the controller. The first
entries are a 1:1 mapping of the available chip-select on the
NAND controller (even if they are not used). As many additional
chip-select as needed may follow and should be phandles of GPIO
lines. 'reg' entries of the NAND chip subnodes become indexes of
this array when this property is present.
minItems: 1
maxItems: 8
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml#
required:
- "#address-cells"
- "#size-cells"
# This is a generic file other binding inherit from and extend
additionalProperties: true
examples:
- |
nand-controller {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
/* controller specific properties */
nand@0 {
reg = <0>; /* Native CS */
/* NAND chip specific properties */
};
nand@1 {
reg = <1>; /* GPIO CS */
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/nand-macronix.txt
+27
View File
@@ -0,0 +1,27 @@
Macronix NANDs Device Tree Bindings
-----------------------------------
Macronix NANDs support randomizer operation for scrambling user data,
which can be enabled with a SET_FEATURE. The penalty when using the
randomizer are subpage accesses prohibited and more time period needed
for program operation, i.e., tPROG 300us to 340us (randomizer enabled).
Enabling the randomizer is a one time persistent and non reversible
operation.
For more high-reliability concern, if subpage write is not available
with hardware ECC and not enabled at UBI level, then enabling the
randomizer is recommended by default by adding a new specific property
in children nodes.
Required NAND chip properties in children mode:
- randomizer enable: should be "mxic,enable-randomizer-otp"
Example:
nand: nand-controller@unit-address {
nand@0 {
reg = <0>;
mxic,enable-randomizer-otp;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/nand-property.yaml
+64
View File
@@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-property.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NAND Chip Common Properties
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
description: |
This file covers the generic properties of a NAND chip. It implies that the
bus interface should not be taken into account: both raw NAND devices and
SPI-NAND devices are concerned by this description.
properties:
nand-ecc-engine:
description: |
A phandle on the hardware ECC engine if any. There are
basically three possibilities:
1/ The ECC engine is part of the NAND controller, in this
case the phandle should reference the parent node.
2/ The ECC engine is part of the NAND part (on-die), in this
case the phandle should reference the node itself.
3/ The ECC engine is external, in this case the phandle should
reference the specific ECC engine node.
$ref: /schemas/types.yaml#/definitions/phandle
nand-use-soft-ecc-engine:
description: Use a software ECC engine.
type: boolean
nand-no-ecc-engine:
description: Do not use any ECC correction.
type: boolean
nand-ecc-algo:
description:
Desired ECC algorithm.
$ref: /schemas/types.yaml#/definitions/string
enum: [hamming, bch, rs]
nand-ecc-strength:
description:
Maximum number of bits that can be corrected per ECC step.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
nand-ecc-step-size:
description:
Number of data bytes covered by a single ECC step.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
secure-regions:
description:
Regions in the NAND chip which are protected using a secure element
like Trustzone. This property contains the start address and size of
the secure regions present.
$ref: /schemas/types.yaml#/definitions/uint64-matrix
# This file can be referenced by more specific devices (like spi-nands)
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
+95
View File
@@ -0,0 +1,95 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
maintainers:
- Hui-Ping Chen <hpchen0nvt@gmail.com>
allOf:
- $ref: nand-controller.yaml#
properties:
compatible:
enum:
- nuvoton,ma35d1-nand-controller
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 1
nand-ecc-step-size:
enum: [512, 1024]
nand-ecc-strength:
enum: [8, 12, 24]
required:
- reg
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
nand-controller@401A0000 {
compatible = "nuvoton,ma35d1-nand-controller";
reg = <0x0 0x401A0000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NAND_GATE>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-step-size = <512>;
nand-ecc-strength = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot@0 {
label = "nand-uboot";
read-only;
reg = <0x0 0x300000>;
};
};
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
+102
View File
@@ -0,0 +1,102 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NAND Flash Controller
maintainers:
- Jonathan Hunter <jonathanh@nvidia.com>
allOf:
- $ref: nand-controller.yaml
description:
The NVIDIA NAND controller provides an interface between NVIDIA SoCs
and raw NAND flash devices. It supports standard NAND operations,
hardware-assisted ECC, OOB data access, and DMA transfers, and
integrates with the Linux MTD NAND subsystem for reliable flash management.
properties:
compatible:
const: nvidia,tegra20-nand
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nand
resets:
maxItems: 1
reset-names:
items:
- const: nand
power-domains:
maxItems: 1
operating-points-v2:
maxItems: 1
patternProperties:
'^nand@':
type: object
description: Individual NAND chip connected to the NAND controller
$ref: raw-nand-chip.yaml#
properties:
reg:
maximum: 5
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
nand-controller@70008000 {
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
clock-names = "nand";
resets = <&tegra_car 13>;
reset-names = "nand";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <8>;
nand-on-flash-bbt;
nand-ecc-algo = "bch";
nand-ecc-strength = <8>;
wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/nxp,lpc1773-spifi.yaml
+74
View File
@@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nxp,lpc1773-spifi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP SPI Flash Interface (SPIFI)
description:
NXP SPIFI is a specialized SPI interface for serial Flash devices.
It supports one Flash device with 1-, 2- and 4-bits width in SPI
mode 0 or 3. The controller operates in either command or memory
mode. In memory mode the Flash is accessible from the CPU as
normal memory.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc1773-spifi
reg:
maxItems: 2
reg-names:
items:
- const: spifi
- const: flash
interrupts:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: spifi
- const: reg
resets:
maxItems: 1
spi-cpol:
enum: [0, 3]
required:
- compatible
- reg
- reg-names
- interrupts
- clocks
- clock-names
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-ccu.h>
spi@40003000 {
compatible = "nxp,lpc1773-spifi";
reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
reg-names = "spifi", "flash";
interrupts = <30>;
clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
clock-names = "spifi", "reg";
resets = <&rgu 53>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/orion-nand.txt
+50
View File
@@ -0,0 +1,50 @@
NAND support for Marvell Orion SoC platforms
Required properties:
- compatible : "marvell,orion-nand".
- reg : Base physical address of the NAND and length of memory mapped
region
Optional properties:
- cle : Address line number connected to CLE. Default is 0
- ale : Address line number connected to ALE. Default is 1
- bank-width : Width in bytes of the device. Default is 1
- chip-delay : Chip dependent delay for transferring data from array to read
registers in usecs
The device tree may optionally contain sub-nodes describing partitions of the
address space. See mtd.yaml for more detail.
Example:
nand@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
cle = <0>;
ale = <1>;
bank-width = <1>;
chip-delay = <25>;
compatible = "marvell,orion-nand";
reg = <0xf4000000 0x400>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
partition@100000 {
label = "uImage";
reg = <0x0100000 0x200000>;
};
partition@300000 {
label = "dtb";
reg = <0x0300000 0x100000>;
};
partition@400000 {
label = "root";
reg = <0x0400000 0x7d00000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/arm,arm-firmware-suite.yaml
+28
View File
@@ -0,0 +1,28 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/arm,arm-firmware-suite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Firmware Suite (AFS) Partitions
maintainers:
- Linus Walleij <linusw@kernel.org>
description: |
The ARM Firmware Suite is a flash partitioning system found on the
ARM reference designs: Integrator AP, Integrator CP, Versatile AB,
Versatile PB, the RealView family, Versatile Express and Juno.
properties:
compatible:
const: arm,arm-firmware-suite
additionalProperties: false
examples:
- |
partitions {
compatible = "arm,arm-firmware-suite";
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml
+66
View File
@@ -0,0 +1,66 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm4908-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4908 partitioning
description: |
Broadcom BCM4908 CFE bootloader supports two firmware partitions. One is used
for regular booting, the other is treated as fallback.
This binding allows defining all fixed partitions and marking those containing
firmware. System can use that information e.g. for booting or flashing
purposes.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: brcm,bcm4908-partitions
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
patternProperties:
"^partition@[0-9a-f]+$":
$ref: partition.yaml#/$defs/partition-node
required:
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
partitions {
compatible = "brcm,bcm4908-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "cferom";
reg = <0x0 0x100000>;
};
partition@100000 {
compatible = "brcm,bcm4908-firmware";
reg = <0x100000 0xf00000>;
};
partition@1000000 {
compatible = "brcm,bcm4908-firmware";
reg = <0x1000000 0xf00000>;
};
partition@1f00000 {
label = "calibration";
reg = <0x1f00000 0x100000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.yaml
+48
View File
@@ -0,0 +1,48 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm947xx-cfe-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM47xx Partitions
description: |
Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in
home routers. Their BCM947xx boards using CFE bootloader have several
partitions without any on-flash partition table. On some devices their sizes
and/or meanings can also vary so fixed partitioning can't be used.
Discovering partitions on these devices is possible thanks to having a special
header and/or magic signature at the beginning of each of them. They are also
block aligned which is important for determinig a size.
Most of partitions use ASCII text based magic for determining a type. More
complex partitions (like TRX with its HDR0 magic) may include extra header
containing some details, including a length.
A list of supported partitions includes:
1) Bootloader with Broadcom's CFE (Common Firmware Environment)
2) NVRAM with configuration/calibration data
3) Device manufacturer's data with some default values (e.g. SSIDs)
4) TRX firmware container which can hold up to 4 subpartitions
5) Backup TRX firmware used after failed upgrade
As mentioned earlier, role of some partitions may depend on extra
configuration. For example both: main firmware and backup firmware use the
same TRX format with the same header. To distinguish currently used firmware a
CFE's environment variable "bootpartition" is used.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: brcm,bcm947xx-cfe-partitions
additionalProperties: false
examples:
- |
partitions {
compatible = "brcm,bcm947xx-cfe-partitions";
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm963xx-cfe-nor-partitions.txt
+24
View File
@@ -0,0 +1,24 @@
Broadcom BCM963XX CFE Loader NOR Flash Partitions
=================================================
Most Broadcom BCM63XX SoC based devices follow the Broadcom reference layout for
NOR. The first erase block used for the CFE bootloader, the last for an
NVRAM partition, and the remainder in-between for one to two firmware partitions
at fixed offsets. A valid firmware partition is identified by the ImageTag
header found at beginning of the second erase block, containing the rootfs and
kernel offsets and sizes within the firmware partition.
Required properties:
- compatible : must be "brcm,bcm963xx-cfe-nor-partitions"
Example:
flash@1fc00000 {
compatible = "cfi-flash";
reg = <0x1fc00000 0x400000>;
bank-width = <2>;
partitions {
compatible = "brcm,bcm963xx-cfe-nor-partitions";
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.yaml
+65
View File
@@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/brcm,trx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom TRX Container Partition
maintainers:
- Hauke Mehrtens <hauke@hauke-m.de>
- Rafał Miłecki <rafal@milecki.pl>
description: >
TRX is Broadcom's official firmware format for the BCM947xx boards. It's used by
most of the vendors building devices based on Broadcom's BCM47xx SoCs and is
supported by the CFE bootloader.
Design of the TRX format is very minimalistic. Its header contains
identification fields, CRC32 checksum and the locations of embedded partitions.
Its purpose is to store a few partitions in a format that can be distributed as
a standalone file and written in a flash memory.
Container can hold up to 4 partitions. The first partition has to contain a
device executable binary (e.g. a kernel) as it's what the CFE bootloader starts
executing. Other partitions can be used for operating system purposes. This is
useful for systems that keep kernel and rootfs separated.
TRX doesn't enforce any strict partition boundaries or size limits. All
partitions have to be less than the 4GiB max size limit.
There are two existing/known TRX variants:
1) v1 which contains 3 partitions
2) v2 which contains 4 partitions
There aren't separated compatible bindings for them as version can be trivially
detected by a software parsing TRX header.
properties:
compatible:
oneOf:
- items:
- const: linksys,ns-firmware
- const: brcm,trx
- const: brcm,trx
brcm,trx-magic:
description: TRX magic, if it is different from the default magic.
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x30524448
required:
- compatible
allOf:
- $ref: partition.yaml#
unevaluatedProperties: false
examples:
- |
flash {
partitions {
compatible = "brcm,trx";
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
+162
View File
@@ -0,0 +1,162 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Fixed partitions
description: |
This binding can be used on platforms which have strong conventions about
which portions of a flash are used for what purposes, but which don't use an
on-flash partition table such as RedBoot.
The partition table should be a node named "partitions". Partitions are then
defined as subnodes.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
oneOf:
- const: fixed-partitions
- items:
- const: sercomm,sc-partitions
- const: fixed-partitions
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
patternProperties:
"@[0-9a-f]+$":
$ref: partition.yaml#/$defs/partition-node
required:
- "#address-cells"
- "#size-cells"
# fixed-partitions can be nested
allOf:
- $ref: partition.yaml#
unevaluatedProperties: false
examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
uimage@100000 {
reg = <0x0100000 0x200000>;
compression = "lzma";
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <2>;
/* a 4 GiB partition */
partition@0 {
label = "filesystem";
reg = <0x00000000 0x1 0x00000000>;
linux,rootfs;
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <2>;
/* an 8 GiB partition */
partition@0 {
label = "filesystem #1";
reg = <0x0 0x00000000 0x2 0x00000000>;
};
/* a 4 GiB partition */
partition@200000000 {
label = "filesystem #2";
reg = <0x2 0x00000000 0x1 0x00000000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x000000 0x100000>;
read-only;
};
firmware@100000 {
compatible = "brcm,trx";
label = "firmware";
reg = <0x100000 0xe00000>;
};
calibration@f00000 {
compatible = "fixed-partitions";
label = "calibration";
reg = <0xf00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "wifi0";
reg = <0x000000 0x080000>;
};
partition@80000 {
label = "wifi1";
reg = <0x080000 0x080000>;
};
};
};
- |
partitions {
compatible = "sercomm,sc-partitions", "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
sercomm,scpart-id = <0>;
read-only;
};
partition@100000 {
label = "dynamic partition map";
reg = <0x100000 0x100000>;
sercomm,scpart-id = <1>;
};
partition@200000 {
label = "Factory";
reg = <0x200000 0x100000>;
sercomm,scpart-id = <2>;
read-only;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml
+68
View File
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/linksys,ns-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Linksys Northstar partitioning
description: |
Linksys devices based on Broadcom Northstar architecture often use two
firmware partitions. One is used for regular booting, the other is treated as
fallback.
This binding allows defining all fixed partitions and marking those containing
firmware. System can use that information e.g. for booting or flashing
purposes.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: linksys,ns-partitions
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
patternProperties:
"^partition@[0-9a-f]+$":
$ref: partition.yaml#/$defs/partition-node
required:
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
partitions {
compatible = "linksys,ns-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "nvram";
reg = <0x100000 0x100000>;
};
partition@200000 {
compatible = "linksys,ns-firmware", "brcm,trx";
reg = <0x200000 0xf00000>;
};
partition@1100000 {
compatible = "linksys,ns-firmware", "brcm,trx";
reg = <0x1100000 0xf00000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+75
View File
@@ -0,0 +1,75 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Unsorted Block Images
description: |
UBI ("Unsorted Block Images") is a volume management system for raw
flash devices which manages multiple logical volumes on a single
physical flash device and spreads the I/O load (i.e wear-leveling)
across the whole flash chip.
maintainers:
- Daniel Golle <daniel@makrotopia.org>
allOf:
- $ref: partition.yaml#
properties:
compatible:
const: linux,ubi
volumes:
type: object
description: UBI Volumes
patternProperties:
"^ubi-volume-.*$":
$ref: /schemas/mtd/partitions/ubi-volume.yaml#
unevaluatedProperties: false
required:
- compatible
unevaluatedProperties: false
examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x100000>;
label = "bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x1ff00000>;
label = "ubi";
compatible = "linux,ubi";
volumes {
ubi-volume-caldata {
volid = <2>;
volname = "rf";
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom@0 {
reg = <0x0 0x1000>;
};
};
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/nvmem-cells.yaml
+100
View File
@@ -0,0 +1,100 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/nvmem-cells.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nvmem cells
description: |
Any partition containing the compatible "nvmem-cells" will register as a
nvmem provider.
Each direct subnodes represents a nvmem cell following the nvmem binding.
Nvmem binding to declare nvmem-cells can be found in:
Documentation/devicetree/bindings/nvmem/nvmem.yaml
maintainers:
- Ansuel Smith <ansuelsmth@gmail.com>
allOf:
- $ref: /schemas/mtd/partitions/partition.yaml#
- $ref: /schemas/nvmem/nvmem.yaml#
- $ref: /schemas/nvmem/nvmem-deprecated-cells.yaml#
properties:
compatible:
const: nvmem-cells
required:
- compatible
unevaluatedProperties: false
examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* ... */
};
art: art@1200000 {
compatible = "nvmem-cells";
reg = <0x1200000 0x0140000>;
label = "art";
read-only;
#address-cells = <1>;
#size-cells = <1>;
macaddr_gmac1: macaddr_gmac1@0 {
reg = <0x0 0x6>;
};
macaddr_gmac2: macaddr_gmac2@6 {
reg = <0x6 0x6>;
};
pre_cal_24g: pre_cal_24g@1000 {
reg = <0x1000 0x2f20>;
};
pre_cal_5g: pre_cal_5g@5000{
reg = <0x5000 0x2f20>;
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x000000 0x100000>;
read-only;
};
firmware@100000 {
compatible = "brcm,trx";
label = "firmware";
reg = <0x100000 0xe00000>;
};
calibration@f00000 {
compatible = "nvmem-cells";
label = "calibration";
reg = <0xf00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
wifi0@0 {
reg = <0x000000 0x080000>;
};
wifi1@80000 {
reg = <0x080000 0x080000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/partition.yaml
+203
View File
@@ -0,0 +1,203 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/partition.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Partition
description: |
This binding describes a single flash partition. Each partition must have its
relative offset and size specified. Depending on partition function extra
properties can be used.
A partition may be dynamically allocated by a specific parser at runtime.
In this specific case, a specific suffix is required to the node name.
Everything after 'partition-' will be used as the partition name to compare
with the one dynamically allocated by the specific parser.
If the partition contains invalid char a label can be provided that will
be used instead of the node name to make the comparison.
This is used to assign an OF node to the dynamiccally allocated partition
so that subsystem like NVMEM can provide an OF node and declare NVMEM cells.
The OF node will be assigned only if the partition label declared match the
one assigned by the parser at runtime.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
reg:
description: partition's offset and size within the flash
maxItems: 1
label:
description: The label / name for this partition. If omitted, the label
is taken from the node name (excluding the unit address).
read-only:
description: This parameter, if present, is a hint that this partition
should only be mounted read-only. This is usually used for flash
partitions containing early-boot firmware images or data which should
not be clobbered.
type: boolean
lock:
description: Do not unlock the partition at initialization time (not
supported on all devices)
type: boolean
slc-mode:
description: This parameter, if present, allows one to emulate SLC mode
on a partition attached to an MLC NAND thus making this partition
immune to paired-pages corruptions
type: boolean
linux,rootfs:
description: Marks partition that contains root filesystem to mount and boot
user space from
type: boolean
part-concat-next:
description: List of phandles to MTD partitions that need be concatenated
with the current partition.
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 16
items:
maxItems: 1
align:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 2
maximum: 0x80000000
multipleOf: 2
description:
This sets the alignment of the entry in bytes.
The entry offset is adjusted so that the entry starts on an aligned
boundary within the containing section or image. For example ‘align =
<16>’ means that the entry will start on a 16-byte boundary. This may
mean that padding is added before the entry. The padding is part of
the containing section but is not included in the entry, meaning that
an empty space may be created before the entry starts. Alignment
must be a power of 2. If ‘align’ is not provided, no alignment is
performed.
align-size:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 2
maximum: 0x80000000
multipleOf: 2
description:
This sets the alignment of the entry size in bytes. It must be a power
of 2.
For example, to ensure that the size of an entry is a multiple of 64
bytes, set this to 64. While this does not affect the content of the
entry itself (the padding is performed only when its parent section is
assembled), the end result is that the entry ends with the padding
bytes, so may grow. If ‘align-size’ is not provided, no alignment is
performed.
align-end:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 2
maximum: 0x80000000
multipleOf: 2
description:
This sets the alignment (in bytes) of the end of an entry with respect
to the containing section. It must be a power of 2.
Some entries require that they end on an alignment boundary,
regardless of where they start. This does not move the start of the
entry, so the content of the entry will still start at the beginning.
But there may be padding at the end. While this does not affect the
content of the entry itself (the padding is performed only when its
parent section is assembled), the end result is that the entry ends
with the padding bytes, so may grow. If ‘align-end’ is not provided,
no alignment is performed.
compression:
$ref: /schemas/types.yaml#/definitions/string
description: |
Compression algorithm used to store the data in this partition, chosen
from a list of well-known algorithms.
The contents are compressed using this algorithm.
enum:
- none
- bzip2
- gzip
- lzop
- lz4
- lzma
- xz
- zstd
sercomm,scpart-id:
description: Partition id in Sercomm partition map. Mtd parser
uses this id to find a record in the partition map containing
offset and size of the current partition. The values from
partition map overrides partition offset and size defined in
reg property of the dts. Frequently these values are the same,
but may differ if device has bad eraseblocks on a flash.
$ref: /schemas/types.yaml#/definitions/uint32
nvmem-layout:
$ref: /schemas/nvmem/layouts/nvmem-layout.yaml
if:
not:
required: [ reg ]
then:
properties:
$nodename:
pattern: '^partitions?(-.+)?$'
# This is a generic file other binding inherit from and extend
additionalProperties: true
$defs:
partition-node:
type: object
if:
not:
required: [ compatible ]
then:
$ref: '#'
unevaluatedProperties: false
else:
$ref: '#'
examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@100000 {
compatible = "u-boot";
reg = <0x100000 0xf00000>;
align-size = <0x1000>;
align-end = <0x10000>;
};
partition@200000 {
compatible = "tfa-bl31";
reg = <0x200000 0x100000>;
align = <0x4000>;
};
part0: partition@400000 {
part-concat-next = <&part1>;
label = "part0_0";
reg = <0x400000 0x100000>;
};
part1: partition@800000 {
label = "part0_1";
reg = <0x800000 0x800000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml
+62
View File
@@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SMEM NAND flash partition parser
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
The Qualcomm SoCs supporting the NAND controller interface features a Shared
Memory (SMEM) based partition table scheme. The maximum partitions supported
varies between partition table revisions. V3 supports maximum 16 partitions
and V4 supports 48 partitions.
select: false
properties:
compatible:
const: qcom,smem-part
patternProperties:
"^partition-[0-9a-z]+$":
$ref: nvmem-cells.yaml
required:
- compatible
additionalProperties: false
examples:
- |
flash {
partitions {
compatible = "qcom,smem-part";
};
};
- |
/* Example declaring dynamic partition */
flash {
partitions {
compatible = "qcom,smem-part";
partition-art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
label = "0:art";
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/redboot-fis.yaml
+44
View File
@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/redboot-fis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RedBoot FLASH Image System (FIS) Partitions
description: The FLASH Image System (FIS) directory is a flash description
format closely associated with the RedBoot boot loader.
It uses one single flash eraseblock in the flash to store an index of
all images in the flash.
This block size will vary depending on flash but is typically
32 KB in size.
maintainers:
- Linus Walleij <linusw@kernel.org>
select: false
properties:
compatible:
const: redboot-fis
fis-index-block:
$ref: /schemas/types.yaml#/definitions/uint32
description: a index to the eraseblock containing the FIS directory on this
device. On a flash memory with 32KB eraseblocks, 0 means the first
eraseblock at 0x00000000, 1 means the second eraseblock at 0x00008000 and so on.
required:
- compatible
- fis-index-block
additionalProperties: false
examples:
- |
flash {
partitions {
compatible = "redboot-fis";
fis-index-block = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/simple-partition.yaml
+61
View File
@@ -0,0 +1,61 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/simple-partition.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple partition types
description:
Simple partition types which only define a "compatible" value and no custom
properties.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
- Simon Glass <sjg@chromium.org>
allOf:
- $ref: partition.yaml#
properties:
compatible:
oneOf:
- const: brcm,bcm4908-firmware
description:
Broadcom BCM4908 CFE bootloader firmware partition
- const: brcm,bcm963xx-imagetag
description:
The BCM963XX ImageTag is a simple firmware header describing the
offsets and sizes of the rootfs and kernel parts contained in the
firmware.
- const: seama
description:
The SEAttle iMAge (SEAMA) partition is a type of partition used for
NAND flash devices. This type of flash image is found in some D-Link
routers such as DIR-645, DIR-842, DIR-859, DIR-860L, DIR-885L, DIR890L
and DCH-M225, as well as in WD and NEC routers on the ath79 (MIPS),
Broadcom BCM53xx, and RAMIPS platforms. This partition type does not
have children defined in the device tree, they need to be detected by
software.
- const: u-boot
description: >
u-boot.bin from U-Boot project.
This corresponds to a binman 'entry'. It is a single partition which holds
data of a defined type.
Binman uses the type to indicate what data file / type to place in the
partition. There are quite a number of binman-specific entry types, such as
section, fill and files, to be added later.
- const: tfa-bl31
description: >
bl31.bin or bl31.elf from TF-A project
This corresponds to a binman 'entry'. It is a single partition which holds
data of a defined type.
unevaluatedProperties: false
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/tplink,safeloader-partitions.yaml
+57
View File
@@ -0,0 +1,57 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/tplink,safeloader-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TP-Link SafeLoader partitions
description: |
TP-Link home routers store various data on flash (e.g. bootloader,
flash layout, firmware, product info, configuration, calibration
data). That requires flash partitioning.
Flash space layout of TP-Link devices is stored on flash itself using
a custom ASCII-based format. That format was first found in TP-Link
devices with a custom SafeLoader bootloader. Later it was adapted to
CFE and U-Boot bootloaders.
Partitions specified in partitions table cover whole flash space. Some
contain static data that shouldn't get modified (device's MAC or WiFi
calibration data). Others are semi-static (like kernel). Finally some
partitions contain fully changeable content (like rootfs).
This binding describes partitioning method and defines offset of ASCII
based partitions table. That offset is picked at manufacturing process
and doesn't change.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: tplink,safeloader-partitions
partitions-table-offset:
description: Flash offset of partitions table
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
"^partition-.*$":
$ref: partition.yaml#/$defs/partition-node
required:
- partitions-table-offset
additionalProperties: false
examples:
- |
partitions {
compatible = "tplink,safeloader-partitions";
partitions-table-offset = <0x100000>;
partition-file-system {
linux,rootfs;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml
+56
View File
@@ -0,0 +1,56 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/u-boot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: U-Boot bootloader partition
description: |
U-Boot is a bootloader commonly used in embedded devices. It's almost always
located on some kind of flash device.
Device configuration is stored as a set of environment variables that are
located in a (usually standalone) block of data.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
allOf:
- $ref: partition.yaml#
properties:
compatible:
oneOf:
- const: brcm,u-boot
description: |
Broadcom stores environment variables inside a U-Boot partition. They
can be identified by a custom header with magic value.
patternProperties:
"^partition-.*$":
$ref: partition.yaml#/$defs/partition-node
unevaluatedProperties: false
examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
compatible = "brcm,u-boot";
reg = <0x0 0x100000>;
label = "u-boot";
partition-u-boot-env {
};
};
partition@100000 {
reg = <0x100000 0x1ff00000>;
label = "firmware";
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+40
View File
@@ -0,0 +1,40 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UBI volume
description: |
This binding describes a single UBI volume. Volumes can be matches either
by their ID or their name, or both.
maintainers:
- Daniel Golle <daniel@makrotopia.org>
properties:
volid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Match UBI volume ID
volname:
$ref: /schemas/types.yaml#/definitions/string
description:
Match UBI volume ID
nvmem-layout:
$ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
description:
This container may reference an NVMEM layout parser.
anyOf:
- required:
- volid
- required:
- volname
# This is a generic file other binding inherit from and extend
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
+241
View File
@@ -0,0 +1,241 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm NAND controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,sdx75-nand
- const: qcom,sdx55-nand
- items:
- enum:
- qcom,ipq806x-nand
- qcom,ipq4019-nand
- qcom,ipq6018-nand
- qcom,ipq8074-nand
- qcom,sdx55-nand
reg:
maxItems: 1
clocks:
items:
- description: Core Clock
- description: Always ON Clock
clock-names:
items:
- const: core
- const: aon
qcom,cmd-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Must contain the ADM command type CRCI block instance number specified for
the NAND controller on the given platform
qcom,data-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Must contain the ADM data type CRCI block instance number specified for
the NAND controller on the given platform
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
nand-bus-width:
const: 8
nand-ecc-strength:
enum: [1, 4, 8]
nand-ecc-step-size:
enum:
- 512
qcom,boot-partitions:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: offset
- description: size
description:
Boot partition use a different layout where the 4 bytes of spare
data are not protected by ECC. Use this to declare these special
partitions by defining first the offset and then the size.
It's in the form of <offset1 size1 offset2 size2 offset3 ...>
and should be declared in ascending order.
Refer to the ipq8064 example on how to use this special binding.
unevaluatedProperties: false
allOf:
- $ref: nand-controller.yaml#
- if:
properties:
compatible:
contains:
const: qcom,ipq806x-nand
then:
properties:
dmas:
items:
- description: rxtx DMA channel
dma-names:
items:
- const: rxtx
- if:
properties:
compatible:
contains:
enum:
- qcom,sdx75-nand
then:
properties:
iommus:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq4019-nand
- qcom,ipq6018-nand
- qcom,ipq8074-nand
- qcom,sdx55-nand
then:
properties:
dmas:
items:
- description: tx DMA channel
- description: rx DMA channel
- description: cmd DMA channel
dma-names:
items:
- const: tx
- const: rx
- const: cmd
qcom,cmd-crci: false
qcom,data-crci: false
patternProperties:
"^nand@[a-f0-9]$":
properties:
qcom,boot-partitions: false
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
nand-controller@1ac00000 {
compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
<&gcc EBI2_AON_CLK>;
clock-names = "core", "aon";
dmas = <&adm_dma 3>;
dma-names = "rxtx";
qcom,cmd-crci = <15>;
qcom,data-crci = <3>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-bus-width = <8>;
qcom,boot-partitions = <0x0 0x58a0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot-nand";
reg = <0 0x58a0000>;
};
partition@58a0000 {
label = "fs-nand";
reg = <0x58a0000 0x4000000>;
};
};
};
};
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
nand-controller@79b0000 {
compatible = "qcom,ipq4019-nand";
reg = <0x79b0000 0x1000>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>;
clock-names = "core", "aon";
dmas = <&qpicbam 0>,
<&qpicbam 1>,
<&qpicbam 2>;
dma-names = "tx", "rx", "cmd";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot-nand";
reg = <0 0x58a0000>;
};
partition@58a0000 {
label = "fs-nand";
reg = <0x58a0000 0x4000000>;
};
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml
+39
View File
@@ -0,0 +1,39 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Raw NAND Chip Common Properties
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
allOf:
- $ref: nand-chip.yaml#
- $ref: raw-nand-property.yaml#
description: |
The ECC strength and ECC step size properties define the user
desires in terms of correction capability of a controller. Together,
they request the ECC engine to correct {strength} bit errors per
{size} bytes for a particular raw NAND chip.
The interpretation of these parameters is implementation-defined, so
not all implementations must support all possible
combinations. However, implementations are encouraged to further
specify the value(s) they support.
properties:
$nodename:
pattern: "^nand@[a-f0-9]$"
reg:
description:
Contains the chip-select IDs.
required:
- reg
# This is a generic file other binding inherit from and extend
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/mtd/raw-nand-property.yaml
+98
View File
@@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/raw-nand-property.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Raw NAND Chip Common Properties
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
description: |
The ECC strength and ECC step size properties define the user
desires in terms of correction capability of a controller. Together,
they request the ECC engine to correct {strength} bit errors per
{size} bytes for a particular raw NAND chip.
The interpretation of these parameters is implementation-defined, so
not all implementations must support all possible
combinations. However, implementations are encouraged to further
specify the value(s) they support.
properties:
nand-ecc-placement:
description:
Location of the ECC bytes. This location is unknown by default
but can be explicitly set to "oob", if all ECC bytes are
known to be stored in the OOB area, or "interleaved" if ECC
bytes will be interleaved with regular data in the main area.
$ref: /schemas/types.yaml#/definitions/string
enum: [ oob, interleaved ]
deprecated: true
nand-ecc-mode:
description:
Legacy ECC configuration mixing the ECC engine choice and
configuration.
$ref: /schemas/types.yaml#/definitions/string
enum: [none, soft, soft_bch, hw, hw_syndrome, on-die]
deprecated: true
nand-bus-width:
description:
Bus width to the NAND chip
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
default: 8
nand-on-flash-bbt:
description:
With this property, the OS will search the device for a Bad
Block Table (BBT). If not found, it will create one, reserve
a few blocks at the end of the device to store it and update
it as the device ages. Otherwise, the out-of-band area of a
few pages of all the blocks will be scanned at boot time to
find Bad Block Markers (BBM). These markers will help to
build a volatile BBT in RAM.
$ref: /schemas/types.yaml#/definitions/flag
nand-ecc-maximize:
description:
Whether or not the ECC strength should be maximized. The
maximum ECC strength is both controller and chip
dependent. The ECC engine has to select the ECC config
providing the best strength and taking the OOB area size
constraint into account. This is particularly useful when
only the in-band area is used by the upper layers, and you
want to make your NAND as reliable as possible.
$ref: /schemas/types.yaml#/definitions/flag
nand-is-boot-medium:
description:
Whether or not the NAND chip is a boot medium. Drivers might
use this information to select ECC algorithms supported by
the boot ROM or similar restrictions.
$ref: /schemas/types.yaml#/definitions/flag
nand-rb:
description:
Contains the native Ready/Busy IDs.
$ref: /schemas/types.yaml#/definitions/uint32-array
rb-gpios:
description:
Contains one or more GPIO descriptor (the numper of descriptor
depends on the number of R/B pins exposed by the flash) for the
Ready/Busy pins. Active state refers to the NAND ready state and
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
wp-gpios:
description:
Contains one GPIO descriptor for the Write Protect pin.
Active state refers to the NAND Write Protect state and should be
set to GPIOD_ACTIVE_LOW unless the signal is inverted.
maxItems: 1
# This is a generic file other binding inherit from and extend
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/mtd/realtek,rtl9301-ecc.yaml
+41
View File
@@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/realtek,rtl9301-ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek SoCs NAND ECC engine
maintainers:
- Markus Stockhausen <markus.stockhausen@gmx.de>
properties:
compatible:
const: realtek,rtl9301-ecc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <1>;
#size-cells = <1>;
ecc0: ecc@1a600 {
compatible = "realtek,rtl9301-ecc";
reg = <0x1a600 0x54>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
+66
View File
@@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/renesas-nandc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
allOf:
- $ref: nand-controller.yaml
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r9a06g032-nandc
- const: renesas,rzn1-nandc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: APB host controller clock
- description: External NAND bus clock
clock-names:
items:
- const: hclk
- const: eclk
power-domains:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
nand-controller@40102000 {
compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
reg = <0x40102000 0x2000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
power-domains = <&sysctrl>;
#address-cells = <1>;
#size-cells = <0>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
+165
View File
@@ -0,0 +1,165 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SoCs NAND FLASH Controller (NFC)
allOf:
- $ref: nand-controller.yaml#
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
oneOf:
- const: rockchip,px30-nfc
- const: rockchip,rk2928-nfc
- const: rockchip,rv1108-nfc
- items:
- enum:
- rockchip,rk3036-nfc
- rockchip,rk3128-nfc
- const: rockchip,rk2928-nfc
- items:
- const: rockchip,rk3308-nfc
- const: rockchip,rv1108-nfc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: Bus Clock
- description: Module Clock
clock-names:
minItems: 1
items:
- const: ahb
- const: nfc
assigned-clocks:
maxItems: 1
assigned-clock-rates:
maxItems: 1
power-domains:
maxItems: 1
patternProperties:
"^nand@[0-7]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 7
nand-ecc-mode:
const: hw
nand-ecc-step-size:
const: 1024
nand-ecc-strength:
enum: [16, 24, 40, 60, 70]
description: |
The ECC configurations that can be supported are as follows.
NFC v600 ECC 16, 24, 40, 60
RK2928, RK3066, RK3188
NFC v622 ECC 16, 24, 40, 60
RK3036, RK3128
NFC v800 ECC 16
RK3308, RV1108
NFC v900 ECC 16, 40, 60, 70
RK3326, PX30
nand-bus-width:
const: 8
rockchip,boot-blks:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 2
default: 16
description:
The NFC driver need this information to select ECC
algorithms supported by the boot ROM.
Only used in combination with 'nand-is-boot-medium'.
rockchip,boot-ecc-strength:
enum: [16, 24, 40, 60, 70]
$ref: /schemas/types.yaml#/definitions/uint32
description: |
If specified it indicates that a different BCH/ECC setting is
supported by the boot ROM.
NFC v600 ECC 16, 24
RK2928, RK3066, RK3188
NFC v622 ECC 16, 24, 40, 60
RK3036, RK3128
NFC v800 ECC 16
RK3308, RV1108
NFC v900 ECC 16, 70
RK3326, PX30
Only used in combination with 'nand-is-boot-medium'.
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rk3308-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
nfc: nand-controller@ff4b0000 {
compatible = "rockchip,rk3308-nfc",
"rockchip,rv1108-nfc";
reg = <0xff4b0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
clock-names = "ahb", "nfc";
assigned-clocks = <&clks SCLK_NANDC>;
assigned-clock-rates = <150000000>;
pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
&flash_rdn &flash_rdy &flash_wrn>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
label = "rk-nand";
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <16>;
nand-is-boot-medium;
rockchip,boot-blks = <8>;
rockchip,boot-ecc-strength = <16>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/samsung,s5pv210-onenand.yaml
+65
View File
@@ -0,0 +1,65 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/samsung,s5pv210-onenand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5Pv210 SoC OneNAND Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
enum:
- samsung,s5pv210-onenand
reg:
items:
- description: Control registers
- description: OneNAND interface nCE[0]
- description: OneNAND interface nCE[1]
clocks:
maxItems: 2
clock-names:
items:
- const: bus
- const: onenand
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
allOf:
- $ref: nand-controller.yaml
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/s5pv210.h>
nand-controller@b0600000 {
compatible = "samsung,s5pv210-onenand";
reg = <0xb0600000 0x2000>,
<0xb0000000 0x20000>,
<0xb0040000 0x20000>;
clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
clock-names = "bus", "onenand";
interrupt-parent = <&vic1>;
interrupts = <31>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/spi-nand.yaml
+28
View File
@@ -0,0 +1,28 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/spi-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPI-NAND flash
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
allOf:
- $ref: nand-chip.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
const: spi-nand
reg:
description: Encode the chip-select line on the SPI bus
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
linux-7.2.3/Documentation/devicetree/bindings/mtd/st,spear600-smi.yaml
+84
View File
@@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/st,spear600-smi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics SPEAr600 Serial Memory Interface (SMI) Controller
maintainers:
- Richard Weinberger <richard@nod.at>
description:
The SPEAr600 Serial Memory Interface (SMI) is a dedicated serial flash
controller supporting up to four chip selects for serial NOR flashes
connected in parallel. The controller is memory-mapped and the attached
flash devices appear in the CPU address space.The driver
(drivers/mtd/devices/spear_smi.c) probes the attached flashes
dynamically by sending commands (e.g., RDID) to each bank.
Flash sub nodes describe the memory range and optional per-flash
properties.
properties:
compatible:
const: st,spear600-smi
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
clock-rate:
$ref: /schemas/types.yaml#/definitions/uint32
description: Functional clock rate of the SMI controller in Hz.
patternProperties:
"^flash@.*$":
$ref: /schemas/mtd/mtd.yaml#
properties:
reg:
maxItems: 1
st,smi-fast-mode:
type: boolean
description: Indicates that the attached flash supports fast read mode.
unevaluatedProperties: false
required:
- reg
required:
- compatible
- reg
- clock-rate
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
flash@fc000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xfc000000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <12>;
clock-rate = <50000000>; /* 50 MHz */
flash@fc000000 {
reg = <0xfc000000 0x1000>;
st,smi-fast-mode;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/st,spi-fsm.yaml
+68
View File
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/st,spi-fsm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics SPI FSM Serial NOR Flash Controller
maintainers:
- Angus Clark <angus.clark@st.com>
description:
The STMicroelectronics Fast Sequence Mode (FSM) controller is a dedicated
hardware accelerator integrated in older STiH4xx/STiDxxx set-top box SoCs
(such as STiH407, STiH416, STiD127). It connects directly to a single
external serial flash device used as the primary boot device. The FSM
executes hard-coded or configurable instruction sequences in hardware,
providing low-latency reads suitable for execute-in-place (XIP) boot
and high read bandwidth.
properties:
compatible:
const: st,spi-fsm
reg:
maxItems: 1
reg-names:
const: spi-fsm
interrupts:
maxItems: 1
st,syscfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to the system configuration registers used for boot-device selection.
st,boot-device-reg:
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset of the boot-device register within the st,syscfg node.
st,boot-device-spi:
$ref: /schemas/types.yaml#/definitions/uint32
description: Expected boot-device value when booting from this SPI controller.
required:
- compatible
- reg
- reg-names
- interrupts
- pinctrl-0
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
spifsm@fe902000 {
compatible = "st,spi-fsm";
reg = <0xfe902000 0x1000>;
reg-names = "spi-fsm";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&pinctrl_fsm>;
st,syscfg = <&syscfg_rear>;
st,boot-device-reg = <0x958>;
st,boot-device-spi = <0x1a>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
+158
View File
@@ -0,0 +1,158 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
maintainers:
- Christophe Kerello <christophe.kerello@foss.st.com>
properties:
compatible:
enum:
- st,stm32mp15-fmc2
- st,stm32mp1-fmc2-nfc
- st,stm32mp25-fmc2-nfc
reg:
minItems: 6
maxItems: 12
interrupts:
maxItems: 1
dmas:
items:
- description: tx DMA channel
- description: rx DMA channel
- description: ecc DMA channel
dma-names:
items:
- const: tx
- const: rx
- const: ecc
patternProperties:
"^nand@[a-f0-9]$":
type: object
$ref: raw-nand-chip.yaml
properties:
nand-ecc-step-size:
const: 512
nand-ecc-strength:
enum: [1, 4, 8]
unevaluatedProperties: false
allOf:
- $ref: nand-controller.yaml#
- if:
properties:
compatible:
contains:
const: st,stm32mp15-fmc2
then:
properties:
reg:
items:
- description: Registers
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
clocks:
maxItems: 1
resets:
maxItems: 1
required:
- clocks
- if:
properties:
compatible:
contains:
const: st,stm32mp1-fmc2-nfc
then:
properties:
reg:
items:
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
- if:
properties:
compatible:
contains:
const: st,stm32mp25-fmc2-nfc
then:
properties:
reg:
items:
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
- description: Chip select 2 data
- description: Chip select 2 command
- description: Chip select 2 address space
- description: Chip select 3 data
- description: Chip select 3 command
- description: Chip select 3 address space
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
nand-controller@58002000 {
compatible = "st,stm32mp15-fmc2";
reg = <0x58002000 0x1000>,
<0x80000000 0x1000>,
<0x88010000 0x1000>,
<0x88020000 0x1000>,
<0x81000000 0x1000>,
<0x89010000 0x1000>,
<0x89020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/mtd/technologic,nand.yaml
+45
View File
@@ -0,0 +1,45 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/technologic,nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Technologic Systems NAND controller
maintainers:
- Nikita Shubin <nikita.shubin@maquefel.me>
allOf:
- $ref: nand-controller.yaml
properties:
compatible:
oneOf:
- const: technologic,ts7200-nand
- items:
- enum:
- technologic,ts7300-nand
- technologic,ts7260-nand
- technologic,ts7250-nand
- const: technologic,ts7200-nand
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
nand-controller@60000000 {
compatible = "technologic,ts7200-nand";
reg = <0x60000000 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.yaml
+71
View File
@@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,am654-hbmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs
maintainers:
- Vignesh Raghavendra <vigneshr@ti.com>
properties:
compatible:
const: ti,am654-hbmc
reg:
maxItems: 2
power-domains: true
'#address-cells': true
'#size-cells': true
ranges: true
mux-controls:
description: MMIO mux controller node to select b/w OSPI and HBMC.
clocks:
maxItems: 1
patternProperties:
"^flash@[0-1],[0-9a-f]+$":
type: object
$ref: mtd-physmap.yaml
unevaluatedProperties: false
required:
- compatible
- reg
- ranges
- clocks
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
hbmc: memory-controller@47034000 {
compatible = "ti,am654-hbmc";
reg = <0x0 0x47034000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
<0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
clocks = <&k3_clks 102 0>;
#address-cells = <2>;
#size-cells = <1>;
power-domains = <&k3_pds 55>;
mux-controls = <&hbmc_mux 0>;
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
+126
View File
@@ -0,0 +1,126 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DaVinci NAND controller
maintainers:
- Marcus Folkesson <marcus.folkesson@gmail.com>
allOf:
- $ref: nand-controller.yaml
properties:
compatible:
enum:
- ti,davinci-nand
- ti,keystone-nand
reg:
items:
- description: Access window.
- description: AEMIF control registers.
partitions:
type: object
required:
- compatible
ti,davinci-chipselect:
description:
Number of chipselect. Indicate on the davinci_nand driver which
chipselect is used for accessing the nand.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
ti,davinci-mask-ale:
description:
Mask for ALE. Needed for executing address phase. These offset will be
added to the base address for the chip select space the NAND Flash
device is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x08
ti,davinci-mask-cle:
description:
Mask for CLE. Needed for executing command phase. These offset will be
added to the base address for the chip select space the NAND Flash device
is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x10
ti,davinci-mask-chipsel:
description:
Mask for chipselect address. Needed to mask addresses for given
chipselect.
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
ti,davinci-ecc-bits:
description: Used ECC bits.
enum: [1, 4]
ti,davinci-ecc-mode:
description: Operation mode of the NAND ECC mode.
$ref: /schemas/types.yaml#/definitions/string
enum: [none, soft, hw, on-die]
deprecated: true
ti,davinci-nand-buswidth:
description: Bus width to the NAND chip.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
default: 8
deprecated: true
ti,davinci-nand-use-bbt:
type: boolean
description:
Use flash based bad block table support. OOB identifier is saved in OOB
area.
deprecated: true
required:
- compatible
- reg
- ti,davinci-chipselect
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <1>;
nand-controller@2000000,0 {
compatible = "ti,davinci-nand";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x02000000 0x02000000>,
<1 0x00000000 0x00008000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-nand-buswidth = <16>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot env";
reg = <0 0x020000>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ti,elm.yaml
+72
View File
@@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,elm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments Error Location Module (ELM).
maintainers:
- Roger Quadros <rogerq@kernel.org>
description:
ELM module is used together with GPMC and NAND Flash to detect
errors and the location of the error based on BCH algorithms
so they can be corrected if possible.
properties:
compatible:
enum:
- ti,am3352-elm
- ti,am64-elm
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
description: Functional clock.
clock-names:
items:
- const: fck
power-domains:
maxItems: 1
ti,hwmods:
description:
Name of the HWMOD associated with ELM. This is for legacy
platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
required:
- compatible
- reg
- interrupts
allOf:
- if:
properties:
compatible:
contains:
const: ti,am64-elm
then:
required:
- clocks
- clock-names
- power-domains
additionalProperties: false
examples:
- |
elm: ecc@0 {
compatible = "ti,am3352-elm";
reg = <0x0 0x2000>;
interrupts = <4>;
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ti,gpmc-nand.yaml
+126
View File
@@ -0,0 +1,126 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC NAND Flash controller.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC NAND controller/Flash is represented as a child of the
GPMC controller node.
properties:
compatible:
items:
- enum:
- ti,am64-nand
- ti,omap2-nand
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for fifoevent
- description: Interrupt for termcount
"#address-cells": true
"#size-cells": true
ti,nand-ecc-opt:
description: Desired ECC algorithm
$ref: /schemas/types.yaml#/definitions/string
enum: [sw, ham1, bch4, bch8, bch16]
ti,nand-xfer-type:
description: Data transfer method between controller and chip.
$ref: /schemas/types.yaml#/definitions/string
enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
default: prefetch-polled
ti,elm-id:
description:
phandle to the ELM (Error Location Module).
$ref: /schemas/types.yaml#/definitions/phandle
nand-bus-width:
description:
Bus width to the NAND chip
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
default: 8
rb-gpios:
description:
GPIO connection to R/B signal from NAND chip
maxItems: 1
allOf:
- $ref: /schemas/memory-controllers/ti,gpmc-child.yaml
- $ref: mtd.yaml#
required:
- compatible
- reg
- ti,nand-ecc-opt
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
#address-cells = <1>;
#size-cells = <1>;
/* NAND generic properties */
nand-bus-width = <8>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
/* GPMC properties*/
gpmc,device-width = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/mtd/ti,gpmc-onenand.yaml
+84
View File
@@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-onenand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OneNAND over Texas Instruments GPMC bus.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC connected OneNAND (found on OMAP boards) are represented
as child nodes of the GPMC controller.
properties:
$nodename:
pattern: "^onenand@[0-9],[0,9]$"
compatible:
const: ti,omap2-onenand
reg:
items:
- description: |
Chip Select number, register offset and size of
OneNAND register window.
"#address-cells": true
"#size-cells": true
int-gpios:
description: GPIO specifier for the INT pin.
patternProperties:
"@[0-9a-f]+$":
$ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node
allOf:
- $ref: /schemas/memory-controllers/ti,gpmc-child.yaml
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
gpmc: memory-controller@6e000000 {
compatible = "ti,omap3430-gpmc";
reg = <0x6e000000 0x02d0>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
<1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
onenand@0,0 {
compatible = "ti,omap2-onenand";
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x00000000 0x00100000>;
};
partition@100000 {
label = "config";
reg = <0x00100000 0x002c0000>;
};
};
};