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lastdragon
2026-09-06 12:53:21 -06:00
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linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm.txt
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* Freescale Communications Processor Module
NOTE: This is an interim binding, and will likely change slightly,
as more devices are supported. The QE bindings especially are
incomplete.
* Root CPM node
Properties:
- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
- reg : A 48-byte region beginning with CPCR.
Example:
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <119c0 30>;
}
* Properties common to multiple CPM/QE devices
- fsl,cpm-command : This value is ORed with the opcode and command flag
to specify the device on which a CPM command operates.
- fsl,cpm-brg : Indicates which baud rate generator the device
is associated with. If absent, an unused BRG
should be dynamically allocated. If zero, the
device uses an external clock rather than a BRG.
- reg : Unless otherwise specified, the first resource represents the
scc/fcc/ucc registers, and the second represents the device's
parameter RAM region (if it has one).
* Multi-User RAM (MURAM)
The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
Ranges must be set up subject to the following restrictions:
- Children's reg nodes must be offsets from the start of all muram, even
if the user-data area does not begin at zero.
- If multiple range entries are used, the difference between the parent
address and the child address must be the same in all, so that a single
mapping can cover them all while maintaining the ability to determine
CPM-side offsets with pointer subtraction. It is recommended that
multiple range entries not be used.
- A child address of zero must be translatable, even if no reg resources
contain it.
A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
indicate the portion of muram that is usable by the OS for arbitrary
purposes. The data node may have an arbitrary number of reg resources,
all of which contribute to the allocatable muram pool.
Example, based on mpc8272:
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/brg.txt
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* Baud Rate Generators
Currently defined compatibles:
fsl,cpm-brg
fsl,cpm1-brg
fsl,cpm2-brg
Properties:
- reg : There may be an arbitrary number of reg resources; BRG
numbers are assigned to these in order.
- clock-frequency : Specifies the base frequency driving
the BRG.
Example:
brg@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
clock-frequency = <d#25000000>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/i2c.txt
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* I2C
The I2C controller is expressed as a bus under the CPM node.
Properties:
- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
- reg : On CPM2 devices, the second resource doesn't specify the I2C
Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
(typically 0x8afc 0x2).
- #address-cells : Should be one. The cell is the i2c device address with
the r/w bit set to zero.
- #size-cells : Should be zero.
- clock-frequency : Can be used to set the i2c clock frequency. If
unspecified, a default frequency of 60kHz is being used.
The following two properties are deprecated. They are only used by legacy
i2c drivers to find the bus to probe:
- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
the bus number is dynamically assigned by the i2c core.
- linux,i2c-class : Can be used to override the i2c class. The class is used
by legacy i2c device drivers to find a bus in a specific context like
system management, video or sound. By default, I2C_CLASS_HWMON (1) is
being used. The definition of the classes can be found in
include/i2c/i2c.h
Example, based on mpc823:
i2c@860 {
compatible = "fsl,mpc823-i2c",
"fsl,cpm1-i2c";
reg = <0x860 0x20 0x3c80 0x30>;
interrupts = <16>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-command = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "dallas,ds1307";
reg = <0x68>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/pic.txt
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* Interrupt Controllers
Currently defined compatibles:
- fsl,cpm1-pic
- only one interrupt cell
- fsl,pq1-pic
- fsl,cpm2-pic
- second interrupt cell is level/sense:
- 2 is falling edge
- 8 is active low
Example:
interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
compatible = "mpc8272-pic", "fsl,cpm2-pic";
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/usb.txt
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* USB (Universal Serial Bus Controller)
Properties:
- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
Example:
usb@11bc0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,cpm2-usb";
reg = <11b60 18 8b00 100>;
interrupts = <b 8>;
interrupt-parent = <&PIC>;
fsl,cpm-command = <2e600000>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
maintainers:
- Herve Codina <herve.codina@bootlin.com>
description:
The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
serial controller using the same TDM physical interface routed from TSA.
properties:
compatible:
items:
- enum:
- fsl,mpc885-scc-qmc
- fsl,mpc866-scc-qmc
- const: fsl,cpm1-scc-qmc
reg:
items:
- description: SCC (Serial communication controller) register base
- description: SCC parameter ram base
- description: Dual port ram base
reg-names:
items:
- const: scc_regs
- const: scc_pram
- const: dpram
interrupts:
maxItems: 1
description: SCC interrupt line in the CPM interrupt controller
fsl,tsa-serial:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to TSA node
- enum: [1, 2, 3]
description: |
TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these
values)
- 1: SCC2
- 2: SCC3
- 3: SCC4
description:
Should be a phandle/number pair. The phandle to TSA node and the TSA
serial interface to use.
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^channel@([0-9]|[1-5][0-9]|6[0-3])$':
description:
A channel managed by this controller
type: object
additionalProperties: false
properties:
reg:
minimum: 0
maximum: 63
description:
The channel number
fsl,operational-mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [transparent, hdlc]
default: transparent
description: |
The channel operational mode
- hdlc: The channel handles HDLC frames
- transparent: The channel handles raw data without any processing
fsl,reverse-data:
$ref: /schemas/types.yaml#/definitions/flag
description:
The bit order as seen on the channels is reversed,
transmitting/receiving the MSB of each octet first.
This flag is used only in 'transparent' mode.
fsl,tx-ts-mask:
$ref: /schemas/types.yaml#/definitions/uint64
description:
Channel assigned Tx time-slots within the Tx time-slots routed by the
TSA to this cell.
fsl,rx-ts-mask:
$ref: /schemas/types.yaml#/definitions/uint64
description:
Channel assigned Rx time-slots within the Rx time-slots routed by the
TSA to this cell.
compatible:
items:
- enum:
- fsl,mpc885-scc-qmc-hdlc
- fsl,mpc866-scc-qmc-hdlc
- const: fsl,cpm1-scc-qmc-hdlc
- const: fsl,qmc-hdlc
fsl,framer:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the framer node. The framer is in charge of an E1/T1 line
interface connected to the TDM bus. It can be used to get the E1/T1 line
status such as link up/down.
allOf:
- if:
properties:
compatible:
not:
contains:
const: fsl,qmc-hdlc
then:
properties:
fsl,framer: false
required:
- reg
- fsl,tx-ts-mask
- fsl,rx-ts-mask
required:
- compatible
- reg
- reg-names
- interrupts
- fsl,tsa-serial
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/cpm1-fsl,tsa.h>
qmc@a60 {
compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
reg = <0xa60 0x20>,
<0x3f00 0xc0>,
<0x2000 0x1000>;
reg-names = "scc_regs", "scc_pram", "dpram";
interrupts = <27>;
interrupt-parent = <&CPM_PIC>;
#address-cells = <1>;
#size-cells = <0>;
fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;
channel@16 {
/* Ch16 : First 4 even TS from all routed from TSA */
reg = <16>;
fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x000000aa>;
fsl,rx-ts-mask = <0x00000000 0x000000aa>;
};
channel@17 {
/* Ch17 : First 4 odd TS from all routed from TSA */
reg = <17>;
fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x00000055>;
fsl,rx-ts-mask = <0x00000000 0x00000055>;
};
channel@19 {
/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
compatible = "fsl,mpc885-scc-qmc-hdlc",
"fsl,cpm1-scc-qmc-hdlc",
"fsl,qmc-hdlc";
reg = <19>;
fsl,operational-mode = "hdlc";
fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
fsl,framer = <&framer>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PowerQUICC CPM Time-slot assigner (TSA) controller
maintainers:
- Herve Codina <herve.codina@bootlin.com>
description:
The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
Its purpose is to route some TDM time-slots to other internal serial
controllers.
properties:
compatible:
items:
- enum:
- fsl,mpc885-tsa
- fsl,mpc866-tsa
- const: fsl,cpm1-tsa
reg:
items:
- description: SI (Serial Interface) register base
- description: SI RAM base
reg-names:
items:
- const: si_regs
- const: si_ram
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^tdm@[0-1]$':
description:
The TDM managed by this controller
type: object
additionalProperties: false
properties:
reg:
minimum: 0
maximum: 1
description:
The TDM number for this TDM, 0 for TDMa and 1 for TDMb
fsl,common-rxtx-pins:
$ref: /schemas/types.yaml#/definitions/flag
description:
The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
Without the 'fsl,common-rxtx-pins' property, the four pins are used.
With the 'fsl,common-rxtx-pins' property, two pins are used.
clocks:
minItems: 2
items:
- description: External clock connected to L1RSYNC pin
- description: External clock connected to L1RCLK pin
- description: External clock connected to L1TSYNC pin
- description: External clock connected to L1TCLK pin
clock-names:
minItems: 2
items:
- const: l1rsync
- const: l1rclk
- const: l1tsync
- const: l1tclk
fsl,rx-frame-sync-delay-bits:
enum: [0, 1, 2, 3]
default: 0
description: |
Receive frame sync delay in number of bits.
Indicates the delay between the Rx sync and the first bit of the Rx
frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
fsl,tx-frame-sync-delay-bits:
enum: [0, 1, 2, 3]
default: 0
description: |
Transmit frame sync delay in number of bits.
Indicates the delay between the Tx sync and the first bit of the Tx
frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
fsl,clock-falling-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Data is sent on falling edge of the clock (and received on the rising
edge). If 'clock-falling-edge' is not present, data is sent on the
rising edge (and received on the falling edge).
fsl,fsync-rising-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Frame sync pulses are sampled with the rising edge of the channel
clock. If 'fsync-rising-edge' is not present, pulses are sampled with
the falling edge.
fsl,double-speed-clock:
$ref: /schemas/types.yaml#/definitions/flag
description:
The channel clock is twice the data rate.
patternProperties:
'^fsl,[rt]x-ts-routes$':
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
A list of tuple that indicates the Tx or Rx time-slots routes.
items:
items:
- description:
The number of time-slots
minimum: 1
maximum: 64
- description: |
The source (Tx) or destination (Rx) serial interface
(dt-bindings/soc/cpm1-fsl,tsa.h defines these values)
- 0: No destination
- 1: SCC2
- 2: SCC3
- 3: SCC4
- 4: SMC1
- 5: SMC2
enum: [0, 1, 2, 3, 4, 5]
minItems: 1
maxItems: 64
allOf:
# If fsl,common-rxtx-pins is present, only 2 clocks are needed.
# Else, the 4 clocks must be present.
- if:
required:
- fsl,common-rxtx-pins
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
else:
properties:
clocks:
minItems: 4
clock-names:
minItems: 4
required:
- reg
- clocks
- clock-names
required:
- compatible
- reg
- reg-names
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/cpm1-fsl,tsa.h>
tsa@ae0 {
compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
reg = <0xae0 0x10>,
<0xc00 0x200>;
reg-names = "si_regs", "si_ram";
#address-cells = <1>;
#size-cells = <0>;
tdm@0 {
/* TDMa */
reg = <0>;
clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
clock-names = "l1rsync", "l1rclk";
fsl,common-rxtx-pins;
fsl,fsync-rising-edge;
fsl,tx-ts-routes = <2 0>, /* TS 0..1 */
<24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */
<1 0>, /* TS 26 */
<5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */
fsl,rx-ts-routes = <2 0>, /* TS 0..1 */
<24 FSL_CPM_TSA_SCC4>, /* 2..25 */
<1 0>, /* TS 26 */
<5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QUICC Engine module Firmware Node
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
This node defines a firmware binary that is embedded in the device tree, for
the purpose of passing the firmware from bootloader to the kernel, or from
the hypervisor to the guest.
The firmware node itself contains the firmware binary contents, a compatible
property, and any firmware-specific properties. The node should be placed
inside a QE node that needs it. Doing so eliminates the need for a
fsl,firmware-phandle property. Other QE nodes that need the same firmware
should define an fsl,firmware-phandle property that points to the firmware node
in the first QE node.
The fsl,firmware property can be specified in the DTS (possibly using incbin)
or can be inserted by the boot loader at boot time.
properties:
compatible:
enum:
- fsl,qe-firmware
fsl,firmware:
$ref: /schemas/types.yaml#/definitions/uint8-array
description:
A standard property. This property contains the firmware binary "blob".
required:
- compatible
- fsl,firmware
additionalProperties: false
examples:
- |
qe-firmware {
compatible = "fsl,qe-firmware";
fsl,firmware = <0x70 0xcd 0x00 0x00 0x01 0x46 0x45>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QUICC Engine module Interrupt Controller (IC)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,qe-ic
reg:
maxItems: 1
interrupts:
items:
- description: QE interrupt
- description: QE critical
- description: QE error
minItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 1
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
examples:
- |
interrupt-controller@80 {
compatible = "fsl,qe-ic";
reg = <0x80 0x80>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <95 2 0 0 94 2 0 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QUICC Engine Multi-User RAM (MURAM)
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: Multi-User RAM (MURAM)
properties:
compatible:
items:
- const: fsl,qe-muram
- const: fsl,cpm-muram
ranges:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [host, slave]
patternProperties:
'^data\-only@[a-f0-9]+$':
type: object
properties:
compatible:
items:
- const: fsl,qe-muram-data
- const: fsl,cpm-muram-data
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
required:
- compatible
- ranges
additionalProperties: false
examples:
- |
muram@10000 {
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 0x00010000 0x0000c000>;
#address-cells = <1>;
#size-cells = <1>;
data-only@0{
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0 0xc000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QUICC Engine module Serial Interface Block (SI)
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
The SI manages the routing of eight TDM lines to the QE block serial drivers,
the MCC and the UCCs, for receive and transmit.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,ls1043-qe-si
- const: fsl,t1040-qe-si
- enum:
- fsl,t1040-qe-si
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
si@700 {
compatible = "fsl,t1040-qe-si";
reg = <0x700 0x80>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QUICC Engine module Serial Interface Block RAM(SIRAM)
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
store the routing entries of SI
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,ls1043-qe-siram
- const: fsl,t1040-qe-siram
- const: fsl,t1040-qe-siram
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
siram@1000 {
compatible = "fsl,t1040-qe-siram";
reg = <0x1000 0x800>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PowerQUICC QE Time-slot assigner (TSA) controller
maintainers:
- Herve Codina <herve.codina@bootlin.com>
description:
The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
Its purpose is to route some TDM time-slots to other internal serial
controllers.
properties:
compatible:
items:
- enum:
- fsl,mpc8321-tsa
- const: fsl,qe-tsa
reg:
items:
- description: SI (Serial Interface) register base
- description: SI RAM base
reg-names:
items:
- const: si_regs
- const: si_ram
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^tdm@[0-3]$':
description:
The TDM managed by this controller
type: object
additionalProperties: false
properties:
reg:
minimum: 0
maximum: 3
description:
The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3
for TDMd.
fsl,common-rxtx-pins:
$ref: /schemas/types.yaml#/definitions/flag
description:
The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
Without the 'fsl,common-rxtx-pins' property, the four pins are used.
With the 'fsl,common-rxtx-pins' property, two pins are used.
clocks:
minItems: 2
items:
- description: Receive sync clock
- description: Receive data clock
- description: Transmit sync clock
- description: Transmit data clock
clock-names:
minItems: 2
items:
- const: rsync
- const: rclk
- const: tsync
- const: tclk
fsl,rx-frame-sync-delay-bits:
enum: [0, 1, 2, 3]
default: 0
description: |
Receive frame sync delay in number of bits.
Indicates the delay between the Rx sync and the first bit of the Rx
frame.
fsl,tx-frame-sync-delay-bits:
enum: [0, 1, 2, 3]
default: 0
description: |
Transmit frame sync delay in number of bits.
Indicates the delay between the Tx sync and the first bit of the Tx
frame.
fsl,clock-falling-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Data is sent on falling edge of the clock (and received on the rising
edge). If not present, data is sent on the rising edge (and received
on the falling edge).
fsl,fsync-rising-edge:
$ref: /schemas/types.yaml#/definitions/flag
description:
Frame sync pulses are sampled with the rising edge of the channel
clock. If not present, pulses are sampled with the falling edge.
fsl,fsync-active-low:
$ref: /schemas/types.yaml#/definitions/flag
description:
Frame sync signals are active on low logic level.
If not present, sync signals are active on high level.
fsl,double-speed-clock:
$ref: /schemas/types.yaml#/definitions/flag
description:
The channel clock is twice the data rate.
patternProperties:
'^fsl,[rt]x-ts-routes$':
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
A list of tuple that indicates the Tx or Rx time-slots routes.
items:
items:
- description:
The number of time-slots
minimum: 1
maximum: 64
- description: |
The source (Tx) or destination (Rx) serial interface
(dt-bindings/soc/qe-fsl,tsa.h defines these values)
- 0: No destination
- 1: UCC1
- 2: UCC2
- 3: UCC3
- 4: UCC4
- 5: UCC5
enum: [0, 1, 2, 3, 4, 5]
minItems: 1
maxItems: 64
allOf:
# If fsl,common-rxtx-pins is present, only 2 clocks are needed.
# Else, the 4 clocks must be present.
- if:
required:
- fsl,common-rxtx-pins
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
else:
properties:
clocks:
minItems: 4
clock-names:
minItems: 4
required:
- reg
- clocks
- clock-names
required:
- compatible
- reg
- reg-names
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qe-fsl,tsa.h>
tsa@ae0 {
compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa";
reg = <0xae0 0x10>,
<0xc00 0x200>;
reg-names = "si_regs", "si_ram";
#address-cells = <1>;
#size-cells = <0>;
tdm@0 {
/* TDMa */
reg = <0>;
clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
clock-names = "rsync", "rclk";
fsl,common-rxtx-pins;
fsl,fsync-rising-edge;
fsl,tx-ts-routes = <2 0>, /* TS 0..1 */
<24 FSL_QE_TSA_UCC4>, /* TS 2..25 */
<1 0>, /* TS 26 */
<5 FSL_QE_TSA_UCC3>; /* TS 27..31 */
fsl,rx-ts-routes = <2 0>, /* TS 0..1 */
<24 FSL_QE_TSA_UCC4>, /* 2..25 */
<1 0>, /* TS 26 */
<5 FSL_QE_TSA_UCC3>; /* TS 27..31 */
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PowerQUICC QE QUICC Multichannel Controller (QMC)
maintainers:
- Herve Codina <herve.codina@bootlin.com>
description:
The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
serial controller using the same TDM physical interface routed from TSA.
properties:
compatible:
items:
- enum:
- fsl,mpc8321-ucc-qmc
- const: fsl,qe-ucc-qmc
reg:
items:
- description: UCC (Unified communication controller) register base
- description: Dual port ram base
reg-names:
items:
- const: ucc_regs
- const: dpram
interrupts:
maxItems: 1
description: UCC interrupt line in the QE interrupt controller
fsl,tsa-serial:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to TSA node
- enum: [1, 2, 3, 4, 5]
description: |
TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these
values)
- 1: UCC1
- 2: UCC2
- 3: UCC3
- 4: UCC4
- 5: UCC5
description:
Should be a phandle/number pair. The phandle to TSA node and the TSA
serial interface to use.
fsl,soft-qmc:
$ref: /schemas/types.yaml#/definitions/string
description:
Soft QMC firmware name to load. If this property is omitted, no firmware
are used.
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^channel@([0-9]|[1-5][0-9]|6[0-3])$':
description:
A channel managed by this controller
type: object
additionalProperties: false
properties:
compatible:
items:
- enum:
- fsl,mpc8321-ucc-qmc-hdlc
- const: fsl,qe-ucc-qmc-hdlc
- const: fsl,qmc-hdlc
reg:
minimum: 0
maximum: 63
description:
The channel number
fsl,operational-mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [transparent, hdlc]
default: transparent
description: |
The channel operational mode
- hdlc: The channel handles HDLC frames
- transparent: The channel handles raw data without any processing
fsl,reverse-data:
$ref: /schemas/types.yaml#/definitions/flag
description:
The bit order as seen on the channels is reversed,
transmitting/receiving the MSB of each octet first.
This flag is used only in 'transparent' mode.
fsl,tx-ts-mask:
$ref: /schemas/types.yaml#/definitions/uint64
description:
Channel assigned Tx time-slots within the Tx time-slots routed by the
TSA to this cell.
fsl,rx-ts-mask:
$ref: /schemas/types.yaml#/definitions/uint64
description:
Channel assigned Rx time-slots within the Rx time-slots routed by the
TSA to this cell.
fsl,framer:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the framer node. The framer is in charge of an E1/T1 line
interface connected to the TDM bus. It can be used to get the E1/T1 line
status such as link up/down.
allOf:
- if:
properties:
compatible:
not:
contains:
const: fsl,qmc-hdlc
then:
properties:
fsl,framer: false
required:
- reg
- fsl,tx-ts-mask
- fsl,rx-ts-mask
required:
- compatible
- reg
- reg-names
- interrupts
- fsl,tsa-serial
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qe-fsl,tsa.h>
qmc@a60 {
compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";
reg = <0x3200 0x200>,
<0x10000 0x1000>;
reg-names = "ucc_regs", "dpram";
interrupts = <35>;
interrupt-parent = <&qeic>;
fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin";
#address-cells = <1>;
#size-cells = <0>;
fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>;
channel@16 {
/* Ch16 : First 4 even TS from all routed from TSA */
reg = <16>;
fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x000000aa>;
fsl,rx-ts-mask = <0x00000000 0x000000aa>;
};
channel@17 {
/* Ch17 : First 4 odd TS from all routed from TSA */
reg = <17>;
fsl,operational-mode = "transparent";
fsl,reverse-data;
fsl,tx-ts-mask = <0x00000000 0x00000055>;
fsl,rx-ts-mask = <0x00000000 0x00000055>;
};
channel@19 {
/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
compatible = "fsl,mpc8321-ucc-qmc-hdlc",
"fsl,qe-ucc-qmc-hdlc",
"fsl,qmc-hdlc";
reg = <19>;
fsl,operational-mode = "hdlc";
fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
fsl,framer = <&framer>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale QUICC Engine module (QE)
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
This represents qe module that is installed on PowerQUICC II Pro.
NOTE: This is an interim binding; it should be updated to fit
in with the CPM binding later in this document.
Basically, it is a bus of devices, that could act more or less
as a complete entity (UCC, USB etc ). All of them should be siblings on
the "root" qe node, using the common properties from there.
The description below applies to the qe of MPC8360 and
more nodes and properties would be extended in the future.
properties:
compatible:
items:
- const: fsl,qe
- const: simple-bus
reg:
maxItems: 1
ranges:
maxItems: 1
model:
$ref: /schemas/types.yaml#/definitions/string
enum: [QE, CPM, CPM2]
bus-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: the clock frequency for QUICC Engine.
fsl,qe-num-riscs:
$ref: /schemas/types.yaml#/definitions/uint32
description: define how many RISC engines the QE has.
fsl,qe-snums:
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 28
description:
defining the array of serial number (SNUM) values for the virtual
threads.
fsl,firmware-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
required only if there is no fsl,qe-firmware child node
Points to a firmware node (see "QE Firmware Node" below)
that contains the firmware that should be uploaded for this QE.
The compatible property for the firmware node should say,
"fsl,qe-firmware".
brg-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
the internal clock source frequency for baud-rate
generators in Hz.
fsl,qe-num-snums:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
description: |
define how many serial number(SNUM) the QE can use
for the threads. Use fsl,qe-snums instead to not only specify the
number of snums, but also their values.
patternProperties:
'^muram@[a-f0-9]+$':
$ref: fsl,qe-muram.yaml
'^interrupt-controller@[a-f0-9]+$':
$ref: fsl,qe-ic.yaml
'^si@[a-f0-9]+$':
$ref: fsl,qe-si.yaml
'^siram@[a-f0-9]+$':
$ref: fsl,qe-siram.yaml
required:
- compatible
- reg
- bus-frequency
allOf:
- $ref: /schemas/simple-bus.yaml#
unevaluatedProperties: false
examples:
- |
qe-bus@e0100000 {
compatible = "fsl,qe", "simple-bus";
reg = <0xe0100000 0x480>;
ranges = <0 0xe0100000 0x00100000>;
#address-cells = <1>;
#size-cells = <1>;
brg-frequency = <0>;
bus-frequency = <0x179a7b00>;
fsl,qe-snums = /bits/ 8 <
0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d
0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89
0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9
0xd8 0xd9 0xe8 0xe9>;
interrupt-controller@80 {
compatible = "fsl,qe-ic";
reg = <0x80 0x80>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <95 2 0 0 94 2 0 0>;
};
si@700 {
compatible = "fsl,t1040-qe-si";
reg = <0x700 0x80>;
};
siram@1000 {
compatible = "fsl,t1040-qe-siram";
reg = <0x1000 0x800>;
};
muram@10000 {
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 0x00010000 0x0000c000>;
#address-cells = <1>;
#size-cells = <1>;
data-only@0{
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0 0xc000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: High-Level Data Link Control(HDLC)
description: HDLC part in Universal communication controllers (UCCs)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,ucc-hdlc
reg:
maxItems: 1
interrupts:
maxItems: 1
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
rx-clock-name:
$ref: /schemas/types.yaml#/definitions/string
oneOf:
- pattern: "^brg([0-9]|1[0-6])$"
- pattern: "^clk([0-9]|1[0-9]|2[0-4])$"
tx-clock-name:
$ref: /schemas/types.yaml#/definitions/string
oneOf:
- pattern: "^brg([0-9]|1[0-6])$"
- pattern: "^clk([0-9]|1[0-9]|2[0-4])$"
fsl,tdm-interface:
$ref: /schemas/types.yaml#/definitions/flag
description: Specify that hdlc is based on tdm-interface
fsl,rx-sync-clock:
$ref: /schemas/types.yaml#/definitions/string
description: rx-sync
enum:
- none
- rsync_pin
- brg9
- brg10
- brg11
- brg13
- brg14
- brg15
fsl,tx-sync-clock:
$ref: /schemas/types.yaml#/definitions/string
description: tx-sync
enum:
- none
- tsync_pin
- brg9
- brg10
- brg11
- brg13
- brg14
- brg15
fsl,tdm-framer-type:
$ref: /schemas/types.yaml#/definitions/string
description: required for tdm interface
enum: [e1, t1]
fsl,tdm-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: number of TDM ID
fsl,tx-timeslot-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description:
required for tdm interface.
time slot mask for TDM operation. Indicates which time
slots used for transmitting and receiving.
fsl,rx-timeslot-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description:
required for tdm interface.
time slot mask for TDM operation. Indicates which time
slots used for transmitting and receiving.
fsl,siram-entry-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
required for tdm interface
Must be 0,2,4...64. the number of TDM entry.
fsl,tdm-internal-loopback:
$ref: /schemas/types.yaml#/definitions/flag
description:
optional for tdm interface
Internal loopback connecting on TDM layer.
fsl,hmask:
$ref: /schemas/types.yaml#/definitions/uint16
description: |
HDLC address recognition. Set to zero to disable
address filtering of packets:
fsl,hmask = /bits/ 16 <0x0000>;
required:
- compatible
- reg
additionalProperties: false
examples:
- |
communication@2000 {
compatible = "fsl,ucc-hdlc";
reg = <0x2000 0x200>;
rx-clock-name = "clk8";
tx-clock-name = "clk9";
fsl,rx-sync-clock = "rsync_pin";
fsl,tx-sync-clock = "tsync_pin";
fsl,tx-timeslot-mask = <0xfffffffe>;
fsl,rx-timeslot-mask = <0xfffffffe>;
fsl,tdm-framer-type = "e1";
fsl,tdm-id = <0>;
fsl,siram-entry-id = <0>;
fsl,tdm-interface;
};
- |
communication@2000 {
compatible = "fsl,ucc-hdlc";
reg = <0x2000 0x200>;
rx-clock-name = "brg1";
tx-clock-name = "brg1";
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt
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Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
On CPM1 devices, all ports are using slightly different register layouts.
Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
On CPM2 devices, all ports are 32bit ports and use a common register layout.
Required properties:
- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
"fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
"fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- gpio-controller : Marks the port as GPIO controller.
Optional properties:
- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
on CPM1), this item tells which ports have an associated interrupt (ports are
listed in the same order as in PCINT register)
- interrupts : This property provides the list of interrupt for each GPIO having
one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
many interrupts as number of ones in the mask property. The first interrupt in
the list corresponds to the most significant bit of the mask.
Example of four SOC GPIO banks defined as gpio-controller nodes:
CPM1_PIO_A: gpio-controller@950 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-a";
reg = <0x950 0x10>;
gpio-controller;
};
CPM1_PIO_B: gpio-controller@ab8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-b";
reg = <0xab8 0x10>;
gpio-controller;
};
CPM1_PIO_C: gpio-controller@960 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-c";
reg = <0x960 0x10>;
fsl,cpm1-gpio-irq-mask = <0x0fff>;
interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
interrupt-parent = <&CPM_PIC>;
gpio-controller;
};
CPM1_PIO_E: gpio-controller@ac8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-e";
reg = <0xac8 0x18>;
gpio-controller;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/firmware.txt
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* Uploaded QE firmware
If a new firmware has been uploaded to the QE (usually by the
boot loader), then a 'firmware' child node should be added to the QE
node. This node provides information on the uploaded firmware that
device drivers may need.
Required properties:
- id: The string name of the firmware. This is taken from the 'id'
member of the qe_firmware structure of the uploaded firmware.
Device drivers can search this string to determine if the
firmware they want is already present.
- extended-modes: The Extended Modes bitfield, taken from the
firmware binary. It is a 64-bit number represented
as an array of two 32-bit numbers.
- virtual-traps: The virtual traps, taken from the firmware binary.
It is an array of 8 32-bit numbers.
Example:
firmware {
id = "Soft-UART";
extended-modes = <0 0>;
virtual-traps = <0 0 0 0 0 0 0 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
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* Parallel I/O Ports
This node configures Parallel I/O ports for CPUs with QE support.
The node should reside in the "soc" node of the tree. For each
device that using parallel I/O ports, a child node should be created.
See the definition of the Pin configuration nodes below for more
information.
Required properties:
- device_type : should be "par_io".
- reg : offset to the register set and its length.
- num-ports : number of Parallel I/O ports
Example:
par_io@1400 {
reg = <1400 100>;
#address-cells = <1>;
#size-cells = <0>;
device_type = "par_io";
num-ports = <7>;
ucc_pin@1 {
......
};
Note that "par_io" nodes are obsolete, and should not be used for
the new device trees. Instead, each Par I/O bank should be represented
via its own gpio-controller node:
Required properties:
- #gpio-cells : should be "2".
- compatible : should be "fsl,<chip>-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank".
- reg : offset to the register set and its length.
- gpio-controller : node to identify gpio controllers.
Example:
qe_pio_a: gpio-controller@1400 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x1400 0x18>;
gpio-controller;
};
qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt
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* Pin configuration nodes
Required properties:
- pio-map : array of pin configurations. Each pin is defined by 6
integers. The six numbers are respectively: port, pin, dir,
open_drain, assignment, has_irq.
- port : port number of the pin; 0-6 represent port A-G in UM.
- pin : pin number in the port.
- dir : direction of the pin, should encode as follows:
0 = The pin is disabled
1 = The pin is an output
2 = The pin is an input
3 = The pin is I/O
- open_drain : indicates the pin is normal or wired-OR:
0 = The pin is actively driven as an output
1 = The pin is an open-drain driver. As an output, the pin is
driven active-low, otherwise it is three-stated.
- assignment : function number of the pin according to the Pin Assignment
tables in User Manual. Each pin can have up to 4 possible functions in
QE and two options for CPM.
- has_irq : indicates if the pin is used as source of external
interrupts.
Example:
ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 3 1 0 1 0 /* TxD0 */
0 4 1 0 1 0 /* TxD1 */
0 5 1 0 1 0 /* TxD2 */
0 6 1 0 1 0 /* TxD3 */
1 6 1 0 3 0 /* TxD4 */
1 7 1 0 1 0 /* TxD5 */
1 9 1 0 2 0 /* TxD6 */
1 a 1 0 2 0 /* TxD7 */
0 9 2 0 1 0 /* RxD0 */
0 a 2 0 1 0 /* RxD1 */
0 b 2 0 1 0 /* RxD2 */
0 c 2 0 1 0 /* RxD3 */
0 d 2 0 1 0 /* RxD4 */
1 1 2 0 2 0 /* RxD5 */
1 0 2 0 2 0 /* RxD6 */
1 4 2 0 2 0 /* RxD7 */
0 7 1 0 1 0 /* TX_EN */
0 8 1 0 1 0 /* TX_ER */
0 f 2 0 1 0 /* RX_DV */
0 10 2 0 1 0 /* RX_ER */
0 0 2 0 1 0 /* RX_CLK */
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
2 8 2 0 1 0>; /* GTX125 - CLK9 */
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ucc.txt
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* UCC (Unified Communications Controllers)
Required properties:
- device_type : should be "network", "hldc", "uart", "transparent"
"bisync", "atm", or "serial".
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- pio-handle : The phandle for the Parallel I/O port configuration.
- port-number : for UART drivers, the port number to use, between 0 and 3.
This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
The port number is added to the minor number of the device. Unlike the
CPM UART driver, the port-number is required for the QE UART driver.
- soft-uart : for UART drivers, if specified this means the QE UART device
driver should use "Soft-UART" mode, which is needed on some SOCs that have
broken UART hardware. Soft-UART is provided via a microcode upload.
- rx-clock-name: the UCC receive clock source
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
- tx-clock-name: the UCC transmit clock source
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
The following two properties are deprecated. rx-clock has been replaced
with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
Drivers that currently use the deprecated properties should continue to
do so, in order to support older device trees, but they should be updated
to check for the new properties first.
- rx-clock : represents the UCC receive clock source.
0x00 : clock source is disabled;
0x1~0x10 : clock source is BRG1~BRG16 respectively;
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
- tx-clock: represents the UCC transmit clock source;
0x00 : clock source is disabled;
0x1~0x10 : clock source is BRG1~BRG16 respectively;
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
Required properties for network device_type:
- mac-address : list of bytes representing the ethernet address.
- phy-handle : The phandle for the PHY connected to this controller.
Recommended properties:
- phy-connection-type : a string naming the controller/PHY interface type,
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
"tbi", or "rtbi".
Example:
ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <2000 200>;
interrupts = <a0 0>;
interrupt-parent = <700>;
mac-address = [ 00 04 9f 00 23 23 ];
rx-clock = "none";
tx-clock = "clk9";
phy-handle = <212000>;
phy-connection-type = "gmii";
pio-handle = <140001>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/usb.txt
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Freescale QUICC Engine USB Controller
Required properties:
- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
- reg : the first two cells should contain usb registers location and
length, the next two two cells should contain PRAM location and
length.
- interrupts : should contain USB interrupt.
- fsl,fullspeed-clock : specifies the full speed USB clock source:
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
- fsl,lowspeed-clock : specifies the low speed USB clock source:
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
- hub-power-budget : USB power budget for the root hub, in mA.
- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
USBRN, SPEED (optional), and POWER (optional).
Example:
usb@6c0 {
compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
reg = <0x6c0 0x40 0x8b00 0x100>;
interrupts = <11>;
interrupt-parent = <&qeic>;
fsl,fullspeed-clock = "clk21";
gpios = <&qe_pio_b 2 0 /* USBOE */
&qe_pio_b 3 0 /* USBTP */
&qe_pio_b 8 0 /* USBTN */
&qe_pio_b 9 0 /* USBRP */
&qe_pio_b 11 0 /* USBRN */
&qe_pio_e 20 0 /* SPEED */
&qe_pio_e 21 0 /* POWER */>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/serial.txt
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* Serial
Currently defined compatibles:
- fsl,cpm1-smc-uart
- fsl,cpm2-smc-uart
- fsl,cpm1-scc-uart
- fsl,cpm2-scc-uart
- fsl,qe-uart
Modem control lines connected to GPIO controllers are listed in the gpios
property as described in booting-without-of.txt, section IX.1 in the following
order:
CTS, RTS, DCD, DSR, DTR, and RI.
The gpios property is optional and can be left out when control lines are
not used.
Example:
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
interrupts = <28 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
gpios = <&gpio_c 15 0
&gpio_d 29 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt
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* Serial
Required Properties:
compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
"fsl,t1040-ucc-uart".
port-number : port number of UCC-UART
tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
should be "clk1"-"clk28" for external clock source.
Example:
ucc_serial: ucc@2200 {
compatible = "fsl,t1040-ucc-uart";
port-number = <0>;
rx-clock-name = "brg2";
tx-clock-name = "brg2";
};