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lastdragon
2026-09-06 12:53:21 -06:00
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linux-7.2.3/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Timer Counter Block
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
description: |
The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
timer has three channels with two counters each.
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91rm9200-tcb
- atmel,at91sam9x5-tcb
- atmel,sama5d2-tcb
- const: simple-mfd
- const: syscon
- items:
- const: microchip,sam9x7-tcb
- const: atmel,sama5d2-tcb
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
interrupts:
description:
List of interrupts. One interrupt per TCB channel if available or one
interrupt for the TC block
minItems: 1
maxItems: 3
clock-names:
description:
List of clock names. Always includes t0_clk and slow clk. Also includes
t1_clk and t2_clk if a clock per channel is available.
minItems: 2
maxItems: 4
clocks:
minItems: 2
maxItems: 4
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^timer@[0-2]$':
description: The timer block channels that are used as timers or counters.
type: object
additionalProperties: false
properties:
compatible:
items:
- enum:
- atmel,tcb-timer
- atmel,tcb-pwm
- microchip,tcb-capture
reg:
description:
List of channels to use for this particular timer. In Microchip TCB capture
mode channels are registered as a counter devices, for the qdec mode TCB0's
channel <0> and <1> are required.
minItems: 1
maxItems: 3
required:
- compatible
- reg
'^pwm@[0-2]$':
description: The timer block channels that are used as PWMs.
$ref: /schemas/pwm/pwm.yaml#
type: object
properties:
compatible:
const: atmel,tcb-pwm
reg:
description:
TCB channel to use for this PWM.
enum: [ 0, 1, 2 ]
'#pwm-cells':
description:
The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
const: 3
required:
- compatible
- reg
- '#pwm-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: atmel,sama5d2-tcb
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: t0_clk
- const: gclk
- const: slow_clk
else:
properties:
clocks:
minItems: 2
maxItems: 4
clock-names:
oneOf:
- items:
- const: t0_clk
- const: slow_clk
- items:
- const: t0_clk
- const: t1_clk
- const: t2_clk
- const: slow_clk
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
/* One interrupt per TC block: */
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <18 4>;
clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
/* One interrupt per TC channel in a TC block: */
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffdc000 0x100>;
interrupts = <26 4>, <27 4>, <28 4>;
clocks = <&tcb1_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
pwm@2 {
compatible = "atmel,tcb-pwm";
reg = <2>;
#pwm-cells = <3>;
};
};
/* TCB0 Capture with QDEC: */
timer@f800c000 {
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <18 4>;
clocks = <&tcb0_clk>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
timer@0 {
compatible = "microchip,tcb-capture";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-irqmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Polarfire SoC GPIO Interrupt Mux
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description: |
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used to
ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct mode",
as they provide an exclusive connection from a GPIO to the PLIC.
Lines 18 to 23 on GPIO controller 1 are always in "direct mode".
The 3 remaining interrupts are used to mux the interrupts which do not have
a exclusive connection, one for each GPIO controller.
properties:
compatible:
oneOf:
- items:
- const: microchip,pic64gx-irqmux
- const: microchip,mpfs-irqmux
- const: microchip,mpfs-irqmux
reg:
maxItems: 1
"#address-cells":
const: 0
"#interrupt-cells":
const: 1
interrupt-map-mask:
items:
- const: 0x7f
interrupt-map:
description: |
Specifies the mapping from GPIO interrupt lines to plic interrupts.
The child interrupt number set in arrays items is computed using the
following formula:
gpio_bank * 32 + gpio_number
with:
- gpio_bank: The GPIO bank number
- 0 for GPIO0,
- 1 for GPIO1,
- 2 for GPIO2
- gpio_number: Number of the gpio in the bank (0..31)
maxItems: 70
required:
- compatible
- reg
- "#address-cells"
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
additionalProperties: false
examples:
- |
interrupt-controller@54 {
compatible = "microchip,mpfs-irqmux";
reg = <0x54 0x4>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x7f>;
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description:
An wide assortment of registers that control elements of the MSS on PolarFire
SoC, including pinmuxing, resets and clocks among others.
properties:
compatible:
oneOf:
- items:
- const: microchip,mpfs-mss-top-sysreg
- const: syscon
- const: simple-mfd
- items:
- const: microchip,pic64gx-mss-top-sysreg
- const: microchip,mpfs-mss-top-sysreg
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
'#reset-cells':
description:
The AHB/AXI peripherals on the PolarFire SoC have reset support, so
from CLK_ENVM to CLK_CFM. The reset consumer should specify the
desired peripheral via the clock ID in its "resets" phandle cell.
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
of PolarFire clock/reset IDs.
const: 1
interrupt-controller@54:
type: object
$ref: /schemas/soc/microchip/microchip,mpfs-irqmux.yaml
pinctrl@200:
type: object
$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
pinctrl@204:
type: object
$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x20002000 0x1000>;
#reset-cells = <1>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description: |
PolarFire SoC devices include a microcontroller acting as the system controller,
which provides "services" to the main processor and to the FPGA fabric. These
services include hardware rng, reprogramming of the FPGA and verification of the
eNVM contents etc. More information on these services can be found online, at
https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
Communication with the system controller is done via a mailbox, of which the client
portion is documented here.
properties:
mboxes:
maxItems: 1
compatible:
enum:
- microchip,mpfs-sys-controller
- microchip,pic64gx-sys-controller
microchip,bitstream-flash:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The SPI flash connected to the system controller's QSPI controller.
The system controller may retrieve FPGA bitstreams from this flash to
perform In-Application Programming (IAP) or during device initialisation
for Auto Update. The MSS and system controller have separate QSPI
controllers and this flash is connected to both. Software running in the
MSS can write bitstreams to the flash.
required:
- compatible
- mboxes
additionalProperties: false
examples:
- |
syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/soc/microchip/microchip,sparx5-cpu-syscon.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,sparx5-cpu-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Sparx5 CPU Syscon
maintainers:
- Lars Povlsen <lars.povlsen@microchip.com>
properties:
compatible:
items:
- const: microchip,sparx5-cpu-syscon
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
mux-controller:
$ref: /schemas/mux/reg-mux.yaml#
required:
- compatible
- reg
- mux-controller
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <1>;
syscon@600000000 {
compatible = "microchip,sparx5-cpu-syscon", "syscon",
"simple-mfd";
reg = <0x6 0x00000000 0xd0>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x88 0xf0>;
};
};
};