Resguardo inicial

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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMD AXI 1-wire bus host for programmable logic
maintainers:
- Kris Chaplin <kris.chaplin@amd.com>
properties:
compatible:
const: amd,axi-1wire-host
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
onewire@a0000000 {
compatible = "amd,axi-1wire-host";
reg = <0xa0000000 0x10000>;
clocks = <&zynqmp_clk 0x47>;
interrupts = <GIC_SPI 0x59 IRQ_TYPE_LEVEL_HIGH>;
};
...
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/w1/fsl-imx-owire.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX One wire bus master controller
maintainers:
- Martin Fuzzey <mfuzzey@parkeon.com>
properties:
compatible:
oneOf:
- const: fsl,imx21-owire
- items:
- enum:
- fsl,imx27-owire
- fsl,imx50-owire
- fsl,imx51-owire
- fsl,imx53-owire
- const: fsl,imx21-owire
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
owire@63fa4000 {
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
interrupts = <88>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
};
@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/w1/maxim,ds2482.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim One wire bus master controller
maintainers:
- Stefan Wahren <stefan.wahren@chargebyte.com>
description: |
I2C to 1-wire bridges
https://www.analog.com/media/en/technical-documentation/data-sheets/ds2482-100.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/DS2482-800.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/DS2484.pdf
properties:
compatible:
enum:
- maxim,ds2482
- maxim,ds2484
reg:
maxItems: 1
vcc-supply: true
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
onewire@18 {
compatible = "maxim,ds2484";
reg = <0x18>;
};
};
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* OMAP HDQ One wire bus master controller
Required properties:
- compatible : should be "ti,omap3-1w" or "ti,am4372-hdq"
- reg : Address and length of the register set for the device
- interrupts : interrupt line.
- ti,hwmods : "hdq1w"
Optional properties:
- ti,mode: should be "hdq": HDQ mode "1w": one-wire mode.
If not specified HDQ mode is implied.
Example:
- From omap3.dtsi
hdqw1w: 1w@480b2000 {
compatible = "ti,omap3-1w";
reg = <0x480b2000 0x1000>;
interrupts = <58>;
ti,hwmods = "hdq1w";
ti,mode = "hdq";
};
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/w1/w1-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bitbanged GPIO 1-Wire Bus
maintainers:
- Daniel Mack <zonque@gmail.com>
properties:
compatible:
const: w1-gpio
gpios:
minItems: 1
items:
- description: Data I/O pin
- description: Enable pin for an external pull-up resistor
linux,open-drain:
type: boolean
description: >
If specified, the data pin is considered in open-drain mode.
required:
- compatible
- gpios
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/gpio/gpio.h>
onewire {
compatible = "w1-gpio";
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
};
...
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/w1/w1-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UART 1-Wire Bus
maintainers:
- Christoph Winklhofer <cj.winklhofer@gmail.com>
description: |
UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
to create the 1-Wire timing patterns.
The UART peripheral must support full-duplex and operate in open-drain
mode. The timing patterns are generated by a specific combination of
baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
write bit or reset pulse.
The default baud-rate for reset and presence detection is 9600 and for
a 1-Wire read or write operation 115200. In case the actual baud-rate
is different from the requested one, the transmitted byte is adapted
to generate the 1-Wire timing patterns.
https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html
properties:
compatible:
const: w1-uart
reset-bps:
default: 9600
description:
The baud rate for the 1-Wire reset and presence detect.
write-0-bps:
default: 115200
description:
The baud rate for the 1-Wire write-0 cycle.
write-1-bps:
default: 115200
description:
The baud rate for the 1-Wire write-1 and read cycle.
required:
- compatible
additionalProperties:
type: object
examples:
- |
serial {
onewire {
compatible = "w1-uart";
};
};
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Generic devicetree bindings for onewire (w1) busses
===================================================
Onewire busses are described through nodes of their master bus controller.
Slave devices are listed as sub-nodes of such master devices. For now, only
one slave is allowed per bus master.
Example:
charger: charger {
compatible = "gpio-charger";
charger-type = "mains";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
onewire {
compatible = "w1-gpio";
gpios = <&gpio 100 0>, <&gpio 101 0>;
battery {
compatible = "maxim,ds2760";
power-supplies = <&charger>;
};
};