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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arc/boot/.gitignore
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# SPDX-License-Identifier: GPL-2.0-only
uImage
linux-7.2.3/arch/arc/boot/Makefile
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# SPDX-License-Identifier: GPL-2.0
# uImage build relies on mkimage being available on your host for ARC target
# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
# and make sure it's reachable from your PATH
OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S
LINUX_START_TEXT = $$($(READELF) -h vmlinux | \
grep "Entry point address" | grep -o 0x.*)
UIMAGE_LOADADDR = $(CONFIG_LINUX_LINK_BASE)
UIMAGE_ENTRYADDR = $(LINUX_START_TEXT)
targets += vmlinux.bin
targets += vmlinux.bin.gz
targets += vmlinux.bin.lzma
targets += uImage.bin
targets += uImage.gz
targets += uImage.lzma
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
$(call if_changed,gzip)
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzma)
$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
$(call if_changed,uimage,none)
$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
$(call if_changed,uimage,gzip)
$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE
$(call if_changed,uimage,lzma)
linux-7.2.3/arch/arc/boot/dts/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-y := $(addsuffix .dtb, $(CONFIG_BUILTIN_DTB_NAME))
# for CONFIG_OF_ALL_DTBS test
dtb- := $(patsubst $(src)/%.dts,%.dtb, $(wildcard $(src)/*.dts))
# board-specific dtc flags
DTC_FLAGS_hsdk += --pad 20
linux-7.2.3/arch/arc/boot/dts/abilis_tb100.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB100 SOC device tree
*
* Copyright (C) Abilis Systems 2013
*
* Author: Christian Ruppert <christian.ruppert@abilis.com>
*/
/include/ "abilis_tb10x.dtsi"
/ {
soc100 {
bus-frequency = <166666666>;
pll0: oscillator {
clock-frequency = <1000000000>;
};
cpu_clk: clkdiv_cpu {
clock-mult = <1>;
clock-div = <2>;
};
ahb_clk: clkdiv_ahb {
clock-mult = <1>;
clock-div = <6>;
};
iomux: iomux@ff10601c {
/* Port 1 */
pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
abilis,function = "mis0";
};
pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
abilis,function = "mis1";
};
pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
abilis,function = "gpioa";
};
pctl_tsin_p1: pctl-tsin-p1 { /* Parallel TS-in 1 */
abilis,function = "mip1";
};
/* Port 2 */
pctl_tsin_s2: pctl-tsin-s2 { /* Serial TS-in 2 */
abilis,function = "mis2";
};
pctl_tsin_s3: pctl-tsin-s3 { /* Serial TS-in 3 */
abilis,function = "mis3";
};
pctl_gpio_c: pctl-gpio-c { /* GPIO bank C */
abilis,function = "gpioc";
};
pctl_tsin_p3: pctl-tsin-p3 { /* Parallel TS-in 3 */
abilis,function = "mip3";
};
/* Port 3 */
pctl_tsin_s4: pctl-tsin-s4 { /* Serial TS-in 4 */
abilis,function = "mis4";
};
pctl_tsin_s5: pctl-tsin-s5 { /* Serial TS-in 5 */
abilis,function = "mis5";
};
pctl_gpio_e: pctl-gpio-e { /* GPIO bank E */
abilis,function = "gpioe";
};
pctl_tsin_p5: pctl-tsin-p5 { /* Parallel TS-in 5 */
abilis,function = "mip5";
};
/* Port 4 */
pctl_tsin_s6: pctl-tsin-s6 { /* Serial TS-in 6 */
abilis,function = "mis6";
};
pctl_tsin_s7: pctl-tsin-s7 { /* Serial TS-in 7 */
abilis,function = "mis7";
};
pctl_gpio_g: pctl-gpio-g { /* GPIO bank G */
abilis,function = "gpiog";
};
pctl_tsin_p7: pctl-tsin-p7 { /* Parallel TS-in 7 */
abilis,function = "mip7";
};
/* Port 5 */
pctl_gpio_j: pctl-gpio-j { /* GPIO bank J */
abilis,function = "gpioj";
};
pctl_gpio_k: pctl-gpio-k { /* GPIO bank K */
abilis,function = "gpiok";
};
pctl_ciplus: pctl-ciplus { /* CI+ interface */
abilis,function = "ciplus";
};
pctl_mcard: pctl-mcard { /* M-Card interface */
abilis,function = "mcard";
};
/* Port 6 */
pctl_tsout_p: pctl-tsout-p { /* Parallel TS-out */
abilis,function = "mop";
};
pctl_tsout_s0: pctl-tsout-s0 { /* Serial TS-out 0 */
abilis,function = "mos0";
};
pctl_tsout_s1: pctl-tsout-s1 { /* Serial TS-out 1 */
abilis,function = "mos1";
};
pctl_tsout_s2: pctl-tsout-s2 { /* Serial TS-out 2 */
abilis,function = "mos2";
};
pctl_tsout_s3: pctl-tsout-s3 { /* Serial TS-out 3 */
abilis,function = "mos3";
};
/* Port 7 */
pctl_uart0: pctl-uart0 { /* UART 0 */
abilis,function = "uart0";
};
pctl_uart1: pctl-uart1 { /* UART 1 */
abilis,function = "uart1";
};
pctl_gpio_l: pctl-gpio-l { /* GPIO bank L */
abilis,function = "gpiol";
};
pctl_gpio_m: pctl-gpio-m { /* GPIO bank M */
abilis,function = "gpiom";
};
/* Port 8 */
pctl_spi3: pctl-spi3 {
abilis,function = "spi3";
};
/* Port 9 */
pctl_spi1: pctl-spi1 {
abilis,function = "spi1";
};
pctl_gpio_n: pctl-gpio-n {
abilis,function = "gpion";
};
/* Unmuxed GPIOs */
pctl_gpio_b: pctl-gpio-b {
abilis,function = "gpiob";
};
pctl_gpio_d: pctl-gpio-d {
abilis,function = "gpiod";
};
pctl_gpio_f: pctl-gpio-f {
abilis,function = "gpiof";
};
pctl_gpio_h: pctl-gpio-h {
abilis,function = "gpioh";
};
pctl_gpio_i: pctl-gpio-i {
abilis,function = "gpioi";
};
};
gpioa: gpio@ff140000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff140000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioa";
};
gpiob: gpio@ff141000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff141000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiob";
};
gpioc: gpio@ff142000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff142000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioc";
};
gpiod: gpio@ff143000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff143000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiod";
};
gpioe: gpio@ff144000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff144000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioe";
};
gpiof: gpio@ff145000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff145000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiof";
};
gpiog: gpio@ff146000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff146000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiog";
};
gpioh: gpio@ff147000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff147000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioh";
};
gpioi: gpio@ff148000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff148000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <12>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioi";
};
gpioj: gpio@ff149000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff149000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <32>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioj";
};
gpiok: gpio@ff14a000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14a000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <22>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiok";
};
gpiol: gpio@ff14b000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14b000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <4>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiol";
};
gpiom: gpio@ff14c000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14c000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <4>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiom";
};
gpion: gpio@ff14d000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14d000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <5>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpion";
};
};
};
linux-7.2.3/arch/arc/boot/dts/abilis_tb100_dvk.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB100 Development Kit PCB device tree
*
* Copyright (C) Abilis Systems 2013
*
* Author: Christian Ruppert <christian.ruppert@abilis.com>
*/
/dts-v1/;
/include/ "abilis_tb100.dtsi"
/ {
model = "abilis,tb100";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
};
aliases { };
memory {
device_type = "memory";
reg = <0x80000000 0x08000000>; /* 128M */
};
soc100 {
uart@ff100000 {
pinctrl-names = "default";
pinctrl-0 = <&pctl_uart0>;
};
ethernet@fe100000 {
phy-mode = "rgmii";
};
i2c0: i2c@ff120000 {
i2c-sda-hold-time-ns = <432>;
};
i2c1: i2c@ff121000 {
i2c-sda-hold-time-ns = <432>;
};
i2c2: i2c@ff122000 {
i2c-sda-hold-time-ns = <432>;
};
i2c3: i2c@ff123000 {
i2c-sda-hold-time-ns = <432>;
};
i2c4: i2c@ff124000 {
i2c-sda-hold-time-ns = <432>;
};
leds {
compatible = "gpio-leds";
power {
label = "Power";
gpios = <&gpioi 0 0>;
linux,default-trigger = "default-on";
};
heartbeat {
label = "Heartbeat";
gpios = <&gpioi 1 0>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "LED2";
gpios = <&gpioi 2 0>;
default-state = "off";
};
led3 {
label = "LED3";
gpios = <&gpioi 3 0>;
default-state = "off";
};
led4 {
label = "LED4";
gpios = <&gpioi 4 0>;
default-state = "off";
};
led5 {
label = "LED5";
gpios = <&gpioi 5 0>;
default-state = "off";
};
led6 {
label = "LED6";
gpios = <&gpioi 6 0>;
default-state = "off";
};
led7 {
label = "LED7";
gpios = <&gpioi 7 0>;
default-state = "off";
};
led8 {
label = "LED8";
gpios = <&gpioi 8 0>;
default-state = "off";
};
led9 {
label = "LED9";
gpios = <&gpioi 9 0>;
default-state = "off";
};
led10 {
label = "LED10";
gpios = <&gpioi 10 0>;
default-state = "off";
};
led11 {
label = "LED11";
gpios = <&gpioi 11 0>;
default-state = "off";
};
};
};
};
linux-7.2.3/arch/arc/boot/dts/abilis_tb101.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB101 SOC device tree
*
* Copyright (C) Abilis Systems 2013
*
* Author: Christian Ruppert <christian.ruppert@abilis.com>
*/
/include/ "abilis_tb10x.dtsi"
/ {
soc100 {
bus-frequency = <166666666>;
pll0: oscillator {
clock-frequency = <1000000000>;
};
cpu_clk: clkdiv_cpu {
clock-mult = <1>;
clock-div = <2>;
};
ahb_clk: clkdiv_ahb {
clock-mult = <1>;
clock-div = <6>;
};
iomux: iomux@ff10601c {
/* Port 1 */
pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
abilis,function = "mis0";
};
pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
abilis,function = "mis1";
};
pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
abilis,function = "gpioa";
};
pctl_tsin_p1: pctl-tsin-p1 { /* Parallel TS-in 1 */
abilis,function = "mip1";
};
/* Port 2 */
pctl_tsin_s2: pctl-tsin-s2 { /* Serial TS-in 2 */
abilis,function = "mis2";
};
pctl_tsin_s3: pctl-tsin-s3 { /* Serial TS-in 3 */
abilis,function = "mis3";
};
pctl_gpio_c: pctl-gpio-c { /* GPIO bank C */
abilis,function = "gpioc";
};
pctl_tsin_p3: pctl-tsin-p3 { /* Parallel TS-in 3 */
abilis,function = "mip3";
};
/* Port 3 */
pctl_tsin_s4: pctl-tsin-s4 { /* Serial TS-in 4 */
abilis,function = "mis4";
};
pctl_tsin_s5: pctl-tsin-s5 { /* Serial TS-in 5 */
abilis,function = "mis5";
};
pctl_gpio_e: pctl-gpio-e { /* GPIO bank E */
abilis,function = "gpioe";
};
pctl_tsin_p5: pctl-tsin-p5 { /* Parallel TS-in 5 */
abilis,function = "mip5";
};
/* Port 4 */
pctl_tsin_s6: pctl-tsin-s6 { /* Serial TS-in 6 */
abilis,function = "mis6";
};
pctl_tsin_s7: pctl-tsin-s7 { /* Serial TS-in 7 */
abilis,function = "mis7";
};
pctl_gpio_g: pctl-gpio-g { /* GPIO bank G */
abilis,function = "gpiog";
};
pctl_tsin_p7: pctl-tsin-p7 { /* Parallel TS-in 7 */
abilis,function = "mip7";
};
/* Port 5 */
pctl_gpio_j: pctl-gpio-j { /* GPIO bank J */
abilis,function = "gpioj";
};
pctl_gpio_k: pctl-gpio-k { /* GPIO bank K */
abilis,function = "gpiok";
};
pctl_ciplus: pctl-ciplus { /* CI+ interface */
abilis,function = "ciplus";
};
pctl_mcard: pctl-mcard { /* M-Card interface */
abilis,function = "mcard";
};
pctl_stc0: pctl-stc0 { /* Smart card I/F 0 */
abilis,function = "stc0";
};
pctl_stc1: pctl-stc1 { /* Smart card I/F 1 */
abilis,function = "stc1";
};
/* Port 6 */
pctl_tsout_p: pctl-tsout-p { /* Parallel TS-out */
abilis,function = "mop";
};
pctl_tsout_s0: pctl-tsout-s0 { /* Serial TS-out 0 */
abilis,function = "mos0";
};
pctl_tsout_s1: pctl-tsout-s1 { /* Serial TS-out 1 */
abilis,function = "mos1";
};
pctl_tsout_s2: pctl-tsout-s2 { /* Serial TS-out 2 */
abilis,function = "mos2";
};
pctl_tsout_s3: pctl-tsout-s3 { /* Serial TS-out 3 */
abilis,function = "mos3";
};
/* Port 7 */
pctl_uart0: pctl-uart0 { /* UART 0 */
abilis,function = "uart0";
};
pctl_uart1: pctl-uart1 { /* UART 1 */
abilis,function = "uart1";
};
pctl_gpio_l: pctl-gpio-l { /* GPIO bank L */
abilis,function = "gpiol";
};
pctl_gpio_m: pctl-gpio-m { /* GPIO bank M */
abilis,function = "gpiom";
};
/* Port 8 */
pctl_spi3: pctl-spi3 {
abilis,function = "spi3";
};
pctl_jtag: pctl-jtag {
abilis,function = "jtag";
};
/* Port 9 */
pctl_spi1: pctl-spi1 {
abilis,function = "spi1";
};
pctl_gpio_n: pctl-gpio-n {
abilis,function = "gpion";
};
/* Unmuxed GPIOs */
pctl_gpio_b: pctl-gpio-b {
abilis,function = "gpiob";
};
pctl_gpio_d: pctl-gpio-d {
abilis,function = "gpiod";
};
pctl_gpio_f: pctl-gpio-f {
abilis,function = "gpiof";
};
pctl_gpio_h: pctl-gpio-h {
abilis,function = "gpioh";
};
pctl_gpio_i: pctl-gpio-i {
abilis,function = "gpioi";
};
};
gpioa: gpio@ff140000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff140000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioa";
};
gpiob: gpio@ff141000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff141000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiob";
};
gpioc: gpio@ff142000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff142000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioc";
};
gpiod: gpio@ff143000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff143000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiod";
};
gpioe: gpio@ff144000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff144000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioe";
};
gpiof: gpio@ff145000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff145000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiof";
};
gpiog: gpio@ff146000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff146000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiog";
};
gpioh: gpio@ff147000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff147000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <2>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioh";
};
gpioi: gpio@ff148000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff148000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <12>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioi";
};
gpioj: gpio@ff149000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff149000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <32>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioj";
};
gpiok: gpio@ff14a000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14a000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <22>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiok";
};
gpiol: gpio@ff14b000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14b000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <4>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiol";
};
gpiom: gpio@ff14c000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14c000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <4>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpiom";
};
gpion: gpio@ff14d000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xff14d000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <5>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpion";
};
};
};
linux-7.2.3/arch/arc/boot/dts/abilis_tb101_dvk.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB101 Development Kit PCB device tree
*
* Copyright (C) Abilis Systems 2013
*
* Author: Christian Ruppert <christian.ruppert@abilis.com>
*/
/dts-v1/;
/include/ "abilis_tb101.dtsi"
/ {
model = "abilis,tb101";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
};
aliases { };
memory {
device_type = "memory";
reg = <0x80000000 0x08000000>; /* 128M */
};
soc100 {
uart@ff100000 {
pinctrl-names = "default";
pinctrl-0 = <&pctl_uart0>;
};
ethernet@fe100000 {
phy-mode = "rgmii";
};
i2c0: i2c@ff120000 {
i2c-sda-hold-time-ns = <432>;
};
i2c1: i2c@ff121000 {
i2c-sda-hold-time-ns = <432>;
};
i2c2: i2c@ff122000 {
i2c-sda-hold-time-ns = <432>;
};
i2c3: i2c@ff123000 {
i2c-sda-hold-time-ns = <432>;
};
i2c4: i2c@ff124000 {
i2c-sda-hold-time-ns = <432>;
};
leds {
compatible = "gpio-leds";
power {
label = "Power";
gpios = <&gpioi 0 0>;
linux,default-trigger = "default-on";
};
heartbeat {
label = "Heartbeat";
gpios = <&gpioi 1 0>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "LED2";
gpios = <&gpioi 2 0>;
default-state = "off";
};
led3 {
label = "LED3";
gpios = <&gpioi 3 0>;
default-state = "off";
};
led4 {
label = "LED4";
gpios = <&gpioi 4 0>;
default-state = "off";
};
led5 {
label = "LED5";
gpios = <&gpioi 5 0>;
default-state = "off";
};
led6 {
label = "LED6";
gpios = <&gpioi 6 0>;
default-state = "off";
};
led7 {
label = "LED7";
gpios = <&gpioi 7 0>;
default-state = "off";
};
led8 {
label = "LED8";
gpios = <&gpioi 8 0>;
default-state = "off";
};
led9 {
label = "LED9";
gpios = <&gpioi 9 0>;
default-state = "off";
};
led10 {
label = "LED10";
gpios = <&gpioi 10 0>;
default-state = "off";
};
led11 {
label = "LED11";
gpios = <&gpioi 11 0>;
default-state = "off";
};
};
};
};
linux-7.2.3/arch/arc/boot/dts/abilis_tb10x.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB10X SOC device tree
*
* Copyright (C) Abilis Systems 2013
*
* Author: Christian Ruppert <christian.ruppert@abilis.com>
*/
/ {
compatible = "abilis,arc-tb10x";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arc770d";
reg = <0>;
};
};
/* TIMER0 with interrupt for clockevent */
timer0 {
compatible = "snps,arc-timer";
interrupts = <3>;
interrupt-parent = <&intc>;
clocks = <&cpu_clk>;
};
/* TIMER1 for free running clocksource */
timer1 {
compatible = "snps,arc-timer";
clocks = <&cpu_clk>;
};
soc100 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0xfe000000 0xfe000000 0x02000000
0x000f0000 0x000f0000 0x00010000>;
compatible = "abilis,tb10x", "simple-bus";
pll0: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "pll0";
};
cpu_clk: clkdiv_cpu {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&pll0>;
clock-output-names = "cpu_clk";
};
ahb_clk: clkdiv_ahb {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&pll0>;
clock-output-names = "ahb_clk";
};
iomux: iomux@ff10601c {
compatible = "abilis,tb10x-iomux";
#gpio-range-cells = <3>;
reg = <0xff10601c 0x4>;
};
intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
tb10x_ictl: pic@fe002000 {
compatible = "abilis,tb10x-ictl";
reg = <0xfe002000 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31>;
};
uart@ff100000 {
compatible = "snps,dw-apb-uart";
reg = <0xff100000 0x100>;
clock-frequency = <166666666>;
interrupts = <25 8>;
reg-shift = <2>;
reg-io-width = <4>;
interrupt-parent = <&tb10x_ictl>;
};
ethernet@fe100000 {
compatible = "snps,dwmac-3.70a","snps,dwmac";
reg = <0xfe100000 0x1058>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <6 8>;
interrupt-names = "macirq";
clocks = <&ahb_clk>;
clock-names = "stmmaceth";
};
dma@fe000000 {
compatible = "snps,dma-spear1340";
reg = <0xfe000000 0x400>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <14 8>;
dma-channels = <6>;
dma-requests = <0>;
dma-masters = <1>;
#dma-cells = <3>;
chan_allocation_order = <0>;
chan_priority = <1>;
block_size = <0x7ff>;
data-width = <4>;
clocks = <&ahb_clk>;
clock-names = "hclk";
multi-block = <1 1 1 1 1 1>;
};
i2c0: i2c@ff120000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xff120000 0x1000>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <12 8>;
clocks = <&ahb_clk>;
};
i2c1: i2c@ff121000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xff121000 0x1000>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <12 8>;
clocks = <&ahb_clk>;
};
i2c2: i2c@ff122000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xff122000 0x1000>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <12 8>;
clocks = <&ahb_clk>;
};
i2c3: i2c@ff123000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xff123000 0x1000>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <12 8>;
clocks = <&ahb_clk>;
};
i2c4: i2c@ff124000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xff124000 0x1000>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <12 8>;
clocks = <&ahb_clk>;
};
spi0: spi@fe010000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "abilis,tb100-spi";
num-cs = <1>;
reg = <0xfe010000 0x20>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <26 8>;
clocks = <&ahb_clk>;
};
spi1: spi@fe011000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "abilis,tb100-spi";
num-cs = <2>;
reg = <0xfe011000 0x20>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <10 8>;
clocks = <&ahb_clk>;
};
tb10x_tsm: tb10x-tsm@ff316000 {
compatible = "abilis,tb100-tsm";
reg = <0xff316000 0x400>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <17 8>;
output-clkdiv = <4>;
global-packet-delay = <0x21>;
port-packet-delay = <0>;
};
tb10x_stream_proc: tb10x-stream-proc {
compatible = "abilis,tb100-streamproc";
reg = <0xfff00000 0x200>,
<0x000f0000 0x10000>,
<0xfff00200 0x105>,
<0xff10600c 0x1>,
<0xfe001018 0x1>;
reg-names = "mbox",
"sp_iccm",
"mbox_irq",
"cpuctrl",
"a6it_int_force";
interrupt-parent = <&tb10x_ictl>;
interrupts = <20 2>, <19 2>;
interrupt-names = "cmd_irq", "event_irq";
};
tb10x_mdsc0: tb10x-mdscr@ff300000 {
compatible = "abilis,tb100-mdscr";
reg = <0xff300000 0x7000>;
tb100-mdscr-manage-tsin;
};
tb10x_mscr0: tb10x-mdscr@ff307000 {
compatible = "abilis,tb100-mdscr";
reg = <0xff307000 0x7000>;
};
tb10x_scr0: tb10x-mdscr@ff30e000 {
compatible = "abilis,tb100-mdscr";
reg = <0xff30e000 0x4000>;
tb100-mdscr-manage-tsin;
};
tb10x_scr1: tb10x-mdscr@ff312000 {
compatible = "abilis,tb100-mdscr";
reg = <0xff312000 0x4000>;
tb100-mdscr-manage-tsin;
};
tb10x_wfb: tb10x-wfb@ff319000 {
compatible = "abilis,tb100-wfb";
reg = <0xff319000 0x1000>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <16 8>;
};
};
};
linux-7.2.3/arch/arc/boot/dts/axc001.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device tree for AXC001 770D/EM6/AS221 CPU card
* Note that this file only supports the 770D CPU
*/
/include/ "skeleton.dtsi"
/ {
compatible = "snps,arc";
#address-cells = <2>;
#size-cells = <2>;
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <750000000>;
};
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333333>;
};
core_intc: arc700-intc@cpu {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
/*
* this GPIO block ORs all interrupts on CPU card (creg,..)
* to uplink only 1 IRQ to ARC core intc
*/
dw-apb-gpio@2000 {
compatible = "snps,dw-apb-gpio";
reg = < 0x2000 0x80 >;
#address-cells = <1>;
#size-cells = <0>;
ictl_intc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <30>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&core_intc>;
interrupts = <15>;
};
};
debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33333000>;
interrupt-parent = <&ictl_intc>;
interrupts = <19 4>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
arcpct0: pct {
compatible = "snps,arc700-pct";
};
};
/*
* This INTC is actually connected to DW APB GPIO
* which acts as a wire between MB INTC and CPU INTC.
* GPIO INTC is configured in platform init code
* and here we mimic direct connection from MB INTC to
* CPU INTC, thus we set "interrupts = <7>" instead of
* "interrupts = <12>"
*
* This intc actually resides on MB, but we move it here to
* avoid duplicating the MB dtsi file given that IRQ from
* this intc to cpu intc are different for axs101 and axs103
*/
mb_intc: interrupt-controller@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0x0 0xe0012000 0x0 0x200 >;
interrupt-controller;
interrupt-parent = <&core_intc>;
interrupts = < 7 >;
};
memory {
device_type = "memory";
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* We just move frame buffer area to the very end of
* available DDR. And even though in case of ARC770 there's
* no strict requirement for a frame-buffer to be in any
* particular location it allows us to use the same
* base board's DT node for ARC PGU as for ARc HS38.
*/
frame_buffer: frame_buffer@9e000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9e000000 0x0 0x2000000>;
no-map;
};
};
};
linux-7.2.3/arch/arc/boot/dts/axc003.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device tree for AXC003 CPU card: HS38x UP configuration
*/
/include/ "skeleton_hs.dtsi"
/ {
compatible = "snps,arc";
#address-cells = <2>;
#size-cells = <2>;
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333333>;
};
core_clk: core-clk@80 {
compatible = "snps,axs10x-arc-pll-clock";
reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
/*
* Set initial core pll output frequency to 90MHz.
* It will be applied at the core pll driver probing
* on early boot.
*/
assigned-clocks = <&core_clk>;
assigned-clock-rates = <90000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
/*
* this GPIO block ORs all interrupts on CPU card (creg,..)
* to uplink only 1 IRQ to ARC core intc
*/
dw-apb-gpio@2000 {
compatible = "snps,dw-apb-gpio";
reg = < 0x2000 0x80 >;
#address-cells = <1>;
#size-cells = <0>;
ictl_intc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <30>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&core_intc>;
interrupts = <25>;
};
};
debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33333000>;
interrupt-parent = <&ictl_intc>;
interrupts = <2 4>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupt-parent = <&core_intc>;
interrupts = <20>;
};
};
/*
* Mark DMA peripherals connected via IOC port as dma-coherent. We do
* it via overlay because peripherals defined in axs10x_mb.dtsi are
* used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
* only AXS103 board has HW-coherent DMA peripherals)
* We don't need to mark pgu@17000 as dma-coherent because it uses
* external DMA buffer located outside of IOC aperture.
*/
axs10x_mb {
ethernet@18000 {
dma-coherent;
};
usb@40000 {
dma-coherent;
};
usb@60000 {
dma-coherent;
};
mmc@15000 {
dma-coherent;
};
};
/*
* The DW APB ICTL intc on MB is connected to CPU intc via a
* DT "invisible" DW APB GPIO block, configured to simply pass thru
* interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
*
* So here we mimic a direct connection between them, ignoring the
* ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
* instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*
* This intc actually resides on MB, but we move it here to
* avoid duplicating the MB dtsi file given that IRQ from
* this intc to cpu intc are different for axs101 and axs103
*/
mb_intc: interrupt-controller@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0x0 0xe0012000 0x0 0x200 >;
interrupt-controller;
interrupt-parent = <&core_intc>;
interrupts = < 24 >;
};
memory {
device_type = "memory";
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* Move frame buffer out of IOC aperture (0x8z-0xaz).
*/
frame_buffer: frame_buffer@be000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xbe000000 0x0 0x2000000>;
no-map;
};
};
};
linux-7.2.3/arch/arc/boot/dts/axc003_idu.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
*/
/include/ "skeleton_hs_idu.dtsi"
/ {
compatible = "snps,arc";
#address-cells = <2>;
#size-cells = <2>;
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333333>;
};
core_clk: core-clk@80 {
compatible = "snps,axs10x-arc-pll-clock";
reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
/*
* Set initial core pll output frequency to 100MHz.
* It will be applied at the core pll driver probing
* on early boot.
*/
assigned-clocks = <&core_clk>;
assigned-clock-rates = <100000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <1>;
};
/*
* this GPIO block ORs all interrupts on CPU card (creg,..)
* to uplink only 1 IRQ to ARC core intc
*/
dw-apb-gpio@2000 {
compatible = "snps,dw-apb-gpio";
reg = < 0x2000 0x80 >;
#address-cells = <1>;
#size-cells = <0>;
ictl_intc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <30>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&idu_intc>;
interrupts = <1>;
};
};
debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33333000>;
interrupt-parent = <&ictl_intc>;
interrupts = <2 4>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupt-parent = <&core_intc>;
interrupts = <20>;
};
};
/*
* Mark DMA peripherals connected via IOC port as dma-coherent. We do
* it via overlay because peripherals defined in axs10x_mb.dtsi are
* used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
* only AXS103 board has HW-coherent DMA peripherals)
* We don't need to mark pgu@17000 as dma-coherent because it uses
* external DMA buffer located outside of IOC aperture.
*/
axs10x_mb {
ethernet@18000 {
dma-coherent;
};
usb@40000 {
dma-coherent;
};
usb@60000 {
dma-coherent;
};
mmc@15000 {
dma-coherent;
};
};
/*
* This INTC is actually connected to DW APB GPIO
* which acts as a wire between MB INTC and CPU INTC.
* GPIO INTC is configured in platform init code
* and here we mimic direct connection from MB INTC to
* CPU INTC, thus we set "interrupts = <0 1>" instead of
* "interrupts = <12>"
*
* This intc actually resides on MB, but we move it here to
* avoid duplicating the MB dtsi file given that IRQ from
* this intc to cpu intc are different for axs101 and axs103
*/
mb_intc: interrupt-controller@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0x0 0xe0012000 0x0 0x200 >;
interrupt-controller;
interrupt-parent = <&idu_intc>;
interrupts = <0>;
};
memory {
device_type = "memory";
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* Move frame buffer out of IOC aperture (0x8z-0xaz).
*/
frame_buffer: frame_buffer@be000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xbe000000 0x0 0x2000000>;
no-map;
};
};
};
linux-7.2.3/arch/arc/boot/dts/axs101.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
*
* ARC AXS101 S/W development platform
*/
/dts-v1/;
/include/ "axc001.dtsi"
/include/ "axs10x_mb.dtsi"
/ {
model = "snps,axs101";
compatible = "snps,axs101", "snps,arc-sdp";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 print-fatal-signals=1";
};
};
linux-7.2.3/arch/arc/boot/dts/axs103.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device Tree for AXS103 SDP with AXS10X Main Board and
* AXC003 FPGA Card (with UP bitfile)
*/
/dts-v1/;
/include/ "axc003.dtsi"
/include/ "axs10x_mb.dtsi"
/ {
model = "snps,axs103";
compatible = "snps,axs103", "snps,arc-sdp";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1";
};
};
linux-7.2.3/arch/arc/boot/dts/axs103_idu.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device Tree for AXS103 SDP with AXS10X Main Board and
* AXC003 FPGA Card (with SMP bitfile)
*/
/dts-v1/;
/include/ "axc003_idu.dtsi"
/include/ "axs10x_mb.dtsi"
/ {
model = "snps,axs103-smp";
compatible = "snps,axs103", "snps,arc-sdp";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0";
};
};
linux-7.2.3/arch/arc/boot/dts/axs10x_mb.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for peripherals on the AXS10x mainboard
*
* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
*/
/ {
aliases {
ethernet = &gmac;
};
axs10x_mb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
interrupt-parent = <&mb_intc>;
creg_rst: reset-controller@11220 {
compatible = "snps,axs10x-reset";
#reset-cells = <1>;
reg = <0x11220 0x4>;
};
i2sclk: i2sclk@100a0 {
compatible = "snps,axs10x-i2s-pll-clock";
reg = <0x100a0 0x10>;
clocks = <&i2spll_clk>;
#clock-cells = <0>;
};
clocks {
i2spll_clk: i2spll_clk {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
};
i2cclk: i2cclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
apbclk: apbclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmcclk: mmcclk {
compatible = "fixed-clock";
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. It divides
* sdio_ref_clk (which comes from CGU) by 16 for
* default. So default mmcclk clock (which comes
* to sdk_in) is 25000000 Hz.
*/
clock-frequency = <25000000>;
#clock-cells = <0>;
};
};
pguclk: pguclk@10080 {
compatible = "snps,axs10x-pgu-pll-clock";
reg = <0x10080 0x10>, <0x110 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
};
gmac: ethernet@18000 {
#interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = < 0x18000 0x2000 >;
interrupts = < 4 >;
interrupt-names = "macirq";
phy-mode = "rgmii";
snps,pbl = < 32 >;
snps,multicast-filter-bins = <256>;
clocks = <&apbclk>;
clock-names = "stmmaceth";
max-speed = <100>;
resets = <&creg_rst 5>;
reset-names = "stmmaceth";
mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
};
usb@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
};
usb@60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
interrupts = < 8 >;
};
/*
* According to DW Mobile Storage databook it is required
* to use "Hold Register" if card is enumerated in SDR12 or
* SDR25 modes.
*
* Utilization of "Hold Register" is already implemented via
* dw_mci_pltfm_prepare_command() which in its turn gets
* used through dw_mci_drv_data->prepare_command call-back.
* This call-back is used in Altera Socfpga platform and so
* we may reuse it saying that we're compatible with their
* "altr,socfpga-dw-mshc".
*
* Most probably "Hold Register" utilization is platform-
* independent requirement which means that single unified
* "snps,dw-mshc" should be enough for all users of DW MMC once
* dw_mci_pltfm_prepare_command() is used in generic platform
* code.
*/
mmc@15000 {
compatible = "altr,socfpga-dw-mshc";
reg = < 0x15000 0x400 >;
fifo-depth = < 16 >;
card-detect-delay = < 200 >;
clocks = <&apbclk>, <&mmcclk>;
clock-names = "biu", "ciu";
interrupts = < 7 >;
bus-width = < 4 >;
};
uart@20000 {
compatible = "snps,dw-apb-uart";
reg = <0x20000 0x100>;
clock-frequency = <33333333>;
interrupts = <17>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@21000 {
compatible = "snps,dw-apb-uart";
reg = <0x21000 0x100>;
clock-frequency = <33333333>;
interrupts = <18>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
/* UART muxed with USB data port (ttyS3) */
uart@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
clock-frequency = <33333333>;
interrupts = <19>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
i2c@1d000 {
compatible = "snps,designware-i2c";
reg = <0x1d000 0x100>;
clock-frequency = <400000>;
clocks = <&i2cclk>;
interrupts = <14>;
};
i2s: i2s@1e000 {
compatible = "snps,designware-i2s";
reg = <0x1e000 0x100>;
clocks = <&i2sclk 0>;
clock-names = "i2sclk";
interrupts = <15>;
#sound-dai-cells = <0>;
};
i2c@1f000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1f000 0x100>;
clock-frequency = <400000>;
clocks = <&i2cclk>;
interrupts = <16>;
adv7511:adv7511@39{
compatible="adi,adv7511";
reg = <0x39>;
interrupts = <23>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,clock-delay = <0x03>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* RGB/YUV input */
port@0 {
reg = <0>;
adv7511_input:endpoint {
remote-endpoint = <&pgu_output>;
};
};
/* HDMI output */
port@1 {
reg = <1>;
adv7511_output: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
eeprom@54{
compatible = "atmel,24c01";
reg = <0x54>;
pagesize = <0x8>;
};
eeprom@57{
compatible = "atmel,24c04";
reg = <0x57>;
pagesize = <0x8>;
};
};
hdmi0: connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7511_output>;
};
};
};
gpio0:gpio@13000 {
compatible = "snps,dw-apb-gpio";
reg = <0x13000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
gpio0_banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
};
gpio0_bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <1>;
};
gpio0_bankc: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <2>;
};
};
gpio1:gpio@14000 {
compatible = "snps,dw-apb-gpio";
reg = <0x14000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
gpio1_banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <30>;
reg = <0>;
};
gpio1_bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <10>;
reg = <1>;
};
gpio1_bankc: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <2>;
};
};
pgu@17000 {
compatible = "snps,arcpgu";
reg = <0x17000 0x400>;
clocks = <&pguclk>;
clock-names = "pxlclk";
memory-region = <&frame_buffer>;
port {
pgu_output: endpoint {
remote-endpoint = <&adv7511_input>;
};
};
};
sound_playback {
compatible = "simple-audio-card";
simple-audio-card,name = "AXS10x HDMI Audio";
simple-audio-card,format = "i2s";
simple-audio-card,cpu {
sound-dai = <&i2s>;
};
simple-audio-card,codec {
sound-dai = <&adv7511>;
};
};
};
};
linux-7.2.3/arch/arc/boot/dts/haps_hs.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
/include/ "skeleton_hs.dtsi"
/ {
model = "snps,zebu_hs";
compatible = "snps,zebu_hs";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&core_intc>;
memory {
device_type = "memory";
/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* only perip space at end of low mem accessible
bus addr, parent bus addr, size */
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
core_intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupts = <24>;
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
virtio0: virtio@f0100000 {
compatible = "virtio,mmio";
reg = <0xf0100000 0x2000>;
interrupts = <31>;
};
virtio1: virtio@f0102000 {
compatible = "virtio,mmio";
reg = <0xf0102000 0x2000>;
interrupts = <32>;
};
virtio2: virtio@f0104000 {
compatible = "virtio,mmio";
reg = <0xf0104000 0x2000>;
interrupts = <33>;
};
virtio3: virtio@f0106000 {
compatible = "virtio,mmio";
reg = <0xf0106000 0x2000>;
interrupts = <34>;
};
virtio4: virtio@f0108000 {
compatible = "virtio,mmio";
reg = <0xf0108000 0x2000>;
interrupts = <35>;
};
};
};
linux-7.2.3/arch/arc/boot/dts/haps_hs_idu.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
/include/ "skeleton_hs_idu.dtsi"
/ {
model = "snps,zebu_hs-smp";
compatible = "snps,zebu_hs";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 */
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>; /* 50 MHZ */
};
core_intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
interrupts = <0>;
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
};
};
linux-7.2.3/arch/arc/boot/dts/hsdk.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device Tree for ARC HS Development Kit
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/snps,hsdk-reset.h>
/ {
model = "snps,hsdk";
compatible = "snps,hsdk";
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
};
aliases {
ethernet = &gmac;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <0>;
clocks = <&core_clk>;
};
cpu@1 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <1>;
clocks = <&core_clk>;
};
cpu@2 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <2>;
clocks = <&core_clk>;
};
cpu@3 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <3>;
clocks = <&core_clk>;
};
};
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333333>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
cpu_intc: cpu-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
};
arcpct: pct {
compatible = "snps,archs-pct";
interrupt-parent = <&cpu_intc>;
interrupts = <20>;
};
/* TIMER0 with interrupt for clockevent */
timer {
compatible = "snps,arc-timer";
interrupts = <16>;
interrupt-parent = <&cpu_intc>;
clocks = <&core_clk>;
};
/* 64-bit Global Free Running Counter */
gfrc {
compatible = "snps,archs-timer-gfrc";
clocks = <&core_clk>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&idu_intc>;
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
cgu_rst: reset-controller@8a0 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0x8a0 0x4>, <0xff0 0x4>;
};
core_clk: core-clk@0 {
compatible = "snps,hsdk-core-pll-clock";
reg = <0x00 0x10>, <0x14b8 0x4>;
#clock-cells = <0>;
clocks = <&input_clk>;
/*
* Set initial core pll output frequency to 1GHz.
* It will be applied at the core pll driver probing
* on early boot.
*/
assigned-clocks = <&core_clk>;
assigned-clock-rates = <1000000000>;
};
serial: serial@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <33330000>;
interrupts = <6>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
gmacclk: gmacclk {
compatible = "fixed-clock";
clock-frequency = <400000000>;
#clock-cells = <0>;
};
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. Due to its
* unexpected default value (it should divide by 1
* but it divides by 8) SDIO IP uses wrong clock and
* works unstable (see STAR 9001204800)
* We switched to the minimum possible value of the
* divisor (div-by-2) in HSDK platform code.
* So add temporary fix and change clock frequency
* to 50000000 Hz until we fix dw sdio driver itself.
*/
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmcclk_biu: mmcclk-biu {
compatible = "fixed-clock";
clock-frequency = <400000000>;
#clock-cells = <0>;
};
gpu_core_clk: gpu-core-clk {
compatible = "fixed-clock";
clock-frequency = <400000000>;
#clock-cells = <0>;
};
gpu_dma_clk: gpu-dma-clk {
compatible = "fixed-clock";
clock-frequency = <400000000>;
#clock-cells = <0>;
};
gpu_cfg_clk: gpu-cfg-clk {
compatible = "fixed-clock";
clock-frequency = <200000000>;
#clock-cells = <0>;
};
dmac_core_clk: dmac-core-clk {
compatible = "fixed-clock";
clock-frequency = <400000000>;
#clock-cells = <0>;
};
dmac_cfg_clk: dmac-gpu-cfg-clk {
compatible = "fixed-clock";
clock-frequency = <200000000>;
#clock-cells = <0>;
};
gmac: ethernet@8000 {
compatible = "snps,dwmac";
reg = <0x8000 0x2000>;
interrupts = <10>;
interrupt-names = "macirq";
phy-mode = "rgmii-id";
snps,pbl = <32>;
snps,multicast-filter-bins = <256>;
clocks = <&gmacclk>;
clock-names = "stmmaceth";
phy-handle = <&phy0>;
resets = <&cgu_rst HSDK_ETH_RESET>;
reset-names = "stmmaceth";
mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
dma-coherent;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
reg = <0>;
};
};
};
usb@60000 {
compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
reg = <0x60000 0x100>;
interrupts = <15>;
resets = <&cgu_rst HSDK_USB_RESET>;
dma-coherent;
};
usb@40000 {
compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
reg = <0x40000 0x100>;
interrupts = <15>;
resets = <&cgu_rst HSDK_USB_RESET>;
dma-coherent;
};
mmc@a000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xa000 0x400>;
num-slots = <1>;
fifo-depth = <16>;
card-detect-delay = <200>;
clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
clock-names = "biu", "ciu";
interrupts = <12>;
bus-width = <4>;
dma-coherent;
};
spi0: spi@20000 {
compatible = "snps,dw-apb-ssi";
reg = <0x20000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <16>;
num-cs = <2>;
reg-io-width = <4>;
clocks = <&input_clk>;
cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
<&creg_gpio 1 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "sst26wf016b", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <4000000>;
};
adc@1 {
compatible = "ti,adc108s102";
reg = <1>;
vref-supply = <&reg_5v0>;
spi-max-frequency = <1000000>;
};
};
creg_gpio: gpio@14b0 {
compatible = "snps,creg-gpio-hsdk";
reg = <0x14b0 0x4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <2>;
};
gpio: gpio@3000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
gpio_port_a: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
reg = <0>;
};
};
gpu_3d: gpu@90000 {
compatible = "vivante,gc";
reg = <0x90000 0x4000>;
clocks = <&gpu_dma_clk>,
<&gpu_cfg_clk>,
<&gpu_core_clk>,
<&gpu_core_clk>;
clock-names = "bus", "reg", "core", "shader";
interrupts = <28>;
};
dmac: dmac@80000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x80000 0x400>;
interrupts = <27>;
clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
clock-names = "core-clk", "cfgr-clk";
dma-channels = <4>;
snps,dma-masters = <2>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <16>;
};
};
memory@80000000 {
#address-cells = <2>;
#size-cells = <2>;
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
/* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
};
};
linux-7.2.3/arch/arc/boot/dts/nsim_700.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/ {
model = "snps,nsim";
compatible = "snps,nsim";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupts = <24>;
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
arcpct0: pct {
compatible = "snps,arc700-pct";
};
};
};
linux-7.2.3/arch/arc/boot/dts/nsimosci.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/ {
model = "snps,nsimosci";
compatible = "snps,nsimosci";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
chosen {
/* this is for console on PGU */
/* bootargs = "console=tty0 consoleblank=0"; */
/* this is for console on serial */
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns8250";
reg = <0xf0000000 0x2000>;
interrupts = <11>;
clock-frequency = <3686400>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
pguclk: pguclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25175000>;
};
pgu@f9000000 {
compatible = "snps,arcpgu";
reg = <0xf9000000 0x400>;
clocks = <&pguclk>;
clock-names = "pxlclk";
};
ps2: ps2@f9001000 {
compatible = "snps,arc_ps2";
reg = <0xf9000400 0x14>;
interrupts = <13>;
interrupt-names = "arc_ps2_irq";
};
eth0: ethernet@f0003000 {
compatible = "ezchip,nps-mgt-enet";
reg = <0xf0003000 0x44>;
interrupts = <7>;
};
arcpct0: pct {
compatible = "snps,arc700-pct";
};
};
};
linux-7.2.3/arch/arc/boot/dts/nsimosci_hs.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
/include/ "skeleton_hs.dtsi"
/ {
model = "snps,nsimosci_hs";
compatible = "snps,nsimosci_hs";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
chosen {
/* this is for console on PGU */
/* bootargs = "console=tty0 consoleblank=0"; */
/* this is for console on serial */
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns8250";
reg = <0xf0000000 0x2000>;
interrupts = <24>;
clock-frequency = <3686400>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
pguclk: pguclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25175000>;
};
pgu@f9000000 {
compatible = "snps,arcpgu";
reg = <0xf9000000 0x400>;
clocks = <&pguclk>;
clock-names = "pxlclk";
};
ps2: ps2@f9001000 {
compatible = "snps,arc_ps2";
reg = <0xf9000400 0x14>;
interrupts = <27>;
interrupt-names = "arc_ps2_irq";
};
eth0: ethernet@f0003000 {
compatible = "ezchip,nps-mgt-enet";
reg = <0xf0003000 0x44>;
interrupts = <25>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
};
};
linux-7.2.3/arch/arc/boot/dts/nsimosci_hs_idu.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
/include/ "skeleton_hs_idu.dtsi"
/ {
model = "snps,nsimosci_hs-smp";
compatible = "snps,nsimosci_hs";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;
chosen {
/* this is for console on serial */
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
};
aliases {
serial0 = &uart0;
};
fpga {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <5000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns8250";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
interrupts = <0>;
clock-frequency = <3686400>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test = <1>;
};
pguclk: pguclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25175000>;
};
pgu@f9000000 {
compatible = "snps,arcpgu";
reg = <0xf9000000 0x400>;
clocks = <&pguclk>;
clock-names = "pxlclk";
};
ps2: ps2@f9001000 {
compatible = "snps,arc_ps2";
reg = <0xf9000400 0x14>;
interrupts = <3>;
interrupt-parent = <&idu_intc>;
interrupt-names = "arc_ps2_irq";
};
eth0: ethernet@f0003000 {
compatible = "ezchip,nps-mgt-enet";
reg = <0xf0003000 0x44>;
interrupt-parent = <&idu_intc>;
interrupts = <1>;
};
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupts = <20>;
};
};
};
linux-7.2.3/arch/arc/boot/dts/skeleton.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value.
*/
/ {
compatible = "snps,arc";
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arc770d";
reg = <0>;
clocks = <&core_clk>;
};
};
/* TIMER0 with interrupt for clockevent */
timer0 {
compatible = "snps,arc-timer";
interrupts = <3>;
interrupt-parent = <&core_intc>;
clocks = <&core_clk>;
};
/* TIMER1 for free running clocksource */
timer1 {
compatible = "snps,arc-timer";
clocks = <&core_clk>;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
};
};
linux-7.2.3/arch/arc/boot/dts/skeleton_hs.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
*/
/ {
compatible = "snps,arc";
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <0>;
clocks = <&core_clk>;
};
};
/* TIMER0 with interrupt for clockevent */
timer0 {
compatible = "snps,arc-timer";
interrupts = <16>;
interrupt-parent = <&core_intc>;
clocks = <&core_clk>;
};
/* 64-bit Local RTC: preferred clocksource for UP */
rtc {
compatible = "snps,archs-timer-rtc";
clocks = <&core_clk>;
};
/* TIMER1 for free running clocksource: Fallback if rtc not found */
timer1 {
compatible = "snps,arc-timer";
clocks = <&core_clk>;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
};
};
linux-7.2.3/arch/arc/boot/dts/skeleton_hs_idu.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
*/
/ {
compatible = "snps,arc";
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <0>;
clocks = <&core_clk>;
};
cpu@1 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <1>;
clocks = <&core_clk>;
};
cpu@2 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <2>;
clocks = <&core_clk>;
};
cpu@3 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <3>;
clocks = <&core_clk>;
};
};
/* TIMER0 with interrupt for clockevent */
timer0 {
compatible = "snps,arc-timer";
interrupts = <16>;
interrupt-parent = <&core_intc>;
clocks = <&core_clk>;
};
/* 64-bit Global Free Running Counter */
gfrc {
compatible = "snps,archs-timer-gfrc";
clocks = <&core_clk>;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
};
};
linux-7.2.3/arch/arc/boot/dts/vdk_axc003.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
*/
/include/ "skeleton_hs.dtsi"
/ {
compatible = "snps,arc";
#address-cells = <1>;
#size-cells = <1>;
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <2403200>;
interrupt-parent = <&core_intc>;
interrupts = <19>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
};
mb_intc: interrupt-controller@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&core_intc>;
interrupts = < 18 >;
};
memory {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x40000000>;
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */
};
};
linux-7.2.3/arch/arc/boot/dts/vdk_axc003_idu.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
*/
/*
* Device tree for AXC003 CPU card:
* HS38x2 (Dual Core) with IDU intc (VDK version)
*/
/include/ "skeleton_hs_idu.dtsi"
/ {
compatible = "snps,arc";
#address-cells = <1>;
#size-cells = <1>;
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <1>;
};
debug_uart: dw-apb-uart@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
clock-frequency = <2403200>;
interrupt-parent = <&idu_intc>;
interrupts = <2>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
};
mb_intc: interrupt-controller@e0012000 {
#interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&idu_intc>;
interrupts = <0>;
};
memory {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x40000000>;
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */
};
};
linux-7.2.3/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for peripherals on the AXS10x mainboard (VDK version)
*
* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
*/
/ {
axs10x_mb_vdk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xe0000000 0x10000000>;
interrupt-parent = <&mb_intc>;
clocks {
apbclk: apbclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmcclk: mmcclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
pguclk: pguclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25175000>;
};
};
ethernet@18000 {
#interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = < 0x18000 0x2000 >;
interrupts = < 4 >;
interrupt-names = "macirq";
phy-mode = "rgmii";
snps,phy-addr = < 0 >; // VDK model phy address is 0
snps,pbl = < 32 >;
clocks = <&apbclk>;
clock-names = "stmmaceth";
};
usb@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
};
uart@20000 {
compatible = "snps,dw-apb-uart";
reg = <0x20000 0x100>;
clock-frequency = <2403200>;
interrupts = <17>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@21000 {
compatible = "snps,dw-apb-uart";
reg = <0x21000 0x100>;
clock-frequency = <2403200>;
interrupts = <18>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
clock-frequency = <2403200>;
interrupts = <19>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
pgu@17000 {
compatible = "snps,arcpgu";
reg = <0x17000 0x400>;
clocks = <&pguclk>;
clock-names = "pxlclk";
};
/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
ps2: ps2@e0017400 {
compatible = "snps,arc_ps2";
reg = <0x17400 0x14>;
interrupts = <5>;
interrupt-names = "arc_ps2_irq";
};
mmc@15000 {
compatible = "snps,dw-mshc";
reg = <0x15000 0x400>;
fifo-depth = <1024>;
card-detect-delay = <200>;
clocks = <&apbclk>, <&mmcclk>;
clock-names = "biu", "ciu";
interrupts = <7>;
bus-width = <4>;
};
};
/*
* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
*
* This node is intentionally put outside of MB above because
* it maps areas outside of MB's 0xez-0xfz.
*/
uio_ev: uio@d0000000 {
compatible = "generic-uio";
reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
interrupt-parent = <&mb_intc>;
interrupts = <23>;
};
};
linux-7.2.3/arch/arc/boot/dts/vdk_hs38.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
*
* ARC HS38 Virtual Development Kit (VDK)
*/
/dts-v1/;
/include/ "vdk_axc003.dtsi"
/include/ "vdk_axs10x_mb.dtsi"
/ {
model = "snps,vdk_archs";
compatible = "snps,axs103";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0";
};
};
linux-7.2.3/arch/arc/boot/dts/vdk_hs38_smp.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
*
* ARC HS38 Virtual Development Kit, SMP version (VDK)
*/
/dts-v1/;
/include/ "vdk_axc003_idu.dtsi"
/include/ "vdk_axs10x_mb.dtsi"
/ {
model = "snps,vdk_archs-smp";
compatible = "snps,axs103";
chosen {
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=640x480-24";
};
};