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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm/boot/dts/hisilicon/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIP01) += \
hip01-ca9x2.dtb
dtb-$(CONFIG_ARCH_HIP04) += \
hip04-d01.dtb
dtb-$(CONFIG_ARCH_HISI) += \
hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_SD5203) += \
sd5203.dtb
linux-7.2.3/arch/arm/boot/dts/hisilicon/hi3519-demb.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
*/
/dts-v1/;
#include "hi3519.dtsi"
/ {
model = "HiSilicon HI3519 DEMO Board";
compatible = "hisilicon,hi3519";
aliases {
serial0 = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
&uart0 {
status = "okay";
};
&dual_timer0 {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hi3519.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
*/
#include <dt-bindings/clock/hi3519-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
};
};
gic: interrupt-controller@10300000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
};
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
crg: clock-reset-controller@12010000 {
compatible = "hisilicon,hi3519-crg";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12010000 0x10000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
uart0: serial@12100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12100000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@12101000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12101000 0x1000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@12102000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12102000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: serial@12103000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12103000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart4: serial@12104000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12104000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
dual_timer0: timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12000000 0x1000>;
clocks = <&clk_3m>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer1: timer@12001000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12001000 0x1000>;
clocks = <&clk_3m>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer2: timer@12002000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12002000 0x1000>;
clocks = <&clk_3m>;
clock-names = "apb_pclk";
status = "disabled";
};
spi_bus0: spi@12120000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12120000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi_bus1: spi@12121000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12121000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi_bus2: spi@12122000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12122000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sysctrl: system-controller@12020000 {
compatible = "hisilicon,hi3519-sysctrl", "syscon";
reg = <0x12020000 0x1000>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctrl>;
offset = <0x4>;
mask = <0xdeadbeef>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012-2013 Linaro Ltd.
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*/
/dts-v1/;
#include "hi3620.dtsi"
/ {
model = "Hisilicon Hi4511 Development Board";
compatible = "hisilicon,hi3620-hi4511";
chosen {
bootargs = "root=/dev/ram0";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
amba-bus {
dual_timer0: dual_timer@800000 {
status = "okay";
};
uart0: serial@b00000 { /* console */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
status = "okay";
};
uart1: serial@b01000 { /* modem */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
status = "okay";
};
uart2: serial@b02000 { /* audience */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
status = "okay";
};
uart3: serial@b03000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
status = "okay";
};
uart4: serial@b04000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
status = "okay";
};
pmx0: pinmux@803000 {
pinctrl-names = "default";
pinctrl-0 = <&board_pmx_pins>;
board_pmx_pins: board-pins {
pinctrl-single,pins = <
0x008 0x0 /* GPIO -- eFUSE_DOUT */
0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
>;
};
uart0_pmx_func: uart0-pins {
pinctrl-single,pins = <
0x0f0 0x0
0x0f4 0x0 /* UART0_RX & UART0_TX */
>;
};
uart0_pmx_idle: uart0-idle-pins {
pinctrl-single,pins = <
/*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */
0x0f4 0x1 /* UART0_RX & UART0_TX */
>;
};
uart1_pmx_func: uart1-pins {
pinctrl-single,pins = <
0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */
0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */
>;
};
uart1_pmx_idle: uart1-idle-pins {
pinctrl-single,pins = <
0x0f8 0x1 /* GPIO (IOMG61) */
0x0fc 0x1 /* GPIO (IOMG62) */
>;
};
uart2_pmx_func: uart2-pins {
pinctrl-single,pins = <
0x104 0x2 /* UART2_RXD (IOMG96) */
0x108 0x2 /* UART2_TXD (IOMG64) */
>;
};
uart2_pmx_idle: uart2-idle-pins {
pinctrl-single,pins = <
0x104 0x1 /* GPIO (IOMG96) */
0x108 0x1 /* GPIO (IOMG64) */
>;
};
uart3_pmx_func: uart3-pins {
pinctrl-single,pins = <
0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */
0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */
>;
};
uart3_pmx_idle: uart3-idle-pins {
pinctrl-single,pins = <
0x160 0x1 /* GPIO (IOMG85) */
0x164 0x1 /* GPIO (IOMG86) */
>;
};
uart4_pmx_func: uart4-pins {
pinctrl-single,pins = <
0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */
0x16c 0x0 /* UART4_RXD (IOMG88) */
0x170 0x0 /* UART4_TXD (IOMG93) */
>;
};
uart4_pmx_idle: uart4-idle-pins {
pinctrl-single,pins = <
0x168 0x1 /* GPIO (IOMG87) */
0x16c 0x1 /* GPIO (IOMG88) */
0x170 0x1 /* GPIO (IOMG93) */
>;
};
i2c0_pmx_func: i2c0-pins {
pinctrl-single,pins = <
0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */
>;
};
i2c0_pmx_idle: i2c0-idle-pins {
pinctrl-single,pins = <
0x0b4 0x1 /* GPIO (IOMG45) */
>;
};
i2c1_pmx_func: i2c1-pins {
pinctrl-single,pins = <
0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */
>;
};
i2c1_pmx_idle: i2c1-idle-pins {
pinctrl-single,pins = <
0x0b8 0x1 /* GPIO (IOMG46) */
>;
};
i2c2_pmx_func: i2c2-pins {
pinctrl-single,pins = <
0x068 0x0 /* I2C2_SCL (IOMG26) */
0x06c 0x0 /* I2C2_SDA (IOMG27) */
>;
};
i2c2_pmx_idle: i2c2-idle-pins {
pinctrl-single,pins = <
0x068 0x1 /* GPIO (IOMG26) */
0x06c 0x1 /* GPIO (IOMG27) */
>;
};
i2c3_pmx_func: i2c3-pins {
pinctrl-single,pins = <
0x050 0x2 /* I2C3_SCL (IOMG20) */
0x054 0x2 /* I2C3_SDA (IOMG21) */
>;
};
i2c3_pmx_idle: i2c3-idle-pins {
pinctrl-single,pins = <
0x050 0x1 /* GPIO (IOMG20) */
0x054 0x1 /* GPIO (IOMG21) */
>;
};
spi0_pmx_func: spi0-pins {
pinctrl-single,pins = <
0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */
0x0d8 0x0 /* SPI0_CS0 (IOMG54) */
0x0dc 0x0 /* SPI0_CS1 (IOMG55) */
0x0e0 0x0 /* SPI0_CS2 (IOMG56) */
0x0e4 0x0 /* SPI0_CS3 (IOMG57) */
>;
};
spi0_pmx_idle: spi0-idle-pins {
pinctrl-single,pins = <
0x0d4 0x1 /* GPIO (IOMG53) */
0x0d8 0x1 /* GPIO (IOMG54) */
0x0dc 0x1 /* GPIO (IOMG55) */
0x0e0 0x1 /* GPIO (IOMG56) */
0x0e4 0x1 /* GPIO (IOMG57) */
>;
};
spi1_pmx_func: spi1-pins {
pinctrl-single,pins = <
0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */
0x0e8 0x0 /* SPI1_DO (IOMG58) */
0x0ec 0x0 /* SPI1_CS (IOMG95) */
>;
};
spi1_pmx_idle: spi1-idle-pins {
pinctrl-single,pins = <
0x184 0x1 /* GPIO (IOMG98) */
0x0e8 0x1 /* GPIO (IOMG58) */
0x0ec 0x1 /* GPIO (IOMG95) */
>;
};
kpc_pmx_func: kpc-pins {
pinctrl-single,pins = <
0x12c 0x0 /* KEY_IN0 (IOMG73) */
0x130 0x0 /* KEY_IN1 (IOMG74) */
0x134 0x0 /* KEY_IN2 (IOMG75) */
0x10c 0x0 /* KEY_OUT0 (IOMG65) */
0x110 0x0 /* KEY_OUT1 (IOMG66) */
0x114 0x0 /* KEY_OUT2 (IOMG67) */
>;
};
kpc_pmx_idle: kpc-idle-pins {
pinctrl-single,pins = <
0x12c 0x1 /* GPIO (IOMG73) */
0x130 0x1 /* GPIO (IOMG74) */
0x134 0x1 /* GPIO (IOMG75) */
0x10c 0x1 /* GPIO (IOMG65) */
0x110 0x1 /* GPIO (IOMG66) */
0x114 0x1 /* GPIO (IOMG67) */
>;
};
gpio_key_func: gpio-key-pins {
pinctrl-single,pins = <
0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */
0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */
>;
};
emmc_pmx_func: emmc-pins {
pinctrl-single,pins = <
0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */
0x018 0x0 /* NAND_CS3_N (IOMG6) */
0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */
>;
};
emmc_pmx_idle: emmc-idle-pins {
pinctrl-single,pins = <
0x030 0x0 /* GPIO (IOMG12) */
0x018 0x1 /* GPIO (IOMG6) */
0x024 0x1 /* GPIO (IOMG8) */
0x028 0x1 /* GPIO (IOMG9) */
0x02c 0x1 /* GPIO (IOMG10) */
>;
};
sd_pmx_func: sd-pins {
pinctrl-single,pins = <
0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */
0x0c0 0x0 /* SD_DATA3 (IOMG48) */
>;
};
sd_pmx_idle: sd-idle-pins {
pinctrl-single,pins = <
0x0bc 0x1 /* GPIO (IOMG47) */
0x0c0 0x1 /* GPIO (IOMG48) */
>;
};
nand_pmx_func: nand-pins {
pinctrl-single,pins = <
0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */
0x010 0x0 /* NAND_CS1_N (IOMG4) */
0x014 0x0 /* NAND_CS2_N (IOMG5) */
0x018 0x0 /* NAND_CS3_N (IOMG6) */
0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */
0x020 0x0 /* NAND_BUSY1_N (IOMG7) */
0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */
>;
};
nand_pmx_idle: nand-idle-pins {
pinctrl-single,pins = <
0x00c 0x1 /* GPIO (IOMG3) */
0x010 0x1 /* GPIO (IOMG4) */
0x014 0x1 /* GPIO (IOMG5) */
0x018 0x1 /* GPIO (IOMG6) */
0x01c 0x1 /* GPIO (IOMG94) */
0x020 0x1 /* GPIO (IOMG7) */
0x024 0x1 /* GPIO (IOMG8) */
0x028 0x1 /* GPIO (IOMG9) */
0x02c 0x1 /* GPIO (IOMG10) */
>;
};
sdio_pmx_func: sdio-pins {
pinctrl-single,pins = <
0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */
>;
};
sdio_pmx_idle: sdio-idle-pins {
pinctrl-single,pins = <
0x0c4 0x1 /* GPIO (IOMG49) */
>;
};
audio_out_pmx_func: audio-out-pins {
pinctrl-single,pins = <
0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */
>;
};
};
pmx1: pinmux@803800 {
pinctrl-names = "default";
pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins
&board_np_pins &board_ps_pins &kpc_cfg_func
&audio_out_cfg_func>;
board_pu_pins: board-pu-pins {
pinctrl-single,pins = <
0x014 0 /* GPIO_158 (IOCFG2) */
0x018 0 /* GPIO_159 (IOCFG3) */
0x01c 0 /* BOOT_MODE0 (IOCFG4) */
0x020 0 /* BOOT_MODE1 (IOCFG5) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
};
board_pd_pins: board-pd-pins {
pinctrl-single,pins = <
0x038 0 /* eFUSE_DOUT (IOCFG11) */
0x150 0 /* ISP_GPIO8 (IOCFG93) */
0x154 0 /* ISP_GPIO9 (IOCFG94) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
board_pd_ps_pins: board-pd-ps-pins {
pinctrl-single,pins = <
0x2d8 0 /* CLK_OUT0 (IOCFG190) */
0x004 0 /* PMU_SPI_DATA (IOCFG192) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
board_np_pins: board-np-pins {
pinctrl-single,pins = <
0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
board_ps_pins: board-ps-pins {
pinctrl-single,pins = <
0x000 0 /* PMU_SPI_CLK (IOCFG191) */
0x008 0 /* PMU_SPI_CS_N (IOCFG193) */
>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
uart0_cfg_func: uart0-cfg-pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart0_cfg_idle: uart0-cfg-idle-pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart1_cfg_func: uart1-cfg-pins {
pinctrl-single,pins = <
0x210 0 /* UART1_CTS (IOCFG140) */
0x214 0 /* UART1_RTS (IOCFG141) */
0x218 0 /* UART1_RXD (IOCFG142) */
0x21c 0 /* UART1_TXD (IOCFG143) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart1_cfg_idle: uart1-cfg-idle-pins {
pinctrl-single,pins = <
0x210 0 /* UART1_CTS (IOCFG140) */
0x214 0 /* UART1_RTS (IOCFG141) */
0x218 0 /* UART1_RXD (IOCFG142) */
0x21c 0 /* UART1_TXD (IOCFG143) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart2_cfg_func: uart2-cfg-pins {
pinctrl-single,pins = <
0x220 0 /* UART2_CTS (IOCFG144) */
0x224 0 /* UART2_RTS (IOCFG145) */
0x228 0 /* UART2_RXD (IOCFG146) */
0x22c 0 /* UART2_TXD (IOCFG147) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart2_cfg_idle: uart2-cfg-idle-pins {
pinctrl-single,pins = <
0x220 0 /* GPIO (IOCFG144) */
0x224 0 /* GPIO (IOCFG145) */
0x228 0 /* GPIO (IOCFG146) */
0x22c 0 /* GPIO (IOCFG147) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart3_cfg_func: uart3-cfg-pins {
pinctrl-single,pins = <
0x294 0 /* UART3_CTS (IOCFG173) */
0x298 0 /* UART3_RTS (IOCFG174) */
0x29c 0 /* UART3_RXD (IOCFG175) */
0x2a0 0 /* UART3_TXD (IOCFG176) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart3_cfg_idle: uart3-cfg-idle-pins {
pinctrl-single,pins = <
0x294 0 /* UART3_CTS (IOCFG173) */
0x298 0 /* UART3_RTS (IOCFG174) */
0x29c 0 /* UART3_RXD (IOCFG175) */
0x2a0 0 /* UART3_TXD (IOCFG176) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart4_cfg_func: uart4-cfg-pins {
pinctrl-single,pins = <
0x2a4 0 /* UART4_CTS (IOCFG177) */
0x2a8 0 /* UART4_RTS (IOCFG178) */
0x2ac 0 /* UART4_RXD (IOCFG179) */
0x2b0 0 /* UART4_TXD (IOCFG180) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
i2c0_cfg_func: i2c0-cfg-pins {
pinctrl-single,pins = <
0x17c 0 /* I2C0_SCL (IOCFG103) */
0x180 0 /* I2C0_SDA (IOCFG104) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c1_cfg_func: i2c1-cfg-pins {
pinctrl-single,pins = <
0x184 0 /* I2C1_SCL (IOCFG105) */
0x188 0 /* I2C1_SDA (IOCFG106) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c2_cfg_func: i2c2-cfg-pins {
pinctrl-single,pins = <
0x118 0 /* I2C2_SCL (IOCFG79) */
0x11c 0 /* I2C2_SDA (IOCFG80) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c3_cfg_func: i2c3-cfg-pins {
pinctrl-single,pins = <
0x100 0 /* I2C3_SCL (IOCFG73) */
0x104 0 /* I2C3_SDA (IOCFG74) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi0_cfg_func1: spi0-cfg-func1-pins {
pinctrl-single,pins = <
0x1d4 0 /* SPI0_CLK (IOCFG125) */
0x1d8 0 /* SPI0_DI (IOCFG126) */
0x1dc 0 /* SPI0_DO (IOCFG127) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi0_cfg_func2: spi0-cfg-func2-pins {
pinctrl-single,pins = <
0x1e0 0 /* SPI0_CS0 (IOCFG128) */
0x1e4 0 /* SPI0_CS1 (IOCFG129) */
0x1e8 0 /* SPI0_CS2 (IOCFG130 */
0x1ec 0 /* SPI0_CS3 (IOCFG131) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi1_cfg_func1: spi1-cfg-func1-pins {
pinctrl-single,pins = <
0x1f0 0 /* SPI1_CLK (IOCFG132) */
0x1f4 0 /* SPI1_DI (IOCFG133) */
0x1f8 0 /* SPI1_DO (IOCFG134) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi1_cfg_func2: spi1-cfg-func2-pins {
pinctrl-single,pins = <
0x1fc 0 /* SPI1_CS (IOCFG135) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
kpc_cfg_func: kpc-cfg-pins {
pinctrl-single,pins = <
0x250 0 /* KEY_IN0 (IOCFG156) */
0x254 0 /* KEY_IN1 (IOCFG157) */
0x258 0 /* KEY_IN2 (IOCFG158) */
0x230 0 /* KEY_OUT0 (IOCFG148) */
0x234 0 /* KEY_OUT1 (IOCFG149) */
0x238 0 /* KEY_OUT2 (IOCFG150) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
emmc_cfg_func: emmc-cfg-pins {
pinctrl-single,pins = <
0x0ac 0 /* eMMC_CMD (IOCFG40) */
0x0b0 0 /* eMMC_CLK (IOCFG41) */
0x058 0 /* NAND_CS3_N (IOCFG19) */
0x064 0 /* NAND_BUSY2_N (IOCFG22) */
0x068 0 /* NAND_BUSY3_N (IOCFG23) */
0x08c 0 /* NAND_DATA8 (IOCFG32) */
0x090 0 /* NAND_DATA9 (IOCFG33) */
0x094 0 /* NAND_DATA10 (IOCFG34) */
0x098 0 /* NAND_DATA11 (IOCFG35) */
0x09c 0 /* NAND_DATA12 (IOCFG36) */
0x0a0 0 /* NAND_DATA13 (IOCFG37) */
0x0a4 0 /* NAND_DATA14 (IOCFG38) */
0x0a8 0 /* NAND_DATA15 (IOCFG39) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sd_cfg_func1: sd-cfg-func1-pins {
pinctrl-single,pins = <
0x18c 0 /* SD_CLK (IOCFG107) */
0x190 0 /* SD_CMD (IOCFG108) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sd_cfg_func2: sd-cfg-func2-pins {
pinctrl-single,pins = <
0x194 0 /* SD_DATA0 (IOCFG109) */
0x198 0 /* SD_DATA1 (IOCFG110) */
0x19c 0 /* SD_DATA2 (IOCFG111) */
0x1a0 0 /* SD_DATA3 (IOCFG112) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x70 0xf0>;
};
nand_cfg_func1: nand-cfg-func1-pins {
pinctrl-single,pins = <
0x03c 0 /* NAND_ALE (IOCFG12) */
0x040 0 /* NAND_CLE (IOCFG13) */
0x06c 0 /* NAND_DATA0 (IOCFG24) */
0x070 0 /* NAND_DATA1 (IOCFG25) */
0x074 0 /* NAND_DATA2 (IOCFG26) */
0x078 0 /* NAND_DATA3 (IOCFG27) */
0x07c 0 /* NAND_DATA4 (IOCFG28) */
0x080 0 /* NAND_DATA5 (IOCFG29) */
0x084 0 /* NAND_DATA6 (IOCFG30) */
0x088 0 /* NAND_DATA7 (IOCFG31) */
0x08c 0 /* NAND_DATA8 (IOCFG32) */
0x090 0 /* NAND_DATA9 (IOCFG33) */
0x094 0 /* NAND_DATA10 (IOCFG34) */
0x098 0 /* NAND_DATA11 (IOCFG35) */
0x09c 0 /* NAND_DATA12 (IOCFG36) */
0x0a0 0 /* NAND_DATA13 (IOCFG37) */
0x0a4 0 /* NAND_DATA14 (IOCFG38) */
0x0a8 0 /* NAND_DATA15 (IOCFG39) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
nand_cfg_func2: nand-cfg-func2-pins {
pinctrl-single,pins = <
0x044 0 /* NAND_RE_N (IOCFG14) */
0x048 0 /* NAND_WE_N (IOCFG15) */
0x04c 0 /* NAND_CS0_N (IOCFG16) */
0x050 0 /* NAND_CS1_N (IOCFG17) */
0x054 0 /* NAND_CS2_N (IOCFG18) */
0x058 0 /* NAND_CS3_N (IOCFG19) */
0x05c 0 /* NAND_BUSY0_N (IOCFG20) */
0x060 0 /* NAND_BUSY1_N (IOCFG21) */
0x064 0 /* NAND_BUSY2_N (IOCFG22) */
0x068 0 /* NAND_BUSY3_N (IOCFG23) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sdio_cfg_func: sdio-cfg-pins {
pinctrl-single,pins = <
0x1a4 0 /* SDIO0_CLK (IOCG113) */
0x1a8 0 /* SDIO0_CMD (IOCG114) */
0x1ac 0 /* SDIO0_DATA0 (IOCG115) */
0x1b0 0 /* SDIO0_DATA1 (IOCG116) */
0x1b4 0 /* SDIO0_DATA2 (IOCG117) */
0x1b8 0 /* SDIO0_DATA3 (IOCG118) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
audio_out_cfg_func: audio-out-cfg-pins {
pinctrl-single,pins = <
0x200 0 /* GPIO (IOCFG136) */
0x204 0 /* GPIO (IOCFG137) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
call {
label = "call";
gpios = <&gpio17 2 0>;
linux,code = <169>; /* KEY_PHONE */
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hi3620.dtsi
+575
View File
@@ -0,0 +1,575 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* HiSilicon Ltd. Hi3620 SoC
*
* Copyright (C) 2012-2013 HiSilicon Ltd.
* Copyright (C) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*/
#include <dt-bindings/clock/hi3620-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
pclk: clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "apb_pclk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hi3620-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
};
amba-bus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0xfc000000 0x2000000>;
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x100000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0x1000 0x1000>, <0x100 0x100>;
};
sysctrl: system-controller@802000 {
compatible = "hisilicon,sysctrl", "syscon";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;
reg = <0x802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
clock: clock@0 {
compatible = "hisilicon,hi3620-clock";
reg = <0 0x10000>;
#clock-cells = <1>;
};
};
dual_timer0: dual_timer@800000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
clocks = <&clock HI3620_TIMER0_MUX>,
<&clock HI3620_TIMER1_MUX>,
<&clock HI3620_TIMER0_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@801000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
clocks = <&clock HI3620_TIMER2_MUX>,
<&clock HI3620_TIMER3_MUX>,
<&clock HI3620_TIMER2_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
dual_timer2: dual_timer@a01000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
clocks = <&clock HI3620_TIMER4_MUX>,
<&clock HI3620_TIMER5_MUX>,
<&clock HI3620_TIMER4_MUX>;
clock-names = "timer0lck", "timer1clk", "apb_pclk";
status = "disabled";
};
dual_timer3: dual_timer@a02000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
clocks = <&clock HI3620_TIMER6_MUX>,
<&clock HI3620_TIMER7_MUX>,
<&clock HI3620_TIMER6_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
dual_timer4: dual_timer@a03000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
clocks = <&clock HI3620_TIMER8_MUX>,
<&clock HI3620_TIMER9_MUX>,
<&clock HI3620_TIMER8_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
timer5: timer@600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x600 0x20>;
interrupts = <1 13 0xf01>;
};
uart0: serial@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb00000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@b01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb01000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb02000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: serial@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb03000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart4: serial@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
gpio0: gpio@806000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x806000 0x1000>;
interrupts = <0 64 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK0>;
clock-names = "apb_pclk";
};
gpio1: gpio@807000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x807000 0x1000>;
interrupts = <0 65 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
&pmx0 6 5 1 &pmx0 7 6 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK1>;
clock-names = "apb_pclk";
};
gpio2: gpio@808000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x808000 0x1000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
&pmx0 6 3 1 &pmx0 7 3 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK2>;
clock-names = "apb_pclk";
};
gpio3: gpio@809000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x809000 0x1000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
&pmx0 6 11 1 &pmx0 7 11 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK3>;
clock-names = "apb_pclk";
};
gpio4: gpio@80a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80a000 0x1000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
&pmx0 6 13 1 &pmx0 7 13 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK4>;
clock-names = "apb_pclk";
};
gpio5: gpio@80b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80b000 0x1000>;
interrupts = <0 69 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
&pmx0 6 16 1 &pmx0 7 16 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK5>;
clock-names = "apb_pclk";
};
gpio6: gpio@80c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80c000 0x1000>;
interrupts = <0 70 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
&pmx0 6 18 1 &pmx0 7 19 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK6>;
clock-names = "apb_pclk";
};
gpio7: gpio@80d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80d000 0x1000>;
interrupts = <0 71 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
&pmx0 6 25 1 &pmx0 7 26 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK7>;
clock-names = "apb_pclk";
};
gpio8: gpio@80e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80e000 0x1000>;
interrupts = <0 72 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
&pmx0 6 33 1 &pmx0 7 34 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK8>;
clock-names = "apb_pclk";
};
gpio9: gpio@80f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80f000 0x1000>;
interrupts = <0 73 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
&pmx0 6 41 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK9>;
clock-names = "apb_pclk";
};
gpio10: gpio@810000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x810000 0x1000>;
interrupts = <0 74 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK10>;
clock-names = "apb_pclk";
};
gpio11: gpio@811000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x811000 0x1000>;
interrupts = <0 75 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
&pmx0 6 49 1 &pmx0 7 49 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK11>;
clock-names = "apb_pclk";
};
gpio12: gpio@812000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x812000 0x1000>;
interrupts = <0 76 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
&pmx0 6 51 1 &pmx0 7 52 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK12>;
clock-names = "apb_pclk";
};
gpio13: gpio@813000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x813000 0x1000>;
interrupts = <0 77 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
&pmx0 6 55 1 &pmx0 7 56 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK13>;
clock-names = "apb_pclk";
};
gpio14: gpio@814000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x814000 0x1000>;
interrupts = <0 78 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
&pmx0 6 60 1 &pmx0 7 61 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK14>;
clock-names = "apb_pclk";
};
gpio15: gpio@815000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x815000 0x1000>;
interrupts = <0 79 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
&pmx0 6 64 1 &pmx0 7 65 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK15>;
clock-names = "apb_pclk";
};
gpio16: gpio@816000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x816000 0x1000>;
interrupts = <0 80 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
&pmx0 6 72 1 &pmx0 7 73 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK16>;
clock-names = "apb_pclk";
};
gpio17: gpio@817000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x817000 0x1000>;
interrupts = <0 81 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
&pmx0 6 80 1 &pmx0 7 81 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK17>;
clock-names = "apb_pclk";
};
gpio18: gpio@818000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x818000 0x1000>;
interrupts = <0 82 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
&pmx0 6 86 1 &pmx0 7 87 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK18>;
clock-names = "apb_pclk";
};
gpio19: gpio@819000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x819000 0x1000>;
interrupts = <0 83 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
&pmx0 3 88 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK19>;
clock-names = "apb_pclk";
};
gpio20: gpio@81a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81a000 0x1000>;
interrupts = <0 84 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK20>;
clock-names = "apb_pclk";
};
gpio21: gpio@81b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81b000 0x1000>;
interrupts = <0 85 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK21>;
clock-names = "apb_pclk";
};
pmx0: pinmux@803000 {
compatible = "pinctrl-single";
reg = <0x803000 0x188>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#gpio-range-cells = <3>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@803800 {
compatible = "pinconf-single";
reg = <0x803800 0x2dc>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* HiSilicon Ltd. HiP01 SoC
*
* Copyright (C) 2014 HiSilicon Ltd.
* Copyright (C) 2014 Huawei Ltd.
*
* Author: Wang Long <long.wanglong@huawei.com>
*/
/dts-v1/;
/* First 8KB reserved for secondary core boot */
/memreserve/ 0x80000000 0x00002000;
#include "hip01.dtsi"
/ {
model = "Hisilicon HIP01 Development Board";
compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hip01-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hip01.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* HiSilicon Ltd. HiP01 SoC
*
* Copyright (c) 2014 HiSilicon Ltd.
* Copyright (c) 2014 Huawei Ltd.
*
* Author: Wang Long <long.wanglong@huawei.com>
*/
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
gic: interrupt-controller@1e001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
};
hisi_refclk144mhz: refclk144mkhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <144000000>;
clock-output-names = "hisi:refclk144khz";
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0x10000000 0x20000000>;
amba-bus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: serial@10001000 {
compatible = "snps,dw-apb-uart";
reg = <0x10001000 0x1000>;
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 32 4>;
status = "disabled";
};
uart1: serial@10002000 {
compatible = "snps,dw-apb-uart";
reg = <0x10002000 0x1000>;
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 33 4>;
status = "disabled";
};
uart2: serial@10003000 {
compatible = "snps,dw-apb-uart";
reg = <0x10003000 0x1000>;
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 34 4>;
status = "disabled";
};
uart3: serial@10006000 {
compatible = "snps,dw-apb-uart";
reg = <0x10006000 0x1000>;
clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <0 4 4>;
status = "disabled";
};
};
system-controller@10000000 {
compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
reg = <0x10000000 0x1000>;
reboot-offset = <0x4>;
};
global_timer@a000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x0a000200 0x100>;
interrupts = <1 11 0xf04>;
clocks = <&hisi_refclk144mhz>;
};
local_timer@a000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x0a000600 0x100>;
interrupts = <1 13 0xf04>;
clocks = <&hisi_refclk144mhz>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hip04-d01.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013-2014 Linaro Ltd.
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*/
/dts-v1/;
#include "hip04.dtsi"
/ {
/* memory bus is 64-bit */
#address-cells = <2>;
#size-cells = <2>;
model = "Hisilicon D01 Development Board";
compatible = "hisilicon,hip04-d01";
memory@0,10000000 {
device_type = "memory";
reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
<0x00000004 0xc0000000 0x00000003 0x40000000>;
};
soc {
uart0: serial@4007000 {
status = "okay";
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hip04.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* HiSilicon Ltd. HiP04 SoC
*
* Copyright (C) 2013-2014 HiSilicon Ltd.
* Copyright (C) 2013-2014 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*/
/ {
/* memory bus is 64-bit */
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
bootwrapper {
compatible = "hisilicon,hip04-bootwrapper";
boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
cluster2 {
core0 {
cpu = <&CPU8>;
};
core1 {
cpu = <&CPU9>;
};
core2 {
cpu = <&CPU10>;
};
core3 {
cpu = <&CPU11>;
};
};
cluster3 {
core0 {
cpu = <&CPU12>;
};
core1 {
cpu = <&CPU13>;
};
core2 {
cpu = <&CPU14>;
};
core3 {
cpu = <&CPU15>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x100>;
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x101>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x102>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x103>;
};
CPU8: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x200>;
};
CPU9: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x201>;
};
CPU10: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x202>;
};
CPU11: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x203>;
};
CPU12: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x300>;
};
CPU13: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x301>;
};
CPU14: cpu@302 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x302>;
};
CPU15: cpu@303 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x303>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
clk_50m: clk_50m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clk_168m: clk_168m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <168000000>;
};
clk_375m: clk_375m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <375000000>;
};
soc {
/* It's a 32-bit SoC. */
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0 0xe0000000 0x10000000>;
gic: interrupt-controller@c01000 {
compatible = "hisilicon,hip04-intc";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
<0xc04000 0x2000>, <0xc06000 0x2000>;
};
sysctrl: sysctrl {
compatible = "hisilicon,sysctrl", "syscon";
reg = <0x3e00000 0x00100000>;
};
fabric: fabric {
compatible = "hisilicon,hip04-fabric";
reg = <0x302a000 0x1000>;
};
dual_timer0: dual_timer@3000000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x3000000 0x1000>;
interrupts = <0 224 4>;
clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
};
arm-pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 64 4>,
<0 65 4>,
<0 66 4>,
<0 67 4>,
<0 68 4>,
<0 69 4>,
<0 70 4>,
<0 71 4>,
<0 72 4>,
<0 73 4>,
<0 74 4>,
<0 75 4>,
<0 76 4>,
<0 77 4>,
<0 78 4>,
<0 79 4>;
};
uart0: serial@4007000 {
compatible = "snps,dw-apb-uart";
reg = <0x4007000 0x1000>;
interrupts = <0 381 4>;
clocks = <&clk_168m>, <&clk_168m>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
status = "disabled";
};
sata0: sata@a000000 {
compatible = "hisilicon,hisi-ahci";
reg = <0xa000000 0x1000000>;
interrupts = <0 372 4>;
};
};
etb@0,e3c42000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3c42000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
etb0_in_port: endpoint@0 {
remote-endpoint = <&replicator0_out_port0>;
};
};
};
};
etb@0,e3c82000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3c82000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
etb1_in_port: endpoint@0 {
remote-endpoint = <&replicator1_out_port0>;
};
};
};
};
etb@0,e3cc2000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3cc2000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
etb2_in_port: endpoint@0 {
remote-endpoint = <&replicator2_out_port0>;
};
};
};
};
etb@0,e3d02000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3d02000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
etb3_in_port: endpoint@0 {
remote-endpoint = <&replicator3_out_port0>;
};
};
};
};
tpiu@0,e3c05000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0xe3c05000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in_port: endpoint@0 {
remote-endpoint = <&funnel4_out_port0>;
};
};
};
};
replicator0 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator0_out_port0: endpoint {
remote-endpoint = <&etb0_in_port>;
};
};
port@1 {
reg = <1>;
replicator0_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port0>;
};
};
};
in-ports {
port {
replicator0_in_port0: endpoint {
remote-endpoint = <&funnel0_out_port0>;
};
};
};
};
replicator1 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator1_out_port0: endpoint {
remote-endpoint = <&etb1_in_port>;
};
};
port@1 {
reg = <1>;
replicator1_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port1>;
};
};
};
in-ports {
port {
replicator1_in_port0: endpoint {
remote-endpoint = <&funnel1_out_port0>;
};
};
};
};
replicator2 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator2_out_port0: endpoint {
remote-endpoint = <&etb2_in_port>;
};
};
port@1 {
reg = <1>;
replicator2_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port2>;
};
};
};
in-ports {
port {
replicator2_in_port0: endpoint {
remote-endpoint = <&funnel2_out_port0>;
};
};
};
};
replicator3 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator3_out_port0: endpoint {
remote-endpoint = <&etb3_in_port>;
};
};
port@1 {
reg = <1>;
replicator3_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port3>;
};
};
};
in-ports {
port {
replicator3_in_port0: endpoint {
remote-endpoint = <&funnel3_out_port0>;
};
};
};
};
funnel@0,e3c41000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3c41000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel0_out_port0: endpoint {
remote-endpoint =
<&replicator0_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel0_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel0_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel0_in_port2: endpoint {
remote-endpoint = <&ptm2_out_port>;
};
};
port@3 {
reg = <3>;
funnel0_in_port3: endpoint {
remote-endpoint = <&ptm3_out_port>;
};
};
};
};
funnel@0,e3c81000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3c81000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel1_out_port0: endpoint {
remote-endpoint =
<&replicator1_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel1_in_port0: endpoint {
remote-endpoint = <&ptm4_out_port>;
};
};
port@1 {
reg = <1>;
funnel1_in_port1: endpoint {
remote-endpoint = <&ptm5_out_port>;
};
};
port@2 {
reg = <2>;
funnel1_in_port2: endpoint {
remote-endpoint = <&ptm6_out_port>;
};
};
port@3 {
reg = <3>;
funnel1_in_port3: endpoint {
remote-endpoint = <&ptm7_out_port>;
};
};
};
};
funnel@0,e3cc1000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3cc1000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel2_out_port0: endpoint {
remote-endpoint =
<&replicator2_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel2_in_port0: endpoint {
remote-endpoint = <&ptm8_out_port>;
};
};
port@1 {
reg = <1>;
funnel2_in_port1: endpoint {
remote-endpoint = <&ptm9_out_port>;
};
};
port@2 {
reg = <2>;
funnel2_in_port2: endpoint {
remote-endpoint = <&ptm10_out_port>;
};
};
port@3 {
reg = <3>;
funnel2_in_port3: endpoint {
remote-endpoint = <&ptm11_out_port>;
};
};
};
};
funnel@0,e3d01000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3d01000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel3_out_port0: endpoint {
remote-endpoint =
<&replicator3_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel3_in_port0: endpoint {
remote-endpoint = <&ptm12_out_port>;
};
};
port@1 {
reg = <1>;
funnel3_in_port1: endpoint {
remote-endpoint = <&ptm13_out_port>;
};
};
port@2 {
reg = <2>;
funnel3_in_port2: endpoint {
remote-endpoint = <&ptm14_out_port>;
};
};
port@3 {
reg = <3>;
funnel3_in_port3: endpoint {
remote-endpoint = <&ptm15_out_port>;
};
};
};
};
funnel@0,e3c04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3c04000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel4_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel4_in_port0: endpoint {
remote-endpoint =
<&replicator0_out_port1>;
};
};
port@1 {
reg = <1>;
funnel4_in_port1: endpoint {
remote-endpoint =
<&replicator1_out_port1>;
};
};
port@2 {
reg = <2>;
funnel4_in_port2: endpoint {
remote-endpoint =
<&replicator2_out_port1>;
};
};
port@3 {
reg = <3>;
funnel4_in_port3: endpoint {
remote-endpoint =
<&replicator3_out_port1>;
};
};
};
};
ptm@0,e3c7c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7c000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
ptm@0,e3c7d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7d000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
ptm@0,e3c7e000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7e000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
out-ports {
port {
ptm2_out_port: endpoint {
remote-endpoint = <&funnel0_in_port2>;
};
};
};
};
ptm@0,e3c7f000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7f000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
out-ports {
port {
ptm3_out_port: endpoint {
remote-endpoint = <&funnel0_in_port3>;
};
};
};
};
ptm@0,e3cbc000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbc000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU4>;
out-ports {
port {
ptm4_out_port: endpoint {
remote-endpoint = <&funnel1_in_port0>;
};
};
};
};
ptm@0,e3cbd000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbd000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU5>;
out-ports {
port {
ptm5_out_port: endpoint {
remote-endpoint = <&funnel1_in_port1>;
};
};
};
};
ptm@0,e3cbe000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbe000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU6>;
out-ports {
port {
ptm6_out_port: endpoint {
remote-endpoint = <&funnel1_in_port2>;
};
};
};
};
ptm@0,e3cbf000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbf000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU7>;
out-ports {
port {
ptm7_out_port: endpoint {
remote-endpoint = <&funnel1_in_port3>;
};
};
};
};
ptm@0,e3cfc000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cfc000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU8>;
out-ports {
port {
ptm8_out_port: endpoint {
remote-endpoint = <&funnel2_in_port0>;
};
};
};
};
ptm@0,e3cfd000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cfd000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU9>;
out-ports {
port {
ptm9_out_port: endpoint {
remote-endpoint = <&funnel2_in_port1>;
};
};
};
};
ptm@0,e3cfe000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cfe000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU10>;
out-ports {
port {
ptm10_out_port: endpoint {
remote-endpoint = <&funnel2_in_port2>;
};
};
};
};
ptm@0,e3cff000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cff000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU11>;
out-ports {
port {
ptm11_out_port: endpoint {
remote-endpoint = <&funnel2_in_port3>;
};
};
};
};
ptm@0,e3d3c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3c000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU12>;
out-ports {
port {
ptm12_out_port: endpoint {
remote-endpoint = <&funnel3_in_port0>;
};
};
};
};
ptm@0,e3d3d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3d000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU13>;
out-ports {
port {
ptm13_out_port: endpoint {
remote-endpoint = <&funnel3_in_port1>;
};
};
};
};
ptm@0,e3d3e000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3e000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU14>;
out-ports {
port {
ptm14_out_port: endpoint {
remote-endpoint = <&funnel3_in_port2>;
};
};
};
};
ptm@0,e3d3f000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3f000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU15>;
out-ports {
port {
ptm15_out_port: endpoint {
remote-endpoint = <&funnel3_in_port3>;
};
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts
+83
View File
@@ -0,0 +1,83 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2013-2014 HiSilicon Limited.
*/
/dts-v1/;
#include "hisi-x5hd2.dtsi"
/ {
model = "Hisilicon HIX5HD2 Development Board";
compatible = "hisilicon,hix5hd2";
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hix5hd2-smp";
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&l2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&l2>;
};
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x80000000>;
};
};
&timer0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&phy2>;
phy-mode = "mii";
/* Placeholder, overwritten by bootloader */
mac-address = [00 00 00 00 00 00];
status = "okay";
phy2: ethernet-phy@2 {
reg = <2>;
};
};
&gmac1 {
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
/* Placeholder, overwritten by bootloader */
mac-address = [00 00 00 00 00 00];
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ahci {
phys = <&sata_phy>;
phy-names = "sata-phy";
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi
+558
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@@ -0,0 +1,558 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2013-2014 HiSilicon Limited.
*/
#include <dt-bindings/clock/hix5hd2-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
};
gic: interrupt-controller@f8a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0xf8000000 0x8000000>;
amba-bus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
timer0: timer@2000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00002000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 24 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer1: timer@a29000 {
/*
* Only used in NORMAL state, not available ins
* SLOW or DOZE state.
* The rate is fixed in 24MHz.
*/
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a29000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 25 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer2: timer@a2a000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a2a000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 26 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer3: timer@a2b000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a2b000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 27 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer4: timer@a81000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a81000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 28 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
uart0: serial@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@6000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00006000 0x1000>;
interrupts = <0 50 4>;
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b02000 0x1000>;
interrupts = <0 51 4>;
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: serial@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b03000 0x1000>;
interrupts = <0 52 4>;
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart4: serial@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 53 4>;
clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
gpio0: gpio@b20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb20000 0x1000>;
interrupts = <0 108 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio1: gpio@b21000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb21000 0x1000>;
interrupts = <0 109 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio2: gpio@b22000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb22000 0x1000>;
interrupts = <0 110 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio3: gpio@b23000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb23000 0x1000>;
interrupts = <0 111 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio4: gpio@b24000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb24000 0x1000>;
interrupts = <0 112 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio5: gpio@4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x004000 0x1000>;
interrupts = <0 113 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio6: gpio@b26000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb26000 0x1000>;
interrupts = <0 114 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio7: gpio@b27000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb27000 0x1000>;
interrupts = <0 115 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio8: gpio@b28000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb28000 0x1000>;
interrupts = <0 116 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio9: gpio@b29000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb29000 0x1000>;
interrupts = <0 117 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio10: gpio@b2a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb2a000 0x1000>;
interrupts = <0 118 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio11: gpio@b2b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb2b000 0x1000>;
interrupts = <0 119 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio12: gpio@b2c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb2c000 0x1000>;
interrupts = <0 120 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio13: gpio@b2d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb2d000 0x1000>;
interrupts = <0 121 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio14: gpio@b2e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb2e000 0x1000>;
interrupts = <0 122 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio15: gpio@b2f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb2f000 0x1000>;
interrupts = <0 123 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio16: gpio@b30000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb30000 0x1000>;
interrupts = <0 124 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio17: gpio@b31000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xb31000 0x1000>;
interrupts = <0 125 0x4>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clock HIX5HD2_FIXED_100M>;
clock-names = "apb_pclk";
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
wdt0: watchdog@a2c000 {
compatible = "arm,sp805", "arm,primecell";
arm,primecell-periphid = <0x00141805>;
reg = <0xa2c000 0x1000>;
interrupts = <0 29 4>;
clocks = <&clock HIX5HD2_WDG0_RST>,
<&clock HIX5HD2_WDG0_RST>;
clock-names = "wdog_clk", "apb_pclk";
};
};
local_timer@a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
};
l2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x00a10000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
sysctrl: system-controller@0 {
compatible = "hisilicon,sysctrl", "syscon";
reg = <0x00000000 0x1000>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctrl>;
offset = <0x4>;
mask = <0xdeadbeef>;
};
cpuctrl@a22000 {
compatible = "hisilicon,cpuctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00a22000 0x2000>;
ranges = <0 0x00a22000 0x2000>;
clock: clock@0 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0 0x2000>;
#clock-cells = <1>;
};
};
/* unremovable emmc as mmcblk0 */
mmc: mmc@1830000 {
compatible = "snps,dw-mshc";
reg = <0x1830000 0x1000>;
interrupts = <0 35 4>;
clocks = <&clock HIX5HD2_MMC_CIU_RST>,
<&clock HIX5HD2_MMC_BIU_CLK>;
clock-names = "biu", "ciu";
};
sd: mmc@1820000 {
compatible = "snps,dw-mshc";
reg = <0x1820000 0x1000>;
interrupts = <0 34 4>;
clocks = <&clock HIX5HD2_SD_CIU_RST>,
<&clock HIX5HD2_SD_BIU_CLK>;
clock-names = "biu", "ciu";
};
gmac0: ethernet@1840000 {
compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
reg = <0x1840000 0x1000>,<0x184300c 0x4>;
interrupts = <0 71 4>;
clocks = <&clock HIX5HD2_MAC0_CLK>;
clock-names = "mac_core";
status = "disabled";
};
gmac1: ethernet@1841000 {
compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
reg = <0x1841000 0x1000>,<0x1843010 0x4>;
interrupts = <0 72 4>;
clocks = <&clock HIX5HD2_MAC1_CLK>;
clock-names = "mac_core";
status = "disabled";
};
usb0: usb@1890000 {
compatible = "generic-ehci";
reg = <0x1890000 0x1000>;
interrupts = <0 66 4>;
clocks = <&clock HIX5HD2_USB_CLK>;
};
usb1: usb@1880000 {
compatible = "generic-ohci";
reg = <0x1880000 0x1000>;
interrupts = <0 67 4>;
clocks = <&clock HIX5HD2_USB_CLK>;
};
peripheral_ctrl: syscon@a20000 {
compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0xa20000 0x1000>;
};
sata_phy: phy@1900000 {
compatible = "hisilicon,hix5hd2-sata-phy";
reg = <0x1900000 0x10000>;
#phy-cells = <0>;
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
hisilicon,power-reg = <0x8 10>;
};
ahci: sata@1900000 {
compatible = "hisilicon,hisi-ahci";
reg = <0x1900000 0x10000>;
interrupts = <0 70 4>;
clocks = <&clock HIX5HD2_SATA_CLK>;
};
ir: ir@1000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0x001000 0x1000>;
interrupts = <0 47 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
hisilicon,power-syscon = <&sysctrl>;
};
i2c0: i2c@b10000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0xb10000 0x1000>;
interrupts = <0 38 4>;
clocks = <&clock HIX5HD2_I2C0_RST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@b11000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0xb11000 0x1000>;
interrupts = <0 39 4>;
clocks = <&clock HIX5HD2_I2C1_RST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@b12000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0xb12000 0x1000>;
interrupts = <0 40 4>;
clocks = <&clock HIX5HD2_I2C2_RST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@b13000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0xb13000 0x1000>;
interrupts = <0 41 4>;
clocks = <&clock HIX5HD2_I2C3_RST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@b16000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0xb16000 0x1000>;
interrupts = <0 43 4>;
clocks = <&clock HIX5HD2_I2C4_RST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@b17000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0xb17000 0x1000>;
interrupts = <0 44 4>;
clocks = <&clock HIX5HD2_I2C5_RST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
linux-7.2.3/arch/arm/boot/dts/hisilicon/sd5203.dts
+96
View File
@@ -0,0 +1,96 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020 HiSilicon Limited.
*
* DTS file for Hisilicon SD5203 Board
*/
/dts-v1/;
/ {
model = "Hisilicon SD5203";
compatible = "H836ASDJ", "hisilicon,sd5203";
interrupt-parent = <&vic>;
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
};
aliases {
serial0 = &uart0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
reg = <0x0>;
};
};
memory@30000000 {
device_type = "memory";
reg = <0x30000000 0x8000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
vic: interrupt-controller@10130000 {
compatible = "snps,dw-apb-ictl";
reg = <0x10130000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
refclk125mhz: refclk125mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
timer0: timer@16002000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x16002000 0x1000>;
interrupts = <4>;
clocks = <&refclk125mhz>;
clock-names = "apb_pclk";
};
timer1: timer@16003000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x16003000 0x1000>;
interrupts = <5>;
clocks = <&refclk125mhz>;
clock-names = "apb_pclk";
};
uart0: serial@1600d000 {
compatible = "snps,dw-apb-uart";
reg = <0x1600d000 0x1000>;
bus_id = "uart0";
clocks = <&refclk125mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <17>;
};
uart1: serial@1600c000 {
compatible = "snps,dw-apb-uart";
reg = <0x1600c000 0x1000>;
clocks = <&refclk125mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <16>;
status = "disabled";
};
};
};