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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm/boot/dts/intel/ixp/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-actiontec-mi424wr-ac.dtb \
intel-ixp42x-actiontec-mi424wr-d.dtb \
intel-ixp42x-linksys-nslu2.dtb \
intel-ixp42x-linksys-wrv54g.dtb \
intel-ixp42x-freecom-fsg-3.dtb \
intel-ixp42x-welltech-epbx100.dtb \
intel-ixp42x-ixdp425.dtb \
intel-ixp43x-kixrp435.dtb \
intel-ixp46x-ixdp465.dtb \
intel-ixp42x-adi-coyote.dtb \
intel-ixp42x-ixdpg425.dtb \
intel-ixp42x-goramo-multilink.dtb \
intel-ixp42x-iomega-nas100d.dtb \
intel-ixp42x-dlink-dsm-g600.dtb \
intel-ixp42x-gateworks-gw2348.dtb \
intel-ixp43x-gateworks-gw2358.dtb \
intel-ixp42x-netgear-wg302v1.dtb \
intel-ixp42x-arcom-vulcan.dtb \
intel-ixp42x-gateway-7001.dtb \
intel-ixp42x-usrobotics-usr8200.dtb
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the IXP425-based Actiontec MI424WR revision A and C
* Based on a board file from OpenWrt by Jose Vasconcellos.
*/
/dts-v1/;
#include "intel-ixp42x-actiontec-mi424wr.dtsi"
/ {
model = "Actiontec MI424WR rev A/C";
compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
/* Connect the switch to EthC */
spi {
ethernet-switch@0 {
ethernet-ports {
ethernet-port@4 {
ethernet = <&ethc>;
};
};
};
};
soc {
/* EthB used for WAN */
ethernet@c8009000 {
phy-handle = <&phy17>; // 17 on revision A-C
mdio {
phy17: ethernet-phy@17 {
/* WAN */
reg = <17>;
};
};
};
/* EthC used for LAN */
ethernet@c800a000 {
/* Fixed link to the CPU MII port on the KS8995 */
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the IXP425-based Actiontec MI424WR revision D
* Based on a board file from OpenWrt by Jose Vasconcellos.
*/
/dts-v1/;
#include "intel-ixp42x-actiontec-mi424wr.dtsi"
/ {
model = "Actiontec MI424WR rev D";
compatible = "actiontec,mi424wr-d", "intel,ixp42x";
/* Connect the switch to EthB */
spi {
ethernet-switch@0 {
ethernet-ports {
ethernet-port@4 {
ethernet = <&ethb>;
};
};
};
};
soc {
/* EthB used for LAN */
ethernet@c8009000 {
/* Fixed link to the CPU MII port on the KS8995 */
fixed-link {
speed = <100>;
full-duplex;
};
mdio {
/* PHY ID 0x00221450 */
phy5: ethernet-phy@5 {
/* WAN */
reg = <5>;
};
};
};
/* EthC used for WAN */
ethernet@c800a000 {
phy-handle = <&phy5>; // 5 on revision D
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the IXP425-based Actiontec MI424WR
* Based on a board file from OpenWrt by Jose Vasconcellos.
*/
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x02000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart1:115200n8";
};
leds {
compatible = "gpio-leds";
led-wan-coax {
color = <LED_COLOR_ID_GREEN>;
function = "wan-coax";
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-power-alarm {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_ALARM;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-power {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-wireless {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-internet-down {
color = <LED_COLOR_ID_RED>;
function = "internet-down";
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-internet-up {
color = <LED_COLOR_ID_GREEN>;
function = "internet-up";
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-lan-coax {
color = <LED_COLOR_ID_GREEN>;
function = "lan-coax";
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-wan-ethernet-alarm {
color = <LED_COLOR_ID_RED>;
function = "wan-ethernet-alarm";
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
/* The last three LEDs are not mounted but traces exist on the PCB */
led-phone-1 {
color = <LED_COLOR_ID_GREEN>;
function = "phone-1";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-phone-2 {
color = <LED_COLOR_ID_GREEN>;
function = "phone-2";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-voip {
color = <LED_COLOR_ID_GREEN>;
function = "voip";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio_keys {
compatible = "gpio-keys";
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
ethernet-switch@0 {
compatible = "micrel,ks8995";
reg = <0>;
spi-max-frequency = <50000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
reg = <0>;
label = "lan1";
phy-mode = "mii";
phy-handle = <&phy1>;
};
ethernet-port@1 {
reg = <1>;
label = "lan2";
phy-mode = "mii";
phy-handle = <&phy2>;
};
ethernet-port@2 {
reg = <2>;
label = "lan3";
phy-mode = "mii";
phy-handle = <&phy3>;
};
ethernet-port@3 {
reg = <3>;
label = "lan4";
phy-mode = "mii";
phy-handle = <&phy4>;
};
ethernet-port@4 {
reg = <4>;
phy-mode = "mii";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 8 MB of Flash in 64 0x20000 sized blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x0800000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
fis-index-block = <0x3f>;
};
};
gpio1: gpio@1,0 {
/* MMIO GPIO at CS1 */
compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
gpio-controller;
#gpio-cells = <2>;
big-endian;
reg = <1 0x00000000 0x2>;
reg-names = "dat";
/* Expansion bus settings */
intel,ixp4xx-eb-write-enable = <1>;
pci-reset-hog {
gpio-hog;
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCI reset";
};
pstn-relay-hog-1 {
gpio-hog;
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PSTN relay control 1";
};
pstn-relay-hog-2 {
gpio-hog;
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PSTN relay control 2";
};
};
};
pci@c0000000 {
status = "okay";
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 13 */
<0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */
<0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */
/* IDSEL 14 */
<0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */
/* IDSEL 15 */
<0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */
<0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */
};
ethb: ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "mii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* 1, 2, 3 and 4 are ports on the KS8995 switch */
phy1: ethernet-phy@1 {
/* LAN1 */
reg = <1>;
};
phy2: ethernet-phy@2 {
/* LAN2 */
reg = <2>;
};
phy3: ethernet-phy@3 {
/* LAN3 */
reg = <3>;
};
phy4: ethernet-phy@4 {
/* LAN4 */
reg = <4>;
};
};
};
ethc: ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "mii";
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for ADI Engineering Coyote platform.
* Derived from boardfiles written by MontaVista software.
* Ethernet set-up from OpenWrt.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "ADI Engineering Coyote reference design";
compatible = "adieng,coyote", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
device_type = "memory";
reg = <0x00000000 0x01000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart1:115200n8";
};
aliases {
/* These are switched around */
serial0 = &uart1;
serial1 = &uart0;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 32 MB of Flash in 128 0x20000 sized blocks
* mapped in at CS0 and CS1
*/
reg = <0 0x00000000 0x2000000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
/* CHECKME: guess this is Redboot FIS */
fis-index-block = <0x1ff>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from Coyote PCI boardfile.
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
<0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
<0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
<0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
<0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Arcom/Eurotech Vulcan board.
* This board is a single board computer in the PC/104 form factor based on
* IXP425, and was released around 2005. It previously had the name "Mercury".
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Arcom/Eurotech Vulcan";
compatible = "arcom,vulcan", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
/* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
onewire {
compatible = "w1-gpio";
gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 32 MB of Flash in 0x20000 byte blocks
* mapped in at CS0 and CS1.
*
* The documentation mentions the existence
* of a 16MB version, which we conveniently
* ignore. Shout if you own one!
*/
reg = <0 0x00000000 0x2000000>;
/* Expansion bus settings */
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
fis-index-block = <0x1ff>;
};
};
sram@2,0 {
/* 256 KB SDRAM memory at CS2 */
compatible = "shared-dma-pool";
device_type = "memory";
reg = <2 0x00000000 0x40000>;
no-map;
/* Expansion bus settings */
intel,ixp4xx-eb-t3 = <1>;
intel,ixp4xx-eb-t4 = <2>;
intel,ixp4xx-eb-ahb-split-transfers = <1>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
serial@3,0 {
/*
* 8250-compatible Exar XR16L2551 2 x UART
*
* CHECKME: if special tweaks are needed, then fix the
* operating system to handle it.
*/
compatible = "exar,xr16l2551", "ns8250";
reg = <3 0x00000000 0x10>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <1843200>;
/* Expansion bus settings */
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
gpio1: gpio@4,0 {
/*
* MMIO GPIO in one byte
*/
compatible = "arcom,vulcan-gpio";
reg = <4 0x00000000 0x1>;
/* Expansion bus settings */
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
watchdog@5,0 {
compatible = "maxim,max6369";
reg = <5 0x00000000 0x1>;
/* Expansion bus settings */
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from Vulcan PCI boardfile.
*
* We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
* per slot. This interrupt is shared (OR:ed) by all four pins.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for D-Link DSM-G600 revision A based on IXP420
* NOTE: revision B of this device uses PowerPC and is NOT supported by
* this device tree.
*
* Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo
* and Michael Westerhof.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "D-Link DSM-G600 rev A";
compatible = "dlink,dsm-g600-a", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-power {
label = "dsmg600:green:power";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-wlan {
label = "dsmg600:green:wlan";
/* CHECKME: flagged as active low in the old board file */
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
default-state = "on";
/* We don't have WLAN trigger in the kernel (yet) */
linux,default-trigger = "netdev";
};
};
gpio_keys {
compatible = "gpio-keys";
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};
};
gpio_keys_polled {
compatible = "gpio-keys-polled";
/*
* According to the board file this key cannot handle interrupts and
* need to be polled. Investigate if this is really the case or if
* this can be moved adjacent to the ordinary gpio-keys above.
*/
button-power {
wakeup-source;
linux,code = <KEY_POWER>;
label = "power";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
timeout-ms = <5000>;
};
soc {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 16 MB of Flash in 128 0x20000 sized blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/*
* A boot log says the directory is at 0xfe0000
* 0x7f * 0x20000 = 0xfe0000
*/
fis-index-block = <0x7f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from DSM-G600 PCI boardfile (dsmg600-pci.c)
* We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
* Only slot 3 have three IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */
<0x1800 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */
<0x1800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */
/* IDSEL 4 */
<0x2000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
+219
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Freecom FSG-3 router.
* This machine is based on IXP425.
* This device tree is inspired by the board file by Rod Whitby.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Freecom FSG-3";
compatible = "freecom,fsg-3", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB memory */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
/* Boot from the first partition on the hard drive */
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
gpio_keys {
compatible = "gpio-keys";
button-sync {
wakeup-source;
/* Closest approximation of what the key should do */
linux,code = <KEY_CONNECT>;
label = "sync";
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
};
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};
button-usb {
wakeup-source;
/* Unplug USB, closest approximation of what the key should do */
linux,code = <KEY_EJECTCD>;
label = "usb";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
hwmon@28 {
/*
* Temperature sensor and fan control chip.
*
* TODO: create a proper device tree binding for
* the sensor and temperature zone and create a
* zone with fan control.
*/
compatible = "winbond,w83781d";
reg = <0x28>;
};
rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 4 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x400000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x3e0000 */
fis-index-block = <0x1f>;
};
};
/* Small syscon with some LEDs at CS2 */
syscon@2,0 {
compatible = "freecom,fsg-cs2-system-controller", "syscon";
reg = <2 0x0 0x200>;
reg-io-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <2 0x0 0x0 0x200>;
led@0,0 {
compatible = "register-bit-led";
reg = <0x00 0x02>;
mask = <0x01>;
label = "fsg:blue:wlan";
linux,default-trigger = "wlan";
default-state = "on";
};
led@0,1 {
compatible = "register-bit-led";
reg = <0x00 0x02>;
mask = <0x02>;
label = "fsg:blue:wan";
linux,default-trigger = "";
default-state = "on";
};
led@0,2 {
compatible = "register-bit-led";
reg = <0x00 0x02>;
mask = <0x04>;
label = "fsg:blue:sata";
linux,default-trigger = "";
default-state = "on";
};
led@0,3 {
compatible = "register-bit-led";
reg = <0x00 0x02>;
mask = <0x04>;
label = "fsg:blue:usb";
linux,default-trigger = "";
default-state = "on";
};
led@0,4 {
compatible = "register-bit-led";
reg = <0x00 0x02>;
mask = <0x08>;
label = "fsg:blue:sync";
linux,default-trigger = "";
default-state = "on";
};
led@0,5 {
compatible = "register-bit-led";
reg = <0x00 0x02>;
mask = <0x10>;
label = "fsg:blue:ring";
linux,default-trigger = "";
default-state = "on";
};
};
};
pci@c0000000 {
status = "okay";
/*
* Written based on the FSG-3 PCI boardfile.
* We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
/* IDSEL 13 */
<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
/* IDSEL 14 */
<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts
+112
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Gateway 7001 AP based on IXP422
* Derived from boardfiles written by Imre Kaloz
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Gateway 7001 AP";
compatible = "gateway,7001", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x2000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart1:115200n8";
};
aliases {
/* second UART is the primary console */
serial0 = &uart1;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 8 MB of flash
*/
reg = <0 0x00000000 0x800000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x7e0000 */
fis-index-block = <0x3f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c)
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */
<0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */
<0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
<0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
<0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
};
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy2>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy2: ethernet-phy@2 {
reg = <2>;
};
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts
+174
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Gateworks Avila GW2348 board.
* This machine is based on IXP425.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Gateworks Avila GW2348";
compatible = "gateworks,gw2348", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-user {
label = "gw2348:green:user";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
hwmon@28 {
compatible = "adi,ad7418";
reg = <0x28>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
eeprom@51 {
compatible = "atmel,24c08";
reg = <0x51>;
pagesize = <16>;
size = <1024>;
read-only;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
ide@1,0 {
compatible = "intel,ixp4xx-compact-flash";
/*
* Set up expansion bus config to a really slow timing.
* The CF driver will dynamically reconfigure these timings
* depending on selected PIO mode (0-4).
*/
intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* First register set is CMD second is CTL (notice it uses CS2) */
reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
interrupt-parent = <&gpio0>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
};
/*
* FIXME: Latch LEDs or extra UARTs at CS4
*/
};
pci@c0000000 {
status = "okay";
/*
* Taken from Avila PCI boardfile.
*
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts
+182
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Goramo MultiLink Router
* There are two variants:
* - MultiLink Basic (a box)
* - MultiLink Max (19" rack mount)
* This device tree supports MultiLink Basic.
* This machine is based on IXP425.
* This is one of the few devices supporting the IXP4xx High-Speed Serial
* (HSS) link for a V.35 WAN interface.
* The hardware originates in Poland.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Goramo MultiLink Router";
compatible = "goramo,multilink-router", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/*
* 64 MB of RAM according to the manual. The MultiLink
* Max has 128 MB.
*/
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
/*
* 74HC4094 which is used as a rudimentary GPIO expander
* FIXME:
* - Create device tree bindings for this as GPIO expander
* - Write a pure DT GPIO driver using these bindings
* - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
*/
gpio_74: gpio-74hc4094 {
compatible = "nxp,74hc4094";
cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
/* oe-gpios is optional */
gpio-controller;
#gpio-cells = <2>;
/* We are not cascaded */
registers-number = <1>;
gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
"CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
"CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
* The slots have Ethernet, Ethernet, NEC and MPCI.
* The IDSELs are 11, 12, 13, 14.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 11 - Ethernet A */
<0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
<0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
<0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
<0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
/* IDSEL 12 - Ethernet B */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
/* IDSEL 13 - MPCI */
<0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
<0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
<0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
<0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
/* IDSEL 14 - NEC */
<0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
<0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
<0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
<0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
};
/* HSS links */
npe@c8006000 {
hss@0 {
status = "okay";
intel,queue-chl-rxtrig = <&qmgr 12>;
intel,queue-chl-txready = <&qmgr 34>;
intel,queue-pkt-rx = <&qmgr 13>;
intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
intel,queue-pkt-txdone = <&qmgr 22>;
/* The Goramo GPIO-based clock etc control */
cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
};
hss@1 {
status = "okay";
intel,queue-chl-rxtrig = <&qmgr 10>;
intel,queue-chl-txready = <&qmgr 35>;
intel,queue-pkt-rx = <&qmgr 0>;
intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
intel,queue-pkt-txdone = <&qmgr 9>;
/* The Goramo GPIO-based clock etc control */
cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
};
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 32>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 33>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
+148
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Iomega NAS 100D
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Iomega NAS 100D";
compatible = "iom,nas-100d", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-wlan {
label = "nas100d:red:wlan";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
default-state = "on";
/* We don't have WLAN trigger in the kernel (yet) */
linux,default-trigger = "netdev";
};
led-disk {
label = "nas100d:red:disk";
gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "disk-activity";
};
led-power {
label = "nas100d:red:power";
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
button-power {
wakeup-source;
linux,code = <KEY_POWER>;
label = "power";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
timeout-ms = <5000>;
};
soc {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 8 MB of Flash in 0x20000 byte blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x800000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x7e0000 */
fis-index-block = <0x3f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from NAS 100D PCI boardfile (nas100d-pci.c)
* We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */
};
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
* processor reference design.
*
* This platform has the codename "Richfield".
*
* This machine is based on a 533 MHz IXP425.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
compatible = "intel,ixdp425", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel IXDPG425 reference design.
* Derived from boardfiles written by MontaVista software.
* Ethernet set-up from OpenWrt.
*
* The device has 4 x FXS RJ11 ports for analog phones for
* internet telephony. (Not supported yet.)
*
* The device has 9 status LEDs we do not support yet.
*
* This device is very similar to ADI engingeering Coyote.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel IXDPG425 reference design";
compatible = "intel,ixdpg425", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x02000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* CHECKME: the product brief says 16MB in a flash
* socket.
*/
reg = <0 0x00000000 0x1000000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
/* CHECKME: guess this is Redboot FIS */
fis-index-block = <0x7f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from IXDPG425 PCI boardfile.
* We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
* for 12 & 13 and one for 14.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
<0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */
<0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */
<0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */
/* IDSEL 13 */
<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
/* IDSEL 14 */
<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
};
/*
* CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind
* of Realtek DSA switch on the board.
*/
/* EthB */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Linksys NSLU2
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)";
compatible = "linksys,nslu2", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x2000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-status {
label = "nslu2:red:status";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-ready {
label = "nslu2:green:ready";
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led-disk-1 {
label = "nslu2:green:disk-1";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-disk-2 {
label = "nslu2:green:disk-2";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio_keys {
compatible = "gpio-keys";
button-power {
wakeup-source;
linux,code = <KEY_POWER>;
label = "power";
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
};
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
rtc@6f {
compatible = "xicor,x1205";
reg = <0x6f>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
timeout-ms = <5000>;
};
gpio_pwm: pwm {
#pwm-cells = <3>;
compatible = "pwm-gpio";
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
};
beeper {
compatible = "pwm-beeper";
pwms = <&gpio_pwm 0 1 0>;
beeper-hz = <1000>;
};
soc {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/*
* 8 MB of Flash in 0x20000 byte blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x800000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x7e0000 */
fis-index-block = <0x3f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
* We have slots (IDSEL) 1, 2 and 3.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
<0x1000 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
<0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
<0x1800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */
};
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Linksys WRV54G router
* Also known as Gemtek GTWX5715
* Based on a board file by George T. Joseph and other patches.
* This machine is based on IXP425.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Linksys WRV54G / Gemtek GTWX5715";
compatible = "linksys,wrv54g", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB memory */
device_type = "memory";
reg = <0x00000000 0x2000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart1:115200n8";
};
aliases {
/* UART2 is the primary console */
serial0 = &uart1;
serial1 = &uart0;
};
/* There is an unpopulated LED slot (3) connected to GPIO 8 */
leds {
compatible = "gpio-leds";
led-power {
label = "wrv54g:yellow:power";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-wireless {
label = "wrv54g:yellow:wireless";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-internet {
label = "wrv54g:yellow:internet";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-dmz {
label = "wrv54g:green:dmz";
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
/* This set-up comes from an OpenWrt patch */
spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
ethernet-switch@0 {
compatible = "micrel,ks8995";
reg = <0>;
spi-max-frequency = <50000000>;
/*
* The PHYs are accessed over the external MDIO
* bus and not internally through the switch control
* registers.
*/
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
reg = <0>;
label = "1";
phy-mode = "mii";
phy-handle = <&phy1>;
};
ethernet-port@1 {
reg = <1>;
label = "2";
phy-mode = "mii";
phy-handle = <&phy2>;
};
ethernet-port@2 {
reg = <2>;
label = "3";
phy-mode = "mii";
phy-handle = <&phy3>;
};
ethernet-port@3 {
reg = <3>;
label = "4";
phy-mode = "mii";
phy-handle = <&phy4>;
};
ethernet-port@4 {
reg = <4>;
ethernet = <&ethb>;
phy-mode = "mii";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 8 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x00800000>;
partitions {
compatible = "fixed-partitions";
/*
* Partition info from a boot log
* CHECKME: not using redboot? FIS index 0x3f @7e00000?
*/
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0 0x140000>;
read-only;
};
partition@140000 {
label = "linux";
reg = <0x140000 0x100000>;
read-only;
};
partition@240000 {
label = "root";
reg = <0x240000 0x480000>;
read-write;
};
};
};
};
pci@c0000000 {
status = "okay";
/*
* We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
* Derived from the GTWX5715 PCI boardfile.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 0 */
<0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */
<0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */
};
/*
* EthB connects to the KS8995 CPU port and faces ports 1-4
* through the switch fabric.
*
* To complicate things, the MDIO channel is also only
* accessible through EthB, but used independently for PHY
* control.
*/
ethb: ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "mii";
fixed-link {
speed = <100>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
/*
* LAN ports 1-4 on the KS8995 switch
* and PHY5 for WAN need to be accessed
* through this external MDIO channel.
*/
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/*
* EthC connects to MII-P5 on the KS8995 bypassing
* all of the switch logic and facing PHY5
*/
ethc: ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "mii";
phy-handle = <&phy5>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Netgear WG302v2 based on IXP422BB
* Derived from boardfiles written by Imre Kaloz
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Netgear WG302 v1";
compatible = "netgear,wg302v1", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 32 MB SDRAM according to boot arguments */
device_type = "memory";
reg = <0x00000000 0x02000000>;
};
chosen {
/* The RedBoot comes up in 9600 baud so let's keep this */
bootargs = "console=ttyS0,9600n8";
stdout-path = "uart1:9600n8";
};
aliases {
/* These are switched around */
serial0 = &uart1;
};
leds {
compatible = "gpio-leds";
test_led: led-test {
color = <LED_COLOR_ID_AMBER>;
function = "test";
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wlan_led: led-wlan {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "phy0tx";
};
};
gpio_keys {
/* RESET is on GPIO13 which can't fire interrupts */
compatible = "gpio-keys-polled";
poll-interval = <100>;
button-reset {
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 8 MB of Flash in 64 0x20000 sized blocks
* mapped in at CS0.
*/
reg = <0 0x00000000 0x800000>;
/* Configure expansion bus to allow writes */
intel,ixp4xx-eb-write-enable = <1>;
partitions {
compatible = "redboot-fis";
fis-index-block = <0x3f>;
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from WG302 v1 PCI boardfile (wg302v1-pci.c)
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
<0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */
<0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
<0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
<0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
};
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy30>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy30: ethernet-phy@30 {
reg = <30>;
};
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the USRobotics USR8200 firewall
* VPN and NAS. Based on know-how from Peter Denison.
*
* This machine is based on IXP422, the USR internal codename
* is "Jeeves".
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "USRobotics USR8200";
compatible = "usr,usr8200", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart1:115200n8";
};
aliases {
/* These are switched around */
serial0 = &uart1;
serial1 = &uart0;
};
leds {
compatible = "gpio-leds";
ieee1394_led: led-1394 {
label = "usr8200:green:1394";
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
default-state = "off";
};
usb1_led: led-usb1 {
label = "usr8200:green:usb1";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
usb2_led: led-usb2 {
label = "usr8200:green:usb2";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wireless_led: led-wireless {
/*
* This LED is mounted inside the case but cannot be
* seen from the outside: probably USR planned at one
* point for the device to have a wireless card, then
* changed their mind and didn't mount it, leaving the
* LED in place.
*/
label = "usr8200:green:wireless";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
pwr_led: led-pwr {
label = "usr8200:green:pwr";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
rtc@2,0 {
/* EPSON RTC7301 DG DIL-capsule */
compatible = "epson,rtc7301dg";
/*
* These timing settings were found in the boardfile patch:
* IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
* IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
*/
intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
intel,ixp4xx-eb-byte-access-on-halfword = <0>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* 512 bytes at CS2 */
reg = <2 0x00000000 0x0000200>;
reg-io-width = <1>;
native-endian;
/* FIXME: try to check if there is an IRQ for the RTC? */
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from USR8200 boardfile from OpenWrt
*
* We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
* We assume the same IRQ for all pins on the remaining slots, that
* is what the boardfile was doing.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 14 used for "Wireless" in the board file */
<0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
/* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
<0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
/* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
<0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
<0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
<0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
};
gpio@c8004000 {
/* Enable clock out on GPIO 15 */
intel,ixp4xx-gpio15-clkout;
};
/* EthB WAN */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy9>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
/*
* PHY 0..4 are internal to the MV88E6060 switch but appear
* as independent devices.
*/
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
/* Altima AMI101L used by the WAN port */
phy9: ethernet-phy@9 {
reg = <9>;
};
/* The switch uses MDIO addresses 16 thru 31 */
switch@16 {
compatible = "marvell,mv88e6060";
reg = <16>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-handle = <&phy2>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&phy3>;
};
port@5 {
/* Port 5 is the CPU port according to the MV88E6060 datasheet */
reg = <5>;
phy-mode = "rgmii-id";
ethernet = <&ethc>;
label = "cpu";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
};
/* EthC LAN connected to the Marvell DSA Switch */
ethc: ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
/ {
model = "Welltech EPBX100";
compatible = "welltech,epbx100", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 16 MB of Flash
*/
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "RedBoot";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "zImage";
reg = <0x00080000 0x00100000>;
read-only;
};
partition@180000 {
label = "ramdisk";
reg = <0x00180000 0x00300000>;
read-only;
};
partition@480000 {
label = "User";
reg = <0x00480000 0x00b60000>;
read-only;
};
partition@fe0000 {
label = "FIS directory";
reg = <0x00fe0000 0x001f000>;
read-only;
};
partition@fff000 {
label = "RedBoot config";
reg = <0x00fff000 0x0001000>;
read-only;
};
};
};
};
/* LAN port */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Intel XScale Network Processors
* in the IXP 42x series. This series has 32 interrupts.
*/
#include "intel-ixp4xx.dtsi"
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x30>;
};
pci@c0000000 {
compatible = "intel,ixp42x-pci";
};
interrupt-controller@c8003000 {
compatible = "intel,ixp42x-interrupt";
};
/*
* This is the USB Device Mode (UDC) controller, which is used
* to present the IXP4xx as a device on a USB bus.
*/
usb@c800b000 {
compatible = "intel,ixp4xx-udc";
reg = <0xc800b000 0x1000>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Gateworks IXP43x-based Cambria GW2358
*/
/dts-v1/;
#include "intel-ixp43x.dtsi"
/ {
model = "Gateworks Cambria GW2358";
compatible = "gateworks,gw2358", "intel,ixp43x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 128 MB SDRAM */
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
leds {
compatible = "gpio-leds";
led-user {
label = "gw2358:green:LED";
gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
hwmon@28 {
compatible = "adi,ad7418";
reg = <0x28>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
eeprom@51 {
compatible = "atmel,24c08";
reg = <0x51>;
pagesize = <16>;
size = <1024>;
read-only;
};
pld0: pld@56 {
compatible = "gateworks,pld-gpio";
reg = <0x56>;
gpio-controller;
#gpio-cells = <2>;
};
/* This PLD just handles the LED and user button */
pld1: pld@57 {
compatible = "gateworks,pld-gpio";
reg = <0x57>;
gpio-controller;
#gpio-cells = <2>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/*
* 32 MB of Flash in 0x20000 byte blocks
* mapped in at CS0 and CS1
*/
reg = <0 0x00000000 0x2000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x1fe0000 */
fis-index-block = <0xff>;
};
};
ide@3,0 {
compatible = "intel,ixp4xx-compact-flash";
/*
* Set up expansion bus config to a really slow timing.
* The CF driver will dynamically reconfigure these timings
* depending on selected PIO mode (0-4).
*/
intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* First register set is CMD second is CTL */
reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
interrupt-parent = <&gpio0>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
};
};
pci@c0000000 {
status = "okay";
/*
* In the boardfile for the Cambria from OpenWRT the interrupts
* are assigned one per IDSEL, so all 4 interrupts from IDSEL
* 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
* connected to IRQ 10 etc. I find this highly unlikely so I
* have instead assumed that they are rotated (swizzled) like
* this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
/* IDSEL 6 */
<0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
<0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
<0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
<0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
/* IDSEL 15 */
<0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
<0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
<0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
<0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
};
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
};
};
ethernet@c800c000 {
status = "okay";
queue-rx = <&qmgr 2>;
queue-txready = <&qmgr 19>;
phy-mode = "rgmii";
phy-handle = <&phy2>;
intel,npe-handle = <&npe 0>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel KIXRP435 Control Plane
* processor reference design.
*/
/dts-v1/;
#include "intel-ixp43x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel KIXRP435 Reference Design";
compatible = "intel,kixrp435", "intel,ixp43x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
/* CHECKME: ethernet set-up taken from Gateworks Cambria */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
};
};
ethernet@c800c000 {
status = "okay";
queue-rx = <&qmgr 2>;
queue-txready = <&qmgr 19>;
phy-mode = "rgmii";
phy-handle = <&phy2>;
intel,npe-handle = <&npe 0>;
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Intel XScale Network Processors
* in the IXP 43x series. This series has 64 interrupts and adds a few more
* peripherals over the 42x series.
*/
#include "intel-ixp4xx.dtsi"
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
/* Uses at least up to 0x230 */
reg = <0xc4000000 0x1000>;
};
pci@c0000000 {
compatible = "intel,ixp43x-pci";
};
interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Intel XScale Network Processors
* in the IXP45x and IXP46x series. This series has 64 interrupts and adds a
* few more peripherals over the 42x and 43x series so this extends the
* basic IXP4xx DTSI.
*/
#include "intel-ixp4xx.dtsi"
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
/* Uses at least up to 0x124 */
reg = <0xc4000000 0x1000>;
};
rng@70002100 {
compatible = "intel,ixp46x-rng";
reg = <0x70002100 4>;
};
interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
};
/*
* This is the USB Device Mode (UDC) controller, which is used
* to present the IXP4xx as a device on a USB bus.
*/
usb@c800b000 {
compatible = "intel,ixp4xx-udc";
reg = <0xc800b000 0x1000>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c@c8011000 {
compatible = "intel,ixp4xx-i2c";
reg = <0xc8011000 0x18>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
/* This is known as EthB1 */
ethernet@c800d000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800d000 0x1000>;
status = "disabled";
intel,npe = <1>;
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
};
/* This is known as EthB2 */
ethernet@c800e000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800e000 0x1000>;
status = "disabled";
intel,npe = <2>;
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
};
/* This is known as EthB3 */
ethernet@c800f000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800f000 0x1000>;
status = "disabled";
intel,npe = <3>;
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
};
ptp-timer@c8010000 {
compatible = "intel,ixp46x-ptp-timer";
reg = <0xc8010000 0x1000>;
interrupt-parent = <&gpio0>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "master", "slave";
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel IXDP465 Control Plane processor reference
* design, codename "BMP".
*/
/dts-v1/;
#include "intel-ixp45x-ixp46x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel IXDP465 BMP Reference Design";
compatible = "intel,ixdp465", "intel,ixp46x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 32 MB of Flash mapped in at CS0 and CS1 */
reg = <0 0x00000000 0x2000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x1fe0000 */
fis-index-block = <0xff>;
};
};
};
/* TODO: configure ethernet etc */
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi
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// SPDX-License-Identifier: ISC
/*
* Device Tree include file for Intel reference designs for the
* XScale Network Processors in the IXP 4xx series. Common device
* set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
*/
/ {
memory@0 {
/*
* The board supports up to 256 MB of memory. Here we put in
* 64 MB and this may be modified by the boot loader.
*/
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
/*
* Philips PCF8582C-2T/03 512byte I2C EEPROM
* should behave like an Atmel 24c04.
*/
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
size = <512>;
read-only;
};
};
soc {
bus@c4000000 {
/* Flash memory defined per-variant */
nand-controller@3,0 {
/* Some designs have a NAND on CS3 enable it here if present */
status = "disabled";
/*
* gen_nand needs to be extended and documented to get
* command byte = 1 and address byte = 2 from the device
* tree.
*/
compatible = "gen_nand";
/* Expansion bus set-up */
intel,ixp4xx-eb-t1 = <0>;
intel,ixp4xx-eb-t2 = <0>;
intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
intel,ixp4xx-eb-t4 = <0>;
intel,ixp4xx-eb-t5 = <0>;
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
intel,ixp4xx-eb-byte-access-on-halfword = <0>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* 512 bytes memory window */
reg = <3 0x00000000 0x200>;
nand-on-flash-bbt;
nand-ecc-mode = "soft_bch";
nand-ecc-step-size = <512>;
nand-ecc-strength = <4>;
nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */
label = "ixp400 NAND";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
fs@0 {
label = "ixp400 NAND FS 0";
reg = <0x0 0x800000>;
};
fs@800000 {
label = "ixp400 NAND FS 1";
reg = <0x800000 0x0>;
};
};
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from IXDP425 PCI boardfile.
* PCI slots on the BIXMB425BD base card.
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
};
};
};
linux-7.2.3/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi
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// SPDX-License-Identifier: ISC
/*
* Device Tree file for Intel XScale Network Processors
* in the IXP 4xx series.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
interrupt-parent = <&intcon>;
/*
* The IXP4xx expansion bus is a set of up to 7 each up to 16MB
* windows in the 256MB space from 0x50000000 to 0x5fffffff.
*/
bus@c4000000 {
/* compatible and reg filled in by per-soc device tree */
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>,
<2 0x0 0x52000000 0x01000000>,
<3 0x0 0x53000000 0x01000000>,
<4 0x0 0x54000000 0x01000000>,
<5 0x0 0x55000000 0x01000000>,
<6 0x0 0x56000000 0x01000000>,
<7 0x0 0x57000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>,
<2 0x0 0x52000000 0x01000000>,
<3 0x0 0x53000000 0x01000000>,
<4 0x0 0x54000000 0x01000000>,
<5 0x0 0x55000000 0x01000000>,
<6 0x0 0x56000000 0x01000000>,
<7 0x0 0x57000000 0x01000000>;
};
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
pci@c0000000 {
/* compatible filled in by per-soc device tree */
reg = <0xc0000000 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
<9 IRQ_TYPE_LEVEL_HIGH>,
<10 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
status = "disabled";
ranges =
/*
* 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
* done in 4 chunks of 16MB each.
*/
<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
/* 64KB I/O space at 0x4c000000 */
<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
/*
* This needs to map to the start of physical memory so
* PCI devices can see all (hopefully) memory. This is done
* using 4 1:1 16MB windows, so the RAM should not be more than
* 64 MB for this to work. If your memory is anywhere else
* than at 0x0 you need to alter this.
*/
dma-ranges =
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
/* Each unique DTS using PCI must specify the swizzling */
};
uart0: serial@c8000000 {
compatible = "intel,xscale-uart";
reg = <0xc8000000 0x1000>;
/*
* The reg-offset and reg-shift is a side effect
* of running the platform in big endian mode.
*/
reg-offset = <3>;
reg-shift = <2>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <14745600>;
no-loopback-test;
};
uart1: serial@c8001000 {
compatible = "intel,xscale-uart";
reg = <0xc8001000 0x1000>;
/*
* The reg-offset and reg-shift is a side effect
* of running the platform in big endian mode.
*/
reg-offset = <3>;
reg-shift = <2>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <14745600>;
no-loopback-test;
};
gpio0: gpio@c8004000 {
compatible = "intel,ixp4xx-gpio";
reg = <0xc8004000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
intcon: interrupt-controller@c8003000 {
/*
* Note: no compatible string. The subvariant of the
* chip needs to define what version it is. The
* location of the interrupt controller is fixed in
* memory across all variants.
*/
reg = <0xc8003000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@c8005000 {
compatible = "intel,ixp4xx-timer";
reg = <0xc8005000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
npe: npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/* NPE-A contains two high-speed serial links */
hss@0 {
compatible = "intel,ixp4xx-hss";
reg = <0>;
intel,npe-handle = <&npe 0>;
status = "disabled";
};
hss@1 {
compatible = "intel,ixp4xx-hss";
reg = <1>;
intel,npe-handle = <&npe 0>;
status = "disabled";
};
/* NPE-C contains a crypto accelerator */
crypto {
compatible = "intel,ixp4xx-crypto";
intel,npe-handle = <&npe 2>;
queue-rx = <&qmgr 30>;
queue-txready = <&qmgr 29>;
};
};
/* This is known as EthB */
ethernet@c8009000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc8009000 0x1000>;
status = "disabled";
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
intel,npe-handle = <&npe 1>;
};
/* This is known as EthC */
ethernet@c800a000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800a000 0x1000>;
status = "disabled";
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
intel,npe-handle = <&npe 2>;
};
/* This is known as EthA */
ethernet@c800c000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800c000 0x1000>;
status = "disabled";
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
intel,npe-handle = <&npe 0>;
};
};
};