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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm/boot/dts/sigmastar/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MSTARV7) += \
mstar-infinity-msc313-breadbee_crust.dtb \
mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \
mstar-infinity2m-ssd202d-miyoo-mini.dtb \
mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \
mstar-infinity2m-ssd202d-ssd201htv2.dtb \
mstar-infinity2m-ssd202d-unitv2.dtb \
mstar-infinity3-msc313e-breadbee.dtb \
mstar-mercury5-ssc8336n-midrived08.dtb
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
vcc_core: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vcc_core";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
};
vcc_dram: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vcc_dram";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
vcc_io: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
red {
gpios = <&gpio MSC313_GPIO_SR_IO16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "activity";
};
yellow {
gpios = <&gpio MSC313_GPIO_SR_IO17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&cpu0 {
cpu-supply = <&vcc_core>;
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-infinity-msc313.dtsi"
#include "mstar-infinity-breadbee-common.dtsi"
/ {
model = "BreadBee Crust";
compatible = "thingyjp,breadbee-crust", "mstar,infinity";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-infinity.dtsi"
/ {
memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x4000000>;
};
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-v7.dtsi"
#include <dt-bindings/gpio/msc313-gpio.h>
/ {
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu0_opp_table>;
};
&imi {
reg = <0xa0000000 0x16000>;
};
&gpio {
compatible = "mstar,msc313-gpio";
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
* Author: Romain Perier <romain.perier@gmail.com>
*/
/ {
reg_vcc_dram: regulator-vcc-dram {
compatible = "regulator-fixed";
regulator-name = "vcc_dram";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2021 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-infinity2m-ssd202d.dtsi"
/ {
model = "DongShanPi One";
compatible = "100ask,dongshanpione", "mstar,infinity2m";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2021 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-infinity2m-ssd202d.dtsi"
/ {
model = "Miyoo Mini";
compatible = "miyoo,miyoo-mini", "mstar,infinity2m";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-infinity2m-ssd202d.dtsi"
/ {
model = "SSD201_HT_V2";
compatible = "honestar,ssd201htv2", "mstar,infinity2m";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2021 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-infinity2m-ssd202d.dtsi"
/ {
model = "UnitV2";
compatible = "m5stack,unitv2", "mstar,infinity2m";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
* Author: Romain Perier <romain.perier@gmail.com>
*/
/dts-v1/;
#include "mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Wireless Tag IDO-SBC2D06-1VB-22W";
compatible = "wirelesstag,ido-sbc2d06-v1b-22w", "mstar,infinity2m";
leds {
compatible = "gpio-leds";
sys_led {
gpios = <&gpio SSD20XD_GPIO_GPIO85 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
* Author: Romain Perier <romain.perier@gmail.com>
*/
/dts-v1/;
#include "mstar-infinity2m-ssd202d.dtsi"
#include "mstar-infinity2m-ssd201-som2d01.dtsi"
/ {
model = "Wireless Tag IDO-SOM2D01 (SSD202D)";
compatible = "wirelesstag,ido-som2d01", "mstar,infinity2m";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&reg_vcc_dram {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-infinity2m-ssd20xd.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x20000000 0x8000000>;
};
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-infinity2m.dtsi"
&gpio {
compatible = "sstar,ssd20xd-gpio";
status = "okay";
};
&smpctrl {
compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-infinity.dtsi"
&cpu0_opp_table {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
};
&cpus {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
operating-points-v2 = <&cpu0_opp_table>;
reg = <0x1>;
clocks = <&cpupll>;
clock-names = "cpuclk";
};
};
&riu {
smpctrl: smpctrl@204000 {
reg = <0x204000 0x200>;
status = "disabled";
};
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-infinity3-msc313e.dtsi"
#include "mstar-infinity-breadbee-common.dtsi"
/ {
model = "BreadBee";
compatible = "thingyjp,breadbee", "mstar,infinity3";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-infinity3.dtsi"
/ {
memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x4000000>;
};
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-infinity.dtsi"
&cpu0_opp_table {
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
// overclock frequencies below, shown to work fine up to 1.3 GHz
opp-108000000 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1188000000 {
opp-hz = /bits/ 64 <1188000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1350000000 {
opp-hz = /bits/ 64 <1350000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1404000000 {
opp-hz = /bits/ 64 <1404000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1458000000 {
opp-hz = /bits/ 64 <1458000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
&imi {
reg = <0xa0000000 0x20000>;
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
/dts-v1/;
#include "mstar-mercury5-ssc8336n.dtsi"
/ {
model = "70mai Midrive D08";
compatible = "70mai,midrived08", "mstar,mercury5";
aliases {
serial0 = &pm_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pm_uart {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-mercury5.dtsi"
/ {
memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x4000000>;
};
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include "mstar-v7.dtsi"
&imi {
reg = <0xa0000000 0x20000>;
};
linux-7.2.3/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mstar-msc313-mpll.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&cpupll>;
clock-names = "cpuclk";
};
};
arch_timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
/*
* we shouldn't need this but the vendor
* u-boot is broken
*/
clock-frequency = <6000000>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
};
clocks: clocks {
xtal: xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
rtc_xtal: rtc_xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
xtal_div2: xtal_div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&xtal>;
clock-div = <2>;
clock-mult = <1>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x16001000 0x16001000 0x00007000>,
<0x1f000000 0x1f000000 0x00400000>,
<0xa0000000 0xa0000000 0x20000>;
gic: interrupt-controller@16001000 {
compatible = "arm,cortex-a7-gic";
reg = <0x16001000 0x1000>,
<0x16002000 0x2000>,
<0x16004000 0x2000>,
<0x16006000 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
};
riu: bus@1f000000 {
compatible = "simple-bus";
reg = <0x1f000000 0x00400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1f000000 0x00400000>;
pmsleep: syscon@1c00 {
compatible = "mstar,msc313-pmsleep", "syscon";
reg = <0x1c00 0x100>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&pmsleep>;
offset = <0xb8>;
mask = <0x79>;
};
rtc@2400 {
compatible = "mstar,msc313-rtc";
reg = <0x2400 0x40>;
clocks = <&xtal_div2>;
interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog@6000 {
compatible = "mstar,msc313e-wdt";
reg = <0x6000 0x1f>;
clocks = <&xtal_div2>;
};
intc_fiq: interrupt-controller@201310 {
compatible = "mstar,mst-intc";
reg = <0x201310 0x40>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
mstar,irqs-map-range = <96 127>;
};
intc_irq: interrupt-controller@201350 {
compatible = "mstar,mst-intc";
reg = <0x201350 0x40>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
mstar,irqs-map-range = <32 95>;
mstar,intc-no-eoi;
};
l3bridge: l3bridge@204400 {
compatible = "mstar,l3bridge";
reg = <0x204400 0x200>;
};
mpll: mpll@206000 {
compatible = "mstar,msc313-mpll";
#clock-cells = <1>;
reg = <0x206000 0x200>;
clocks = <&xtal>;
};
cpupll: cpupll@206400 {
compatible = "mstar,msc313-cpupll";
reg = <0x206400 0x200>;
#clock-cells = <0>;
clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
};
gpio: gpio@207800 {
#gpio-cells = <2>;
reg = <0x207800 0x200>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&intc_fiq>;
status = "disabled";
};
pm_uart: serial@221000 {
compatible = "ns16550a";
reg = <0x221000 0x100>;
reg-shift = <3>;
interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <172000000>;
status = "disabled";
};
};
imi: sram@a0000000 {
compatible = "mmio-sram";
reg = <0xa0000000 0x10000>;
};
};
};