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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm/boot/dts/synaptics/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb \
berlin2cd-valve-steamlink.dtb \
berlin2q-marvell-dmp.dtb
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Sony NSZ-GS7
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*/
/dts-v1/;
#include "berlin2.dtsi"
/ {
model = "Sony NSZ-GS7";
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
};
&ahci { status = "okay"; };
&eth1 { status = "okay"; };
/* Unpopulated SATA plug on solder side */
&sata0 { status = "okay"; };
&sata_phy { status = "okay"; };
/* Samsung M8G2FA 8GB eMMC */
&sdhci2 {
non-removable;
bus-width = <8>;
status = "okay";
};
&uart0 { status = "okay"; };
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*/
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500 (BG2) SoC";
compatible = "marvell,berlin2", "marvell,berlin";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,berlin-smp";
cpu@0 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
cpu@1 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc@f7000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0 0xf7000000 0x1000000>;
sdhci0: mmc@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci1: mmc@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
clock-names = "io", "core";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci2: mmc@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
clock-names = "io", "core";
pinctrl-0 = <&emmc_pmux>;
pinctrl-names = "default";
status = "disabled";
};
l2: cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&chip_clk CLKID_TWD>;
};
eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
clocks = <&chip_clk CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy1>;
status = "disabled";
ethphy1: ethernet-phy@0 {
reg = <0>;
};
};
cpu-ctrl@dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xdd0000 0x10000>;
};
eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>;
clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy0>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
ahci: sata@e90000 {
compatible = "marvell,berlin2-ahci", "generic-ahci";
reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
status = "disabled";
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
status = "disabled";
};
};
sata_phy: phy@e900a0 {
compatible = "marvell,berlin2-sata-phy";
reg = <0xe900a0 0x200>;
clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
sata-phy@0 {
reg = <0>;
};
sata-phy@1 {
reg = <1>;
};
};
chip: chip-control@ea0000 {
compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
chip_clk: clock {
compatible = "marvell,berlin2-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2-soc-pinctrl";
emmc_pmux: emmc-pmux {
groups = "G26";
function = "emmc";
};
};
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
};
};
pwm: pwm@f20000 {
compatible = "marvell,berlin-pwm";
reg = <0xf20000 0x40>;
clocks = <&chip_clk CLKID_CFG>;
#pwm-cells = <3>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
wdt0: watchdog@1000 {
compatible = "snps,dw-wdt";
reg = <0x1000 0x100>;
clocks = <&refclk>;
interrupts = <0>;
};
wdt1: watchdog@2000 {
compatible = "snps,dw-wdt";
reg = <0x2000 0x100>;
clocks = <&refclk>;
interrupts = <1>;
};
wdt2: watchdog@3000 {
compatible = "snps,dw-wdt";
reg = <0x3000 0x100>;
clocks = <&refclk>;
interrupts = <2>;
};
sm_gpio1: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
};
};
sm_gpio0: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <11>;
};
};
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&refclk>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&refclk>;
pinctrl-0 = <&uart1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart2: serial@b000 {
compatible = "snps,dw-apb-uart";
reg = <0xb000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <10>;
clocks = <&refclk>;
pinctrl-0 = <&uart2_pmux>;
pinctrl-names = "default";
status = "disabled";
};
sysctrl: system-controller@d000 {
compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
compatible = "marvell,berlin2-system-pinctrl";
uart0_pmux: uart0-pmux {
groups = "GSM4";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM5";
function = "uart1";
};
uart2_pmux: uart2-pmux {
groups = "GSM3";
function = "uart2";
};
};
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Google Chromecast
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*/
/dts-v1/;
#include "berlin2cd.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Google Chromecast";
compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
/*
* We're using "linux,usable-memory" instead of "reg" here
* because the (signed and encrypted) bootloader that shipped
* with this device provides an incorrect memory range in
* ATAG_MEM. Linux helpfully overrides the "reg" property with
* data from the ATAG, so we can't specify the proper range
* normally. Fortunately, this alternate property is checked
* first by the OF driver, so we can (ab)use it instead.
*/
linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */
};
led-controller {
compatible = "pwm-leds";
pinctrl-0 = <&ledpwm_pmux>;
pinctrl-names = "default";
led-1 {
label = "white";
pwms = <&pwm 0 600000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
led-2 {
label = "red";
pwms = <&pwm 1 600000 0>;
max-brightness = <255>;
};
};
};
/*
* AzureWave AW-NH387 (Marvell 88W8787)
* 802.11b/g/n + Bluetooth 2.1
*/
&sdhci0 {
non-removable;
status = "okay";
};
&uart0 { status = "okay"; };
&usb_phy1 { status = "okay"; };
&usb1 { status = "okay"; };
&soc_pinctrl {
ledpwm_pmux: ledpwm-pmux {
groups = "G0";
function = "pwm";
};
};
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2018 Alexander Monakov <amonakov@gmail.com>
*/
/dts-v1/;
#include "berlin2cd.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Valve Steam Link";
compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
active-delay = <100>;
inactive-delay = <10>;
wait-delay = <100>;
priority = <200>;
};
};
&cpu {
cpu-supply = <&vcpu>;
operating-points = <
/* kHz uV */
1000000 1325000
>;
};
&i2c0 {
status = "okay";
/* There are two regulators on the board. One is accessible via I2C,
* with buck1 providing SoC power (set up by bootloader to 1.325V or
* less depending on leakage value in OTP), and buck2 likely used for
* DRAM (providing 1.35V). The other regulator on the opposite side
* of the board is probably supplying SDIO and NAND fixed voltages. */
regulator@19 {
compatible = "marvell,88pg868";
reg = <0x19>;
vcpu: buck1 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1325000>;
};
};
};
/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */
&sdhci0 {
keep-power-in-suspend;
non-removable;
status = "okay";
};
&uart0 {
/* RX/TX are routed to TP50/TP51 on the board. */
status = "okay";
};
/* The SoC is connected to on-board USB hub that in turn has one downstream
* port wired to the on-board Steam Controller wireless receiver chip. */
&usb_phy1 { status = "okay"; };
&usb1 {
dr_mode = "host";
status = "okay";
};
&eth1 { status = "okay"; };
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2cd.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*/
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500-mini (BG2CD) SoC";
compatible = "marvell,berlin2cd", "marvell,berlin";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
operating-points = <
/* kHz uV */
800000 1200000
600000 1200000
>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc@f7000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0 0xf7000000 0x1000000>;
sdhci0: mmc@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
};
snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x100>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
global-timer@ad0200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xad0200 0x20>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&chip_clk CLKID_TWD>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&chip_clk CLKID_TWD>;
};
local-wdt@ad0620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0xad0620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&chip_clk CLKID_TWD>;
};
usb_phy0: usb-phy@b74000 {
compatible = "marvell,berlin2cd-usb-phy";
reg = <0xb74000 0x128>;
#phy-cells = <0>;
resets = <&chip_rst 0x178 23>;
status = "disabled";
};
usb_phy1: usb-phy@b78000 {
compatible = "marvell,berlin2cd-usb-phy";
reg = <0xb78000 0x128>;
#phy-cells = <0>;
resets = <&chip_rst 0x178 24>;
status = "disabled";
};
eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
clocks = <&chip_clk CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy1>;
status = "disabled";
ethphy1: ethernet-phy@0 {
reg = <0>;
};
};
eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>;
clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy0>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
i2c0: i2c@1400 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1400 0x100>;
interrupts = <16>;
clocks = <&chip_clk CLKID_CFG>;
status = "disabled";
};
i2c1: i2c@1800 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1800 0x100>;
interrupts = <17>;
clocks = <&chip_clk CLKID_CFG>;
status = "disabled";
};
spi0: spi@1c00 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1c00 0x100>;
interrupts = <4>;
clocks = <&chip_clk CLKID_CFG>;
status = "disabled";
};
wdt4: watchdog@2000 {
compatible = "snps,dw-wdt";
reg = <0x2000 0x100>;
clocks = <&chip_clk CLKID_CFG>;
interrupts = <5>;
status = "disabled";
};
wdt5: watchdog@2400 {
compatible = "snps,dw-wdt";
reg = <0x2400 0x100>;
clocks = <&chip_clk CLKID_CFG>;
interrupts = <6>;
status = "disabled";
};
wdt6: watchdog@2800 {
compatible = "snps,dw-wdt";
reg = <0x2800 0x100>;
clocks = <&chip_clk CLKID_CFG>;
interrupts = <7>;
status = "disabled";
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
chip: chip-control@ea0000 {
compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
chip_clk: clock {
compatible = "marvell,berlin2-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2cd-soc-pinctrl";
uart0_pmux: uart0-pmux {
groups = "G6";
function = "uart0";
};
};
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
};
};
usb0: usb@ed0000 {
compatible = "chipidea,usb2";
reg = <0xed0000 0x200>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_USB0>;
phys = <&usb_phy0>;
phy-names = "usb-phy";
status = "disabled";
};
usb1: usb@ee0000 {
compatible = "chipidea,usb2";
reg = <0xee0000 0x200>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_USB1>;
phys = <&usb_phy1>;
phy-names = "usb-phy";
status = "disabled";
};
pwm: pwm@f20000 {
compatible = "marvell,berlin-pwm";
reg = <0xf20000 0x40>;
clocks = <&chip_clk CLKID_CFG>;
#pwm-cells = <3>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
wdt0: watchdog@1000 {
compatible = "snps,dw-wdt";
reg = <0x1000 0x100>;
clocks = <&refclk>;
interrupts = <0>;
};
wdt1: watchdog@2000 {
compatible = "snps,dw-wdt";
reg = <0x2000 0x100>;
clocks = <&refclk>;
interrupts = <1>;
status = "disabled";
};
wdt2: watchdog@3000 {
compatible = "snps,dw-wdt";
reg = <0x3000 0x100>;
clocks = <&refclk>;
interrupts = <2>;
status = "disabled";
};
sm_gpio1: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
};
};
spi1: spi@6000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6000 0x100>;
clocks = <&refclk>;
interrupts = <5>;
status = "disabled";
};
i2c2: i2c@7000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x100>;
interrupts = <6>;
clocks = <&refclk>;
status = "disabled";
};
i2c3: i2c@8000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8000 0x100>;
interrupts = <7>;
clocks = <&refclk>;
status = "disabled";
};
sm_gpio0: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
reg = <0>;
};
};
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&refclk>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&refclk>;
status = "disabled";
};
uart2: serial@b000 {
compatible = "snps,dw-apb-uart";
reg = <0xb000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <10>;
clocks = <&refclk>;
status = "disabled";
};
sysctrl: system-controller@d000 {
compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
compatible = "marvell,berlin2cd-system-pinctrl";
};
adc: adc {
compatible = "marvell,berlin2-adc";
interrupts = <12>, <14>;
interrupt-names = "adc", "tsen";
};
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "berlin2q.dtsi"
/ {
model = "Marvell BG2-Q DMP";
compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x80000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb0_vbus: regulator_usb0 {
compatible = "regulator-fixed";
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&portb 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb1_vbus: regulator_usb1 {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&portb 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb2_vbus: regulator_usb2 {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_sdio1_vmmc: regulator_sdio1_vmmc {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "sdio1_vmmc";
enable-active-high;
regulator-boot-on;
gpio = <&portb 21 GPIO_ACTIVE_HIGH>;
};
reg_sdio1_vqmmc: regulator_sido1_vqmmc {
compatible = "regulator-gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "sdio1_vqmmc";
regulator-type = "voltage";
enable-active-high;
gpios = <&portb 16 GPIO_ACTIVE_HIGH>;
states = <3300000 0x1
1800000 0x0>;
};
};
};
&soc_pinctrl {
sd1gpio_pmux: sd1pwr-pmux {
groups = "G23", "G32";
function = "gpio";
};
};
&sdhci1 {
vmmc-supply = <&reg_sdio1_vmmc>;
vqmmc-supply = <&reg_sdio1_vqmmc>;
cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <8>;
non-removable;
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb_phy2 {
status = "okay";
};
&usb0 {
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
&usb2 {
vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
&eth0 {
status = "okay";
};
&sata0 {
status = "okay";
};
&sata_phy {
status = "okay";
};
linux-7.2.3/arch/arm/boot/dts/synaptics/berlin2q.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
*/
#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500 pro (BG2-Q) SoC";
compatible = "marvell,berlin2q", "marvell,berlin";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,berlin-smp";
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
/* Can be modified by the bootloader */
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
/* Can be modified by the bootloader */
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <2>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
/* Can be modified by the bootloader */
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <3>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
/* Can be modified by the bootloader */
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc@f7000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf7000000 0x1000000>;
interrupt-parent = <&gic>;
sdhci0: mmc@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci1: mmc@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
clock-names = "io", "core";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci2: mmc@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
clock-names = "io", "core";
status = "disabled";
};
l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
arm,data-latency = <2 2 2>;
arm,tag-latency = <2 2 2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
clocks = <&chip_clk CLKID_TWD>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
};
usb_phy2: phy@a2f400 {
compatible = "marvell,berlin2cd-usb-phy";
reg = <0xa2f400 0x128>;
#phy-cells = <0>;
resets = <&chip_rst 0x104 14>;
status = "disabled";
};
usb2: usb@a30000 {
compatible = "chipidea,usb2";
reg = <0xa30000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_USB2>;
phys = <&usb_phy2>;
phy-names = "usb-phy";
status = "disabled";
};
usb_phy0: phy@b74000 {
compatible = "marvell,berlin2cd-usb-phy";
reg = <0xb74000 0x128>;
#phy-cells = <0>;
resets = <&chip_rst 0x104 12>;
status = "disabled";
};
usb_phy1: phy@b78000 {
compatible = "marvell,berlin2cd-usb-phy";
reg = <0xb78000 0x128>;
#phy-cells = <0>;
resets = <&chip_rst 0x104 13>;
status = "disabled";
};
eth0: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
#address-cells = <1>;
#size-cells = <0>;
phy-connection-type = "mii";
phy-handle = <&ethphy0>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
cpu-ctrl@dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xdd0000 0x10000>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
i2c0: i2c@1400 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1400 0x100>;
interrupts = <4>;
clocks = <&chip_clk CLKID_CFG>;
pinctrl-0 = <&twsi0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
i2c1: i2c@1800 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1800 0x100>;
interrupts = <5>;
clocks = <&chip_clk CLKID_CFG>;
pinctrl-0 = <&twsi1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
interrupts = <8>;
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3800 {
compatible = "snps,dw-apb-ictl";
reg = <0x3800 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
chip: chip-control@ea0000 {
compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
chip_clk: clock {
compatible = "marvell,berlin2q-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2q-soc-pinctrl";
sd1_pmux: sd1-pmux {
groups = "G31";
function = "sd1";
};
twsi0_pmux: twsi0-pmux {
groups = "G6";
function = "twsi0";
};
twsi1_pmux: twsi1-pmux {
groups = "G7";
function = "twsi1";
};
};
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
};
};
ahci: sata@e90000 {
compatible = "marvell,berlin2q-ahci", "generic-ahci";
reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
status = "disabled";
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
status = "disabled";
};
};
sata_phy: phy@e900a0 {
compatible = "marvell,berlin2q-sata-phy";
reg = <0xe900a0 0x200>;
clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
sata-phy@0 {
reg = <0>;
};
sata-phy@1 {
reg = <1>;
};
};
usb0: usb@ed0000 {
compatible = "chipidea,usb2";
reg = <0xed0000 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_USB0>;
phys = <&usb_phy0>;
phy-names = "usb-phy";
status = "disabled";
};
usb1: usb@ee0000 {
compatible = "chipidea,usb2";
reg = <0xee0000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip_clk CLKID_USB1>;
phys = <&usb_phy1>;
phy-names = "usb-phy";
status = "disabled";
};
pwm: pwm@f20000 {
compatible = "marvell,berlin-pwm";
reg = <0xf20000 0x40>;
clocks = <&chip_clk CLKID_CFG>;
#pwm-cells = <3>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
wdt0: watchdog@1000 {
compatible = "snps,dw-wdt";
reg = <0x1000 0x100>;
clocks = <&refclk>;
interrupts = <0>;
};
wdt1: watchdog@2000 {
compatible = "snps,dw-wdt";
reg = <0x2000 0x100>;
clocks = <&refclk>;
interrupts = <1>;
};
wdt2: watchdog@3000 {
compatible = "snps,dw-wdt";
reg = <0x3000 0x100>;
clocks = <&refclk>;
interrupts = <2>;
};
sm_gpio1: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
};
};
i2c2: i2c@7000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x100>;
interrupts = <6>;
clocks = <&refclk>;
pinctrl-0 = <&twsi2_pmux>;
pinctrl-names = "default";
status = "disabled";
};
i2c3: i2c@8000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8000 0x100>;
interrupts = <7>;
clocks = <&refclk>;
pinctrl-0 = <&twsi3_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
interrupts = <8>;
clocks = <&refclk>;
reg-shift = <2>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
interrupts = <9>;
clocks = <&refclk>;
reg-shift = <2>;
pinctrl-0 = <&uart1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
sm_gpio0: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
};
};
sysctrl: pin-controller@d000 {
compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
compatible = "marvell,berlin2q-system-pinctrl";
uart0_pmux: uart0-pmux {
groups = "GSM12";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM14";
function = "uart1";
};
twsi2_pmux: twsi2-pmux {
groups = "GSM13";
function = "twsi2";
};
twsi3_pmux: twsi3-pmux {
groups = "GSM14";
function = "twsi3";
};
};
adc: adc {
compatible = "marvell,berlin2-adc";
interrupts = <12>, <14>;
interrupt-names = "adc", "tsen";
};
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};