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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/arch/arm/include/asm/hardware/cache-aurora-l2.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AURORA shared L2 cache controller support
*
* Copyright (C) 2012 Marvell
*
* Yehuda Yitschak <yehuday@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*/
#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
#define __ASM_ARM_HARDWARE_AURORA_L2_H
#define AURORA_SYNC_REG 0x700
#define AURORA_RANGE_BASE_ADDR_REG 0x720
#define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
#define AURORA_INVAL_RANGE_REG 0x774
#define AURORA_CLEAN_RANGE_REG 0x7b4
#define AURORA_FLUSH_RANGE_REG 0x7f4
#define AURORA_ACR_REPLACEMENT_OFFSET 27
#define AURORA_ACR_REPLACEMENT_MASK \
(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \
(0 << AURORA_ACR_REPLACEMENT_OFFSET)
#define AURORA_ACR_REPLACEMENT_TYPE_LFSR \
(1 << AURORA_ACR_REPLACEMENT_OFFSET)
#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
(3 << AURORA_ACR_REPLACEMENT_OFFSET)
#define AURORA_ACR_PARITY_EN (1 << 21)
#define AURORA_ACR_ECC_EN (1 << 20)
#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \
(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
#define AURORA_ACR_FORCE_WRITE_POLICY_DIS \
(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
#define AURORA_ACR_FORCE_WRITE_BACK_POLICY \
(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \
(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
#define AURORA_ERR_CNT_REG 0x600
#define AURORA_ERR_ATTR_CAP_REG 0x608
#define AURORA_ERR_ADDR_CAP_REG 0x60c
#define AURORA_ERR_WAY_CAP_REG 0x610
#define AURORA_ERR_INJECT_CTL_REG 0x614
#define AURORA_ERR_INJECT_MASK_REG 0x618
#define AURORA_ERR_CNT_CLR_OFFSET 31
#define AURORA_ERR_CNT_CLR \
(0x1 << AURORA_ERR_CNT_CLR_OFFSET)
#define AURORA_ERR_CNT_UE_OFFSET 16
#define AURORA_ERR_CNT_UE_MASK \
(0x7fff << AURORA_ERR_CNT_UE_OFFSET)
#define AURORA_ERR_CNT_CE_OFFSET 0
#define AURORA_ERR_CNT_CE_MASK \
(0xffff << AURORA_ERR_CNT_CE_OFFSET)
#define AURORA_ERR_ATTR_SRC_OFF 16
#define AURORA_ERR_ATTR_SRC_MSK \
(0x7 << AURORA_ERR_ATTR_SRC_OFF)
#define AURORA_ERR_ATTR_TXN_OFF 12
#define AURORA_ERR_ATTR_TXN_MSK \
(0xf << AURORA_ERR_ATTR_TXN_OFF)
#define AURORA_ERR_ATTR_ERR_OFF 8
#define AURORA_ERR_ATTR_ERR_MSK \
(0x3 << AURORA_ERR_ATTR_ERR_OFF)
#define AURORA_ERR_ATTR_CAP_VALID_OFF 0
#define AURORA_ERR_ATTR_CAP_VALID \
(0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF)
#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0
#define AURORA_ERR_WAY_IDX_OFF 8
#define AURORA_ERR_WAY_IDX_MSK \
(0xfff << AURORA_ERR_WAY_IDX_OFF)
#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1
#define AURORA_ERR_WAY_CAP_WAY_MASK \
(0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET)
#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0
#define AURORA_ERR_ATTR_TXN_OFF 12
#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3
#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2
#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1
#define AURORA_MAX_RANGE_SIZE 1024
#define AURORA_WAY_SIZE_SHIFT 2
#define AURORA_CTRL_FW 0x100
/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
* the distinction between a number coming from hardware and a number
* coming from the device tree */
#define AURORA_CACHE_ID 0x100
#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
linux-7.2.3/arch/arm/include/asm/hardware/cache-b15-rac.h
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#ifndef __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
#define __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
#ifndef __ASSEMBLY__
void b15_flush_kern_cache_all(void);
#endif
#endif
linux-7.2.3/arch/arm/include/asm/hardware/cache-feroceon-l2.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/cache-feroceon-l2.h
*
* Copyright (C) 2008 Marvell Semiconductor
*/
extern void __init feroceon_l2_init(int l2_wt_override);
extern int __init feroceon_of_init(void);
linux-7.2.3/arch/arm/include/asm/hardware/cache-l2x0.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/cache-l2x0.h
*
* Copyright (C) 2007 ARM Limited
*/
#ifndef __ASM_ARM_HARDWARE_L2X0_H
#define __ASM_ARM_HARDWARE_L2X0_H
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/types.h>
#define L2X0_CACHE_ID 0x000
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
#define L310_TAG_LATENCY_CTRL 0x108
#define L310_DATA_LATENCY_CTRL 0x10C
#define L2X0_EVENT_CNT_CTRL 0x200
#define L2X0_EVENT_CNT1_CFG 0x204
#define L2X0_EVENT_CNT0_CFG 0x208
#define L2X0_EVENT_CNT1_VAL 0x20C
#define L2X0_EVENT_CNT0_VAL 0x210
#define L2X0_INTR_MASK 0x214
#define L2X0_MASKED_INTR_STAT 0x218
#define L2X0_RAW_INTR_STAT 0x21C
#define L2X0_INTR_CLEAR 0x220
#define L2X0_CACHE_SYNC 0x730
#define L2X0_DUMMY_REG 0x740
#define L2X0_INV_LINE_PA 0x770
#define L2X0_INV_WAY 0x77C
#define L2X0_CLEAN_LINE_PA 0x7B0
#define L2X0_CLEAN_LINE_IDX 0x7B8
#define L2X0_CLEAN_WAY 0x7BC
#define L2X0_CLEAN_INV_LINE_PA 0x7F0
#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
#define L2X0_CLEAN_INV_WAY 0x7FC
/*
* The lockdown registers repeat 8 times for L310, the L210 has only one
* D and one I lockdown register at 0x0900 and 0x0904.
*/
#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
#define L2X0_LOCKDOWN_STRIDE 0x08
#define L310_ADDR_FILTER_START 0xC00
#define L310_ADDR_FILTER_END 0xC04
#define L2X0_TEST_OPERATION 0xF00
#define L2X0_LINE_DATA 0xF10
#define L2X0_LINE_TAG 0xF30
#define L2X0_DEBUG_CTRL 0xF40
#define L310_PREFETCH_CTRL 0xF60
#define L310_POWER_CTRL 0xF80
#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
#define L310_STNDBY_MODE_EN (1 << 0)
/* Registers shifts and masks */
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
#define L2X0_CACHE_ID_PART_L220 (2 << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_ID_RTL_MASK 0x3f
#define L210_CACHE_ID_RTL_R0P2_02 0x00
#define L210_CACHE_ID_RTL_R0P1 0x01
#define L210_CACHE_ID_RTL_R0P2_01 0x02
#define L210_CACHE_ID_RTL_R0P3 0x03
#define L210_CACHE_ID_RTL_R0P4 0x0b
#define L210_CACHE_ID_RTL_R0P5 0x0f
#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
#define L310_CACHE_ID_RTL_R0P0 0x00
#define L310_CACHE_ID_RTL_R1P0 0x02
#define L310_CACHE_ID_RTL_R2P0 0x04
#define L310_CACHE_ID_RTL_R3P0 0x05
#define L310_CACHE_ID_RTL_R3P1 0x06
#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
#define L310_CACHE_ID_RTL_R3P2 0x08
#define L310_CACHE_ID_RTL_R3P3 0x09
#define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0)
#define L2X0_EVENT_CNT_CFG_SRC_SHIFT 2
#define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf
#define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0
#define L2X0_EVENT_CNT_CFG_INT_DISABLED 0
#define L2X0_EVENT_CNT_CFG_INT_INCR 1
#define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2
/* L2C auxiliary control register - bits common to L2C-210/220/310 */
#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
/* L2C-210/220 common bits */
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
/* L2C-210 specific bits */
#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
/* L2C-220 specific bits */
#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
#define L220_AUX_CTRL_FWA_SHIFT 23
#define L220_AUX_CTRL_FWA_MASK (3 << 23)
#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
/* L2C-310 specific bits */
#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
#define L310_AUX_CTRL_FWA_SHIFT 23
#define L310_AUX_CTRL_FWA_MASK (3 << 23)
#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
#define L310_ADDR_FILTER_EN 1
#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
#define L2X0_CTRL_EN 1
#define L2X0_WAY_SIZE_SHIFT 3
#ifndef __ASSEMBLY__
extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
#else
static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_CACHE_L2X0_PMU
void l2x0_pmu_register(void __iomem *base, u32 part);
void l2x0_pmu_suspend(void);
void l2x0_pmu_resume(void);
#else
static inline void l2x0_pmu_register(void __iomem *base, u32 part) {}
static inline void l2x0_pmu_suspend(void) {}
static inline void l2x0_pmu_resume(void) {}
#endif
struct l2x0_regs {
unsigned long phy_base;
unsigned long aux_ctrl;
/*
* Whether the following registers need to be saved/restored
* depends on platform
*/
unsigned long tag_latency;
unsigned long data_latency;
unsigned long filter_start;
unsigned long filter_end;
unsigned long prefetch_ctrl;
unsigned long pwr_ctrl;
unsigned long ctrl;
unsigned long aux2_ctrl;
};
extern struct l2x0_regs l2x0_saved_regs;
#endif /* __ASSEMBLY__ */
#endif
linux-7.2.3/arch/arm/include/asm/hardware/cache-tauros2.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/cache-tauros2.h
*
* Copyright (C) 2008 Marvell Semiconductor
*/
#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)
#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
extern void __init tauros2_init(unsigned int features);
linux-7.2.3/arch/arm/include/asm/hardware/cache-uniphier.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#ifndef __CACHE_UNIPHIER_H
#define __CACHE_UNIPHIER_H
#include <linux/errno.h>
#ifdef CONFIG_CACHE_UNIPHIER
int uniphier_cache_init(void);
#else
static inline int uniphier_cache_init(void)
{
return -ENODEV;
}
#endif
#endif /* __CACHE_UNIPHIER_H */
linux-7.2.3/arch/arm/include/asm/hardware/cp14.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*/
#ifndef __ASM_HARDWARE_CP14_H
#define __ASM_HARDWARE_CP14_H
#include <linux/types.h>
/* Accessors for CP14 registers */
#define dbg_read(reg) RCP14_##reg()
#define dbg_write(val, reg) WCP14_##reg(val)
#define etm_read(reg) RCP14_##reg()
#define etm_write(val, reg) WCP14_##reg(val)
/* MRC14 and MCR14 */
#define MRC14(op1, crn, crm, op2) \
({ \
u32 val; \
asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
val; \
})
#define MCR14(val, op1, crn, crm, op2) \
({ \
asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
})
/*
* Debug Registers
*
* Available only in DBGv7
* DBGECR, DBGDSCCR, DBGDSMCR, DBGDRCR
*
* Available only in DBGv7.1
* DBGBXVRm, DBGOSDLR, DBGDEVID2, DBGDEVID1
*
* Read only
* DBGDIDR, DBGDSCRint, DBGDTRRXint, DBGDRAR, DBGOSLSR, DBGOSSRR, DBGPRSR,
* DBGPRSR, DBGDSAR, DBGAUTHSTATUS, DBGDEVID2, DBGDEVID1, DBGDEVID
*
* Write only
* DBGDTRTXint, DBGOSLAR
*/
#define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
#define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
#define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
#define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
#define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
#define RCP14_DBGECR() MRC14(0, c0, c9, 0)
#define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
#define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
#define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
#define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
#define RCP14_DBGDTRTXext() MRC14(0, c0, c3, 2)
#define RCP14_DBGDRCR() MRC14(0, c0, c4, 2)
#define RCP14_DBGBVR0() MRC14(0, c0, c0, 4)
#define RCP14_DBGBVR1() MRC14(0, c0, c1, 4)
#define RCP14_DBGBVR2() MRC14(0, c0, c2, 4)
#define RCP14_DBGBVR3() MRC14(0, c0, c3, 4)
#define RCP14_DBGBVR4() MRC14(0, c0, c4, 4)
#define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
#define RCP14_DBGBVR6() MRC14(0, c0, c6, 4)
#define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
#define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
#define RCP14_DBGBVR9() MRC14(0, c0, c9, 4)
#define RCP14_DBGBVR10() MRC14(0, c0, c10, 4)
#define RCP14_DBGBVR11() MRC14(0, c0, c11, 4)
#define RCP14_DBGBVR12() MRC14(0, c0, c12, 4)
#define RCP14_DBGBVR13() MRC14(0, c0, c13, 4)
#define RCP14_DBGBVR14() MRC14(0, c0, c14, 4)
#define RCP14_DBGBVR15() MRC14(0, c0, c15, 4)
#define RCP14_DBGBCR0() MRC14(0, c0, c0, 5)
#define RCP14_DBGBCR1() MRC14(0, c0, c1, 5)
#define RCP14_DBGBCR2() MRC14(0, c0, c2, 5)
#define RCP14_DBGBCR3() MRC14(0, c0, c3, 5)
#define RCP14_DBGBCR4() MRC14(0, c0, c4, 5)
#define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
#define RCP14_DBGBCR6() MRC14(0, c0, c6, 5)
#define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
#define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
#define RCP14_DBGBCR9() MRC14(0, c0, c9, 5)
#define RCP14_DBGBCR10() MRC14(0, c0, c10, 5)
#define RCP14_DBGBCR11() MRC14(0, c0, c11, 5)
#define RCP14_DBGBCR12() MRC14(0, c0, c12, 5)
#define RCP14_DBGBCR13() MRC14(0, c0, c13, 5)
#define RCP14_DBGBCR14() MRC14(0, c0, c14, 5)
#define RCP14_DBGBCR15() MRC14(0, c0, c15, 5)
#define RCP14_DBGWVR0() MRC14(0, c0, c0, 6)
#define RCP14_DBGWVR1() MRC14(0, c0, c1, 6)
#define RCP14_DBGWVR2() MRC14(0, c0, c2, 6)
#define RCP14_DBGWVR3() MRC14(0, c0, c3, 6)
#define RCP14_DBGWVR4() MRC14(0, c0, c4, 6)
#define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
#define RCP14_DBGWVR6() MRC14(0, c0, c6, 6)
#define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
#define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
#define RCP14_DBGWVR9() MRC14(0, c0, c9, 6)
#define RCP14_DBGWVR10() MRC14(0, c0, c10, 6)
#define RCP14_DBGWVR11() MRC14(0, c0, c11, 6)
#define RCP14_DBGWVR12() MRC14(0, c0, c12, 6)
#define RCP14_DBGWVR13() MRC14(0, c0, c13, 6)
#define RCP14_DBGWVR14() MRC14(0, c0, c14, 6)
#define RCP14_DBGWVR15() MRC14(0, c0, c15, 6)
#define RCP14_DBGWCR0() MRC14(0, c0, c0, 7)
#define RCP14_DBGWCR1() MRC14(0, c0, c1, 7)
#define RCP14_DBGWCR2() MRC14(0, c0, c2, 7)
#define RCP14_DBGWCR3() MRC14(0, c0, c3, 7)
#define RCP14_DBGWCR4() MRC14(0, c0, c4, 7)
#define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
#define RCP14_DBGWCR6() MRC14(0, c0, c6, 7)
#define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
#define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
#define RCP14_DBGWCR9() MRC14(0, c0, c9, 7)
#define RCP14_DBGWCR10() MRC14(0, c0, c10, 7)
#define RCP14_DBGWCR11() MRC14(0, c0, c11, 7)
#define RCP14_DBGWCR12() MRC14(0, c0, c12, 7)
#define RCP14_DBGWCR13() MRC14(0, c0, c13, 7)
#define RCP14_DBGWCR14() MRC14(0, c0, c14, 7)
#define RCP14_DBGWCR15() MRC14(0, c0, c15, 7)
#define RCP14_DBGDRAR() MRC14(0, c1, c0, 0)
#define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
#define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
#define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
#define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1)
#define RCP14_DBGBXVR4() MRC14(0, c1, c4, 1)
#define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
#define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1)
#define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
#define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
#define RCP14_DBGBXVR9() MRC14(0, c1, c9, 1)
#define RCP14_DBGBXVR10() MRC14(0, c1, c10, 1)
#define RCP14_DBGBXVR11() MRC14(0, c1, c11, 1)
#define RCP14_DBGBXVR12() MRC14(0, c1, c12, 1)
#define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1)
#define RCP14_DBGBXVR14() MRC14(0, c1, c14, 1)
#define RCP14_DBGBXVR15() MRC14(0, c1, c15, 1)
#define RCP14_DBGOSLSR() MRC14(0, c1, c1, 4)
#define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4)
#define RCP14_DBGOSDLR() MRC14(0, c1, c3, 4)
#define RCP14_DBGPRCR() MRC14(0, c1, c4, 4)
#define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
#define RCP14_DBGDSAR() MRC14(0, c2, c0, 0)
#define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
#define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
#define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
#define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
#define RCP14_DBGDEVID2() MRC14(0, c7, c0, 7)
#define RCP14_DBGDEVID1() MRC14(0, c7, c1, 7)
#define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
#define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
#define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
#define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0)
#define WCP14_DBGECR(val) MCR14(val, 0, c0, c9, 0)
#define WCP14_DBGDSCCR(val) MCR14(val, 0, c0, c10, 0)
#define WCP14_DBGDSMCR(val) MCR14(val, 0, c0, c11, 0)
#define WCP14_DBGDTRRXext(val) MCR14(val, 0, c0, c0, 2)
#define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2)
#define WCP14_DBGDTRTXext(val) MCR14(val, 0, c0, c3, 2)
#define WCP14_DBGDRCR(val) MCR14(val, 0, c0, c4, 2)
#define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4)
#define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4)
#define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4)
#define WCP14_DBGBVR3(val) MCR14(val, 0, c0, c3, 4)
#define WCP14_DBGBVR4(val) MCR14(val, 0, c0, c4, 4)
#define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
#define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
#define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4)
#define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
#define WCP14_DBGBVR9(val) MCR14(val, 0, c0, c9, 4)
#define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4)
#define WCP14_DBGBVR11(val) MCR14(val, 0, c0, c11, 4)
#define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4)
#define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4)
#define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4)
#define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4)
#define WCP14_DBGBCR0(val) MCR14(val, 0, c0, c0, 5)
#define WCP14_DBGBCR1(val) MCR14(val, 0, c0, c1, 5)
#define WCP14_DBGBCR2(val) MCR14(val, 0, c0, c2, 5)
#define WCP14_DBGBCR3(val) MCR14(val, 0, c0, c3, 5)
#define WCP14_DBGBCR4(val) MCR14(val, 0, c0, c4, 5)
#define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
#define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
#define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5)
#define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
#define WCP14_DBGBCR9(val) MCR14(val, 0, c0, c9, 5)
#define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5)
#define WCP14_DBGBCR11(val) MCR14(val, 0, c0, c11, 5)
#define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5)
#define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5)
#define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5)
#define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5)
#define WCP14_DBGWVR0(val) MCR14(val, 0, c0, c0, 6)
#define WCP14_DBGWVR1(val) MCR14(val, 0, c0, c1, 6)
#define WCP14_DBGWVR2(val) MCR14(val, 0, c0, c2, 6)
#define WCP14_DBGWVR3(val) MCR14(val, 0, c0, c3, 6)
#define WCP14_DBGWVR4(val) MCR14(val, 0, c0, c4, 6)
#define WCP14_DBGWVR5(val) MCR14(val, 0, c0, c5, 6)
#define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6)
#define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6)
#define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
#define WCP14_DBGWVR9(val) MCR14(val, 0, c0, c9, 6)
#define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6)
#define WCP14_DBGWVR11(val) MCR14(val, 0, c0, c11, 6)
#define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6)
#define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6)
#define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6)
#define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6)
#define WCP14_DBGWCR0(val) MCR14(val, 0, c0, c0, 7)
#define WCP14_DBGWCR1(val) MCR14(val, 0, c0, c1, 7)
#define WCP14_DBGWCR2(val) MCR14(val, 0, c0, c2, 7)
#define WCP14_DBGWCR3(val) MCR14(val, 0, c0, c3, 7)
#define WCP14_DBGWCR4(val) MCR14(val, 0, c0, c4, 7)
#define WCP14_DBGWCR5(val) MCR14(val, 0, c0, c5, 7)
#define WCP14_DBGWCR6(val) MCR14(val, 0, c0, c6, 7)
#define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7)
#define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
#define WCP14_DBGWCR9(val) MCR14(val, 0, c0, c9, 7)
#define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7)
#define WCP14_DBGWCR11(val) MCR14(val, 0, c0, c11, 7)
#define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7)
#define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7)
#define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7)
#define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7)
#define WCP14_DBGBXVR0(val) MCR14(val, 0, c1, c0, 1)
#define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1)
#define WCP14_DBGBXVR2(val) MCR14(val, 0, c1, c2, 1)
#define WCP14_DBGBXVR3(val) MCR14(val, 0, c1, c3, 1)
#define WCP14_DBGBXVR4(val) MCR14(val, 0, c1, c4, 1)
#define WCP14_DBGBXVR5(val) MCR14(val, 0, c1, c5, 1)
#define WCP14_DBGBXVR6(val) MCR14(val, 0, c1, c6, 1)
#define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1)
#define WCP14_DBGBXVR8(val) MCR14(val, 0, c1, c8, 1)
#define WCP14_DBGBXVR9(val) MCR14(val, 0, c1, c9, 1)
#define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1)
#define WCP14_DBGBXVR11(val) MCR14(val, 0, c1, c11, 1)
#define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1)
#define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1)
#define WCP14_DBGBXVR14(val) MCR14(val, 0, c1, c14, 1)
#define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1)
#define WCP14_DBGOSLAR(val) MCR14(val, 0, c1, c0, 4)
#define WCP14_DBGOSSRR(val) MCR14(val, 0, c1, c2, 4)
#define WCP14_DBGOSDLR(val) MCR14(val, 0, c1, c3, 4)
#define WCP14_DBGPRCR(val) MCR14(val, 0, c1, c4, 4)
#define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4)
#define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6)
#define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6)
/*
* ETM Registers
*
* Available only in ETMv3.3, 3.4, 3.5
* ETMASICCR, ETMTECR2, ETMFFRR, ETMVDEVR, ETMVDCR1, ETMVDCR2, ETMVDCR3,
* ETMDCVRn, ETMDCMRn
*
* Available only in ETMv3.5 as read only
* ETMIDR2
*
* Available only in ETMv3.5, PFTv1.0, 1.1
* ETMTSEVR, ETMVMIDCVR, ETMPDCR
*
* Read only
* ETMCCR, ETMSCR, ETMIDR, ETMCCER, ETMOSLSR
* ETMLSR, ETMAUTHSTATUS, ETMDEVID, ETMDEVTYPE, ETMPIDR4, ETMPIDR5, ETMPIDR6,
* ETMPIDR7, ETMPIDR0, ETMPIDR1, ETMPIDR2, ETMPIDR2, ETMPIDR3, ETMCIDR0,
* ETMCIDR1, ETMCIDR2, ETMCIDR3
*
* Write only
* ETMOSLAR, ETMLAR
* Note: ETMCCER[11] controls WO nature of certain regs. Refer ETM arch spec.
*/
#define RCP14_ETMCR() MRC14(1, c0, c0, 0)
#define RCP14_ETMCCR() MRC14(1, c0, c1, 0)
#define RCP14_ETMTRIGGER() MRC14(1, c0, c2, 0)
#define RCP14_ETMASICCR() MRC14(1, c0, c3, 0)
#define RCP14_ETMSR() MRC14(1, c0, c4, 0)
#define RCP14_ETMSCR() MRC14(1, c0, c5, 0)
#define RCP14_ETMTSSCR() MRC14(1, c0, c6, 0)
#define RCP14_ETMTECR2() MRC14(1, c0, c7, 0)
#define RCP14_ETMTEEVR() MRC14(1, c0, c8, 0)
#define RCP14_ETMTECR1() MRC14(1, c0, c9, 0)
#define RCP14_ETMFFRR() MRC14(1, c0, c10, 0)
#define RCP14_ETMFFLR() MRC14(1, c0, c11, 0)
#define RCP14_ETMVDEVR() MRC14(1, c0, c12, 0)
#define RCP14_ETMVDCR1() MRC14(1, c0, c13, 0)
#define RCP14_ETMVDCR2() MRC14(1, c0, c14, 0)
#define RCP14_ETMVDCR3() MRC14(1, c0, c15, 0)
#define RCP14_ETMACVR0() MRC14(1, c0, c0, 1)
#define RCP14_ETMACVR1() MRC14(1, c0, c1, 1)
#define RCP14_ETMACVR2() MRC14(1, c0, c2, 1)
#define RCP14_ETMACVR3() MRC14(1, c0, c3, 1)
#define RCP14_ETMACVR4() MRC14(1, c0, c4, 1)
#define RCP14_ETMACVR5() MRC14(1, c0, c5, 1)
#define RCP14_ETMACVR6() MRC14(1, c0, c6, 1)
#define RCP14_ETMACVR7() MRC14(1, c0, c7, 1)
#define RCP14_ETMACVR8() MRC14(1, c0, c8, 1)
#define RCP14_ETMACVR9() MRC14(1, c0, c9, 1)
#define RCP14_ETMACVR10() MRC14(1, c0, c10, 1)
#define RCP14_ETMACVR11() MRC14(1, c0, c11, 1)
#define RCP14_ETMACVR12() MRC14(1, c0, c12, 1)
#define RCP14_ETMACVR13() MRC14(1, c0, c13, 1)
#define RCP14_ETMACVR14() MRC14(1, c0, c14, 1)
#define RCP14_ETMACVR15() MRC14(1, c0, c15, 1)
#define RCP14_ETMACTR0() MRC14(1, c0, c0, 2)
#define RCP14_ETMACTR1() MRC14(1, c0, c1, 2)
#define RCP14_ETMACTR2() MRC14(1, c0, c2, 2)
#define RCP14_ETMACTR3() MRC14(1, c0, c3, 2)
#define RCP14_ETMACTR4() MRC14(1, c0, c4, 2)
#define RCP14_ETMACTR5() MRC14(1, c0, c5, 2)
#define RCP14_ETMACTR6() MRC14(1, c0, c6, 2)
#define RCP14_ETMACTR7() MRC14(1, c0, c7, 2)
#define RCP14_ETMACTR8() MRC14(1, c0, c8, 2)
#define RCP14_ETMACTR9() MRC14(1, c0, c9, 2)
#define RCP14_ETMACTR10() MRC14(1, c0, c10, 2)
#define RCP14_ETMACTR11() MRC14(1, c0, c11, 2)
#define RCP14_ETMACTR12() MRC14(1, c0, c12, 2)
#define RCP14_ETMACTR13() MRC14(1, c0, c13, 2)
#define RCP14_ETMACTR14() MRC14(1, c0, c14, 2)
#define RCP14_ETMACTR15() MRC14(1, c0, c15, 2)
#define RCP14_ETMDCVR0() MRC14(1, c0, c0, 3)
#define RCP14_ETMDCVR2() MRC14(1, c0, c2, 3)
#define RCP14_ETMDCVR4() MRC14(1, c0, c4, 3)
#define RCP14_ETMDCVR6() MRC14(1, c0, c6, 3)
#define RCP14_ETMDCVR8() MRC14(1, c0, c8, 3)
#define RCP14_ETMDCVR10() MRC14(1, c0, c10, 3)
#define RCP14_ETMDCVR12() MRC14(1, c0, c12, 3)
#define RCP14_ETMDCVR14() MRC14(1, c0, c14, 3)
#define RCP14_ETMDCMR0() MRC14(1, c0, c0, 4)
#define RCP14_ETMDCMR2() MRC14(1, c0, c2, 4)
#define RCP14_ETMDCMR4() MRC14(1, c0, c4, 4)
#define RCP14_ETMDCMR6() MRC14(1, c0, c6, 4)
#define RCP14_ETMDCMR8() MRC14(1, c0, c8, 4)
#define RCP14_ETMDCMR10() MRC14(1, c0, c10, 4)
#define RCP14_ETMDCMR12() MRC14(1, c0, c12, 4)
#define RCP14_ETMDCMR14() MRC14(1, c0, c14, 4)
#define RCP14_ETMCNTRLDVR0() MRC14(1, c0, c0, 5)
#define RCP14_ETMCNTRLDVR1() MRC14(1, c0, c1, 5)
#define RCP14_ETMCNTRLDVR2() MRC14(1, c0, c2, 5)
#define RCP14_ETMCNTRLDVR3() MRC14(1, c0, c3, 5)
#define RCP14_ETMCNTENR0() MRC14(1, c0, c4, 5)
#define RCP14_ETMCNTENR1() MRC14(1, c0, c5, 5)
#define RCP14_ETMCNTENR2() MRC14(1, c0, c6, 5)
#define RCP14_ETMCNTENR3() MRC14(1, c0, c7, 5)
#define RCP14_ETMCNTRLDEVR0() MRC14(1, c0, c8, 5)
#define RCP14_ETMCNTRLDEVR1() MRC14(1, c0, c9, 5)
#define RCP14_ETMCNTRLDEVR2() MRC14(1, c0, c10, 5)
#define RCP14_ETMCNTRLDEVR3() MRC14(1, c0, c11, 5)
#define RCP14_ETMCNTVR0() MRC14(1, c0, c12, 5)
#define RCP14_ETMCNTVR1() MRC14(1, c0, c13, 5)
#define RCP14_ETMCNTVR2() MRC14(1, c0, c14, 5)
#define RCP14_ETMCNTVR3() MRC14(1, c0, c15, 5)
#define RCP14_ETMSQ12EVR() MRC14(1, c0, c0, 6)
#define RCP14_ETMSQ21EVR() MRC14(1, c0, c1, 6)
#define RCP14_ETMSQ23EVR() MRC14(1, c0, c2, 6)
#define RCP14_ETMSQ31EVR() MRC14(1, c0, c3, 6)
#define RCP14_ETMSQ32EVR() MRC14(1, c0, c4, 6)
#define RCP14_ETMSQ13EVR() MRC14(1, c0, c5, 6)
#define RCP14_ETMSQR() MRC14(1, c0, c7, 6)
#define RCP14_ETMEXTOUTEVR0() MRC14(1, c0, c8, 6)
#define RCP14_ETMEXTOUTEVR1() MRC14(1, c0, c9, 6)
#define RCP14_ETMEXTOUTEVR2() MRC14(1, c0, c10, 6)
#define RCP14_ETMEXTOUTEVR3() MRC14(1, c0, c11, 6)
#define RCP14_ETMCIDCVR0() MRC14(1, c0, c12, 6)
#define RCP14_ETMCIDCVR1() MRC14(1, c0, c13, 6)
#define RCP14_ETMCIDCVR2() MRC14(1, c0, c14, 6)
#define RCP14_ETMCIDCMR() MRC14(1, c0, c15, 6)
#define RCP14_ETMIMPSPEC0() MRC14(1, c0, c0, 7)
#define RCP14_ETMIMPSPEC1() MRC14(1, c0, c1, 7)
#define RCP14_ETMIMPSPEC2() MRC14(1, c0, c2, 7)
#define RCP14_ETMIMPSPEC3() MRC14(1, c0, c3, 7)
#define RCP14_ETMIMPSPEC4() MRC14(1, c0, c4, 7)
#define RCP14_ETMIMPSPEC5() MRC14(1, c0, c5, 7)
#define RCP14_ETMIMPSPEC6() MRC14(1, c0, c6, 7)
#define RCP14_ETMIMPSPEC7() MRC14(1, c0, c7, 7)
#define RCP14_ETMSYNCFR() MRC14(1, c0, c8, 7)
#define RCP14_ETMIDR() MRC14(1, c0, c9, 7)
#define RCP14_ETMCCER() MRC14(1, c0, c10, 7)
#define RCP14_ETMEXTINSELR() MRC14(1, c0, c11, 7)
#define RCP14_ETMTESSEICR() MRC14(1, c0, c12, 7)
#define RCP14_ETMEIBCR() MRC14(1, c0, c13, 7)
#define RCP14_ETMTSEVR() MRC14(1, c0, c14, 7)
#define RCP14_ETMAUXCR() MRC14(1, c0, c15, 7)
#define RCP14_ETMTRACEIDR() MRC14(1, c1, c0, 0)
#define RCP14_ETMIDR2() MRC14(1, c1, c2, 0)
#define RCP14_ETMVMIDCVR() MRC14(1, c1, c0, 1)
#define RCP14_ETMOSLSR() MRC14(1, c1, c1, 4)
/* Not available in PFTv1.1 */
#define RCP14_ETMOSSRR() MRC14(1, c1, c2, 4)
#define RCP14_ETMPDCR() MRC14(1, c1, c4, 4)
#define RCP14_ETMPDSR() MRC14(1, c1, c5, 4)
#define RCP14_ETMITCTRL() MRC14(1, c7, c0, 4)
#define RCP14_ETMCLAIMSET() MRC14(1, c7, c8, 6)
#define RCP14_ETMCLAIMCLR() MRC14(1, c7, c9, 6)
#define RCP14_ETMLSR() MRC14(1, c7, c13, 6)
#define RCP14_ETMAUTHSTATUS() MRC14(1, c7, c14, 6)
#define RCP14_ETMDEVID() MRC14(1, c7, c2, 7)
#define RCP14_ETMDEVTYPE() MRC14(1, c7, c3, 7)
#define RCP14_ETMPIDR4() MRC14(1, c7, c4, 7)
#define RCP14_ETMPIDR5() MRC14(1, c7, c5, 7)
#define RCP14_ETMPIDR6() MRC14(1, c7, c6, 7)
#define RCP14_ETMPIDR7() MRC14(1, c7, c7, 7)
#define RCP14_ETMPIDR0() MRC14(1, c7, c8, 7)
#define RCP14_ETMPIDR1() MRC14(1, c7, c9, 7)
#define RCP14_ETMPIDR2() MRC14(1, c7, c10, 7)
#define RCP14_ETMPIDR3() MRC14(1, c7, c11, 7)
#define RCP14_ETMCIDR0() MRC14(1, c7, c12, 7)
#define RCP14_ETMCIDR1() MRC14(1, c7, c13, 7)
#define RCP14_ETMCIDR2() MRC14(1, c7, c14, 7)
#define RCP14_ETMCIDR3() MRC14(1, c7, c15, 7)
#define WCP14_ETMCR(val) MCR14(val, 1, c0, c0, 0)
#define WCP14_ETMTRIGGER(val) MCR14(val, 1, c0, c2, 0)
#define WCP14_ETMASICCR(val) MCR14(val, 1, c0, c3, 0)
#define WCP14_ETMSR(val) MCR14(val, 1, c0, c4, 0)
#define WCP14_ETMTSSCR(val) MCR14(val, 1, c0, c6, 0)
#define WCP14_ETMTECR2(val) MCR14(val, 1, c0, c7, 0)
#define WCP14_ETMTEEVR(val) MCR14(val, 1, c0, c8, 0)
#define WCP14_ETMTECR1(val) MCR14(val, 1, c0, c9, 0)
#define WCP14_ETMFFRR(val) MCR14(val, 1, c0, c10, 0)
#define WCP14_ETMFFLR(val) MCR14(val, 1, c0, c11, 0)
#define WCP14_ETMVDEVR(val) MCR14(val, 1, c0, c12, 0)
#define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0)
#define WCP14_ETMVDCR2(val) MCR14(val, 1, c0, c14, 0)
#define WCP14_ETMVDCR3(val) MCR14(val, 1, c0, c15, 0)
#define WCP14_ETMACVR0(val) MCR14(val, 1, c0, c0, 1)
#define WCP14_ETMACVR1(val) MCR14(val, 1, c0, c1, 1)
#define WCP14_ETMACVR2(val) MCR14(val, 1, c0, c2, 1)
#define WCP14_ETMACVR3(val) MCR14(val, 1, c0, c3, 1)
#define WCP14_ETMACVR4(val) MCR14(val, 1, c0, c4, 1)
#define WCP14_ETMACVR5(val) MCR14(val, 1, c0, c5, 1)
#define WCP14_ETMACVR6(val) MCR14(val, 1, c0, c6, 1)
#define WCP14_ETMACVR7(val) MCR14(val, 1, c0, c7, 1)
#define WCP14_ETMACVR8(val) MCR14(val, 1, c0, c8, 1)
#define WCP14_ETMACVR9(val) MCR14(val, 1, c0, c9, 1)
#define WCP14_ETMACVR10(val) MCR14(val, 1, c0, c10, 1)
#define WCP14_ETMACVR11(val) MCR14(val, 1, c0, c11, 1)
#define WCP14_ETMACVR12(val) MCR14(val, 1, c0, c12, 1)
#define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1)
#define WCP14_ETMACVR14(val) MCR14(val, 1, c0, c14, 1)
#define WCP14_ETMACVR15(val) MCR14(val, 1, c0, c15, 1)
#define WCP14_ETMACTR0(val) MCR14(val, 1, c0, c0, 2)
#define WCP14_ETMACTR1(val) MCR14(val, 1, c0, c1, 2)
#define WCP14_ETMACTR2(val) MCR14(val, 1, c0, c2, 2)
#define WCP14_ETMACTR3(val) MCR14(val, 1, c0, c3, 2)
#define WCP14_ETMACTR4(val) MCR14(val, 1, c0, c4, 2)
#define WCP14_ETMACTR5(val) MCR14(val, 1, c0, c5, 2)
#define WCP14_ETMACTR6(val) MCR14(val, 1, c0, c6, 2)
#define WCP14_ETMACTR7(val) MCR14(val, 1, c0, c7, 2)
#define WCP14_ETMACTR8(val) MCR14(val, 1, c0, c8, 2)
#define WCP14_ETMACTR9(val) MCR14(val, 1, c0, c9, 2)
#define WCP14_ETMACTR10(val) MCR14(val, 1, c0, c10, 2)
#define WCP14_ETMACTR11(val) MCR14(val, 1, c0, c11, 2)
#define WCP14_ETMACTR12(val) MCR14(val, 1, c0, c12, 2)
#define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2)
#define WCP14_ETMACTR14(val) MCR14(val, 1, c0, c14, 2)
#define WCP14_ETMACTR15(val) MCR14(val, 1, c0, c15, 2)
#define WCP14_ETMDCVR0(val) MCR14(val, 1, c0, c0, 3)
#define WCP14_ETMDCVR2(val) MCR14(val, 1, c0, c2, 3)
#define WCP14_ETMDCVR4(val) MCR14(val, 1, c0, c4, 3)
#define WCP14_ETMDCVR6(val) MCR14(val, 1, c0, c6, 3)
#define WCP14_ETMDCVR8(val) MCR14(val, 1, c0, c8, 3)
#define WCP14_ETMDCVR10(val) MCR14(val, 1, c0, c10, 3)
#define WCP14_ETMDCVR12(val) MCR14(val, 1, c0, c12, 3)
#define WCP14_ETMDCVR14(val) MCR14(val, 1, c0, c14, 3)
#define WCP14_ETMDCMR0(val) MCR14(val, 1, c0, c0, 4)
#define WCP14_ETMDCMR2(val) MCR14(val, 1, c0, c2, 4)
#define WCP14_ETMDCMR4(val) MCR14(val, 1, c0, c4, 4)
#define WCP14_ETMDCMR6(val) MCR14(val, 1, c0, c6, 4)
#define WCP14_ETMDCMR8(val) MCR14(val, 1, c0, c8, 4)
#define WCP14_ETMDCMR10(val) MCR14(val, 1, c0, c10, 4)
#define WCP14_ETMDCMR12(val) MCR14(val, 1, c0, c12, 4)
#define WCP14_ETMDCMR14(val) MCR14(val, 1, c0, c14, 4)
#define WCP14_ETMCNTRLDVR0(val) MCR14(val, 1, c0, c0, 5)
#define WCP14_ETMCNTRLDVR1(val) MCR14(val, 1, c0, c1, 5)
#define WCP14_ETMCNTRLDVR2(val) MCR14(val, 1, c0, c2, 5)
#define WCP14_ETMCNTRLDVR3(val) MCR14(val, 1, c0, c3, 5)
#define WCP14_ETMCNTENR0(val) MCR14(val, 1, c0, c4, 5)
#define WCP14_ETMCNTENR1(val) MCR14(val, 1, c0, c5, 5)
#define WCP14_ETMCNTENR2(val) MCR14(val, 1, c0, c6, 5)
#define WCP14_ETMCNTENR3(val) MCR14(val, 1, c0, c7, 5)
#define WCP14_ETMCNTRLDEVR0(val) MCR14(val, 1, c0, c8, 5)
#define WCP14_ETMCNTRLDEVR1(val) MCR14(val, 1, c0, c9, 5)
#define WCP14_ETMCNTRLDEVR2(val) MCR14(val, 1, c0, c10, 5)
#define WCP14_ETMCNTRLDEVR3(val) MCR14(val, 1, c0, c11, 5)
#define WCP14_ETMCNTVR0(val) MCR14(val, 1, c0, c12, 5)
#define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5)
#define WCP14_ETMCNTVR2(val) MCR14(val, 1, c0, c14, 5)
#define WCP14_ETMCNTVR3(val) MCR14(val, 1, c0, c15, 5)
#define WCP14_ETMSQ12EVR(val) MCR14(val, 1, c0, c0, 6)
#define WCP14_ETMSQ21EVR(val) MCR14(val, 1, c0, c1, 6)
#define WCP14_ETMSQ23EVR(val) MCR14(val, 1, c0, c2, 6)
#define WCP14_ETMSQ31EVR(val) MCR14(val, 1, c0, c3, 6)
#define WCP14_ETMSQ32EVR(val) MCR14(val, 1, c0, c4, 6)
#define WCP14_ETMSQ13EVR(val) MCR14(val, 1, c0, c5, 6)
#define WCP14_ETMSQR(val) MCR14(val, 1, c0, c7, 6)
#define WCP14_ETMEXTOUTEVR0(val) MCR14(val, 1, c0, c8, 6)
#define WCP14_ETMEXTOUTEVR1(val) MCR14(val, 1, c0, c9, 6)
#define WCP14_ETMEXTOUTEVR2(val) MCR14(val, 1, c0, c10, 6)
#define WCP14_ETMEXTOUTEVR3(val) MCR14(val, 1, c0, c11, 6)
#define WCP14_ETMCIDCVR0(val) MCR14(val, 1, c0, c12, 6)
#define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6)
#define WCP14_ETMCIDCVR2(val) MCR14(val, 1, c0, c14, 6)
#define WCP14_ETMCIDCMR(val) MCR14(val, 1, c0, c15, 6)
#define WCP14_ETMIMPSPEC0(val) MCR14(val, 1, c0, c0, 7)
#define WCP14_ETMIMPSPEC1(val) MCR14(val, 1, c0, c1, 7)
#define WCP14_ETMIMPSPEC2(val) MCR14(val, 1, c0, c2, 7)
#define WCP14_ETMIMPSPEC3(val) MCR14(val, 1, c0, c3, 7)
#define WCP14_ETMIMPSPEC4(val) MCR14(val, 1, c0, c4, 7)
#define WCP14_ETMIMPSPEC5(val) MCR14(val, 1, c0, c5, 7)
#define WCP14_ETMIMPSPEC6(val) MCR14(val, 1, c0, c6, 7)
#define WCP14_ETMIMPSPEC7(val) MCR14(val, 1, c0, c7, 7)
/* Can be read only in ETMv3.4, ETMv3.5 */
#define WCP14_ETMSYNCFR(val) MCR14(val, 1, c0, c8, 7)
#define WCP14_ETMEXTINSELR(val) MCR14(val, 1, c0, c11, 7)
#define WCP14_ETMTESSEICR(val) MCR14(val, 1, c0, c12, 7)
#define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7)
#define WCP14_ETMTSEVR(val) MCR14(val, 1, c0, c14, 7)
#define WCP14_ETMAUXCR(val) MCR14(val, 1, c0, c15, 7)
#define WCP14_ETMTRACEIDR(val) MCR14(val, 1, c1, c0, 0)
#define WCP14_ETMIDR2(val) MCR14(val, 1, c1, c2, 0)
#define WCP14_ETMVMIDCVR(val) MCR14(val, 1, c1, c0, 1)
#define WCP14_ETMOSLAR(val) MCR14(val, 1, c1, c0, 4)
/* Not available in PFTv1.1 */
#define WCP14_ETMOSSRR(val) MCR14(val, 1, c1, c2, 4)
#define WCP14_ETMPDCR(val) MCR14(val, 1, c1, c4, 4)
#define WCP14_ETMPDSR(val) MCR14(val, 1, c1, c5, 4)
#define WCP14_ETMITCTRL(val) MCR14(val, 1, c7, c0, 4)
#define WCP14_ETMCLAIMSET(val) MCR14(val, 1, c7, c8, 6)
#define WCP14_ETMCLAIMCLR(val) MCR14(val, 1, c7, c9, 6)
/* Writes to this from CP14 interface are ignored */
#define WCP14_ETMLAR(val) MCR14(val, 1, c7, c12, 6)
#endif
linux-7.2.3/arch/arm/include/asm/hardware/dec21285.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/dec21285.h
*
* Copyright (C) 1998 Russell King
*
* DC21285 registers
*/
#define DC21285_PCI_IACK 0x79000000
#define DC21285_ARMCSR_BASE 0x42000000
#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
#define DC21285_FLASH 0x41000000
#define DC21285_PCI_IO 0x7c000000
#define DC21285_PCI_MEM 0x80000000
#ifndef __ASSEMBLY__
#include <mach/hardware.h>
#define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))
#else
#define DC21285_IO(x) (x)
#endif
/*
* The footbridge is programmed to expose the system RAM at 0xe0000000.
* The requirement is that the RAM isn't placed at bus address 0, which
* would clash with VGA cards.
*/
#define BUS_OFFSET 0xe0000000
#define CSR_PCICMD DC21285_IO(0x0004)
#define CSR_CLASSREV DC21285_IO(0x0008)
#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
#define CSR_PCICSRBASE DC21285_IO(0x0010)
#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
#define CSR_PCIROMBASE DC21285_IO(0x0030)
#define CSR_MBOX0 DC21285_IO(0x0050)
#define CSR_MBOX1 DC21285_IO(0x0054)
#define CSR_MBOX2 DC21285_IO(0x0058)
#define CSR_MBOX3 DC21285_IO(0x005c)
#define CSR_DOORBELL DC21285_IO(0x0060)
#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)
#define CSR_ROMWRITEREG DC21285_IO(0x0068)
#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
#define CSR_ROMBASEMASK DC21285_IO(0x0108)
#define CSR_SDRAMTIMING DC21285_IO(0x010c)
#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
#define CSR_SA110_CNTL DC21285_IO(0x013c)
#define SA110_CNTL_INITCMPLETE (1 << 0)
#define SA110_CNTL_ASSERTSERR (1 << 1)
#define SA110_CNTL_RXSERR (1 << 3)
#define SA110_CNTL_SA110DRAMPARITY (1 << 4)
#define SA110_CNTL_PCISDRAMPARITY (1 << 5)
#define SA110_CNTL_DMASDRAMPARITY (1 << 6)
#define SA110_CNTL_DISCARDTIMER (1 << 8)
#define SA110_CNTL_PCINRESET (1 << 9)
#define SA110_CNTL_I2O_256 (0 << 10)
#define SA110_CNTL_I20_512 (1 << 10)
#define SA110_CNTL_I2O_1024 (2 << 10)
#define SA110_CNTL_I2O_2048 (3 << 10)
#define SA110_CNTL_I2O_4096 (4 << 10)
#define SA110_CNTL_I2O_8192 (5 << 10)
#define SA110_CNTL_I2O_16384 (6 << 10)
#define SA110_CNTL_I2O_32768 (7 << 10)
#define SA110_CNTL_WATCHDOG (1 << 13)
#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)
#define SA110_CNTL_ROMWIDTH_16 (1 << 14)
#define SA110_CNTL_ROMWIDTH_32 (2 << 14)
#define SA110_CNTL_ROMWIDTH_8 (3 << 14)
#define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
#define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)
#define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)
#define SA110_CNTL_XCSDIR(x) ((x)<<28)
#define SA110_CNTL_PCICFN (1 << 31)
#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
#define CSR_UARTDR DC21285_IO(0x0160)
#define CSR_RXSTAT DC21285_IO(0x0164)
#define CSR_H_UBRLCR DC21285_IO(0x0168)
#define CSR_M_UBRLCR DC21285_IO(0x016c)
#define CSR_L_UBRLCR DC21285_IO(0x0170)
#define CSR_UARTCON DC21285_IO(0x0174)
#define CSR_UARTFLG DC21285_IO(0x0178)
#define CSR_IRQ_STATUS DC21285_IO(0x0180)
#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
#define CSR_IRQ_SOFT DC21285_IO(0x0190)
#define CSR_FIQ_STATUS DC21285_IO(0x0280)
#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
#define CSR_FIQ_SOFT DC21285_IO(0x0290)
#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
#define CSR_TIMER1_CLR DC21285_IO(0x030c)
#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
#define CSR_TIMER2_CLR DC21285_IO(0x032c)
#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
#define CSR_TIMER3_CLR DC21285_IO(0x034c)
#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
#define CSR_TIMER4_CLR DC21285_IO(0x036c)
#define TIMER_CNTL_ENABLE (1 << 7)
#define TIMER_CNTL_AUTORELOAD (1 << 6)
#define TIMER_CNTL_DIV1 (0)
#define TIMER_CNTL_DIV16 (1 << 2)
#define TIMER_CNTL_DIV256 (2 << 2)
#define TIMER_CNTL_CNTEXT (3 << 2)
linux-7.2.3/arch/arm/include/asm/hardware/ioc.h
+69
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/ioc.h
*
* Copyright (C) Russell King
*
* Use these macros to read/write the IOC. All it does is perform the actual
* read/write.
*/
#ifndef __ASMARM_HARDWARE_IOC_H
#define __ASMARM_HARDWARE_IOC_H
#ifndef __ASSEMBLY__
/*
* We use __raw_base variants here so that we give the compiler the
* chance to keep IOC_BASE in a register.
*/
#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
#endif
#define IOC_CONTROL (0x00)
#define IOC_KARTTX (0x04)
#define IOC_KARTRX (0x04)
#define IOC_IRQSTATA (0x10)
#define IOC_IRQREQA (0x14)
#define IOC_IRQCLRA (0x14)
#define IOC_IRQMASKA (0x18)
#define IOC_IRQSTATB (0x20)
#define IOC_IRQREQB (0x24)
#define IOC_IRQMASKB (0x28)
#define IOC_FIQSTAT (0x30)
#define IOC_FIQREQ (0x34)
#define IOC_FIQMASK (0x38)
#define IOC_T0CNTL (0x40)
#define IOC_T0LTCHL (0x40)
#define IOC_T0CNTH (0x44)
#define IOC_T0LTCHH (0x44)
#define IOC_T0GO (0x48)
#define IOC_T0LATCH (0x4c)
#define IOC_T1CNTL (0x50)
#define IOC_T1LTCHL (0x50)
#define IOC_T1CNTH (0x54)
#define IOC_T1LTCHH (0x54)
#define IOC_T1GO (0x58)
#define IOC_T1LATCH (0x5c)
#define IOC_T2CNTL (0x60)
#define IOC_T2LTCHL (0x60)
#define IOC_T2CNTH (0x64)
#define IOC_T2LTCHH (0x64)
#define IOC_T2GO (0x68)
#define IOC_T2LATCH (0x6c)
#define IOC_T3CNTL (0x70)
#define IOC_T3LTCHL (0x70)
#define IOC_T3CNTH (0x74)
#define IOC_T3LTCHH (0x74)
#define IOC_T3GO (0x78)
#define IOC_T3LATCH (0x7c)
#endif
linux-7.2.3/arch/arm/include/asm/hardware/iomd.h
+182
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/iomd.h
*
* Copyright (C) 1999 Russell King
*
* This file contains information out the IOMD ASIC used in the
* Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
*/
#ifndef __ASMARM_HARDWARE_IOMD_H
#define __ASMARM_HARDWARE_IOMD_H
#ifndef __ASSEMBLY__
/*
* We use __raw_base variants here so that we give the compiler the
* chance to keep IOC_BASE in a register.
*/
#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
#endif
#define IOMD_CONTROL (0x000)
#define IOMD_KARTTX (0x004)
#define IOMD_KARTRX (0x004)
#define IOMD_KCTRL (0x008)
#define IOMD_IRQSTATA (0x010)
#define IOMD_IRQREQA (0x014)
#define IOMD_IRQCLRA (0x014)
#define IOMD_IRQMASKA (0x018)
#define IOMD_IRQSTATB (0x020)
#define IOMD_IRQREQB (0x024)
#define IOMD_IRQMASKB (0x028)
#define IOMD_FIQSTAT (0x030)
#define IOMD_FIQREQ (0x034)
#define IOMD_FIQMASK (0x038)
#define IOMD_T0CNTL (0x040)
#define IOMD_T0LTCHL (0x040)
#define IOMD_T0CNTH (0x044)
#define IOMD_T0LTCHH (0x044)
#define IOMD_T0GO (0x048)
#define IOMD_T0LATCH (0x04c)
#define IOMD_T1CNTL (0x050)
#define IOMD_T1LTCHL (0x050)
#define IOMD_T1CNTH (0x054)
#define IOMD_T1LTCHH (0x054)
#define IOMD_T1GO (0x058)
#define IOMD_T1LATCH (0x05c)
#define IOMD_ROMCR0 (0x080)
#define IOMD_ROMCR1 (0x084)
#ifdef CONFIG_ARCH_RPC
#define IOMD_DRAMCR (0x088)
#endif
#define IOMD_REFCR (0x08C)
#define IOMD_FSIZE (0x090)
#define IOMD_ID0 (0x094)
#define IOMD_ID1 (0x098)
#define IOMD_VERSION (0x09C)
#ifdef CONFIG_ARCH_RPC
#define IOMD_MOUSEX (0x0A0)
#define IOMD_MOUSEY (0x0A4)
#endif
#ifdef CONFIG_ARCH_RPC
#define IOMD_DMATCR (0x0C0)
#endif
#define IOMD_IOTCR (0x0C4)
#define IOMD_ECTCR (0x0C8)
#ifdef CONFIG_ARCH_RPC
#define IOMD_DMAEXT (0x0CC)
#endif
#ifdef CONFIG_ARCH_RPC
#define DMA_EXT_IO0 1
#define DMA_EXT_IO1 2
#define DMA_EXT_IO2 4
#define DMA_EXT_IO3 8
#define IOMD_IO0CURA (0x100)
#define IOMD_IO0ENDA (0x104)
#define IOMD_IO0CURB (0x108)
#define IOMD_IO0ENDB (0x10C)
#define IOMD_IO0CR (0x110)
#define IOMD_IO0ST (0x114)
#define IOMD_IO1CURA (0x120)
#define IOMD_IO1ENDA (0x124)
#define IOMD_IO1CURB (0x128)
#define IOMD_IO1ENDB (0x12C)
#define IOMD_IO1CR (0x130)
#define IOMD_IO1ST (0x134)
#define IOMD_IO2CURA (0x140)
#define IOMD_IO2ENDA (0x144)
#define IOMD_IO2CURB (0x148)
#define IOMD_IO2ENDB (0x14C)
#define IOMD_IO2CR (0x150)
#define IOMD_IO2ST (0x154)
#define IOMD_IO3CURA (0x160)
#define IOMD_IO3ENDA (0x164)
#define IOMD_IO3CURB (0x168)
#define IOMD_IO3ENDB (0x16C)
#define IOMD_IO3CR (0x170)
#define IOMD_IO3ST (0x174)
#endif
#define IOMD_SD0CURA (0x180)
#define IOMD_SD0ENDA (0x184)
#define IOMD_SD0CURB (0x188)
#define IOMD_SD0ENDB (0x18C)
#define IOMD_SD0CR (0x190)
#define IOMD_SD0ST (0x194)
#ifdef CONFIG_ARCH_RPC
#define IOMD_SD1CURA (0x1A0)
#define IOMD_SD1ENDA (0x1A4)
#define IOMD_SD1CURB (0x1A8)
#define IOMD_SD1ENDB (0x1AC)
#define IOMD_SD1CR (0x1B0)
#define IOMD_SD1ST (0x1B4)
#endif
#define IOMD_CURSCUR (0x1C0)
#define IOMD_CURSINIT (0x1C4)
#define IOMD_VIDCUR (0x1D0)
#define IOMD_VIDEND (0x1D4)
#define IOMD_VIDSTART (0x1D8)
#define IOMD_VIDINIT (0x1DC)
#define IOMD_VIDCR (0x1E0)
#define IOMD_DMASTAT (0x1F0)
#define IOMD_DMAREQ (0x1F4)
#define IOMD_DMAMASK (0x1F8)
#define DMA_END_S (1 << 31)
#define DMA_END_L (1 << 30)
#define DMA_CR_C 0x80
#define DMA_CR_D 0x40
#define DMA_CR_E 0x20
#define DMA_ST_OFL 4
#define DMA_ST_INT 2
#define DMA_ST_AB 1
/*
* DMA (MEMC) compatibility
*/
#define HALF_SAM vram_half_sam
#define VDMA_ALIGNMENT (HALF_SAM * 2)
#define VDMA_XFERSIZE (HALF_SAM)
#define VDMA_INIT IOMD_VIDINIT
#define VDMA_START IOMD_VIDSTART
#define VDMA_END IOMD_VIDEND
#ifndef __ASSEMBLY__
extern unsigned int vram_half_sam;
#define video_set_dma(start,end,offset) \
do { \
outl (SCREEN_START + start, VDMA_START); \
outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
if (offset >= end - VDMA_XFERSIZE) \
offset |= 0x40000000; \
outl (SCREEN_START + offset, VDMA_INIT); \
} while (0)
#endif
#endif
linux-7.2.3/arch/arm/include/asm/hardware/locomo.h
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/*
* arch/arm/include/asm/hardware/locomo.h
*
* This file contains the definitions for the LoCoMo G/A Chip
*
* (C) Copyright 2004 John Lenz
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Based on sa1111.h
*/
#ifndef _ASM_ARCH_LOCOMO
#define _ASM_ARCH_LOCOMO
#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
#define locomo_readl(addr) (*(volatile u16 *)(addr))
/* LOCOMO version */
#define LOCOMO_VER 0x00
/* Pin status */
#define LOCOMO_ST 0x04
/* Pin status */
#define LOCOMO_C32K 0x08
/* Interrupt controller */
#define LOCOMO_ICR 0x0C
/* MCS decoder for boot selecting */
#define LOCOMO_MCSX0 0x10
#define LOCOMO_MCSX1 0x14
#define LOCOMO_MCSX2 0x18
#define LOCOMO_MCSX3 0x1c
/* Touch panel controller */
#define LOCOMO_ASD 0x20 /* AD start delay */
#define LOCOMO_HSD 0x28 /* HSYS delay */
#define LOCOMO_HSC 0x2c /* HSYS period */
#define LOCOMO_TADC 0x30 /* tablet ADC clock */
/* Long time timer */
#define LOCOMO_LTC 0xd8 /* LTC interrupt setting */
#define LOCOMO_LTINT 0xdc /* LTC interrupt */
/* DAC control signal for LCD (COMADJ ) */
#define LOCOMO_DAC 0xe0
/* DAC control */
#define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */
#define LOCOMO_DAC_TEST 0x04 /* Test bit */
#define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
/* SPI interface */
#define LOCOMO_SPI 0x60
#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
#define LOCOMO_SPICT 0x04 /* SPI mode control */
#define LOCOMO_SPIST 0x08 /* SPI status */
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
#define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
#define LOCOMO_SPI_RFR (1) /* read buffer bit */
#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */
#define LOCOMO_SPITD 0x20 /* SPI transfer data write */
#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
/* GPIO */
#define LOCOMO_GPD 0x90 /* GPIO direction */
#define LOCOMO_GPE 0x94 /* GPIO input enable */
#define LOCOMO_GPL 0x98 /* GPIO level */
#define LOCOMO_GPO 0x9c /* GPIO out data setting */
#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
#define LOCOMO_GWE 0xac /* GPIO status write enable */
#define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
#define LOCOMO_GIR 0xb4 /* GPIO interrupt request */
#define LOCOMO_GPIO(Nb) (0x01 << (Nb))
#define LOCOMO_GPIO_RTS LOCOMO_GPIO(0)
#define LOCOMO_GPIO_CTS LOCOMO_GPIO(1)
#define LOCOMO_GPIO_DSR LOCOMO_GPIO(2)
#define LOCOMO_GPIO_DTR LOCOMO_GPIO(3)
#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
#define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6)
#define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7)
#define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8)
#define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9)
#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
#define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14)
#define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15)
/* Start the definitions of the devices. Each device has an initial
* base address and a series of offsets from that base address. */
/* Keyboard controller */
#define LOCOMO_KEYBOARD 0x40
#define LOCOMO_KIB 0x00 /* KIB level */
#define LOCOMO_KSC 0x04 /* KSTRB control */
#define LOCOMO_KCMD 0x08 /* KSTRB command */
#define LOCOMO_KIC 0x0c /* Key interrupt */
/* Front light adjustment controller */
#define LOCOMO_FRONTLIGHT 0xc8
#define LOCOMO_ALS 0x00 /* Adjust light cycle */
#define LOCOMO_ALD 0x04 /* Adjust light duty */
#define LOCOMO_ALC_EN 0x8000
/* Backlight controller: TFT signal */
#define LOCOMO_BACKLIGHT 0x38
#define LOCOMO_TC 0x00 /* TFT control signal */
#define LOCOMO_CPSD 0x04 /* CPS delay */
/* Audio controller */
#define LOCOMO_AUDIO 0x54
#define LOCOMO_ACC 0x00 /* Audio clock */
#define LOCOMO_PAIF 0xD0 /* PCM audio interface */
/* Audio clock */
#define LOCOMO_ACC_XON 0x80
#define LOCOMO_ACC_XEN 0x40
#define LOCOMO_ACC_XSEL0 0x00
#define LOCOMO_ACC_XSEL1 0x20
#define LOCOMO_ACC_MCLKEN 0x10
#define LOCOMO_ACC_64FSEN 0x08
#define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
#define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */
#define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */
#define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */
#define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */
#define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */
/* PCM audio interface */
#define LOCOMO_PAIF_SCINV 0x20
#define LOCOMO_PAIF_SCEN 0x10
#define LOCOMO_PAIF_LRCRST 0x08
#define LOCOMO_PAIF_LRCEVE 0x04
#define LOCOMO_PAIF_LRCINV 0x02
#define LOCOMO_PAIF_LRCEN 0x01
/* LED controller */
#define LOCOMO_LED 0xe8
#define LOCOMO_LPT0 0x00
#define LOCOMO_LPT1 0x04
/* LED control */
#define LOCOMO_LPT_TOFH 0x80
#define LOCOMO_LPT_TOFL 0x08
#define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4)
#define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7))
#define LOCOMO_DEVID_KEYBOARD 0
#define LOCOMO_DEVID_FRONTLIGHT 1
#define LOCOMO_DEVID_BACKLIGHT 2
#define LOCOMO_DEVID_AUDIO 3
#define LOCOMO_DEVID_LED 4
#define LOCOMO_DEVID_UART 5
#define LOCOMO_DEVID_SPI 6
struct locomo_dev {
struct device dev;
unsigned int devid;
unsigned int irq[1];
void *mapbase;
unsigned long length;
u64 dma_mask;
};
#define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev)
#define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev)
#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
struct locomo_driver {
struct device_driver drv;
unsigned int devid;
int (*probe)(struct locomo_dev *);
void (*remove)(struct locomo_dev *);
};
#define LOCOMO_DRV(_d) container_of_const((_d), struct locomo_driver, drv)
#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
extern void locomolcd_power(int on);
int locomo_driver_register(struct locomo_driver *);
void locomo_driver_unregister(struct locomo_driver *);
/* GPIO control functions */
void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
int locomo_gpio_read_level(struct device *dev, unsigned int bits);
int locomo_gpio_read_output(struct device *dev, unsigned int bits);
void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
/* M62332 control function */
void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
/* Frontlight control */
void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf);
struct locomo_platform_data {
int irq_base; /* IRQ base for cascaded on-chip IRQs */
};
#endif
linux-7.2.3/arch/arm/include/asm/hardware/memc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/memc.h
*
* Copyright (C) Russell King.
*/
#define VDMA_ALIGNMENT PAGE_SIZE
#define VDMA_XFERSIZE 16
#define VDMA_INIT 0
#define VDMA_START 1
#define VDMA_END 2
#ifndef __ASSEMBLY__
extern void memc_write(unsigned int reg, unsigned long val);
#define video_set_dma(start,end,offset) \
do { \
memc_write (VDMA_START, (start >> 2)); \
memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
memc_write (VDMA_INIT, (offset >> 2)); \
} while (0)
#endif
linux-7.2.3/arch/arm/include/asm/hardware/sa1111.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/hardware/sa1111.h
*
* Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
*
* This file contains definitions for the SA-1111 Companion Chip.
* (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
*
* Macro that calculates real address for registers in the SA-1111
*/
#ifndef _ASM_ARCH_SA1111
#define _ASM_ARCH_SA1111
/*
* Don't ask the (SAC) DMA engines to move less than this amount.
*/
#define SA1111_SAC_DMA_MIN_XFER (0x800)
/*
* System Bus Interface (SBI)
*
* Registers
* SKCR Control Register
* SMCR Shared Memory Controller Register
* SKID ID Register
*/
#define SA1111_SKCR 0x0000
#define SA1111_SMCR 0x0004
#define SA1111_SKID 0x0008
#define SKCR_PLL_BYPASS (1<<0)
#define SKCR_RCLKEN (1<<1)
#define SKCR_SLEEP (1<<2)
#define SKCR_DOZE (1<<3)
#define SKCR_VCO_OFF (1<<4)
#define SKCR_SCANTSTEN (1<<5)
#define SKCR_CLKTSTEN (1<<6)
#define SKCR_RDYEN (1<<7)
#define SKCR_SELAC (1<<8)
#define SKCR_OPPC (1<<9)
#define SKCR_PLLTSTEN (1<<10)
#define SKCR_USBIOTSTEN (1<<11)
/*
* Don't believe the specs! Take them, throw them outside. Leave them
* there for a week. Spit on them. Walk on them. Stamp on them.
* Pour gasoline over them and finally burn them. Now think about coding.
* - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
* - The Feb 2001 errata (278260-010) says that the previous errata
* (278260-009) is wrong, and its bit actually 12, fixed in spec
* 278242-003.
* - The SA1111 manual (278242) says bit 12, but 0 to enable.
* - Reality is bit 13, 1 to enable.
* -- rmk
*/
#define SKCR_OE_EN (1<<13)
#define SMCR_DTIM (1<<0)
#define SMCR_MBGE (1<<1)
#define SMCR_DRAC_0 (1<<2)
#define SMCR_DRAC_1 (1<<3)
#define SMCR_DRAC_2 (1<<4)
#define SMCR_DRAC Fld(3, 2)
#define SMCR_CLAT (1<<5)
#define SKID_SIREV_MASK (0x000000f0)
#define SKID_MTREV_MASK (0x0000000f)
#define SKID_ID_MASK (0xffffff00)
#define SKID_SA1111_ID (0x690cc200)
/*
* System Controller
*
* Registers
* SKPCR Power Control Register
* SKCDR Clock Divider Register
* SKAUD Audio Clock Divider Register
* SKPMC PS/2 Mouse Clock Divider Register
* SKPTC PS/2 Track Pad Clock Divider Register
* SKPEN0 PWM0 Enable Register
* SKPWM0 PWM0 Clock Register
* SKPEN1 PWM1 Enable Register
* SKPWM1 PWM1 Clock Register
*/
#define SA1111_SKPCR 0x0200
#define SA1111_SKCDR 0x0204
#define SA1111_SKAUD 0x0208
#define SA1111_SKPMC 0x020c
#define SA1111_SKPTC 0x0210
#define SA1111_SKPEN0 0x0214
#define SA1111_SKPWM0 0x0218
#define SA1111_SKPEN1 0x021c
#define SA1111_SKPWM1 0x0220
#define SKPCR_UCLKEN (1<<0)
#define SKPCR_ACCLKEN (1<<1)
#define SKPCR_I2SCLKEN (1<<2)
#define SKPCR_L3CLKEN (1<<3)
#define SKPCR_SCLKEN (1<<4)
#define SKPCR_PMCLKEN (1<<5)
#define SKPCR_PTCLKEN (1<<6)
#define SKPCR_DCLKEN (1<<7)
#define SKPCR_PWMCLKEN (1<<8)
/* USB Host controller */
#define SA1111_USB 0x0400
/*
* Serial Audio Controller
*
* Registers
* SACR0 Serial Audio Common Control Register
* SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
* SACR2 Serial Audio AC-link Control Register
* SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
* SASR1 Serial Audio AC-link Interface & FIFO Status Register
* SASCR Serial Audio Status Clear Register
* L3_CAR L3 Control Bus Address Register
* L3_CDR L3 Control Bus Data Register
* ACCAR AC-link Command Address Register
* ACCDR AC-link Command Data Register
* ACSAR AC-link Status Address Register
* ACSDR AC-link Status Data Register
* SADTCS Serial Audio DMA Transmit Control/Status Register
* SADTSA Serial Audio DMA Transmit Buffer Start Address A
* SADTCA Serial Audio DMA Transmit Buffer Count Register A
* SADTSB Serial Audio DMA Transmit Buffer Start Address B
* SADTCB Serial Audio DMA Transmit Buffer Count Register B
* SADRCS Serial Audio DMA Receive Control/Status Register
* SADRSA Serial Audio DMA Receive Buffer Start Address A
* SADRCA Serial Audio DMA Receive Buffer Count Register A
* SADRSB Serial Audio DMA Receive Buffer Start Address B
* SADRCB Serial Audio DMA Receive Buffer Count Register B
* SAITR Serial Audio Interrupt Test Register
* SADR Serial Audio Data Register (16 x 32-bit)
*/
#define SA1111_SERAUDIO 0x0600
/*
* These are offsets from the above base.
*/
#define SA1111_SACR0 0x00
#define SA1111_SACR1 0x04
#define SA1111_SACR2 0x08
#define SA1111_SASR0 0x0c
#define SA1111_SASR1 0x10
#define SA1111_SASCR 0x18
#define SA1111_L3_CAR 0x1c
#define SA1111_L3_CDR 0x20
#define SA1111_ACCAR 0x24
#define SA1111_ACCDR 0x28
#define SA1111_ACSAR 0x2c
#define SA1111_ACSDR 0x30
#define SA1111_SADTCS 0x34
#define SA1111_SADTSA 0x38
#define SA1111_SADTCA 0x3c
#define SA1111_SADTSB 0x40
#define SA1111_SADTCB 0x44
#define SA1111_SADRCS 0x48
#define SA1111_SADRSA 0x4c
#define SA1111_SADRCA 0x50
#define SA1111_SADRSB 0x54
#define SA1111_SADRCB 0x58
#define SA1111_SAITR 0x5c
#define SA1111_SADR 0x80
#ifndef CONFIG_ARCH_PXA
#define SACR0_ENB (1<<0)
#define SACR0_BCKD (1<<2)
#define SACR0_RST (1<<3)
#define SACR1_AMSL (1<<0)
#define SACR1_L3EN (1<<1)
#define SACR1_L3MB (1<<2)
#define SACR1_DREC (1<<3)
#define SACR1_DRPL (1<<4)
#define SACR1_ENLBF (1<<5)
#define SACR2_TS3V (1<<0)
#define SACR2_TS4V (1<<1)
#define SACR2_WKUP (1<<2)
#define SACR2_DREC (1<<3)
#define SACR2_DRPL (1<<4)
#define SACR2_ENLBF (1<<5)
#define SACR2_RESET (1<<6)
#define SASR0_TNF (1<<0)
#define SASR0_RNE (1<<1)
#define SASR0_BSY (1<<2)
#define SASR0_TFS (1<<3)
#define SASR0_RFS (1<<4)
#define SASR0_TUR (1<<5)
#define SASR0_ROR (1<<6)
#define SASR0_L3WD (1<<16)
#define SASR0_L3RD (1<<17)
#define SASR1_TNF (1<<0)
#define SASR1_RNE (1<<1)
#define SASR1_BSY (1<<2)
#define SASR1_TFS (1<<3)
#define SASR1_RFS (1<<4)
#define SASR1_TUR (1<<5)
#define SASR1_ROR (1<<6)
#define SASR1_CADT (1<<16)
#define SASR1_SADR (1<<17)
#define SASR1_RSTO (1<<18)
#define SASR1_CLPM (1<<19)
#define SASR1_CRDY (1<<20)
#define SASR1_RS3V (1<<21)
#define SASR1_RS4V (1<<22)
#define SASCR_TUR (1<<5)
#define SASCR_ROR (1<<6)
#define SASCR_DTS (1<<16)
#define SASCR_RDD (1<<17)
#define SASCR_STO (1<<18)
#define SADTCS_TDEN (1<<0)
#define SADTCS_TDIE (1<<1)
#define SADTCS_TDBDA (1<<3)
#define SADTCS_TDSTA (1<<4)
#define SADTCS_TDBDB (1<<5)
#define SADTCS_TDSTB (1<<6)
#define SADTCS_TBIU (1<<7)
#define SADRCS_RDEN (1<<0)
#define SADRCS_RDIE (1<<1)
#define SADRCS_RDBDA (1<<3)
#define SADRCS_RDSTA (1<<4)
#define SADRCS_RDBDB (1<<5)
#define SADRCS_RDSTB (1<<6)
#define SADRCS_RBIU (1<<7)
#define SAD_CS_DEN (1<<0)
#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
#define SAD_CS_DSTA (1<<4)
#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
#define SAD_CS_DSTB (1<<6)
#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
#define SAITR_TFS (1<<0)
#define SAITR_RFS (1<<1)
#define SAITR_TUR (1<<2)
#define SAITR_ROR (1<<3)
#define SAITR_CADT (1<<4)
#define SAITR_SADR (1<<5)
#define SAITR_RSTO (1<<6)
#define SAITR_TDBDA (1<<8)
#define SAITR_TDBDB (1<<9)
#define SAITR_RDBDA (1<<10)
#define SAITR_RDBDB (1<<11)
#endif /* !CONFIG_ARCH_PXA */
/*
* General-Purpose I/O Interface
*
* Registers
* PA_DDR GPIO Block A Data Direction
* PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
* PA_SDR GPIO Block A Sleep Direction
* PA_SSR GPIO Block A Sleep State
* PB_DDR GPIO Block B Data Direction
* PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
* PB_SDR GPIO Block B Sleep Direction
* PB_SSR GPIO Block B Sleep State
* PC_DDR GPIO Block C Data Direction
* PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
* PC_SDR GPIO Block C Sleep Direction
* PC_SSR GPIO Block C Sleep State
*/
#define SA1111_GPIO 0x1000
#define SA1111_GPIO_PADDR (0x000)
#define SA1111_GPIO_PADRR (0x004)
#define SA1111_GPIO_PADWR (0x004)
#define SA1111_GPIO_PASDR (0x008)
#define SA1111_GPIO_PASSR (0x00c)
#define SA1111_GPIO_PBDDR (0x010)
#define SA1111_GPIO_PBDRR (0x014)
#define SA1111_GPIO_PBDWR (0x014)
#define SA1111_GPIO_PBSDR (0x018)
#define SA1111_GPIO_PBSSR (0x01c)
#define SA1111_GPIO_PCDDR (0x020)
#define SA1111_GPIO_PCDRR (0x024)
#define SA1111_GPIO_PCDWR (0x024)
#define SA1111_GPIO_PCSDR (0x028)
#define SA1111_GPIO_PCSSR (0x02c)
#define GPIO_A0 (1 << 0)
#define GPIO_A1 (1 << 1)
#define GPIO_A2 (1 << 2)
#define GPIO_A3 (1 << 3)
#define GPIO_B0 (1 << 8)
#define GPIO_B1 (1 << 9)
#define GPIO_B2 (1 << 10)
#define GPIO_B3 (1 << 11)
#define GPIO_B4 (1 << 12)
#define GPIO_B5 (1 << 13)
#define GPIO_B6 (1 << 14)
#define GPIO_B7 (1 << 15)
#define GPIO_C0 (1 << 16)
#define GPIO_C1 (1 << 17)
#define GPIO_C2 (1 << 18)
#define GPIO_C3 (1 << 19)
#define GPIO_C4 (1 << 20)
#define GPIO_C5 (1 << 21)
#define GPIO_C6 (1 << 22)
#define GPIO_C7 (1 << 23)
/*
* Interrupt Controller
*
* Registers
* INTTEST0 Test register 0
* INTTEST1 Test register 1
* INTEN0 Interrupt Enable register 0
* INTEN1 Interrupt Enable register 1
* INTPOL0 Interrupt Polarity selection 0
* INTPOL1 Interrupt Polarity selection 1
* INTTSTSEL Interrupt source selection
* INTSTATCLR0 Interrupt Status/Clear 0
* INTSTATCLR1 Interrupt Status/Clear 1
* INTSET0 Interrupt source set 0
* INTSET1 Interrupt source set 1
* WAKE_EN0 Wake-up source enable 0
* WAKE_EN1 Wake-up source enable 1
* WAKE_POL0 Wake-up polarity selection 0
* WAKE_POL1 Wake-up polarity selection 1
*/
#define SA1111_INTC 0x1600
/*
* These are offsets from the above base.
*/
#define SA1111_INTTEST0 0x0000
#define SA1111_INTTEST1 0x0004
#define SA1111_INTEN0 0x0008
#define SA1111_INTEN1 0x000c
#define SA1111_INTPOL0 0x0010
#define SA1111_INTPOL1 0x0014
#define SA1111_INTTSTSEL 0x0018
#define SA1111_INTSTATCLR0 0x001c
#define SA1111_INTSTATCLR1 0x0020
#define SA1111_INTSET0 0x0024
#define SA1111_INTSET1 0x0028
#define SA1111_WAKEEN0 0x002c
#define SA1111_WAKEEN1 0x0030
#define SA1111_WAKEPOL0 0x0034
#define SA1111_WAKEPOL1 0x0038
/* PS/2 Trackpad and Mouse Interfaces */
#define SA1111_KBD 0x0a00
#define SA1111_MSE 0x0c00
/* PCMCIA Interface */
#define SA1111_PCMCIA 0x1600
extern const struct bus_type sa1111_bus_type;
#define SA1111_DEVID_SBI (1 << 0)
#define SA1111_DEVID_SK (1 << 1)
#define SA1111_DEVID_USB (1 << 2)
#define SA1111_DEVID_SAC (1 << 3)
#define SA1111_DEVID_SSP (1 << 4)
#define SA1111_DEVID_PS2 (3 << 5)
#define SA1111_DEVID_PS2_KBD (1 << 5)
#define SA1111_DEVID_PS2_MSE (1 << 6)
#define SA1111_DEVID_GPIO (1 << 7)
#define SA1111_DEVID_INT (1 << 8)
#define SA1111_DEVID_PCMCIA (1 << 9)
struct sa1111_dev {
struct device dev;
unsigned int devid;
struct resource res;
void __iomem *mapbase;
unsigned int skpcr_mask;
unsigned int hwirq[6];
u64 dma_mask;
};
#define to_sa1111_device(x) container_of(x, struct sa1111_dev, dev)
#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
struct sa1111_driver {
struct device_driver drv;
unsigned int devid;
int (*probe)(struct sa1111_dev *);
void (*remove)(struct sa1111_dev *);
};
#define SA1111_DRV(_d) container_of_const((_d), struct sa1111_driver, drv)
#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
/*
* These frob the SKPCR register, and call platform specific
* enable/disable functions.
*/
int sa1111_enable_device(struct sa1111_dev *);
void sa1111_disable_device(struct sa1111_dev *);
int sa1111_get_irq(struct sa1111_dev *, unsigned num);
unsigned int sa1111_pll_clock(struct sa1111_dev *);
#define SA1111_AUDIO_ACLINK 0
#define SA1111_AUDIO_I2S 1
void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
int sa1111_get_audio_rate(struct sa1111_dev *sadev);
int sa1111_check_dma_bug(dma_addr_t addr);
int sa1111_driver_register(struct sa1111_driver *);
void sa1111_driver_unregister(struct sa1111_driver *);
struct sa1111_platform_data {
int irq_base; /* base for cascaded on-chip IRQs */
unsigned disable_devs;
void *data;
int (*enable)(void *, unsigned);
void (*disable)(void *, unsigned);
};
#endif /* _ASM_ARCH_SA1111 */
linux-7.2.3/arch/arm/include/asm/hardware/scoop.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Definitions for the SCOOP interface found on various Sharp PDAs
*
* Copyright (c) 2004 Richard Purdie
*/
#define SCOOP_MCR 0x00
#define SCOOP_CDR 0x04
#define SCOOP_CSR 0x08
#define SCOOP_CPR 0x0C
#define SCOOP_CCR 0x10
#define SCOOP_IRR 0x14
#define SCOOP_IRM 0x14
#define SCOOP_IMR 0x18
#define SCOOP_ISR 0x1C
#define SCOOP_GPCR 0x20
#define SCOOP_GPWR 0x24
#define SCOOP_GPRR 0x28
#define SCOOP_CPR_OUT (1 << 7)
#define SCOOP_CPR_SD_3V (1 << 2)
#define SCOOP_CPR_CF_XV (1 << 1)
#define SCOOP_CPR_CF_3V (1 << 0)
#define SCOOP_GPCR_PA22 (1 << 12)
#define SCOOP_GPCR_PA21 (1 << 11)
#define SCOOP_GPCR_PA20 (1 << 10)
#define SCOOP_GPCR_PA19 (1 << 9)
#define SCOOP_GPCR_PA18 (1 << 8)
#define SCOOP_GPCR_PA17 (1 << 7)
#define SCOOP_GPCR_PA16 (1 << 6)
#define SCOOP_GPCR_PA15 (1 << 5)
#define SCOOP_GPCR_PA14 (1 << 4)
#define SCOOP_GPCR_PA13 (1 << 3)
#define SCOOP_GPCR_PA12 (1 << 2)
#define SCOOP_GPCR_PA11 (1 << 1)
struct scoop_config {
unsigned short io_out;
unsigned short io_dir;
unsigned short suspend_clr;
unsigned short suspend_set;
int gpio_base;
};
/* Structure for linking scoop devices to PCMCIA sockets */
struct scoop_pcmcia_dev {
struct device *dev; /* Pointer to this socket's scoop device */
int irq; /* irq for socket */
int cd_irq;
const char *cd_irq_str;
unsigned char keep_vs;
unsigned char keep_rd;
};
struct scoop_pcmcia_config {
struct scoop_pcmcia_dev *devs;
int num_devs;
void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
};
extern struct scoop_pcmcia_config *platform_scoop_config;
void reset_scoop(struct device *dev);
unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
linux-7.2.3/arch/arm/include/asm/hardware/ssp.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* ssp.h
*
* Copyright (C) 2003 Russell King, All Rights Reserved.
*/
#ifndef SSP_H
#define SSP_H
struct ssp_state {
unsigned int cr0;
unsigned int cr1;
};
int ssp_write_word(u16 data);
int ssp_read_word(u16 *data);
int ssp_flush(void);
void ssp_enable(void);
void ssp_disable(void);
void ssp_save_state(struct ssp_state *ssp);
void ssp_restore_state(struct ssp_state *ssp);
int ssp_init(void);
void ssp_exit(void);
#endif