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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm64/boot/dts/altera/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \
socfpga_stratix10_socdk_emmc.dtb \
socfpga_stratix10_socdk_nand.dtb \
socfpga_stratix10_swvp.dtb
linux-7.2.3/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/stratix10-clock.h>
/ {
compatible = "altr,socfpga-stratix10";
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
service_reserved: svcbuffer@0 {
compatible = "shared-dma-pool";
reg = <0x0 0x0 0x0 0x1000000>;
alignment = <0x1000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x3>;
};
l2_shared: cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
fpga_mgr: fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
};
};
};
fpga-region {
compatible = "fpga-region";
#address-cells = <0x2>;
#size-cells = <0x2>;
fpga-mgr = <&fpga_mgr>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <0 170 4>,
<0 171 4>,
<0 172 4>,
<0 173 4>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
interrupt-parent = <&intc>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
/* Local timer */
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
interrupt-parent = <&intc>;
};
intc: interrupt-controller@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xfffc1000 0x0 0x1000>,
<0x0 0xfffc2000 0x0 0x2000>,
<0x0 0xfffc4000 0x0 0x2000>,
<0x0 0xfffc6000 0x0 0x2000>;
};
clocks {
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <150000000>;
};
cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <300000000>;
};
f2s_free_clk: f2s-free-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
status = "disabled";
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
};
qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
soc@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
iommus = <&smmu 1>;
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
status = "disabled";
};
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
iommus = <&smmu 2>;
altr,sysmgr-syscon = <&sysmgr 0x48 8>;
status = "disabled";
};
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
iommus = <&smmu 3>;
altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
status = "disabled";
};
gpio0: gpio@ffc03200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
};
};
gpio1: gpio@ffc03300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03300 0x100>;
resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 111 4>;
};
};
i2c0: i2c@ffc02800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
i2c1: i2c@ffc02900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
i2c2: i2c@ffc02a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
i2c3: i2c@ffc02b00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
i2c4: i2c@ffc02c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
mmc: mmc@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>;
reset-names = "reset";
clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
<&clkmgr STRATIX10_SDMMC_CLK>;
clock-names = "biu", "ciu";
iommus = <&smmu 5>;
altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};
nand: nand-controller@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xffb90000 0x10000>,
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 97 4>;
clocks = <&clkmgr STRATIX10_NAND_CLK>,
<&clkmgr STRATIX10_NAND_X_CLK>,
<&clkmgr STRATIX10_NAND_ECC_CLK>;
clock-names = "nand", "nand_x", "ecc";
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
status = "disabled";
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xffe00000 0x100000>;
};
pdma: dma-controller@ffda0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffda0000 0x1000>;
interrupts = <0 81 4>,
<0 82 4>,
<0 83 4>,
<0 84 4>,
<0 85 4>,
<0 86 4>,
<0 87 4>,
<0 88 4>,
<0 89 4>;
#dma-cells = <1>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp";
};
pinctrl0: pinctrl@ffd13000 {
compatible = "pinctrl-single";
reg = <0xffd13000 0xa0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
};
pinctrl1: pinctrl@ffd13100 {
compatible = "pinctrl-single";
reg = <0xffd13100 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
};
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
};
smmu: iommu@fa000000 {
compatible = "arm,mmu-500", "arm,smmu-v2";
reg = <0xfa000000 0x40000>;
#global-interrupts = <2>;
#iommu-cells = <1>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
clock-names = "iommu";
interrupt-parent = <&intc>;
interrupts = <0 128 4>, /* Global Secure Fault */
<0 129 4>, /* Global Non-secure Fault */
/* Non-secure Context Interrupts (32) */
<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
stream-match-mask = <0x7ff0>;
status = "disabled";
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
interrupts = <0 99 4>;
resets = <&rst SPIM0_RESET>;
reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
status = "disabled";
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;
interrupts = <0 100 4>;
resets = <&rst SPIM1_RESET>;
reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
status = "disabled";
};
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr-s10","altr,sys-mgr";
reg = <0xffd12000 0x228>;
};
timer0: timer0@ffc03000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>;
reg = <0xffc03000 0x100>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
clock-names = "timer";
};
timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 114 4>;
reg = <0xffc03100 0x100>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
clock-names = "timer";
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 4>;
reg = <0xffd00000 0x100>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
clock-names = "timer";
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 4>;
reg = <0xffd00100 0x100>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
clock-names = "timer";
};
uart0: serial@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 108 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
uart1: serial@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 109 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART1_RESET>;
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
status = "disabled";
};
usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
clocks = <&clkmgr STRATIX10_USB_CLK>;
clock-names = "otg";
iommus = <&smmu 6>;
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
clocks = <&clkmgr STRATIX10_USB_CLK>;
clock-names = "otg";
iommus = <&smmu 7>;
status = "disabled";
};
watchdog0: watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>;
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog2: watchdog@ffd00400 {
compatible = "snps,dw-wdt";
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>;
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog3: watchdog@ffd00500 {
compatible = "snps,dw-wdt";
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>;
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
status = "disabled";
};
sdr: sdr@f8011100 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xf8011100 0xc0>;
};
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager",
"altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 15 4>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
interrupts = <16 4>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc",
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 4>;
};
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc",
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 4>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 4>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 4>;
};
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 4>,
<15 4>;
};
};
qspi: spi@ff8d2000 {
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff8d2000 0x100>,
<0xff900000 0x100000>;
interrupts = <0 3 4>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
status = "disabled";
};
};
usbphy0: usbphy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
linux-7.2.3/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*/
#include "socfpga_stratix10_socdk.dtsi"
/ {
model = "SoCFPGA Stratix 10 SoCDK";
compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
};
&pinctrl0 {
i2c1_pmx_func: i2c1-pmx-func-pins {
pinctrl-single,pins = <
0x78 0x4 /* I2C1_SDA (IO6-B) PIN30SEL) */
0x7c 0x4 /* I2C1_SCL (IO7-B) PIN31SEL */
>;
};
i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins {
pinctrl-single,pins = <
0x78 0x8 /* I2C1_SDA (IO6-B) PIN30SEL) */
0x7c 0x8 /* I2C1_SCL (IO7-B) PIN31SEL */
>;
};
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@4 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
cap-sd-highspeed;
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
i2c-sda-falling-time-ns = <890>; /* hcnt */
i2c-scl-falling-time-ns = <890>; /* lcnt */
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_pmx_func>;
pinctrl-1 = <&i2c1_pmx_func_gpio>;
scl-gpios = <&portb 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&portb 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
adc@14 {
compatible = "lltc,ltc2497";
reg = <0x14>;
vref-supply = <&ref_033v>;
};
temp@4c {
compatible = "maxim,max1619";
reg = <0x4c>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x04200000>;
};
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
reg = <0x04200000 0x0be00000>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Altera Corporation (C) 2026. All rights reserved.
*/
#include "socfpga_stratix10.dtsi"
/ {
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
led-hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
led-hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0x80000000 0 0>;
};
ref_033v: regulator-0v33-ref {
compatible = "regulator-fixed";
regulator-name = "0.33V";
regulator-min-microvolt = <330000>;
regulator-max-microvolt = <330000>;
};
};
&gpio1 {
status = "okay";
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
disable-over-current;
};
&watchdog0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_emmc.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Altera Corporation (C) 2026. All rights reserved.
*/
#include "socfpga_stratix10_socdk.dtsi"
/ {
model = "SoCFPGA Stratix 10 SoCDK eMMC daughter board";
compatible = "altr,socfpga-stratix10-socdk-emmc",
"altr,socfpga-stratix10-socdk",
"altr,socfpga-stratix10";
};
&gmac2 {
status = "okay";
/* PHY delays is configured via skew properties */
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@4 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
i2c-sda-falling-time-ns = <890>; /* hcnt */
i2c-scl-falling-time-ns = <890>; /* lcnt */
adc@14 {
compatible = "lltc,ltc2497";
reg = <0x14>;
vref-supply = <&ref_033v>;
};
temp@4c {
compatible = "maxim,max1619";
reg = <0x4c>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
linux-7.2.3/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*/
#include "socfpga_stratix10.dtsi"
/ {
model = "SoCFPGA Stratix 10 SoCDK";
compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
led-hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
led-hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0x80000000 0 0>;
};
ref_033v: regulator-v-ref {
compatible = "regulator-fixed";
regulator-name = "0.33V";
regulator-min-microvolt = <330000>;
regulator-max-microvolt = <330000>;
};
};
&gpio1 {
status = "okay";
};
&gmac2 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <16>;
partition@0 {
label = "u-boot";
reg = <0 0x200000>;
};
partition@200000 {
label = "root";
reg = <0x200000 0x3fe00000>;
};
};
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
disable-over-current;
};
&watchdog0 {
status = "okay";
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
i2c-sda-falling-time-ns = <890>; /* hcnt */
i2c-scl-falling-time-ns = <890>; /* lcnt */
adc@14 {
compatible = "lltc,ltc2497";
reg = <0x14>;
vref-supply = <&ref_033v>;
};
temp@4c {
compatible = "maxim,max1619";
reg = <0x4c>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x03fe0000>;
};
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03fe0000 0x0c020000>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022, Intel Corporation
*/
#include "socfpga_stratix10.dtsi"
/ {
model = "SOCFPGA Stratix 10 SWVP";
compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
aliases {
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial1:115200n8";
linux,initrd-start = <0x10000000>;
linux,initrd-end = <0x125c8324>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&cpu0 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&cpu1 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&cpu2 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&cpu3 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&osc1 {
clock-frequency = <25000000>;
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
};
&gmac2 {
status = "okay";
phy-mode = "rgmii";
};
&mmc {
status = "okay";
cap-sd-highspeed;
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
status = "okay";
};
&usb1 {
clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
status = "okay";
};
&sysmgr {
reg = <0xffd12000 0x1000>;
};