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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958802a802x.dtb
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stingray-board-base.dtsi"
/ {
sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio0_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 18 0>;
states = <3300000 0x0
1800000 0x1>;
};
sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio1_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 19 0>;
states = <3300000 0x0
1800000 0x1>;
};
};
&pwm {
status = "okay";
};
&i2c0 {
status = "okay";
pca9505: pca9505@20 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
&i2c1 {
status = "okay";
pcf8574: pcf8574@27 {
compatible = "nxp,pcf8574a";
gpio-controller;
#gpio-cells = <2>;
reg = <0x27>;
};
};
&enet {
status = "okay";
};
&nand {
status = "okay";
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <16>;
brcm,nand-oob-sector-size = <16>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&sdio0 {
vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
status = "okay";
};
&sdio1 {
vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm958742-base.dtsi"
/ {
compatible = "brcm,bcm958742k", "brcm,stingray";
model = "Stingray Combo SVK (BCM958742K)";
};
&gphy0 {
enet-phy-lane-swap;
};
&sdio0 {
mmc-ddr-1_8v;
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&ssp0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio_hsls 34 0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&ssp1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio_hsls 96 0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
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/*
* BSD LICENSE
*
* Copyright(c) 2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm958742-base.dtsi"
/ {
compatible = "brcm,bcm958742t", "brcm,stingray";
model = "Stingray SST100 (BCM958742T)";
};
&gphy0 {
enet-phy-lane-swap;
};
&sdio0 {
mmc-ddr-1_8v;
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
*Copyright(c) 2018 Broadcom
*/
/dts-v1/;
#include "stingray-board-base.dtsi"
/ {
compatible = "brcm,bcm958802a802x", "brcm,stingray";
model = "Stingray PS225xx (BCM958802A802x)";
};
&enet {
status = "disabled";
};
&sdio0 {
no-1-8-v;
status = "okay";
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright(c) 2016-2018 Broadcom
*/
#include "stingray.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &uart1;
serial1 = &uart0;
serial2 = &uart2;
serial3 = &uart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&memory { /* Default DRAM banks */
reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
};
&enet {
phy-mode = "rgmii-id";
phy-handle = <&gphy0>;
};
&uart1 {
status = "okay";
};
&sdio0 {
non-removable;
full-pwr-cycle;
};
&sdio1 {
full-pwr-cycle;
};
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
reg = <0x10>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi
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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
fs4: fs4-bus@67000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x67000000 0x00800000>;
crypto_mbox: crypto_mbox@0 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x00000000 0x200000>;
msi-parent = <&gic_its 0x4100>;
#mbox-cells = <3>;
dma-coherent;
};
raid_mbox: raid_mbox@400000 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x00400000 0x200000>;
dma-coherent;
msi-parent = <&gic_its 0x4300>;
#mbox-cells = <3>;
};
};
raid0: raid-0 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 0 0x1 0xff00>,
<&raid_mbox 1 0x1 0xff00>,
<&raid_mbox 2 0x1 0xff00>,
<&raid_mbox 3 0x1 0xff00>;
};
raid1: raid-1 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 4 0x1 0xff00>,
<&raid_mbox 5 0x1 0xff00>,
<&raid_mbox 6 0x1 0xff00>,
<&raid_mbox 7 0x1 0xff00>;
};
raid2: raid-2 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 8 0x1 0xff00>,
<&raid_mbox 9 0x1 0xff00>,
<&raid_mbox 10 0x1 0xff00>,
<&raid_mbox 11 0x1 0xff00>;
};
raid3: raid-3 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 12 0x1 0xff00>,
<&raid_mbox 13 0x1 0xff00>,
<&raid_mbox 14 0x1 0xff00>,
<&raid_mbox 15 0x1 0xff00>;
};
raid4: raid-4 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 16 0x1 0xff00>,
<&raid_mbox 17 0x1 0xff00>,
<&raid_mbox 18 0x1 0xff00>,
<&raid_mbox 19 0x1 0xff00>;
};
raid5: raid-5 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 20 0x1 0xff00>,
<&raid_mbox 21 0x1 0xff00>,
<&raid_mbox 22 0x1 0xff00>,
<&raid_mbox 23 0x1 0xff00>;
};
raid6: raid-6 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 24 0x1 0xff00>,
<&raid_mbox 25 0x1 0xff00>,
<&raid_mbox 26 0x1 0xff00>,
<&raid_mbox 27 0x1 0xff00>;
};
raid7: raid-7 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 28 0x1 0xff00>,
<&raid_mbox 29 0x1 0xff00>,
<&raid_mbox 30 0x1 0xff00>,
<&raid_mbox 31 0x1 0xff00>;
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
*Copyright(c) 2018 Broadcom
*/
pcie8: pcie@60400000 {
compatible = "brcm,iproc-pcie-paxc-v2";
reg = <0 0x60400000 0 0x1000>;
linux,pci-domain = <8>;
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
dma-coherent;
msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
<0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
<0x101 &gic_its 0x2080 0x1>, /* PF1 */
<0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
<0x102 &gic_its 0x2100 0x1>, /* PF2 */
<0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
<0x103 &gic_its 0x2180 0x1>, /* PF3 */
<0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */
<0x104 &gic_its 0x2200 0x1>, /* PF4 */
<0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */
<0x105 &gic_its 0x2280 0x1>, /* PF5 */
<0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */
<0x106 &gic_its 0x2300 0x1>, /* PF6 */
<0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */
<0x107 &gic_its 0x2380 0x1>, /* PF7 */
<0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */
phys = <&pcie_phy 8>;
phy-names = "pcie-phy";
};
pcie-ss-bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x800>;
pcie_phy: phy@0 {
compatible = "brcm,sr-pcie-phy";
reg = <0x0 0x200>;
brcm,sr-cdru = <&cdru>;
brcm,sr-mhb = <&mhb>;
#phy-cells = <1>;
};
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
pinconf: pinctrl@140000 {
compatible = "pinconf-single";
reg = <0x00140000 0x250>;
pinctrl-single,register-width = <32>;
/* pinconf functions */
};
pinmux: pinmux@14029c {
compatible = "pinctrl-single";
reg = <0x0014029c 0x26c>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
pinctrl-single,gpio-range = <
&range 0 91 MODE_GPIO
&range 95 60 MODE_GPIO
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
/* pinctrl functions */
tsio_pins: gpio-14-pins {
pinctrl-single,pins = <
0x038 MODE_NITRO /* tsio_0 */
0x03c MODE_NITRO /* tsio_1 */
>;
};
nor_pins: pnor-adv-n-pins {
pinctrl-single,pins = <
0x0ac MODE_PNOR /* nand_ce1_n */
0x0b0 MODE_PNOR /* nand_ce0_n */
0x0b4 MODE_PNOR /* nand_we_n */
0x0b8 MODE_PNOR /* nand_wp_n */
0x0bc MODE_PNOR /* nand_re_n */
0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
0x0c4 MODE_PNOR /* nand_io0_0 */
0x0c8 MODE_PNOR /* nand_io1_0 */
0x0cc MODE_PNOR /* nand_io2_0 */
0x0d0 MODE_PNOR /* nand_io3_0 */
0x0d4 MODE_PNOR /* nand_io4_0 */
0x0d8 MODE_PNOR /* nand_io5_0 */
0x0dc MODE_PNOR /* nand_io6_0 */
0x0e0 MODE_PNOR /* nand_io7_0 */
0x0e4 MODE_PNOR /* nand_io8_0 */
0x0e8 MODE_PNOR /* nand_io9_0 */
0x0ec MODE_PNOR /* nand_io10_0 */
0x0f0 MODE_PNOR /* nand_io11_0 */
0x0f4 MODE_PNOR /* nand_io12_0 */
0x0f8 MODE_PNOR /* nand_io13_0 */
0x0fc MODE_PNOR /* nand_io14_0 */
0x100 MODE_PNOR /* nand_io15_0 */
0x104 MODE_PNOR /* nand_ale_0 */
0x108 MODE_PNOR /* nand_cle_0 */
0x040 MODE_PNOR /* pnor_adv_n */
0x044 MODE_PNOR /* pnor_baa_n */
0x048 MODE_PNOR /* pnor_bls_0_n */
0x04c MODE_PNOR /* pnor_bls_1_n */
0x050 MODE_PNOR /* pnor_cre */
0x054 MODE_PNOR /* pnor_cs_2_n */
0x058 MODE_PNOR /* pnor_cs_1_n */
0x05c MODE_PNOR /* pnor_cs_0_n */
0x060 MODE_PNOR /* pnor_we_n */
0x064 MODE_PNOR /* pnor_oe_n */
0x068 MODE_PNOR /* pnor_intr */
0x06c MODE_PNOR /* pnor_dat_0 */
0x070 MODE_PNOR /* pnor_dat_1 */
0x074 MODE_PNOR /* pnor_dat_2 */
0x078 MODE_PNOR /* pnor_dat_3 */
0x07c MODE_PNOR /* pnor_dat_4 */
0x080 MODE_PNOR /* pnor_dat_5 */
0x084 MODE_PNOR /* pnor_dat_6 */
0x088 MODE_PNOR /* pnor_dat_7 */
0x08c MODE_PNOR /* pnor_dat_8 */
0x090 MODE_PNOR /* pnor_dat_9 */
0x094 MODE_PNOR /* pnor_dat_10 */
0x098 MODE_PNOR /* pnor_dat_11 */
0x09c MODE_PNOR /* pnor_dat_12 */
0x0a0 MODE_PNOR /* pnor_dat_13 */
0x0a4 MODE_PNOR /* pnor_dat_14 */
0x0a8 MODE_PNOR /* pnor_dat_15 */
>;
};
nand_pins: nand-ce1-n-pins {
pinctrl-single,pins = <
0x0ac MODE_NAND /* nand_ce1_n */
0x0b0 MODE_NAND /* nand_ce0_n */
0x0b4 MODE_NAND /* nand_we_n */
0x0b8 MODE_NAND /* nand_wp_n */
0x0bc MODE_NAND /* nand_re_n */
0x0c0 MODE_NAND /* nand_rdy_bsy_n */
0x0c4 MODE_NAND /* nand_io0_0 */
0x0c8 MODE_NAND /* nand_io1_0 */
0x0cc MODE_NAND /* nand_io2_0 */
0x0d0 MODE_NAND /* nand_io3_0 */
0x0d4 MODE_NAND /* nand_io4_0 */
0x0d8 MODE_NAND /* nand_io5_0 */
0x0dc MODE_NAND /* nand_io6_0 */
0x0e0 MODE_NAND /* nand_io7_0 */
0x0e4 MODE_NAND /* nand_io8_0 */
0x0e8 MODE_NAND /* nand_io9_0 */
0x0ec MODE_NAND /* nand_io10_0 */
0x0f0 MODE_NAND /* nand_io11_0 */
0x0f4 MODE_NAND /* nand_io12_0 */
0x0f8 MODE_NAND /* nand_io13_0 */
0x0fc MODE_NAND /* nand_io14_0 */
0x100 MODE_NAND /* nand_io15_0 */
0x104 MODE_NAND /* nand_ale_0 */
0x108 MODE_NAND /* nand_cle_0 */
>;
};
pwm0_pins: pwm-0-pins {
pinctrl-single,pins = <
0x10c MODE_NITRO
>;
};
pwm1_pins: pwm-1-pins {
pinctrl-single,pins = <
0x110 MODE_NITRO
>;
};
pwm2_pins: pwm-2-pins {
pinctrl-single,pins = <
0x114 MODE_NITRO
>;
};
pwm3_pins: pwm-3-pins {
pinctrl-single,pins = <
0x118 MODE_NITRO
>;
};
dbu_rxd_pins: uart1-sin-nitro-pins {
pinctrl-single,pins = <
0x11c MODE_NITRO /* dbu_rxd */
0x120 MODE_NITRO /* dbu_txd */
>;
};
uart1_pins: uart1-sin-nand-pins {
pinctrl-single,pins = <
0x11c MODE_NAND /* uart1_sin */
0x120 MODE_NAND /* uart1_out */
>;
};
uart2_pins: uart2-sin-pins {
pinctrl-single,pins = <
0x124 MODE_NITRO /* uart2_sin */
0x128 MODE_NITRO /* uart2_out */
>;
};
uart3_pins: uart3-sin-pins {
pinctrl-single,pins = <
0x12c MODE_NITRO /* uart3_sin */
0x130 MODE_NITRO /* uart3_out */
>;
};
i2s_pins: i2s-bitclk-pins {
pinctrl-single,pins = <
0x134 MODE_NITRO /* i2s_bitclk */
0x138 MODE_NITRO /* i2s_sdout */
0x13c MODE_NITRO /* i2s_sdin */
0x140 MODE_NITRO /* i2s_ws */
0x144 MODE_NITRO /* i2s_mclk */
0x148 MODE_NITRO /* i2s_spdif_out */
>;
};
qspi_pins: qspi-hold-n-pins {
pinctrl-single,pins = <
0x14c MODE_NAND /* qspi_hold_n */
0x150 MODE_NAND /* qspi_wp_n */
0x154 MODE_NAND /* qspi_sck */
0x158 MODE_NAND /* qspi_cs_n */
0x15c MODE_NAND /* qspi_mosi */
0x160 MODE_NAND /* qspi_miso */
>;
};
mdio_pins: ext-mdio-pins {
pinctrl-single,pins = <
0x164 MODE_NITRO /* ext_mdio */
0x168 MODE_NITRO /* ext_mdc */
>;
};
i2c0_pins: i2c0-sda-pins {
pinctrl-single,pins = <
0x16c MODE_NITRO /* i2c0_sda */
0x170 MODE_NITRO /* i2c0_scl */
>;
};
i2c1_pins: i2c1-sda-pins {
pinctrl-single,pins = <
0x174 MODE_NITRO /* i2c1_sda */
0x178 MODE_NITRO /* i2c1_scl */
>;
};
sdio0_pins: sdio0-cd-l-pins {
pinctrl-single,pins = <
0x17c MODE_NITRO /* sdio0_cd_l */
0x180 MODE_NITRO /* sdio0_clk_sdcard */
0x184 MODE_NITRO /* sdio0_data0 */
0x188 MODE_NITRO /* sdio0_data1 */
0x18c MODE_NITRO /* sdio0_data2 */
0x190 MODE_NITRO /* sdio0_data3 */
0x194 MODE_NITRO /* sdio0_data4 */
0x198 MODE_NITRO /* sdio0_data5 */
0x19c MODE_NITRO /* sdio0_data6 */
0x1a0 MODE_NITRO /* sdio0_data7 */
0x1a4 MODE_NITRO /* sdio0_cmd */
0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
0x1ac MODE_NITRO /* sdio0_led_on */
0x1b0 MODE_NITRO /* sdio0_wp */
>;
};
sdio1_pins: sdio1-cd-l-pins {
pinctrl-single,pins = <
0x1b4 MODE_NITRO /* sdio1_cd_l */
0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
0x1bc MODE_NITRO /* sdio1_data0 */
0x1c0 MODE_NITRO /* sdio1_data1 */
0x1c4 MODE_NITRO /* sdio1_data2 */
0x1c8 MODE_NITRO /* sdio1_data3 */
0x1cc MODE_NITRO /* sdio1_data4 */
0x1d0 MODE_NITRO /* sdio1_data5 */
0x1d4 MODE_NITRO /* sdio1_data6 */
0x1d8 MODE_NITRO /* sdio1_data7 */
0x1dc MODE_NITRO /* sdio1_cmd */
0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
0x1e4 MODE_NITRO /* sdio1_led_on */
0x1e8 MODE_NITRO /* sdio1_wp */
>;
};
spi0_pins: spi0-sck-nand-pins {
pinctrl-single,pins = <
0x1ec MODE_NITRO /* spi0_sck */
0x1f0 MODE_NITRO /* spi0_rxd */
0x1f4 MODE_NITRO /* spi0_fss */
0x1f8 MODE_NITRO /* spi0_txd */
>;
};
spi1_pins: spi1-sck-nand-pins {
pinctrl-single,pins = <
0x1fc MODE_NITRO /* spi1_sck */
0x200 MODE_NITRO /* spi1_rxd */
0x204 MODE_NITRO /* spi1_fss */
0x208 MODE_NITRO /* spi1_txd */
>;
};
nuart_pins: uart0-sin-nitro-pins {
pinctrl-single,pins = <
0x20c MODE_NITRO /* nuart_rxd */
0x210 MODE_NITRO /* nuart_txd */
>;
};
uart0_pins: uart0-sin-nand-pins {
pinctrl-single,pins = <
0x20c MODE_NAND /* uart0_sin */
0x210 MODE_NAND /* uart0_out */
0x214 MODE_NAND /* uart0_rts */
0x218 MODE_NAND /* uart0_cts */
0x21c MODE_NAND /* uart0_dtr */
0x220 MODE_NAND /* uart0_dcd */
0x224 MODE_NAND /* uart0_dsr */
0x228 MODE_NAND /* uart0_ri */
>;
};
drdu2_pins: drdu2-overcurrent-pins {
pinctrl-single,pins = <
0x22c MODE_NITRO /* drdu2_overcurrent */
0x230 MODE_NITRO /* drdu2_vbus_ppc */
0x234 MODE_NITRO /* drdu2_vbus_present */
0x238 MODE_NITRO /* drdu2_id */
>;
};
drdu3_pins: drdu3-overcurrent-pins {
pinctrl-single,pins = <
0x23c MODE_NITRO /* drdu3_overcurrent */
0x240 MODE_NITRO /* drdu3_vbus_ppc */
0x244 MODE_NITRO /* drdu3_vbus_present */
0x248 MODE_NITRO /* drdu3_id */
>;
};
usb3h_pins: usb3h-overcurrent-pins {
pinctrl-single,pins = <
0x24c MODE_NITRO /* usb3h_overcurrent */
0x250 MODE_NITRO /* usb3h_vbus_ppc */
>;
};
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi
+58
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
*Copyright(c) 2018 Broadcom
*/
usb-bus@68500000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x68500000 0x0 0x00400000>;
/*
* Internally, USB bus to the interconnect can only address up
* to 40-bit
*/
dma-ranges = <0 0 0 0 0x100 0x0>;
usbphy0: usb-phy@0 {
compatible = "brcm,sr-usb-combo-phy";
reg = <0x0 0x00000000 0x0 0x100>;
#phy-cells = <1>;
status = "disabled";
};
xhci0: usb@1000 {
compatible = "generic-xhci";
reg = <0x0 0x00001000 0x0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy0 1>, <&usbphy0 0>;
phy-names = "phy0", "phy1";
dma-coherent;
status = "disabled";
};
usbphy1: usb-phy@10000 {
compatible = "brcm,sr-usb-combo-phy";
reg = <0x0 0x00010000 0x0 0x100>;
#phy-cells = <1>;
status = "disabled";
};
usbphy2: usb-phy@20000 {
compatible = "brcm,sr-usb-hs-phy";
reg = <0x0 0x00020000 0x0 0x100>;
#phy-cells = <0>;
status = "disabled";
};
xhci1: usb@11000 {
compatible = "generic-xhci";
reg = <0x0 0x00011000 0x0 0x1000>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>;
phy-names = "phy0", "phy1", "phy2";
dma-coherent;
status = "disabled";
};
};
linux-7.2.3/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+834
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@@ -0,0 +1,834 @@
/*
* BSD LICENSE
*
* Copyright(c) 2015-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/clock/bcm-sr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,stingray";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x201>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x301>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
memory: memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
mhb: syscon@60401000 {
compatible = "brcm,sr-mhb", "syscon";
reg = <0 0x60401000 0 0x38c>;
};
osc: clock-50000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
crmu_ref25m: hsls_25m_clk: clock-25000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&osc>;
clock-div = <2>;
clock-mult = <1>;
};
hsls_div2_clk: hsls_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
hsls_div4_clk: hsls_div4_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
hsls_25m_div2_clk: clock-12500000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hsls_25m_clk>;
clock-div = <2>;
clock-mult = <1>;
};
scr-bus@61000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
ccn: ccn@0 {
compatible = "arm,ccn-502";
reg = <0x00000000 0x900000>;
interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@2c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
reg = <0x02c00000 0x010000>, /* GICD */
<0x02e00000 0x600000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@63c20000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x02c20000 0x10000>;
};
};
smmu: iommu@3000000 {
compatible = "arm,mmu-500";
reg = <0x03000000 0x80000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <2>;
};
};
crmu: crmu-bus@66400000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x66400000 0x100000>;
otp: otp@1c400 {
compatible = "brcm,ocotp-v2";
reg = <0x0001c400 0x68>;
brcm,ocotp-size = <2048>;
status = "okay";
};
cdru: syscon@1d000 {
compatible = "brcm,sr-cdru", "syscon";
reg = <0x0001d000 0x400>;
};
lcpll0: clock-controller@1d0c4 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll0";
reg = <0x0001d0c4 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll0", "clk_sata_refp",
"clk_sata_refn", "clk_sata_350",
"clk_sata_500";
};
genpll0: clock-controller@1d104 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll0";
reg = <0x0001d104 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll0", "clk_125m", "clk_scr",
"clk_250", "clk_pcie_axi",
"clk_paxc_axi_x2",
"clk_paxc_axi";
};
lcpll1: clock-controller@1d138 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll1";
reg = <0x0001d138 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll1", "clk_wan",
"clk_usb_ref",
"clk_crmu_ts";
};
genpll2: clock-controller@1d1ac {
#clock-cells = <1>;
compatible = "brcm,sr-genpll2";
reg = <0x0001d1ac 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll2", "clk_nic",
"clk_ts_500_ref", "clk_125_nitro",
"clk_chimp", "clk_nic_flash",
"clk_fs";
};
genpll3: clock-controller@1d1e0 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll3";
reg = <0x0001d1e0 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll3", "clk_hsls",
"clk_sdio";
};
genpll4: clock-controller@1d214 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll4";
reg = <0x0001d214 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll4", "clk_ccn",
"clk_tpiu_pll", "clk_noc",
"clk_chclk_fs4",
"clk_bridge_fscpu";
};
genpll5: clock-controller@1d248 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll5";
reg = <0x0001d248 0x32>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "genpll5", "clk_fs4_hf",
"clk_crypto_ae", "clk_raid_ae";
};
gpio_crmu: gpio@24800 {
compatible = "brcm,iproc-gpio";
reg = <0x00024800 0x4c>;
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
};
};
#include "stingray-fs4.dtsi"
#include "stingray-pcie.dtsi"
#include "stingray-usb.dtsi"
hsls-bus@68900000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x68900000 0x17700000>;
#include "stingray-pinctrl.dtsi"
mdio_mux_iproc: mdio-mux@20000 {
compatible = "brcm,mdio-mux-iproc";
reg = <0x00020000 0x250>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 { /* PCIe serdes */
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@3 { /* USB */
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@10 { /* RGMII */
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
};
};
pwm: pwm@10000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
clocks = <&crmu_ref25m>;
#pwm-cells = <3>;
status = "disabled";
};
timer0: timer@30000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00030000 0x1000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer1: timer@40000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00040000 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer2: timer@50000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00050000 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer3: timer@60000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00060000 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer4: timer@70000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00070000 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer5: timer@80000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00080000 0x1000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer6: timer@90000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00090000 0x1000>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer7: timer@a0000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x000a0000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
i2c0: i2c@b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <100000>;
status = "disabled";
};
wdt0: watchdog@c0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x000c0000 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
clock-names = "wdog_clk", "apb_pclk";
timeout-sec = <60>;
};
gpio_hsls: gpio@d0000 {
compatible = "brcm,iproc-gpio";
reg = <0x000d0000 0x864>;
ngpios = <151>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinmux 0 0 16>,
<&pinmux 16 71 2>,
<&pinmux 18 131 8>,
<&pinmux 26 83 6>,
<&pinmux 32 123 4>,
<&pinmux 36 43 24>,
<&pinmux 60 89 2>,
<&pinmux 62 73 4>,
<&pinmux 66 95 28>,
<&pinmux 94 127 4>,
<&pinmux 98 139 10>,
<&pinmux 108 16 27>,
<&pinmux 135 77 6>,
<&pinmux 141 67 4>,
<&pinmux 145 149 6>;
};
i2c1: i2c@e0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000e0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <100000>;
status = "disabled";
};
uart0: serial@100000 {
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: serial@110000 {
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart2: serial@120000 {
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart3: serial@130000 {
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
ssp0: spi@180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00180000 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssp1: spi@190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00190000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hwrng: hwrng@220000 {
compatible = "brcm,iproc-rng200";
reg = <0x00220000 0x28>;
};
dma0: dma-controller@310000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x00310000 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&hsls_div2_clk>;
clock-names = "apb_pclk";
iommus = <&smmu 0x6000 0x0000>;
};
enet: ethernet@340000 {
compatible = "brcm,amac";
reg = <0x00340000 0x1000>;
reg-names = "amac_base";
dma-coherent;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
nand: nand-controller@360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,
<0x0050a408 0x600>,
<0x00360f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
status = "disabled";
};
sdio0: mmc@3f1000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f1000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
iommus = <&smmu 0x6002 0x0000>;
status = "disabled";
};
sdio1: mmc@3f2000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f2000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
iommus = <&smmu 0x6003 0x0000>;
status = "disabled";
};
};
tmons-bus@8f100000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x8f100000 0x100>;
tmon: tmon@0 {
compatible = "brcm,sr-thermal";
reg = <0x0 0x40>;
brcm,tmon-mask = <0x3f>;
#thermal-sensor-cells = <1>;
};
};
thermal-zones {
ihost0_thermal: ihost0-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&tmon 0>;
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
};
};
ihost1_thermal: ihost1-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&tmon 1>;
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
};
};
ihost2_thermal: ihost2-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&tmon 2>;
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
};
};
ihost3_thermal: ihost3-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&tmon 3>;
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
};
};
crmu_thermal: crmu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&tmon 4>;
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
};
};
nitro_thermal: nitro-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&tmon 5>;
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
nic-hsls-bus@60800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x60800000 0x6fffff>;
nic_i2c0: i2c@26100 {
compatible = "brcm,iproc-nic-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x026100 0x100>,
<0x600408 0x1000>;
brcm,ape-hsls-addr-mask = <0x03400000>;
clock-frequency = <100000>;
status = "disabled";
};
};
};