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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm64/boot/dts/mediatek/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
mt7986a-bananapi-bpi-r3-emmc-nand-dtbs := \
mt7986a-bananapi-bpi-r3.dtb \
mt7986a-bananapi-bpi-r3-emmc.dtbo \
mt7986a-bananapi-bpi-r3-nand.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nand.dtb
mt7986a-bananapi-bpi-r3-emmc-nor-dtbs := \
mt7986a-bananapi-bpi-r3.dtb \
mt7986a-bananapi-bpi-r3-emmc.dtbo \
mt7986a-bananapi-bpi-r3-nor.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nor.dtb
mt7986a-bananapi-bpi-r3-sd-nand-dtbs := \
mt7986a-bananapi-bpi-r3.dtb \
mt7986a-bananapi-bpi-r3-sd.dtbo \
mt7986a-bananapi-bpi-r3-nand.dtbo \
mt7986a-bananapi-bpi-r3-sata.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nand.dtb
mt7986a-bananapi-bpi-r3-sd-nor-dtbs := \
mt7986a-bananapi-bpi-r3.dtb \
mt7986a-bananapi-bpi-r3-sd.dtbo \
mt7986a-bananapi-bpi-r3-nor.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nor.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-4e.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn13.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn14.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn15.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
mt7988a-bananapi-bpi-r4-emmc-dtbs := \
mt7988a-bananapi-bpi-r4.dtb \
mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtb
mt7988a-bananapi-bpi-r4-sd-dtbs := \
mt7988a-bananapi-bpi-r4.dtb \
mt7988a-bananapi-bpi-r4-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtb
mt7988a-bananapi-bpi-r4-2g5-emmc-dtbs := \
mt7988a-bananapi-bpi-r4-2g5.dtb \
mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-emmc.dtb
mt7988a-bananapi-bpi-r4-2g5-sd-dtbs := \
mt7988a-bananapi-bpi-r4-2g5.dtb \
mt7988a-bananapi-bpi-r4-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-sd.dtb
mt7988a-bananapi-bpi-r4-pro-8x-emmc-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x.dtb \
mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \
mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \
mt7988a-bananapi-bpi-r4-pro-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-emmc.dtb
mt7988a-bananapi-bpi-r4-pro-8x-sd-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x.dtb \
mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \
mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \
mt7988a-bananapi-bpi-r4-pro-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb
mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \
mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \
mt7988a-bananapi-bpi-r4-pro-cn15.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15.dtb
mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \
mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \
mt7988a-bananapi-bpi-r4-pro-cn18.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-squirtle.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-tungsten-smarc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
mt8395-radxa-nio-12l-8-hd-panel-dtbs := mt8395-radxa-nio-12l.dtb mt8395-radxa-nio-12l-8-hd-panel.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
# Device tree overlays support
DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@
DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-4e := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-8x := -@
DTC_FLAGS_mt8395-radxa-nio-12l := -@
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+238
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/*
* Copyright (c) 2017 MediaTek Inc.
* Author: YT Shen <yt.shen@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt2712e.dtsi"
/ {
model = "MediaTek MT2712 evaluation board";
chassis-type = "embedded";
compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
cpus_fixed_vproc0: regulator-vproc-buck0 {
compatible = "regulator-fixed";
regulator-name = "vproc_buck0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
cpus_fixed_vproc1: regulator-vproc-buck1 {
compatible = "regulator-fixed";
regulator-name = "vproc_buck1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
extcon_usb: extcon_iddig {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_iddig1 {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
};
usb_p0_vbus: regulator-usb-p0-vbus {
compatible = "regulator-fixed";
regulator-name = "p0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p1_vbus: regulator-usb-p1-vbus {
compatible = "regulator-fixed";
regulator-name = "p1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p2_vbus: regulator-usb-p2-vbus {
compatible = "regulator-fixed";
regulator-name = "p2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p3_vbus: regulator-usb-p3-vbus {
compatible = "regulator-fixed";
regulator-name = "p3_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&auxadc {
status = "okay";
};
&cpu0 {
proc-supply = <&cpus_fixed_vproc0>;
};
&cpu1 {
proc-supply = <&cpus_fixed_vproc0>;
};
&cpu2 {
proc-supply = <&cpus_fixed_vproc1>;
};
&eth {
phy-mode = "rgmii-rxid";
phy-handle = <&ethernet_phy0>;
mediatek,tx-delay-ps = <1530>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
snps,reset-delays-us = <0 10000 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_default>;
pinctrl-1 = <&eth_sleep>;
mediatek,mac-wol;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy0: ethernet-phy@5 {
compatible = "ethernet-phy-id0243.0d90";
reg = <0x5>;
};
};
};
&pio {
eth_default: eth-default-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
<MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>,
<MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
<MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
<MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
drive-strength = <8>;
};
rx_pins {
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
<MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>,
<MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>,
<MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>,
<MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>,
<MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>;
input-enable;
};
mdio_pins {
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
<MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
drive-strength = <8>;
input-enable;
};
};
eth_sleep: eth-sleep-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
<MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>,
<MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>,
<MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>,
<MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>;
};
rx_pins {
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>,
<MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>,
<MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>,
<MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>,
<MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>,
<MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>;
input-disable;
};
mdio_pins {
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>,
<MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>;
input-disable;
bias-disable;
};
};
usb0_id_pins_float: usb0-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up;
};
};
usb1_id_pins_float: usb1-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up;
};
};
};
&ssusb {
vbus-supply = <&usb_p0_vbus>;
extcon = <&extcon_usb>;
dr_mode = "otg";
wakeup-source;
mediatek,u3p-dis-msk = <0x1>;
//enable-manual-drd;
//maximum-speed = "full-speed";
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_pins_float>;
status = "okay";
};
&ssusb1 {
vbus-supply = <&usb_p1_vbus>;
extcon = <&extcon_usb1>;
dr_mode = "otg";
//mediatek,u3p-dis-msk = <0x1>;
enable-manual-drd;
wakeup-source;
//maximum-speed = "full-speed";
pinctrl-names = "default";
pinctrl-0 = <&usb1_id_pins_float>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_host0 {
vbus-supply = <&usb_p2_vbus>;
status = "okay";
};
&usb_host1 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6331.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2023 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include <dt-bindings/input/input.h>
&pwrap {
pmic: pmic {
compatible = "mediatek,mt6331";
interrupt-controller;
#interrupt-cells = <2>;
mt6331regulator: regulators {
compatible = "mediatek,mt6331-regulator";
mt6331_vdvfs11_reg: buck-vdvfs11 {
regulator-name = "vdvfs11";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1493750>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
};
mt6331_vdvfs12_reg: buck-vdvfs12 {
regulator-name = "vdvfs12";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1493750>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
};
mt6331_vdvfs13_reg: buck-vdvfs13 {
regulator-name = "vdvfs13";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1493750>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
};
mt6331_vdvfs14_reg: buck-vdvfs14 {
regulator-name = "vdvfs14";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1493750>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
};
mt6331_vcore2_reg: buck-vcore2 {
regulator-name = "vcore2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1493750>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
};
mt6331_vio18_reg: buck-vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
};
mt6331_vtcxo1_reg: ldo-vtcxo1 {
regulator-name = "vtcxo1";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_vtcxo2_reg: ldo-vtcxo2 {
regulator-name = "vtcxo2";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_avdd32_aud_reg: ldo-avdd32aud {
regulator-name = "avdd32_aud";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3200000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_vauxa32_reg: ldo-vauxa32 {
regulator-name = "vauxa32";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3200000>;
regulator-ramp-delay = <0>;
};
mt6331_vcama_reg: ldo-vcama {
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <0>;
};
mt6331_vio28_reg: ldo-vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_vcamaf_reg: ldo-vcamaf {
regulator-name = "vcam_af";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
};
mt6331_vmc_reg: ldo-vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
};
mt6331_vmch_reg: ldo-vmch {
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
};
mt6331_vemc33_reg: ldo-vemc33 {
regulator-name = "vemc33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vgp1_reg: ldo-vgp1 {
regulator-name = "vgp1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vsim1_reg: ldo-vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vsim2_reg: ldo-vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-ramp-delay = <0>;
};
mt6331_vmipi_reg: ldo-vmipi {
regulator-name = "vmipi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vibr_reg: ldo-vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
};
mt6331_vgp4_reg: ldo-vgp4 {
regulator-name = "vgp4";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <2200000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vcamd_reg: ldo-vcamd {
regulator-name = "vcamd";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vusb10_reg: ldo-vusb10 {
regulator-name = "vusb";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_vcamio_reg: ldo-vcamio {
regulator-name = "vcamio";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <0>;
};
mt6331_vsram_reg: ldo-vsram {
regulator-name = "vsram";
regulator-min-microvolt = <1012500>;
regulator-max-microvolt = <1012500>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_vgp2_reg: ldo-vgp2 {
regulator-name = "vgp2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6331_vgp3_reg: ldo-vgp3 {
regulator-name = "vgp3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vrtc_reg: ldo-vrtc {
regulator-name = "vrtc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
mt6331_vdig18_reg: ldo-vdig18 {
regulator-name = "vdig18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
};
};
mt6331rtc: rtc {
compatible = "mediatek,mt6331-rtc";
};
mt6331keys: keys {
compatible = "mediatek,mt6331-keys";
power {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
home {
linux,keycodes = <KEY_HOME>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6357.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2023 BayLibre Inc.
*/
#include <dt-bindings/input/input.h>
&pwrap {
mt6357_pmic: pmic {
compatible = "mediatek,mt6357";
pmic_adc: adc {
compatible = "mediatek,mt6357-auxadc";
#io-channel-cells = <1>;
};
regulators {
mt6357_vproc_reg: buck-vproc {
regulator-name = "vproc";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
mt6357_vcore_reg: buck-vcore {
regulator-name = "vcore";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
mt6357_vmodem_reg: buck-vmodem {
regulator-name = "vmodem";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <220>;
};
mt6357_vs1_reg: buck-vs1 {
regulator-name = "vs1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2200000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <220>;
regulator-always-on;
};
mt6357_vpa_reg: buck-vpa {
regulator-name = "vpa";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3650000>;
regulator-ramp-delay = <50000>;
regulator-enable-ramp-delay = <220>;
};
mt6357_vfe28_reg: ldo-vfe28 {
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vxo22_reg: ldo-vxo22 {
regulator-name = "vxo22";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2400000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vrf18_reg: ldo-vrf18 {
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vrf12_reg: ldo-vrf12 {
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vefuse_reg: ldo-vefuse {
regulator-name = "vefuse";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn33_bt_reg: ldo-vcn33-bt {
regulator-name = "vcn33-bt";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
regulator-name = "vcn33-wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn28_reg: ldo-vcn28 {
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn18_reg: ldo-vcn18 {
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcama_reg: ldo-vcama {
regulator-name = "vcama";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcamd_reg: ldo-vcamd {
regulator-name = "vcamd";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcamio_reg: ldo-vcamio18 {
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vldo28_reg: ldo-vldo28 {
regulator-name = "vldo28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vsram_others_reg: ldo-vsram-others {
regulator-name = "vsram-others";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <110>;
regulator-always-on;
};
mt6357_vsram_proc_reg: ldo-vsram-proc {
regulator-name = "vsram-proc";
regulator-min-microvolt = <518750>;
regulator-max-microvolt = <1312500>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <110>;
regulator-always-on;
};
mt6357_vaux18_reg: ldo-vaux18 {
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vaud28_reg: ldo-vaud28 {
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vio28_reg: ldo-vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vio18_reg: ldo-vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
regulator-always-on;
};
mt6357_vdram_reg: ldo-vdram {
regulator-name = "vdram";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <3300>;
};
mt6357_vmc_reg: ldo-vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
};
mt6357_vmch_reg: ldo-vmch {
regulator-name = "vmch";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
};
mt6357_vemc_reg: ldo-vemc {
regulator-name = "vemc";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
regulator-always-on;
};
mt6357_vsim1_reg: ldo-vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vsim2_reg: ldo-vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vibr_reg: ldo-vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <44>;
};
mt6357_vusb33_reg: ldo-vusb33 {
regulator-name = "vusb33";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <264>;
};
};
rtc {
compatible = "mediatek,mt6357-rtc";
};
keys {
compatible = "mediatek,mt6357-keys";
key-power {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
key-home {
linux,keycodes = <KEY_HOME>;
wakeup-source;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6358.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2020 MediaTek Inc.
*/
#include <dt-bindings/input/input.h>
&pwrap {
pmic: pmic {
compatible = "mediatek,mt6358";
interrupt-controller;
#interrupt-cells = <2>;
pmic_adc: adc {
compatible = "mediatek,mt6358-auxadc";
#io-channel-cells = <1>;
};
mt6358codec: audio-codec {
compatible = "mediatek,mt6358-sound";
mediatek,dmic-mode = <0>; /* two-wires */
};
mt6358regulator: regulators {
compatible = "mediatek,mt6358-regulator";
mt6358_vdram1_reg: buck_vdram1 {
regulator-name = "vdram1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2087500>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
regulator-allowed-modes = <0 1>;
};
mt6358_vcore_reg: buck_vcore {
regulator-name = "vcore";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <200>;
regulator-always-on;
regulator-allowed-modes = <0 1>;
};
mt6358_vpa_reg: buck_vpa {
regulator-name = "vpa";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3650000>;
regulator-ramp-delay = <50000>;
regulator-enable-ramp-delay = <250>;
regulator-allowed-modes = <0 1>;
};
mt6358_vproc11_reg: buck_vproc11 {
regulator-name = "vproc11";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <200>;
regulator-always-on;
regulator-allowed-modes = <0 1>;
};
mt6358_vproc12_reg: buck_vproc12 {
regulator-name = "vproc12";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <200>;
regulator-always-on;
regulator-allowed-modes = <0 1>;
};
mt6358_vgpu_reg: buck_vgpu {
regulator-name = "vgpu";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1>;
};
mt6358_vs2_reg: buck_vs2 {
regulator-name = "vs2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2087500>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
};
mt6358_vmodem_reg: buck_vmodem {
regulator-name = "vmodem";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <900>;
regulator-always-on;
regulator-allowed-modes = <0 1>;
};
mt6358_vs1_reg: buck_vs1 {
regulator-name = "vs1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <2587500>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
};
mt6358_vdram2_reg: ldo_vdram2 {
regulator-name = "vdram2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <3300>;
};
mt6358_vsim1_reg: ldo_vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <540>;
};
mt6358_vibr_reg: ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <60>;
};
mt6358_vrf12_reg: ldo_vrf12 {
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <120>;
};
mt6358_vio18_reg: ldo_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <2700>;
regulator-always-on;
};
mt6358_vusb_reg: ldo_vusb {
regulator-name = "vusb";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <270>;
regulator-always-on;
};
mt6358_vcamio_reg: ldo_vcamio {
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <325>;
};
mt6358_vcamd_reg: ldo_vcamd {
regulator-name = "vcamd";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <325>;
};
mt6358_vcn18_reg: ldo_vcn18 {
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vfe28_reg: ldo_vfe28 {
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
regulator-name = "vsram_proc11";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6358_vcn28_reg: ldo_vcn28 {
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vsram_others_reg: ldo_vsram_others {
regulator-name = "vsram_others";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6358_vsram_gpu_reg: ldo_vsram_gpu {
regulator-name = "vsram_gpu";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <240>;
};
mt6358_vxo22_reg: ldo_vxo22 {
regulator-name = "vxo22";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
regulator-enable-ramp-delay = <120>;
regulator-always-on;
};
mt6358_vefuse_reg: ldo_vefuse {
regulator-name = "vefuse";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vaux18_reg: ldo_vaux18 {
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vmch_reg: ldo_vmch {
regulator-name = "vmch";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <60>;
};
mt6358_vbif28_reg: ldo_vbif28 {
regulator-name = "vbif28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
regulator-name = "vsram_proc12";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6358_vcama1_reg: ldo_vcama1 {
regulator-name = "vcama1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <325>;
};
mt6358_vemc_reg: ldo_vemc {
regulator-name = "vemc";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <60>;
};
mt6358_vio28_reg: ldo_vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_va12_reg: ldo_va12 {
regulator-name = "va12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <270>;
regulator-always-on;
};
mt6358_vrf18_reg: ldo_vrf18 {
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <120>;
};
mt6358_vcn33_reg: ldo_vcn33 {
regulator-name = "vcn33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vcama2_reg: ldo_vcama2 {
regulator-name = "vcama2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <325>;
};
mt6358_vmc_reg: ldo_vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <60>;
};
mt6358_vldo28_reg: ldo_vldo28 {
regulator-name = "vldo28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vaud28_reg: ldo_vaud28 {
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vsim2_reg: ldo_vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <540>;
};
};
mt6358rtc: rtc {
compatible = "mediatek,mt6358-rtc";
};
mt6358keys: keys {
compatible = "mediatek,mt6358-keys";
power {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
home {
linux,keycodes = <KEY_HOME>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6359.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
*/
&pwrap {
pmic: pmic {
compatible = "mediatek,mt6359";
interrupt-controller;
#interrupt-cells = <2>;
#sound-dai-cells = <1>;
pmic_adc: adc {
compatible = "mediatek,mt6359-auxadc";
#io-channel-cells = <1>;
};
mt6359codec: audio-codec {
compatible = "mediatek,mt6359-codec";
};
regulators {
compatible = "mediatek,mt6359-regulator";
mt6359_vs1_buck_reg: buck_vs1 {
regulator-name = "vs1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2200000>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
};
mt6359_vgpu11_buck_reg: buck_vgpu11 {
regulator-name = "vgpu11";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vmodem_buck_reg: buck_vmodem {
regulator-name = "vmodem";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1100000>;
regulator-ramp-delay = <10760>;
regulator-enable-ramp-delay = <200>;
};
mt6359_vpu_buck_reg: buck_vpu {
regulator-name = "vpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vcore_buck_reg: buck_vcore {
regulator-name = "vcore";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vs2_buck_reg: buck_vs2 {
regulator-name = "vs2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1600000>;
regulator-enable-ramp-delay = <0>;
regulator-always-on;
};
mt6359_vpa_buck_reg: buck_vpa {
regulator-name = "vpa";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3650000>;
regulator-enable-ramp-delay = <300>;
};
mt6359_vproc2_buck_reg: buck_vproc2 {
regulator-name = "vproc2";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vproc1_buck_reg: buck_vproc1 {
regulator-name = "vproc1";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <200>;
regulator-allowed-modes = <0 1 2>;
};
mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {
regulator-name = "vcore_sshub";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
};
mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub {
regulator-name = "vgpu11_sshub";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
};
mt6359_vaud18_ldo_reg: ldo_vaud18 {
regulator-name = "vaud18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vsim1_ldo_reg: ldo_vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
};
mt6359_vibr_ldo_reg: ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
};
mt6359_vrf12_ldo_reg: ldo_vrf12 {
regulator-name = "vrf12";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
};
mt6359_vusb_ldo_reg: ldo_vusb {
regulator-name = "vusb";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <960>;
regulator-always-on;
};
mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
regulator-name = "vsram_proc2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6359_vio18_ldo_reg: ldo_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-enable-ramp-delay = <960>;
regulator-always-on;
};
mt6359_vcamio_ldo_reg: ldo_vcamio {
regulator-name = "vcamio";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
mt6359_vcn18_ldo_reg: ldo_vcn18 {
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vfe28_ldo_reg: ldo_vfe28 {
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <120>;
};
mt6359_vcn13_ldo_reg: ldo_vcn13 {
regulator-name = "vcn13";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1300000>;
};
mt6359_vcn33_1_ldo_reg: ldo_vcn33_1 {
regulator-name = "vcn33_1";
};
mt6359_vaux18_ldo_reg: ldo_vaux18 {
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6359_vsram_others_ldo_reg: ldo_vsram_others {
regulator-name = "vsram_others";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <5000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vefuse_ldo_reg: ldo_vefuse {
regulator-name = "vefuse";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2000000>;
};
mt6359_vxo22_ldo_reg: ldo_vxo22 {
regulator-name = "vxo22";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2200000>;
regulator-always-on;
};
mt6359_vrfck_ldo_reg: ldo_vrfck {
regulator-name = "vrfck";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1700000>;
};
mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {
regulator-name = "vrfck_1";
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1600000>;
};
mt6359_vbif28_ldo_reg: ldo_vbif28 {
regulator-name = "vbif28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vio28_ldo_reg: ldo_vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mt6359_vemc_ldo_reg: ldo_vemc {
regulator-name = "vemc";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3300000>;
};
mt6359_vemc_1_ldo_reg: ldo_vemc_1 {
regulator-name = "vemc_1";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
mt6359_vcn33_2_ldo_reg: ldo_vcn33_2 {
regulator-name = "vcn33_2";
};
mt6359_va12_ldo_reg: ldo_va12 {
regulator-name = "va12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
mt6359_va09_ldo_reg: ldo_va09 {
regulator-name = "va09";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1200000>;
};
mt6359_vrf18_ldo_reg: ldo_vrf18 {
regulator-name = "vrf18";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1810000>;
};
mt6359_vsram_md_ldo_reg: ldo_vsram_md {
regulator-name = "vsram_md";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <10760>;
regulator-enable-ramp-delay = <240>;
};
mt6359_vufs_ldo_reg: ldo_vufs {
regulator-name = "vufs";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
mt6359_vm18_ldo_reg: ldo_vm18 {
regulator-name = "vm18";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-always-on;
};
mt6359_vbbck_ldo_reg: ldo_vbbck {
regulator-name = "vbbck";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1200000>;
};
mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
regulator-name = "vsram_proc1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
regulator-ramp-delay = <7500>;
regulator-enable-ramp-delay = <240>;
regulator-always-on;
};
mt6359_vsim2_ldo_reg: ldo_vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3100000>;
};
mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
regulator-name = "vsram_others_sshub";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
};
};
mt6359rtc: rtc {
compatible = "mediatek,mt6358-rtc";
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6365.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2026 MediaTek Inc.
*/
#include "mt6359.dtsi"
&pmic {
compatible = "mediatek,mt6365", "mediatek,mt6359";
mt6365regulators: regulators {
compatible = "mediatek,mt6365-regulator", "mediatek,mt6359-regulator";
};
};
&pmic_adc {
compatible = "mediatek,mt6365-auxadc", "mediatek,mt6359-auxadc";
};
mt6365codec: &mt6359codec {
compatible = "mediatek,mt6365-codec", "mediatek,mt6359-codec";
};
mt6365rtc: &mt6359rtc {
compatible = "mediatek,mt6365-rtc", "mediatek,mt6358-rtc";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6380.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for MediaTek MT6380 regulator
*
* Copyright (c) 2018 MediaTek Inc.
* Author: Chenglin Xu <chenglin.xu@mediatek.com>
* Sean Wang <sean.wang@mediatek.com>
*/
&pwrap {
regulators {
compatible = "mediatek,mt6380-regulator";
mt6380_vcpu_reg: buck-vcore1 {
regulator-name = "vcore1";
regulator-min-microvolt = < 600000>;
regulator-max-microvolt = <1393750>;
regulator-ramp-delay = <6250>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vcore_reg: buck-vcore {
regulator-name = "vcore";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1393750>;
regulator-ramp-delay = <6250>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vrf_reg: buck-vrf {
regulator-name = "vrf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1575000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vm_reg: ldo-vm {
regulator-name = "vm";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_va_reg: ldo-va {
regulator-name = "va";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vphy_reg: ldo-vphy {
regulator-name = "vphy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vddr_reg: ldo-vddr {
regulator-name = "vddr";
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1840000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vt_reg: ldo-vt {
regulator-name = "vt";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*/
/dts-v1/;
#include "mt6755.dtsi"
/ {
model = "MediaTek MT6755 EVB";
chassis-type = "embedded";
compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6755.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt6755";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
};
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt6755-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200620 0 0x20>;
};
gic: interrupt-controller@10231000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10231000 0 0x1000>,
<0 0x10232000 0 0x2000>,
<0 0x10234000 0 0x2000>,
<0 0x10236000 0 0x2000>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6755-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6755-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
*/
/dts-v1/;
#include "mt6779.dtsi"
/ {
model = "MediaTek MT6779 EVB";
chassis-type = "embedded";
compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6779.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
*/
#include <dt-bindings/clock/mt6779-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
/ {
compatible = "mediatek,mt6779";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x100>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x200>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x300>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x400>;
};
cpu5: cpu@5 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x500>;
};
cpu6: cpu@6 {
device_type = "cpu";
compatible = "arm,cortex-a75";
enable-method = "psci";
reg = <0x600>;
};
cpu7: cpu@7 {
device_type = "cpu";
compatible = "arm,cortex-a75";
enable-method = "psci";
reg = <0x700>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c040000 0 0x200000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 \
&cpu2 &cpu3 &cpu4 &cpu5>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu6 &cpu7>;
};
};
};
sysirq: interrupt-controller@c53a650 {
compatible = "mediatek,mt6779-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x0c53a650 0 0x50>;
};
topckgen: clock-controller@10000000 {
compatible = "mediatek,mt6779-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao: clock-controller@10001000 {
compatible = "mediatek,mt6779-infracfg_ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6779-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11ea0000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rm",
"iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt",
"iocfg_lt", "iocfg_tl",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 210>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
apmixed: clock-controller@1000c000 {
compatible = "mediatek,mt6779-apmixed", "syscon";
reg = <0 0x1000c000 0 0xe00>;
#clock-cells = <1>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt6779-pwrap";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>;
clock-names = "spi", "wrap";
};
devapc: devapc@10207000 {
compatible = "mediatek,mt6779-devapc";
reg = <0 0x10207000 0 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
clock-names = "devapc-infra-clock";
};
uart0: serial@11002000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
clock-names = "baud", "bus";
status = "disabled";
};
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
#clock-cells = <1>;
};
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt6779-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt6779-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt6779-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: clock-controller@16000000 {
compatible = "mediatek,mt6779-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
vencsys: clock-controller@17000000 {
compatible = "mediatek,mt6779-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt6779-camsys", "syscon";
reg = <0 0x1a000000 0 0x10000>;
#clock-cells = <1>;
};
ipesys: clock-controller@1b000000 {
compatible = "mediatek,mt6779-ipesys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*/
/dts-v1/;
#include "mt6795.dtsi"
/ {
model = "MediaTek MT6795 Evaluation Board";
chassis-type = "embedded";
compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Collabora Ltd
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt6795.dtsi"
#include "mt6331.dtsi"
/ {
model = "Sony Xperia M5";
compatible = "sony,xperia-m5", "mediatek,mt6795";
chassis-type = "handset";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
mmc2 = &mmc2;
serial0 = &uart0;
serial1 = &uart1;
};
backlight_lcd0: backlight {
compatible = "led-backlight";
leds = <&disp_led_pwm>, <&pmic_bl_led>;
default-brightness-level = <300>;
};
led-controller-display {
compatible = "pwm-leds";
disp_led_pwm: led-0 {
label = "backlight-pwm";
pwms = <&pwm0 0 500000>;
max-brightness = <1024>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
/* preloader and bootloader regions cannot be touched */
preloader-region@44800000 {
reg = <0 0x44800000 0 0x100000>;
no-map;
};
bootloader-region@46000000 {
reg = <0 0x46000000 0 0x400000>;
no-map;
};
};
vreg_disp_avdd: regulator-disp-avdd {
compatible = "regulator-fixed";
regulator-name = "disp_avdd";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 138 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vreg_disp_avee: regulator-disp-avee {
compatible = "regulator-fixed";
regulator-name = "disp_avee";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 139 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vreg_disp_vddh: regulator-disp-vddh {
compatible = "regulator-fixed";
regulator-name = "disp_vddh";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&dsi0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
panel: panel@0 {
compatible = "sharp,ls060t1sx01";
reg = <0>;
avdd-supply = <&vreg_disp_avdd>;
avee-supply = <&vreg_disp_avee>;
vddi-supply = <&mt6331_vgp3_reg>;
vddh-supply = <&vreg_disp_vddh>;
reset-gpios = <&pio 106 GPIO_ACTIVE_LOW>;
backlight = <&backlight_lcd0>;
pinctrl-0 = <&disp_rst_pins>;
pinctrl-names = "default";
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
port {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&fhctl {
clocks = <&apmixedsys CLK_APMIXED_MAINPLL>, <&apmixedsys CLK_APMIXED_MPLL>,
<&apmixedsys CLK_APMIXED_MSDCPLL>;
mediatek,hopping-ssc-percent = <8>, <5>, <8>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
accelerometer@10 {
compatible = "bosch,bma255";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&accel_pins>;
};
magnetometer@12 {
compatible = "bosch,bmm150";
reg = <0x12>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
touchscreen@20 {
compatible = "syna,rmi4-i2c";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&ts_pins>;
syna,startup-delay-ms = <160>;
syna,reset-delay-ms = <90>;
rmi4-f01@1 {
reg = <0x1>;
syna,nosleep-mode = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
status = "okay";
pn547: nfc@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&nfc_pins>;
enable-gpios = <&pio 149 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&pio 94 GPIO_ACTIVE_HIGH>;
};
proximity@48 {
compatible = "sensortek,stk3310";
reg = <0x48>;
interrupts-extended = <&pio 8 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&proximity_pins>;
};
};
&mmc0 {
/* eMMC controller */
mediatek,latch-ck = <4>; /* hs400 */
mediatek,hs200-cmd-int-delay = <1>;
mediatek,hs400-cmd-int-delay = <1>;
mediatek,hs400-ds-dly3 = <0x1a>;
non-removable;
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <&mt6331_vemc33_reg>;
vqmmc-supply = <&mt6331_vio18_reg>;
status = "okay";
};
&mmc1 {
/* MicroSD card slot */
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_uhs>;
vmmc-supply = <&mt6331_vmc_reg>;
vqmmc-supply = <&mt6331_vmch_reg>;
status = "okay";
};
&mmc2 {
/* SDIO WiFi on MMC2 */
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_uhs>;
vmmc-supply = <&mt6331_vmc_reg>;
vqmmc-supply = <&mt6331_vmch_reg>;
status = "okay";
};
&mt6331_vgp3_reg {
regulator-min-microvolt = <1800000>;
};
&pio {
disp_rst_pins: lcm-pins {
pins-rst {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
};
};
mmc0_pins_default: emmc-sdr-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
};
mmc0_pins_uhs: emmc-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-ds {
pinmux = <PINMUX_GPIO164__FUNC_MSDC0_DSL>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
mmc1_pins_default: microsd-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO172__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO173__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO174__FUNC_MSDC1_DAT3>,
<PINMUX_GPIO170__FUNC_MSDC1_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
drive-strength = <4>;
};
pins-clk {
pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
drive-strength = <4>;
};
};
mmc1_pins_uhs: microsd-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO172__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO173__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO174__FUNC_MSDC1_DAT3>,
<PINMUX_GPIO170__FUNC_MSDC1_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
drive-strength = <6>;
};
pins-clk {
pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
drive-strength = <8>;
};
};
mmc2_pins_default: sdio-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>,
<PINMUX_GPIO101__FUNC_MSDC2_DAT1>,
<PINMUX_GPIO102__FUNC_MSDC2_DAT2>,
<PINMUX_GPIO103__FUNC_MSDC2_DAT3>,
<PINMUX_GPIO105__FUNC_MSDC2_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
drive-strength = <4>;
};
pins-clk {
pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
drive-strength = <4>;
};
};
mmc2_pins_uhs: sdio-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>,
<PINMUX_GPIO101__FUNC_MSDC2_DAT1>,
<PINMUX_GPIO102__FUNC_MSDC2_DAT2>,
<PINMUX_GPIO103__FUNC_MSDC2_DAT3>,
<PINMUX_GPIO105__FUNC_MSDC2_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
drive-strength = <8>;
};
pins-clk {
pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
drive-strength = <8>;
};
};
nfc_pins: nfc-pins {
pins-irq {
pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
bias-pull-down;
input-enable;
};
pins-fw-ven {
pinmux = <PINMUX_GPIO94__FUNC_GPIO94>,
<PINMUX_GPIO149__FUNC_GPIO149>;
};
};
ts_pins: touchscreen-pins {
pins-irq {
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
bias-pull-up;
input-enable;
};
pins-rst {
pinmux = <PINMUX_GPIO102__FUNC_GPIO102>;
output-high;
};
};
proximity_pins: proximity-pins {
pins-irq {
pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
bias-pull-up;
input-enable;
};
};
accel_pins: accelerometer-pins {
pins-irq {
pinmux = <PINMUX_GPIO12__FUNC_GPIO12>;
bias-pull-up;
input-enable;
};
};
i2c0_pins: i2c0-pins {
pins-bus {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
<PINMUX_GPIO46__FUNC_SCL0>;
input-enable;
};
};
i2c1_pins: i2c1-pins {
pins-bus {
pinmux = <PINMUX_GPIO125__FUNC_SDA1>,
<PINMUX_GPIO126__FUNC_SCL1>;
bias-disable;
};
};
i2c2_pins: i2c2-pins {
pins-bus {
pinmux = <PINMUX_GPIO43__FUNC_SDA2>,
<PINMUX_GPIO44__FUNC_SCL2>;
bias-disable;
};
};
i2c3_pins: i2c3-pins {
pins-bus {
pinmux = <PINMUX_GPIO136__FUNC_SDA3>,
<PINMUX_GPIO137__FUNC_SCL3>;
bias-disable;
};
};
i2c4_pins: i2c4-pins {
pins-bus {
pinmux = <PINMUX_GPIO100__FUNC_SDA4>,
<PINMUX_GPIO101__FUNC_SCL4>;
bias-disable;
};
};
uart0_pins: uart0-pins {
pins-rx {
pinmux = <PINMUX_GPIO113__FUNC_URXD0>;
bias-pull-up;
input-enable;
};
pins-tx {
pinmux = <PINMUX_GPIO114__FUNC_UTXD0>;
output-high;
};
};
uart2_pins: uart2-pins {
pins-rx {
pinmux = <PINMUX_GPIO31__FUNC_URXD2>;
bias-pull-up;
input-enable;
};
pins-tx {
pinmux = <PINMUX_GPIO32__FUNC_UTXD2>;
};
};
};
&pmic {
/*
* Smartphones, including the Xperia M5, are equipped with a companion
* MT6332 PMIC: when this is present, the main MT6331 PMIC will fire
* an interrupt on the companion, so we use the MT6332 IRQ GPIO.
*/
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
leds {
compatible = "mediatek,mt6332-led";
#address-cells = <1>;
#size-cells = <0>;
pmic_bl_led: led@0 {
reg = <0>;
label = "backlight-pmic";
};
};
};
&pwm0 {
status = "okay";
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+1004
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*/
/dts-v1/;
#include "mt6797.dtsi"
/ {
model = "MediaTek MT6797 Evaluation Board";
chassis-type = "embedded";
compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
chosen {};
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
+85
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@@ -0,0 +1,85 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for MediaTek X20 Development Board
*
* Copyright (C) 2018, Linaro Ltd.
*
*/
/dts-v1/;
#include "mt6797.dtsi"
/ {
model = "Mediatek X20 Development Board";
chassis-type = "embedded";
compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
aliases {
serial0 = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
/* HDMI */
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
/* HS - I2C2 */
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
/* HS - I2C3 */
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins_a>;
status = "okay";
};
/* LS - I2C0 */
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
status = "okay";
};
/* LS - I2C1 */
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
status = "okay";
};
/* POWER_VPROC */
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins_a>;
status = "okay";
};
/* FAN53555 */
&i2c7 {
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pins_a>;
status = "okay";
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+473
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*/
#include <dt-bindings/clock/mt6797-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
/ {
compatible = "mediatek,mt6797";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
};
cpu8: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
reg = <0x200>;
};
cpu9: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
reg = <0x201>;
};
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
topckgen: topckgen@10000000 {
compatible = "mediatek,mt6797-topckgen";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infrasys: syscon@10001000 {
compatible = "mediatek,mt6797-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart0_pins_a: uart0-pins {
pins-bus {
pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
<MT6797_GPIO235__FUNC_URXD0>;
};
};
uart1_pins_a: uart1-pins {
pins-bus {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
i2c0_pins_a: i2c0-pins {
pins-bus {
pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
<MT6797_GPIO38__FUNC_SDA0_0>;
};
};
i2c1_pins_a: i2c1-pins {
pins-bus {
pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
<MT6797_GPIO56__FUNC_SDA1_0>;
};
};
i2c2_pins_a: i2c2-pins {
pins-bus {
pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
<MT6797_GPIO95__FUNC_SDA2_0>;
};
};
i2c3_pins_a: i2c3-pins {
pins-bus {
pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
<MT6797_GPIO74__FUNC_SCL3_0>;
};
};
i2c4_pins_a: i2c4-pins {
pins-bus {
pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
<MT6797_GPIO239__FUNC_SCL4_0>;
};
};
i2c5_pins_a: i2c5-pins {
pins-bus {
pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
<MT6797_GPIO241__FUNC_SCL5_0>;
};
};
i2c6_pins_a: i2c6-pins {
pins-bus {
pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
<MT6797_GPIO151__FUNC_SCL6_0>;
};
};
i2c7_pins_a: i2c7-pins {
pins-bus {
pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
<MT6797_GPIO153__FUNC_SCL7_0>;
};
};
};
scpsys: power-controller@10006000 {
compatible = "mediatek,mt6797-scpsys";
#power-domain-cells = <1>;
reg = <0 0x10006000 0 0x1000>;
clocks = <&topckgen CLK_TOP_MUX_MFG>,
<&topckgen CLK_TOP_MUX_MM>,
<&topckgen CLK_TOP_MUX_VDEC>;
clock-names = "mfg", "mm", "vdec";
infracfg = <&infrasys>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
apmixedsys: apmixed@1000c000 {
compatible = "mediatek,mt6797-apmixedsys";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220620 0 0x20>,
<0 0x10220690 0 0x10>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART0>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART1>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART2>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART3>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11007000 0 0x1000>,
<0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C0>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11008000 0 0x1000>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C1>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@11009000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11009000 0 0x1000>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C2>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C2_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@1100d000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x1100d000 0 0x1000>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C3>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C3_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@1100e000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x1100e000 0 0x1000>,
<0 0x11000500 0 0x80>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C_APPM>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@11010000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11010000 0 0x1000>,
<0 0x11000580 0 0x80>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@11011000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11011000 0 0x1000>,
<0 0x11000300 0 0x80>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C4>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11013000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11013000 0 0x1000>,
<0 0x11000400 0 0x80>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C2_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@11014000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11014000 0 0x1000>,
<0 0x11000480 0 0x80>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
<&infrasys CLK_INFRA_AP_DMA>,
<&infrasys CLK_INFRA_I2C3_ARB>;
clock-names = "main", "dma", "arb";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@1101c000 {
compatible = "mediatek,mt6797-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x1101c000 0 0x1000>,
<0 0x11000380 0 0x80>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_I2C5>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <10>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt6797-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys: syscon@15000000 {
compatible = "mediatek,mt6797-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt6797-vdecsys", "syscon";
reg = <0 0x16000000 0 0x10000>;
#clock-cells = <1>;
};
vencsys: syscon@17000000 {
compatible = "mediatek,mt6797-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
gic: interrupt-controller@19000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
reg = <0 0x19000000 0 0x10000>, /* GICD */
<0 0x19200000 0 0x200000>, /* GICR */
<0 0x10240000 0 0x2000>; /* GICC */
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h
+1201
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt6893-pinfunc.h
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+647
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/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
/ {
model = "Bananapi BPI-R64";
chassis-type = "embedded";
compatible = "bananapi,bpi-r64", "mediatek,mt7622";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
};
cpus {
cpu@0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
cpu@1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
};
gpio-keys {
compatible = "gpio-keys";
factory-key {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
wps-key {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 102 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
label = "bpi-r64:pio:green";
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-1 {
label = "bpi-r64:pio:red";
color = <LED_COLOR_ID_RED>;
gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&bch {
status = "disabled";
};
&btif {
status = "okay";
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@1f {
compatible = "mediatek,mt7531";
reg = <0x1f>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan0";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port@5 {
reg = <5>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc {
pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>;
status = "disabled";
};
&bch {
status = "okay";
};
&snfi {
pinctrl-names = "default";
pinctrl-0 = <&serial_nand_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
nand-ecc-engine = <&snfi>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "fip";
reg = <0x80000 0x200000>;
read-only;
};
ubi: partition@280000 {
label = "ubi";
reg = <0x280000 0x7d80000>;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&pio {
/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
* SATA functions. i.e. output-high: PCIe, output-low: SATA
*/
asm-sel-hog {
gpio-hog;
gpios = <90 GPIO_ACTIVE_HIGH>;
output-high;
};
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc";
groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
*/
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
};
emmc_pins_uhs: emmc-pins-uhs {
mux {
function = "emmc";
groups = "emmc";
};
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
drive-strength = <4>;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
drive-strength = <4>;
bias-pull-down;
};
};
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2s1_pins: i2s1-pins {
mux {
function = "i2s";
groups = "i2s_out_mclk_bclk_ws",
"i2s1_in_data",
"i2s1_out_data";
};
conf {
pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
"I2S_WS", "I2S_MCLK";
drive-strength = <12>;
bias-pull-down;
};
};
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
};
};
/* Parallel nand is shared pin with eMMC */
parallel_nand_pins: parallel-nand-pins {
mux {
function = "flash";
groups = "par_nand";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
"pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
"pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
"pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
"pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
"pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
};
};
wled_pins: wled-pins {
mux {
function = "led";
groups = "wled";
};
};
sd0_pins_default: sd0-pins-default {
mux {
function = "sd";
groups = "sd_0";
};
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
* DAT2, DAT3, CMD, CLK for SD respectively.
*/
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
drive-strength = <8>;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
drive-strength = <12>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
};
sd0_pins_uhs: sd0-pins-uhs {
mux {
function = "sd";
groups = "sd_0";
};
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
bias-pull-down;
};
};
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
spic0_pins: spic0-pins {
mux {
function = "spi";
groups = "spic0_0";
};
};
spic1_pins: spic1-pins {
mux {
function = "spi";
groups = "spic1_0";
};
};
/* SPI-NOR is shared pin with serial NAND */
spi_nor_pins: spi-nor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
/* serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_1_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&sata {
status = "disabled";
};
&sata_phy {
status = "disabled";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spic0_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic1_pins>;
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&u3phy {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&wmac {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+595
View File
@@ -0,0 +1,595 @@
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ming Huang <ming.huang@mediatek.com>
* Sean Wang <sean.wang@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
/ {
model = "MediaTek MT7622 RFB1 board";
chassis-type = "embedded";
compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
};
cpus {
cpu@0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
cpu@1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
};
gpio-keys {
compatible = "gpio-keys";
key-factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 0 0>;
};
key-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 102 0>;
};
};
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
device_type = "memory";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&bch {
status = "disabled";
};
&btif {
status = "okay";
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
reset-gpios = <&pio 54 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc {
pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>;
status = "disabled";
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&spi_nor_pins>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&pio {
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc";
groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
*/
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
};
emmc_pins_uhs: emmc-pins-uhs {
mux {
function = "emmc";
groups = "emmc";
};
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
drive-strength = <4>;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
drive-strength = <4>;
bias-pull-down;
};
};
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2s1_pins: i2s1-pins {
mux {
function = "i2s";
groups = "i2s_out_mclk_bclk_ws",
"i2s1_in_data",
"i2s1_out_data";
};
conf {
pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
"I2S_WS", "I2S_MCLK";
drive-strength = <12>;
bias-pull-down;
};
};
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
};
};
/* Parallel nand is shared pin with eMMC */
parallel_nand_pins: parallel-nand-pins {
mux {
function = "flash";
groups = "par_nand";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
pwm7_pins: pwm1-2-pins {
mux {
function = "pwm";
groups = "pwm_ch7_2";
};
};
wled_pins: wled-pins {
mux {
function = "led";
groups = "wled";
};
};
sd0_pins_default: sd0-pins-default {
mux {
function = "sd";
groups = "sd_0";
};
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
* DAT2, DAT3, CMD, CLK for SD respectively.
*/
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
drive-strength = <8>;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
drive-strength = <12>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
};
sd0_pins_uhs: sd0-pins-uhs {
mux {
function = "sd";
groups = "sd_0";
};
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
bias-pull-down;
};
};
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
spic0_pins: spic0-pins {
mux {
function = "spi";
groups = "spic0_0";
};
};
spic1_pins: spic1-pins {
mux {
function = "spi";
groups = "spic1_0";
};
};
/* SPI-NOR is shared pin with serial NAND */
spi_nor_pins: spi-nor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
/* serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_1_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
wmac_pins: wmac-pins {
mux {
function = "antsel";
groups = "antsel0", "antsel1", "antsel2", "antsel3",
"antsel4", "antsel5", "antsel6", "antsel7",
"antsel8", "antsel9", "antsel12", "antsel13",
"antsel14", "antsel15", "antsel16", "antsel17";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&sata {
status = "okay";
};
&sata_phy {
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spic0_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic1_pins>;
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&u3phy {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
&wmac {
pinctrl-names = "default";
pinctrl-0 = <&wmac_pins>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7981b.dtsi"
/ {
compatible = "cudy,wr3000-v1", "mediatek,mt7981b";
model = "Cudy WR3000 V1";
memory@40000000 {
reg = <0 0x40000000 0 0x10000000>;
device_type = "memory";
};
keys {
compatible = "gpio-keys";
key-wps {
label = "WPS";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
key-reset {
label = "RESET";
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WAN;
gpios = <&pio 5 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN_2GHZ;
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN_5GHZ;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
led-3 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_LAN;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led-4 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WAN_ONLINE;
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include "mt7981b.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "dt-bindings/pinctrl/mt65xx.h"
/ {
compatible = "openwrt,one", "mediatek,mt7981b";
model = "OpenWrt One";
aliases {
ethernet0 = &gmac1;
ethernet1 = &gmac0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
pwm-leds {
compatible = "pwm-leds";
led-0 {
color = <LED_COLOR_ID_WHITE>;
default-brightness = <0>;
function = LED_FUNCTION_STATUS;
max-brightness = <255>;
pwms = <&pwm 0 10000>;
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-brightness = <0>;
function = LED_FUNCTION_STATUS;
max-brightness = <255>;
pwms = <&pwm 1 10000>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
};
led-1 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_LAN;
gpios = <&pio 34 GPIO_ACTIVE_LOW>;
linux,default-trigger = "netdev";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
gpios = <&pio 35 GPIO_ACTIVE_LOW>;
linux,default-trigger = "netdev";
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&eth {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* WAN interface */
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
nvmem-cells = <&wan_factory_mac 0>;
nvmem-cell-names = "mac-address";
phy-mode = "2500base-x";
phy-handle = <&phy15>;
};
/* LAN interface */
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&int_gbe_phy>;
};
};
&mdio_bus {
phy15: ethernet-phy@f {
compatible = "ethernet-phy-id03a2.a411";
reg = <0xf>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
airoha,pnswap-rx;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_AMBER>;
};
led@1 {
reg = <1>;
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pio {
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0_0", "pwm1_1";
};
};
spi2_flash_pins: spi2-pins {
mux {
function = "spi";
groups = "spi2";
};
conf-pu {
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
drive-strength = <8>;
pins = "SPI2_CS", "SPI2_WP";
};
conf-pd {
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
drive-strength = <8>;
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
};
};
wifi_dbdc_pins: wifi-dbdc-pins {
mux {
function = "eth";
groups = "wf0_mode1";
};
conf {
pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
"WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
"WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
"WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
"WF_CBA_RESETB", "WF_DIG_RESETB";
drive-strength = <4>;
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000 0x40000>;
label = "bl2-nor";
};
partition@40000 {
reg = <0x40000 0xc0000>;
label = "factory";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
wifi_factory_calibration: eeprom@0 {
reg = <0x0 0x1000>;
};
wan_factory_mac: macaddr@24 {
reg = <0x24 0x6>;
compatible = "mac-base";
#nvmem-cell-cells = <1>;
};
};
};
partition@100000 {
reg = <0x100000 0x80000>;
label = "fip-nor";
};
partition@180000 {
reg = <0x180000 0xc80000>;
label = "recovery";
};
};
};
};
&sgmiisys0 {
mediatek,pnswap;
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&wifi {
nvmem-cells = <&wifi_factory_calibration>;
nvmem-cell-names = "eeprom";
pinctrl-names = "dbdc";
pinctrl-0 = <&wifi_dbdc_pins>;
status = "okay";
};
&xhci {
phys = <&u2port0 PHY_TYPE_USB2>;
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
mediatek,u3p-dis-msk = <0x01>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7981b.dtsi"
/ {
compatible = "xiaomi,ax3000t", "mediatek,mt7981b";
model = "Xiaomi AX3000T";
memory@40000000 {
reg = <0 0x40000000 0 0x10000000>;
device_type = "memory";
};
keys {
compatible = "gpio-keys";
key-mesh {
label = "MESH";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_9>;
linux,input-type = <EV_SW>;
};
key-reset {
label = "RESET";
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt7986-resets.h>
/ {
compatible = "mediatek,mt7981b";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
};
};
oscillator-40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "clkxtal";
#clock-cells = <0>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
wo_boot: wo-boot@15194000 {
reg = <0 0x15194000 0 0x1000>;
no-map;
};
wo_ilm0: wo-ilm@151e0000 {
reg = <0 0x151e0000 0 0x8000>;
no-map;
};
wo_dlm0: wo-dlm@151e8000 {
reg = <0 0x151e8000 0 0x2000>;
no-map;
};
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
wmcpu_emi: wmcpu-reserved@47c80000 {
reg = <0 0x47c80000 0 0x100000>;
no-map;
};
wo_emi0: wo-emi@47d80000 {
reg = <0 0x47d80000 0 0x40000>;
no-map;
};
wo_data: wo-data@47dc0000 {
reg = <0 0x47dc0000 0 0x240000>;
no-map;
};
};
soc {
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c080000 0 0x200000>; /* GICR */
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt7981-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: clock-controller@1001b000 {
compatible = "mediatek,mt7981-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
apmixedsys: clock-controller@1001e000 {
compatible = "mediatek,mt7981-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7981-pwm";
reg = <0 0x10048000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_PWM_STA>,
<&infracfg CLK_INFRA_PWM_HCK>,
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
#pwm-cells = <2>;
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
reg = <0 0x10060000 0 0x1000>;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
crypto@10320000 {
compatible = "mediatek,mt7981-crypto",
"inside-secure,safexcel-eip97ies";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&topckgen CLK_TOP_EIP97B>;
clock-names = "core";
assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart", "wakeup";
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
<&infracfg CLK_INFRA_UART0_CK>;
clock-names = "baud", "bus";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart", "wakeup";
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
<&infracfg CLK_INFRA_UART1_CK>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart", "wakeup";
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
<&infracfg CLK_INFRA_UART2_CK>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c@11007000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11007000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
<&infracfg CLK_INFRA_AP_DMA_CK>,
<&infracfg CLK_INFRA_I2C_MCK_CK>,
<&infracfg CLK_INFRA_I2C_PCK_CK>;
clock-names = "main", "dma", "arb", "pmic";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@11009000 {
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x11009000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2_CK>,
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi@1100a000 {
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi@1100b000 {
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI1_CK>,
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
thermal@1100c800 {
compatible = "mediatek,mt7981-thermal",
"mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>;
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
};
auxadc: adc@1100d000 {
compatible = "mediatek,mt7981-auxadc",
"mediatek,mt7986-auxadc";
reg = <0 0x1100d000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
xhci: usb@11200000 {
compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
<&infracfg CLK_INFRA_IUSB_CK>,
<&infracfg CLK_INFRA_IUSB_133_CK>,
<&infracfg CLK_INFRA_IUSB_66M_CK>,
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
status = "disabled";
};
pcie: pcie@11280000 {
compatible = "mediatek,mt7981-pcie",
"mediatek,mt8192-pcie";
reg = <0 0x11280000 0 0x4000>;
reg-names = "pcie-mac";
ranges = <0x82000000 0 0x20000000
0x0 0x20000000 0 0x10000000>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>;
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
device_type = "pci";
phys = <&u3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
status = "disabled";
pcie_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
<0 0x11c00000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x11f10000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
"iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
gpio-ranges = <&pio 0 0 57>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0";
};
};
};
topmisc: topmisc@11d10000 {
compatible = "mediatek,mt7981-topmisc", "syscon";
reg = <0 0x11d10000 0 0x10000>;
#clock-cells = <1>;
};
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7981-tphy",
"mediatek,generic-tphy-v2";
ranges = <0 0 0x11e10000 0x1700>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
clock-names = "ref";
#phy-cells = <1>;
};
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,syscon-type = <&topmisc 0x218 0>;
};
};
efuse@11f20000 {
compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
soc-uuid@140 {
reg = <0x140 0x10>;
};
thermal_calibration: thermal-calib@274 {
reg = <0x274 0xc>;
};
phy_calibration: phy-calib@8dc {
reg = <0x8dc 0x10>;
};
};
ethsys: clock-controller@15000000 {
compatible = "mediatek,mt7981-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wed: wed@15010000 {
compatible = "mediatek,mt7981-wed",
"syscon";
reg = <0 0x15010000 0 0x1000>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
<&wo_data>, <&wo_boot>;
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
"wo-data", "wo-boot";
mediatek,wo-ccif = <&wo_ccif0>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7981-eth";
reg = <0 0x15100000 0 0x40000>;
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
<&topckgen CLK_TOP_CB_SGM_325M>;
clocks = <&ethsys CLK_ETH_FE_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_GP1_EN>,
<&ethsys CLK_ETH_WOCPU0_EN>,
<&topckgen CLK_TOP_SGM_REG>,
<&sgmiisys0 CLK_SGM0_TX_EN>,
<&sgmiisys0 CLK_SGM0_RX_EN>,
<&sgmiisys0 CLK_SGM0_CK0_EN>,
<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
<&sgmiisys1 CLK_SGM1_TX_EN>,
<&sgmiisys1 CLK_SGM1_RX_EN>,
<&sgmiisys1 CLK_SGM1_CK1_EN>,
<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
<&topckgen CLK_TOP_NETSYS_SEL>,
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
clock-names = "fe", "gp2", "gp1", "wocpu0",
"sgmii_ck",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"netsys0", "netsys1";
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
"pdma1", "pdma2", "pdma3";
sram = <&eth_sram>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,infracfg = <&topmisc>;
mediatek,wed = <&wed>;
status = "disabled";
mdio_bus: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
int_gbe_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
phy-mode = "gmii";
phy-is-integrated;
nvmem-cells = <&phy_calibration>;
nvmem-cell-names = "phy-cal-data";
};
};
};
eth_sram: sram@15140000 {
compatible = "mmio-sram";
reg = <0 0x15140000 0 0x40000>;
ranges = <0 0x15140000 0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
};
wo_ccif0: syscon@151a5000 {
compatible = "mediatek,mt7986-wo-ccif", "syscon";
reg = <0 0x151a5000 0 0x1000>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
};
wifi: wifi@18000000 {
compatible = "mediatek,mt7981-wmac";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
memory-region = <&wmcpu_emi>;
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7986a.dtsi"
/ {
compatible = "acelink,ew-7886cax", "mediatek,mt7986a";
model = "Acelink EW-7886CAX";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
device_type = "memory";
};
keys {
compatible = "gpio-keys";
key-restart {
label = "Reset";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
};
led-2 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
};
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy6>;
nvmem-cells = <&macaddr>;
nvmem-cell-names = "mac-address";
};
mdio-bus {
reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
reset-delay-us = <50000>;
reset-post-delay-us = <20000>;
#address-cells = <1>;
#size-cells = <0>;
phy6: phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <6>;
};
};
};
&pcie_phy {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x100000>;
label = "bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x80000>;
label = "u-boot-env";
};
partition@180000 {
compatible = "nvmem-cells";
reg = <0x180000 0x200000>;
label = "factory";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom: eeprom@0 {
reg = <0x0 0x1000>;
};
macaddr: macaddr@4 {
reg = <0x4 0x6>;
};
};
};
partition@380000 {
reg = <0x380000 0x200000>;
label = "fip";
};
partition@580000 {
reg = <0x580000 0x4000000>;
label = "ubi";
};
};
};
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
nvmem-cells = <&eeprom>;
nvmem-cell-names = "eeprom";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
};
&{/soc/mmc@11230000} {
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Authors: Frank Wunderlich <frank-w@public-files.de>
* Eric Woudstra <ericwouds@gmail.com>
* Tianling Shen <cnsztl@immortalwrt.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "Bananapi BPI-R3 Mini";
chassis-type = "embedded";
compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
chosen {
stdout-path = "serial0:115200n8";
};
dcin: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "12vd";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
/*
* The signal is inverted on this board and the PWM driver
* does not support polarity inversion.
*/
/* cooling level (0, 1, 2) */
cooling-levels = <255 96 0>;
pwms = <&pwm 0 10000>;
};
reg_1p8v: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1.8vd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_3p3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
usb_vbus: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&pio 20 GPIO_ACTIVE_LOW>;
regulator-boot-on;
};
en8811_a: regulator-phy1 {
compatible = "regulator-fixed";
regulator-name = "phy1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 16 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
en8811_b: regulator-phy2 {
compatible = "regulator-fixed";
regulator-name = "phy2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 17 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
leds {
compatible = "gpio-leds";
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
gpio-keys {
compatible = "gpio-keys";
reset-key {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
};
};
&cpu_thermal {
cooling-maps {
map0 {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>;
};
map1 {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_med>;
};
map2 {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_active_low>;
};
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
phy-handle = <&phy0>;
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy1>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
status = "okay";
/* MAC Address EEPROM */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
address-width = <8>;
pagesize = <8>;
size = <256>;
};
};
&mdio {
phy0: ethernet-phy@14 {
reg = <14>;
interrupts-extended = <&pio 48 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
phy-mode = "2500base-x";
full-duplex;
pause;
airoha,pnswap-rx;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 { /* en8811_a_gpio5 */
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 { /* en8811_a_gpio4 */
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
default-state = "keep";
};
};
};
phy1: ethernet-phy@15 {
reg = <15>;
interrupts-extended = <&pio 46 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
phy-mode = "2500base-x";
full-duplex;
pause;
airoha,pnswap-rx;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 { /* en8811_b_gpio5 */
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_WAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 { /* en8811_b_gpio4 */
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
function-enumerator = <2>;
default-state = "keep";
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
i2c_pins: i2c-pins {
mux {
function = "i2c";
groups = "i2c";
};
};
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0";
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
usb_ngff_pins: usb-ngff-pins {
ngff-gnss-off-conf {
pins = "GPIO_6";
drive-strength = <8>;
mediatek,pull-up-adv = <1>;
};
ngff-pe-rst-conf {
pins = "GPIO_7";
drive-strength = <8>;
mediatek,pull-up-adv = <1>;
};
ngff-wwan-off-conf {
pins = "GPIO_8";
drive-strength = <8>;
mediatek,pull-up-adv = <1>;
};
ngff-pwr-off-conf {
pins = "GPIO_9";
drive-strength = <8>;
mediatek,pull-up-adv = <1>;
};
ngff-rst-conf {
pins = "GPIO_10";
drive-strength = <8>;
mediatek,pull-up-adv = <1>;
};
ngff-coex-conf {
pins = "SPI1_CS";
drive-strength = <8>;
mediatek,pull-up-adv = <1>;
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_led_pins: wf-led-pins {
mux {
function = "led";
groups = "wifi_led";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <20000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&ssusb {
pinctrl-names = "default";
pinctrl-0 = <&usb_ngff_pins>;
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&usb_vbus>;
status = "okay";
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
led {
led-active-low;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Authors: Daniel Golle <daniel@makrotopia.org>
* Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
};
&{/soc/spi@1100a000} {
#address-cells = <1>;
#size-cells = <0>;
spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "reserved";
reg = <0x100000 0x280000>;
};
partition@380000 {
label = "fip";
reg = <0x380000 0x200000>;
read-only;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x7a80000>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Authors: Daniel Golle <daniel@makrotopia.org>
* Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
};
&{/soc/spi@1100a000} {
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "reserved2";
reg = <0x80000 0x80000>;
};
partition@100000 {
label = "fip";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "recovery";
reg = <0x180000 0xa80000>;
};
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
reg_sata12v: regulator-sata12v {
compatible = "regulator-fixed";
regulator-name = "sata12v";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&pio 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_sata5v: regulator-sata5v {
compatible = "regulator-fixed";
regulator-name = "sata5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_sata12v>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
};
&{/soc/mmc@11230000} {
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Authors: Sam.Shih <sam.shih@mediatek.com>
* Frank Wunderlich <frank-w@public-files.de>
* Daniel Golle <daniel@makrotopia.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "Bananapi BPI-R3";
chassis-type = "embedded";
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
chosen {
stdout-path = "serial0:115200n8";
};
dcin: regulator-12vd {
compatible = "regulator-fixed";
regulator-name = "12vd";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
/* cooling level (0, 1, 2) - pwm inverted */
cooling-levels = <255 40 0>;
pwms = <&pwm 0 10000>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
reset-key {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps-key {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
/* i2c of the left SFP cage (wan) */
i2c_sfp1: i2c-0 {
compatible = "i2c-gpio";
sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
};
/* i2c of the right SFP cage (lan) */
i2c_sfp2: i2c-1 {
compatible = "i2c-gpio";
sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
};
leds {
compatible = "gpio-leds";
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
blue_led: led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1.8vd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3.3vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
/* left SFP cage (wan) */
sfp1: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
};
/* right SFP cage (lan) */
sfp2: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp2>;
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
};
};
&cpu_thermal {
cooling-maps {
map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>;
};
map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_med>;
};
map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_active_low>;
};
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
sfp = <&sfp1>;
managed = "in-band-status";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
switch: switch@31 {
compatible = "mediatek,mt7531";
reg = <31>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
i2c_pins: i2c-pins {
mux {
function = "i2c";
groups = "i2c";
};
};
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1_0";
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_0";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1_rx_tx";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_0_rx_tx";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_led_pins: wf-led-pins {
mux {
function = "led";
groups = "wifi_led";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
status = "okay";
};
&ssusb {
status = "okay";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan0";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port5: port@5 {
reg = <5>;
label = "lan4";
phy-mode = "2500base-x";
sfp = <&sfp2>;
managed = "in-band-status";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
led {
led-active-low;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "MediaTek MT7986a RFB";
chassis-type = "embedded";
compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 0>;
};
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_2";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA";
drive-strength = <4>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
cs-gpios = <0>, <0>;
status = "okay";
};
&ssusb {
status = "okay";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+665
View File
@@ -0,0 +1,665 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt7986a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>;
};
};
clk40m: oscillator-40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
clock-output-names = "clkxtal";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
wmcpu_emi: wmcpu-reserved@4fc00000 {
no-map;
reg = <0 0x4fc00000 0 0x00100000>;
};
wo_emi0: wo-emi@4fd00000 {
reg = <0 0x4fd00000 0 0x40000>;
no-map;
};
wo_emi1: wo-emi@4fd40000 {
reg = <0 0x4fd40000 0 0x40000>;
no-map;
};
wo_ilm0: wo-ilm@151e0000 {
reg = <0 0x151e0000 0 0x8000>;
no-map;
};
wo_ilm1: wo-ilm@151f0000 {
reg = <0 0x151f0000 0 0x8000>;
no-map;
};
wo_data: wo-data@4fd80000 {
reg = <0 0x4fd80000 0 0x240000>;
no-map;
};
wo_dlm0: wo-dlm@151e8000 {
reg = <0 0x151e8000 0 0x2000>;
no-map;
};
wo_dlm1: wo-dlm@151f8000 {
reg = <0 0x151f8000 0 0x2000>;
no-map;
};
wo_boot: wo-boot@15194000 {
reg = <0 0x15194000 0 0x1000>;
no-map;
};
};
soc {
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
reg = <0 0x0c000000 0 0x10000>, /* GICD */
<0 0x0c080000 0 0x80000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7986-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {
compatible = "mediatek,mt7986-wed-pcie",
"syscon";
reg = <0 0x10003000 0 0x10>;
};
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7986-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
#clock-cells = <1>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
status = "disabled";
};
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7986-apmixedsys";
reg = <0 0x1001E000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@1001f000 {
compatible = "mediatek,mt7986a-pinctrl";
reg = <0 0x1001f000 0 0x1000>,
<0 0x11c30000 0 0x1000>,
<0 0x11c40000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e30000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x11f10000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
"iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 101>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7986-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&infracfg CLK_INFRA_PWM_STA>,
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys_0",
"syscon";
reg = <0 0x10060000 0 0x1000>;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7986-sgmiisys_1",
"syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
trng: rng@1020f000 {
compatible = "mediatek,mt7986-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&infracfg CLK_INFRA_TRNG_CK>;
clock-names = "rng";
status = "disabled";
};
crypto: crypto@10320000 {
compatible = "mediatek,mt7986-crypto", "inside-secure,safexcel-eip97ies";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&infracfg CLK_INFRA_EIP97_CK>;
assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
status = "disabled";
};
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
<&infracfg CLK_INFRA_UART0_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
<&infracfg CLK_INFRA_UART1_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
<&infracfg CLK_INFRA_UART2_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
status = "disabled";
};
i2c0: i2c@11008000 {
compatible = "mediatek,mt7986-i2c";
reg = <0 0x11008000 0 0x90>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <5>;
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
<&infracfg CLK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100a000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
spi1: spi@1100b000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100b000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPIM_MST_SEL>,
<&infracfg CLK_INFRA_SPI1_CK>,
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
status = "disabled";
};
thermal: thermal@1100c800 {
compatible = "mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>;
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
};
auxadc: adc@1100d000 {
compatible = "mediatek,mt7986-auxadc";
reg = <0 0x1100d000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
ssusb: usb@11200000 {
compatible = "mediatek,mt7986-xhci",
"mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
<&infracfg CLK_INFRA_IUSB_CK>,
<&infracfg CLK_INFRA_IUSB_133_CK>,
<&infracfg CLK_INFRA_IUSB_66M_CK>,
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
clock-names = "sys_ck",
"ref_ck",
"mcu_ck",
"dma_ck",
"xhci_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7986-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&topckgen CLK_TOP_EMMC_250M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
<&topckgen CLK_TOP_NET1PLL_D5_D2>;
clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
<&infracfg CLK_INFRA_MSDC_CK>,
<&infracfg CLK_INFRA_MSDC_133M_CK>,
<&infracfg CLK_INFRA_MSDC_66M_CK>;
clock-names = "source", "hclk", "source_cg", "bus_clk",
"sys_cg";
status = "disabled";
};
pcie: pcie@11280000 {
compatible = "mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
reg = <0x00 0x11280000 0x00 0x4000>;
reg-names = "pcie-mac";
ranges = <0x82000000 0x00 0x20000000 0x00
0x20000000 0x00 0x10000000>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>;
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
phys = <&pcie_port PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
pcie_phy: t-phy@11c00000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
ranges = <0 0 0x11c00000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
pcie_port: pcie-phy@0 {
reg = <0 0x20000>;
clocks = <&clk40m>;
clock-names = "ref";
#phy-cells = <1>;
};
};
efuse: efuse@11d00000 {
compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
reg = <0 0x11d00000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
soc-uuid@140 {
reg = <0x140 0x8>;
};
thermal_calibration: calib@274 {
reg = <0x274 0xc>;
};
};
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
ranges = <0 0 0x11e10000 0x1700>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u3port0: usb-phy@700 {
reg = <0x700 0x900>;
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
};
u2port1: usb-phy@1000 {
reg = <0x1000 0x700>;
clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
ethsys: syscon@15000000 {
compatible = "mediatek,mt7986-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wed0: wed@15010000 {
compatible = "mediatek,mt7986-wed",
"syscon";
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
<&wo_data>, <&wo_boot>;
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
"wo-data", "wo-boot";
mediatek,wo-ccif = <&wo_ccif0>;
};
wed1: wed@15011000 {
compatible = "mediatek,mt7986-wed",
"syscon";
reg = <0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
<&wo_data>, <&wo_boot>;
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
"wo-data", "wo-boot";
mediatek,wo-ccif = <&wo_ccif1>;
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7986-eth";
reg = <0 0x15100000 0 0x40000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
"pdma1", "pdma2", "pdma3";
clocks = <&ethsys CLK_ETH_FE_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_GP1_EN>,
<&ethsys CLK_ETH_WOCPU1_EN>,
<&ethsys CLK_ETH_WOCPU0_EN>,
<&sgmiisys0 CLK_SGMII0_TX250M_EN>,
<&sgmiisys0 CLK_SGMII0_RX250M_EN>,
<&sgmiisys0 CLK_SGMII0_CDR_REF>,
<&sgmiisys0 CLK_SGMII0_CDR_FB>,
<&sgmiisys1 CLK_SGMII1_TX250M_EN>,
<&sgmiisys1 CLK_SGMII1_RX250M_EN>,
<&sgmiisys1 CLK_SGMII1_CDR_REF>,
<&sgmiisys1 CLK_SGMII1_CDR_FB>,
<&topckgen CLK_TOP_NETSYS_SEL>,
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"netsys0", "netsys1";
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
sram = <&eth_sram>;
#address-cells = <1>;
#size-cells = <0>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,wed-pcie = <&wed_pcie>;
mediatek,wed = <&wed0>, <&wed1>;
status = "disabled";
};
/*15100000+0x40000*/
eth_sram: sram@15140000 {
compatible = "mmio-sram";
reg = <0 0x15140000 0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x15140000 0 0x40000>;
};
wo_ccif0: syscon@151a5000 {
compatible = "mediatek,mt7986-wo-ccif", "syscon";
reg = <0 0x151a5000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
};
wo_ccif1: syscon@151ad000 {
compatible = "mediatek,mt7986-wo-ccif", "syscon";
reg = <0 0x151ad000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};
wifi: wifi@18000000 {
compatible = "mediatek,mt7986-wmac";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wmcpu_emi>;
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <60000>;
hysteresis = <2000>;
type = "active";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986b.dtsi"
/ {
model = "MediaTek MT7986b RFB";
chassis-type = "embedded";
compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&pio {
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_2";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA";
drive-strength = <4>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
cs-gpios = <0>, <0>;
status = "okay";
};
&ssusb {
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
#include "mt7986a.dtsi"
/ {
compatible = "mediatek,mt7986b";
};
&pio {
compatible = "mediatek,mt7986b-pinctrl";
gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include "mt7988a-bananapi-bpi-r4.dtsi"
/ {
compatible = "bananapi,bpi-r4-2g5", "bananapi,bpi-r4", "mediatek,mt7988a";
model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)";
chassis-type = "embedded";
};
&gmac1 {
phy = <&int_2p5g_phy>;
phy-mode = "internal";
status = "okay";
};
&int_2p5g_phy {
pinctrl-0 = <&i2p5gbe_led0_pins>;
pinctrl-names = "i2p5gbe-led";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
};
&{/soc/mmc@11230000} {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_emmc_51>;
pinctrl-1 = <&mmc0_pins_emmc_51>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x12814>;
vqmmc-supply = <&reg_1p8v>;
vmmc-supply = <&reg_3p3v>;
non-removable;
no-sd;
no-sdio;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
#include "mt7988a-bananapi-bpi-r4-pro.dtsi"
/ {
model = "Bananapi BPI-R4 Pro 4E";
compatible = "bananapi,bpi-r4-pro-4e",
"bananapi,bpi-r4-pro",
"mediatek,mt7988a";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
#include "mt7988a-bananapi-bpi-r4-pro.dtsi"
/ {
model = "Bananapi BPI-R4 Pro 8X";
compatible = "bananapi,bpi-r4-pro-8x",
"bananapi,bpi-r4-pro",
"mediatek,mt7988a";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/* This enables key-m slot CN13 on pcie2(11280000 1L0) on BPI-R4-Pro */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/pinctrl@1001f000/pcie-2-hog} {
output-high;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/* This enables key-m slot CN14 on pcie3(11290000 1L1) on BPI-R4-Pro */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/pinctrl@1001f000/pcie-3-hog} {
output-high;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/* This enables key-b slot CN15 on pcie2(11280000 1L0) on BPI-R4-Pro */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/pinctrl@1001f000/pcie-2-hog} {
output-low;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/* This enables key-b slot CN18 on pcie3(11290000 1L1) on BPI-R4-Pro */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/pinctrl@1001f000/pcie-3-hog} {
output-low;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/mmc@11230000} {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_emmc_51>;
pinctrl-1 = <&mmc0_pins_emmc_51>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x12814>;
vqmmc-supply = <&reg_1p8v>;
vmmc-supply = <&reg_3p3v>;
non-removable;
no-sd;
no-sdio;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/mmc@11230000} {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_sdcard>;
pinctrl-1 = <&mmc0_pins_sdcard>;
cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <48000000>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
no-mmc;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
#include "mt7988a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
/ {
aliases {
ethernet0 = &gmac0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
/* PCA9548 (0-0070) provides 4 i2c channels */
i2c3 = &imux0;
i2c4 = &imux1_sfp1;
i2c5 = &imux2_sfp2;
i2c6 = &imux3_wifi;
};
chosen {
stdout-path = &serial0;
};
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
cooling-levels = <0 80 128 255>;
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
pwms = <&pwm 0 50000>;
#cooling-cells = <2>;
};
gpio-keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
gpios = <&pio 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
button-wps {
label = "WPS";
gpios = <&pio 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
gpio-leds {
compatible = "gpio-leds";
led_red: sys-led-red {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_FAULT;
gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>;
};
led_blue: sys-led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_ACTIVITY;
gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>;
};
};
reg_1p8v: regulator-dvdd1v8 {
compatible = "regulator-fixed";
regulator-name = "DVDD1V8_SOC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3v3vd {
compatible = "regulator-fixed";
regulator-name = "3V3VD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* SFP1 cage (LAN) */
sfp1: sfp1 {
compatible = "sff,sfp";
i2c-bus = <&imux1_sfp1>;
los-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 21 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
/* SFP2 cage (WAN) */
sfp2: sfp2 {
compatible = "sff,sfp";
i2c-bus = <&imux2_sfp2>;
los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
&cci {
proc-supply = <&rt5190_buck3>;
};
&cpu0 {
proc-supply = <&rt5190_buck3>;
};
&cpu1 {
proc-supply = <&rt5190_buck3>;
};
&cpu2 {
proc-supply = <&rt5190_buck3>;
};
&cpu3 {
proc-supply = <&rt5190_buck3>;
};
&cpu_thermal {
trips {
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <40000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>;
};
map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
};
};
&eth {
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
status = "okay";
};
&gmac0 {
status = "okay";
};
&gsw_phy0 {
pinctrl-0 = <&gbe0_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy0_led0 {
color = <LED_COLOR_ID_YELLOW>;
status = "okay";
};
&gsw_port0 {
label = "lan5";
};
/* R4Pro has only port 0 connected, so disable the others */
&gsw_phy1 {
status = "disabled";
};
&gsw_port1 {
status = "disabled";
};
&gsw_phy2 {
status = "disabled";
};
&gsw_port2 {
status = "disabled";
};
&gsw_phy3 {
status = "disabled";
};
&gsw_port3 {
status = "disabled";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
rt5190a_64: rt5190a@64 {
compatible = "richtek,rt5190a";
reg = <0x64>;
vin2-supply = <&rt5190_buck1>;
vin3-supply = <&rt5190_buck1>;
vin4-supply = <&rt5190_buck1>;
regulators {
rt5190_buck1: buck1 {
regulator-name = "rt5190a-buck1";
regulator-min-microvolt = <5090000>;
regulator-max-microvolt = <5090000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
buck2 {
regulator-name = "vcore";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
rt5190_buck3: buck3 {
regulator-name = "vproc";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
buck4 {
regulator-name = "rt5190a-buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
ldo {
regulator-name = "rt5190a-ldo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_1_pins>;
pinctrl-names = "default";
status = "okay";
pca9545: i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
imux0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: i2c-gpio-expander@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
address-width = <8>;
pagesize = <8>;
size = <256>;
};
};
imux1_sfp1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
imux2_sfp2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
imux3_wifi: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* mPCIe SIM2 (11300000) */
&pcie0 {
status = "okay";
};
/* mPCIe (11310000 near leds) SIM3 */
&pcie1 {
status = "okay";
};
/* M.2 (11280000) 1L0 key-m SSD1 CN13 / key-b SIM1 CN15 */
&pcie2 {
status = "okay";
};
/* M.2 (11290000) 1L1 key-m SSD2 CN14 / key-b SIM2 CN18 */
&pcie3 {
status = "okay";
};
&pio {
gbe0_led0_pins: gbe0-led0-pins {
mux {
function = "led";
groups = "gbe0_led0";
};
};
i2c0_pins: i2c0-g0-pins {
mux {
function = "i2c";
groups = "i2c0_1";
};
};
i2c1_pins: i2c1-g0-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_1_pins: i2c2-g1-pins {
mux {
function = "i2c";
groups = "i2c2_1";
};
};
mdio0_pins: mdio0-pins {
mux {
function = "eth";
groups = "mdc_mdio0";
};
conf {
pins = "SMI_0_MDC", "SMI_0_MDIO";
drive-strength = <8>;
};
};
mmc0_pins_emmc_51: mmc0-emmc-51-pins {
mux {
function = "flash";
groups = "emmc_51";
};
};
mmc0_pins_sdcard: mmc0-sdcard-pins {
mux {
function = "flash";
groups = "sdcard";
};
};
/* 1L0 0=key-b (CN15), 1=key-m (CN13) */
pcie-2-hog {
gpio-hog;
gpios = <79 GPIO_ACTIVE_HIGH>;
};
/* 1L1 0=key-b (CN18), 1=key-m (CN14) */
pcie-3-hog {
gpio-hog;
gpios = <63 GPIO_ACTIVE_HIGH>;
};
pwm0_pins: pwm0-pins {
mux {
groups = "pwm0";
function = "pwm";
};
};
spi0_flash_pins: spi0-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
};
&pwm {
status = "okay";
};
&serial0 {
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_flash_pins>;
pinctrl-names = "default";
status = "okay";
spi_nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&spi_nand {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x200000>;
label = "bl2";
};
partition@200000 {
compatible = "linux,ubi";
reg = <0x200000 0xfe00000>;
label = "ubi";
};
};
};
/* back USB */
&ssusb0 {
/* Use U2P only instead of both U3P/U2P due to U3P serdes shared with pcie2 */
phys = <&xphyu2port0 PHY_TYPE_USB2>;
mediatek,u3p-dis-msk = <1>;
status = "okay";
};
/* front USB */
&ssusb1 {
status = "okay";
};
&switch {
dsa,member = <1 0>;
status = "okay";
};
&tphy {
status = "okay";
};
&watchdog {
status = "okay";
};
&xsphy {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
};
&{/soc/mmc@11230000} {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_sdcard>;
pinctrl-1 = <&mmc0_pins_sdcard>;
cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
no-mmc;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include "mt7988a-bananapi-bpi-r4.dtsi"
/ {
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
model = "Banana Pi BPI-R4 (2x SFP+)";
chassis-type = "embedded";
/* SFP2 cage (LAN) */
sfp2: sfp2 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp2>;
maximum-power-milliwatt = <3000>;
los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
};
};
&gmac1 {
managed = "in-band-status";
phy-mode = "usxgmii";
sfp = <&sfp2>;
};
&pca9545 {
i2c_sfp2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
#include <dt-bindings/leds/common.h>
#include "mt7988a.dtsi"
/ {
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
cooling-levels = <0 80 128 255>;
#cooling-cells = <2>;
pwms = <&pwm 0 50000>;
status = "okay";
};
gpio-leds {
compatible = "gpio-leds";
led_green: led-green {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_blue: led-blue {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* SFP1 cage (WAN) */
sfp1: sfp1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
maximum-power-milliwatt = <3000>;
los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
};
};
&cci {
proc-supply = <&rt5190_buck3>;
};
&cpu0 {
proc-supply = <&rt5190_buck3>;
};
&cpu1 {
proc-supply = <&rt5190_buck3>;
};
&cpu2 {
proc-supply = <&rt5190_buck3>;
};
&cpu3 {
proc-supply = <&rt5190_buck3>;
};
&cpu_thermal {
trips {
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <40000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>;
};
map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
};
};
&gmac2 {
managed = "in-band-status";
phy-mode = "usxgmii";
sfp = <&sfp1>;
};
&gsw_phy0 {
pinctrl-0 = <&gbe0_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy0_led0 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port0 {
label = "wan";
};
&gsw_phy1 {
pinctrl-0 = <&gbe1_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy1_led0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port1 {
label = "lan1";
};
&gsw_phy2 {
pinctrl-0 = <&gbe2_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy2_led0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port2 {
label = "lan2";
};
&gsw_phy3 {
pinctrl-0 = <&gbe3_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy3_led0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
status = "okay";
};
&gsw_port3 {
label = "lan3";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
rt5190a_64: rt5190a@64 {
compatible = "richtek,rt5190a";
reg = <0x64>;
vin2-supply = <&rt5190_buck1>;
vin3-supply = <&rt5190_buck1>;
vin4-supply = <&rt5190_buck1>;
regulators {
rt5190_buck1: buck1 {
regulator-name = "rt5190a-buck1";
regulator-min-microvolt = <5090000>;
regulator-max-microvolt = <5090000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO>, <RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
buck2 {
regulator-name = "vcore";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
rt5190_buck3: buck3 {
regulator-name = "vproc";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
};
buck4 {
regulator-name = "rt5190a-buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO>, <RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
ldo {
regulator-name = "rt5190a-ldo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_1_pins>;
status = "okay";
pca9545: i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
#clock-cells = <0>;
};
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
size = <256>;
};
};
i2c_sfp1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
/* mPCIe SIM2 */
&pcie0 {
status = "okay";
};
/* mPCIe SIM3 */
&pcie1 {
status = "okay";
};
/* M.2 key-B SIM1 */
&pcie2 {
status = "okay";
};
/* M.2 key-M SSD */
&pcie3 {
status = "okay";
};
&pio {
i2c0_pins: i2c0-g0-pins {
mux {
function = "i2c";
groups = "i2c0_1";
};
};
i2c1_pins: i2c1-g0-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_1_pins: i2c2-g1-pins {
mux {
function = "i2c";
groups = "i2c2_1";
};
};
gbe0_led0_pins: gbe0-led0-pins {
mux {
function = "led";
groups = "gbe0_led0";
};
};
gbe1_led0_pins: gbe1-led0-pins {
mux {
function = "led";
groups = "gbe1_led0";
};
};
gbe2_led0_pins: gbe2-led0-pins {
mux {
function = "led";
groups = "gbe2_led0";
};
};
gbe3_led0_pins: gbe3-led0-pins {
mux {
function = "led";
groups = "gbe3_led0";
};
};
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
mux {
function = "led";
groups = "2p5gbe_led0";
};
};
mmc0_pins_emmc_45: mmc0-emmc-45-pins {
mux {
function = "flash";
groups = "emmc_45";
};
};
mmc0_pins_emmc_51: mmc0-emmc-51-pins {
mux {
function = "flash";
groups = "emmc_51";
};
};
mmc0_pins_sdcard: mmc0-sdcard-pins {
mux {
function = "flash";
groups = "sdcard";
};
};
spi0_flash_pins: spi0-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
};
&pwm {
status = "okay";
};
&serial0 {
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&spi1 {
status = "okay";
};
&spi_nand {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x200000>;
read-only;
};
};
};
&ssusb1 {
status = "okay";
};
&tphy {
status = "okay";
};
&watchdog {
status = "okay";
};
&xsphy {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#ifndef __DTS_MT8167_PINFUNC_H
#define __DTS_MT8167_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1)
#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2)
#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6)
#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7)
#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1)
#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2)
#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3)
#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5)
#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6)
#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7)
#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1)
#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2)
#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)
#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5)
#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6)
#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7)
#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1)
#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2)
#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3)
#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5)
#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6)
#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7)
#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1)
#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2)
#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3)
#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5)
#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6)
#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7)
#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1)
#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2)
#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3)
#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5)
#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6)
#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7)
#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1)
#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2)
#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3)
#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5)
#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6)
#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7)
#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1)
#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2)
#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3)
#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5)
#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6)
#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7)
#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1)
#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2)
#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3)
#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5)
#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6)
#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7)
#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1)
#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2)
#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5)
#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6)
#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7)
#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1)
#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2)
#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3)
#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5)
#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6)
#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7)
#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1)
#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2)
#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3)
#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4)
#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5)
#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6)
#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7)
#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1)
#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2)
#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3)
#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4)
#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5)
#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6)
#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7)
#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3)
#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4)
#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5)
#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6)
#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7)
#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2)
#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3)
#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4)
#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5)
#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6)
#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7)
#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2)
#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3)
#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4)
#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5)
#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6)
#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7)
#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2)
#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3)
#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4)
#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5)
#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6)
#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7)
#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2)
#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3)
#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4)
#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5)
#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6)
#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7)
#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2)
#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3)
#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4)
#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5)
#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6)
#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7)
#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1)
#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2)
#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3)
#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4)
#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5)
#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6)
#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7)
#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1)
#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3)
#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4)
#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5)
#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6)
#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7)
#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1)
#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2)
#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3)
#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7)
#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2)
#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3)
#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4)
#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5)
#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6)
#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7)
#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2)
#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3)
#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4)
#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5)
#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6)
#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7)
#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1)
#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2)
#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3)
#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4)
#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5)
#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6)
#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7)
#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1)
#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2)
#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3)
#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4)
#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5)
#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6)
#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2)
#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6)
#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1)
#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1)
#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1)
#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1)
#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1)
#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1)
#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2)
#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3)
#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4)
#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6)
#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7)
#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)
#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2)
#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3)
#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4)
#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5)
#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6)
#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7)
#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1)
#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2)
#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3)
#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4)
#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5)
#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6)
#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7)
#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1)
#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2)
#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3)
#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4)
#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5)
#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6)
#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7)
#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1)
#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2)
#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3)
#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4)
#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5)
#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6)
#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7)
#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1)
#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2)
#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3)
#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4)
#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5)
#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6)
#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7)
#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1)
#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4)
#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7)
#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1)
#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2)
#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3)
#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4)
#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7)
#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1)
#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7)
#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1)
#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2)
#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3)
#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4)
#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5)
#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6)
#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7)
#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1)
#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2)
#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3)
#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4)
#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5)
#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6)
#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1)
#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2)
#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3)
#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4)
#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5)
#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6)
#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1)
#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2)
#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4)
#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5)
#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6)
#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1)
#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2)
#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4)
#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5)
#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6)
#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1)
#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3)
#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4)
#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7)
#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1)
#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3)
#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4)
#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7)
#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1)
#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2)
#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3)
#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4)
#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7)
#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1)
#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2)
#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3)
#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4)
#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7)
#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1)
#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1)
#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1)
#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2)
#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7)
#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4)
#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6)
#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7)
#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1)
#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4)
#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6)
#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7)
#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1)
#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1)
#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1)
#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2)
#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1)
#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2)
#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1)
#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2)
#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1)
#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2)
#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1)
#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2)
#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7)
#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1)
#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2)
#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7)
#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1)
#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3)
#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7)
#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1)
#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3)
#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7)
#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0)
#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1)
#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0)
#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1)
#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0)
#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1)
#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0)
#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1)
#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0)
#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1)
#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0)
#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1)
#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0)
#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1)
#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0)
#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1)
#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0)
#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1)
#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0)
#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1)
#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0)
#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1)
#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0)
#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1)
#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0)
#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1)
#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0)
#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1)
#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0)
#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1)
#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0)
#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1)
#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0)
#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1)
#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2)
#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1)
#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2)
#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1)
#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2)
#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1)
#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2)
#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1)
#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2)
#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1)
#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2)
#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1)
#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2)
#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3)
#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1)
#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2)
#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3)
#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1)
#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2)
#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1)
#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2)
#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1)
#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2)
#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3)
#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5)
#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7)
#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1)
#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2)
#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3)
#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4)
#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5)
#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7)
#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1)
#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3)
#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5)
#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7)
#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1)
#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2)
#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3)
#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5)
#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5)
#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1)
#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1)
#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1)
#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1)
#endif /* __DTS_MT8167_PINFUNC_H */
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
+21
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 BayLibre, SAS.
* Author: Fabien Parent <fparent@baylibre.com>
*/
/dts-v1/;
#include "mt8167.dtsi"
#include "pumpkin-common.dtsi"
/ {
model = "Pumpkin MT8167";
chassis-type = "embedded";
compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8167.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS.
* Author: Fabien Parent <fparent@baylibre.com>
*/
#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
#include <dt-bindings/power/mt8167-power.h>
#include "mt8167-pinfunc.h"
#include "mt8516.dtsi"
/ {
compatible = "mediatek,mt8167";
soc {
topckgen: topckgen@10000000 {
compatible = "mediatek,mt8167-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt8167-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
spm: power-controller {
compatible = "mediatek,mt8167-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8167_POWER_DOMAIN_MM {
reg = <MT8167_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_SMI_MM>;
clock-names = "mm";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8167_POWER_DOMAIN_VDEC {
reg = <MT8167_POWER_DOMAIN_VDEC>;
clocks = <&topckgen CLK_TOP_SMI_MM>,
<&topckgen CLK_TOP_RG_VDEC>;
clock-names = "mm", "vdec";
#power-domain-cells = <0>;
};
power-domain@MT8167_POWER_DOMAIN_ISP {
reg = <MT8167_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_SMI_MM>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
<&topckgen CLK_TOP_RG_SLOW_MFG>;
clock-names = "axi_mfg", "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
mediatek,infracfg = <&infracfg>;
power-domain@MT8167_POWER_DOMAIN_MFG_2D {
reg = <MT8167_POWER_DOMAIN_MFG_2D>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8167_POWER_DOMAIN_MFG {
reg = <MT8167_POWER_DOMAIN_MFG>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
power-domain@MT8167_POWER_DOMAIN_CONN {
reg = <MT8167_POWER_DOMAIN_CONN>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8167-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
apmixedsys: apmixedsys@10018000 {
compatible = "mediatek,mt8167-apmixedsys", "syscon";
reg = <0 0x10018000 0 0x710>;
#clock-cells = <1>;
};
iommu: m4u@10203000 {
compatible = "mediatek,mt8167-m4u";
reg = <0 0x10203000 0 0x1000>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8167-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
larb0: larb@14016000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x14016000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
smi_common: smi@14017000 {
compatible = "mediatek,mt8167-smi-common";
reg = <0 0x14017000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
larb1: larb@15001000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&imgsys CLK_IMG_LARB1_SMI>,
<&imgsys CLK_IMG_LARB1_SMI>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt8167-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
larb2: larb@16010000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB1_CKEN>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2019 MediaTek Inc.
*/
/dts-v1/;
#include "mt8173-elm-hana.dtsi"
/ {
model = "Google Hanawl";
chassis-type = "laptop";
compatible = "google,hana-rev7", "mediatek,mt8173";
};
&cpu_thermal {
trips {
cpu_crit: cpu-crit0 {
temperature = <100000>;
type = "critical";
};
};
};
&gpio_keys {
/delete-node/switch-tablet-mode;
/delete-node/switch-volume-down;
/delete-node/switch-volume-up;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
+15
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2016 MediaTek Inc.
*/
/dts-v1/;
#include "mt8173-elm-hana.dtsi"
/ {
model = "Google Hana";
chassis-type = "laptop";
compatible = "google,hana-rev6", "google,hana-rev5",
"google,hana-rev4", "google,hana-rev3",
"google,hana", "mediatek,mt8173";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2016 MediaTek Inc.
*/
#include "mt8173-elm.dtsi"
&hdmi_mux_pins {
pins-mux {
pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>;
bias-pull-up;
output-high;
};
};
&i2c0 {
clock-frequency = <200000>;
};
&i2c3 {
touchscreen2: touchscreen@34 {
compatible = "melfas,mip4_ts";
reg = <0x34>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
status = "fail-needs-probe";
};
/*
* Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
* Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a
* second source touchscreen.
*/
touchscreen3: touchscreen@20 {
compatible = "hid-over-i2c";
reg = <0x20>;
hid-descr-addr = <0x0020>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
status = "fail-needs-probe";
};
/* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
hid-descr-addr = <0x0001>;
interrupt-parent = <&pio>;
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
status = "fail-needs-probe";
};
};
&i2c4 {
/*
* Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
* Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a
* second source trackpad.
*/
trackpad2: trackpad@2c {
compatible = "hid-over-i2c";
interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_irq>;
reg = <0x2c>;
hid-descr-addr = <0x0020>;
/*
* The trackpad needs a post-power-on delay of 100ms,
* but at time of writing, the power supply for it on
* this board is always on. The delay is therefore not
* added to avoid impacting the readiness of the
* trackpad.
*/
vdd-supply = <&mt6397_vgp6_reg>;
wakeup-source;
status = "fail-needs-probe";
};
};
&mmc1_pins_default {
pins-wp {
pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>;
input-enable;
bias-pull-up;
};
};
&mmc1 {
wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
};
&touchscreen {
status = "fail-needs-probe";
};
&trackpad {
status = "fail-needs-probe";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2016 MediaTek Inc.
*/
/dts-v1/;
#include "mt8173-elm.dtsi"
/ {
model = "Google Elm";
chassis-type = "laptop";
compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
"google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
"google,elm", "mediatek,mt8173";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+519
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Eddie Huang <eddie.huang@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt8173.dtsi"
/ {
model = "MediaTek MT8173 evaluation board";
chassis-type = "embedded";
compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
chosen { };
connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "d";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi0_out>;
};
};
};
extcon_usb: extcon_iddig {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb_p1_vbus: regulator-usb-p1 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_p0_vbus: regulator-usb-p0 {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&mfg_async {
domain-supply = <&da9211_vgpu_reg>;
};
&cec {
status = "okay";
};
&cpu0 {
proc-supply = <&mt6397_vpca15_reg>;
};
&cpu1 {
proc-supply = <&mt6397_vpca15_reg>;
};
&cpu2 {
proc-supply = <&da9211_vcpu_reg>;
sram-supply = <&mt6397_vsramca7_reg>;
};
&cpu3 {
proc-supply = <&da9211_vcpu_reg>;
sram-supply = <&mt6397_vsramca7_reg>;
};
&dpi0 {
status = "okay";
};
&hdmi_phy {
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
hdmi0_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&i2c1 {
status = "okay";
buck: da9211@68 {
compatible = "dlg,da9211";
reg = <0x68>;
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
regulators {
da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
};
da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
};
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mediatek,hs200-cmd-int-delay = <26>;
mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
non-removable;
};
&mmc1 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_uhs>;
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
sd-uhs-sdr25;
cd-gpios = <&pio 132 0>;
vmmc-supply = <&mt6397_vmch_reg>;
vqmmc-supply = <&mt6397_vmc_reg>;
};
&pio {
disp_pwm0_pins: disp-pwm0-pins {
pins1 {
pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
output-low;
};
};
i2c1_pins_a: i2c1-pins {
pins-da9211 {
pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
bias-pull-up;
};
};
mmc0_pins_default: mmc0-default-pins {
pins-cmd-dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
<MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
<MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
<MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up;
};
pins-clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
bias-pull-down;
};
pins-rst {
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc1_pins_default: mmc1-default-pins {
pins-cmd-dat {
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down;
drive-strength = <4>;
};
pins-insert {
pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>;
bias-pull-up;
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
pins-cmd-dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
<MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
<MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
<MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <2>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
drive-strength = <2>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
spi_pins_a: spi0-pins {
pins-bus {
pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>,
<MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>,
<MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>,
<MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>;
};
};
mmc1_pins_uhs: mmc1-uhs-pins {
pins-cmd-dat {
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
drive-strength = <4>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
usb_id_pins_float: usb-iddig-pu-pins {
pins-iddig-pu {
pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
bias-pull-up;
};
};
usb_id_pins_ground: usb-iddig-pd-pins {
pins-iddig-pd {
pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
bias-pull-down;
};
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&disp_pwm0_pins>;
status = "okay";
};
&pwrap {
/* Only MT8173 E1 needs USB power domain */
power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
pmic: pmic {
compatible = "mediatek,mt6397";
interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vcore_reg: buck_vcore {
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vgpu_reg: buck_vgpu {
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <115>;
};
mt6397_vdrm_reg: buck_vdrm {
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vio18_reg: buck_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-name = "va28";
regulator-always-on;
};
mt6397_vcama_reg: ldo_vcama {
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vio28_reg: ldo_vio28 {
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vmch_reg: ldo_vmch {
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
mt6397_vibr_reg: ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <218>;
};
};
};
};
&spi {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_a>;
mediatek,pad-select = <0>;
status = "okay";
};
&ssusb {
vusb33-supply = <&mt6397_vusb_reg>;
vbus-supply = <&usb_p0_vbus>;
extcon = <&extcon_usb>;
dr_mode = "otg";
wakeup-source;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_pins_float>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_host {
vusb33-supply = <&mt6397_vusb_reg>;
vbus-supply = <&usb_p1_vbus>;
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h
+674
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@@ -0,0 +1,674 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
*/
#ifndef __DTS_MT8173_PINFUNC_H
#define __DTS_MT8173_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1)
#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2)
#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3)
#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4)
#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7)
#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1)
#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2)
#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3)
#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4)
#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7)
#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1)
#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2)
#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3)
#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4)
#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7)
#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1)
#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2)
#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3)
#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4)
#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7)
#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1)
#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2)
#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3)
#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4)
#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6)
#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1)
#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2)
#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3)
#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4)
#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5)
#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6)
#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1)
#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2)
#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3)
#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5)
#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6)
#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1)
#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2)
#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3)
#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5)
#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6)
#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1)
#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2)
#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3)
#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4)
#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5)
#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6)
#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1)
#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2)
#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4)
#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5)
#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6)
#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1)
#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2)
#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3)
#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4)
#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5)
#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1)
#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2)
#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3)
#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4)
#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5)
#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6)
#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7)
#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1)
#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2)
#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3)
#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5)
#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7)
#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1)
#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2)
#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3)
#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5)
#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7)
#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1)
#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2)
#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4)
#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7)
#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1)
#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2)
#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3)
#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4)
#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7)
#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1)
#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2)
#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4)
#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1)
#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1)
#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1)
#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2)
#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1)
#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2)
#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1)
#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1)
#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1)
#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1)
#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1)
#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1)
#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1)
#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1)
#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1)
#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1)
#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1)
#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2)
#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1)
#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2)
#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1)
#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2)
#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1)
#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2)
#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1)
#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2)
#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1)
#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2)
#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1)
#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2)
#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3)
#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4)
#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5)
#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6)
#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1)
#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2)
#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6)
#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1)
#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2)
#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7)
#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1)
#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2)
#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3)
#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7)
#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1)
#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7)
#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1)
#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1)
#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1)
#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1)
#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1)
#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1)
#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1)
#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1)
#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1)
#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1)
#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1)
#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1)
#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2)
#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1)
#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2)
#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1)
#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2)
#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1)
#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7)
#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1)
#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7)
#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1)
#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7)
#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1)
#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2)
#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7)
#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1)
#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2)
#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3)
#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4)
#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5)
#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7)
#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1)
#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2)
#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3)
#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4)
#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5)
#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6)
#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7)
#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1)
#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2)
#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3)
#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4)
#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5)
#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7)
#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1)
#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2)
#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3)
#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4)
#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5)
#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7)
#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1)
#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7)
#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1)
#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7)
#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1)
#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7)
#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1)
#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7)
#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1)
#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7)
#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1)
#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7)
#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1)
#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2)
#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1)
#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2)
#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1)
#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1)
#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1)
#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1)
#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2)
#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1)
#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2)
#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1)
#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1)
#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2)
#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7)
#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1)
#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1)
#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1)
#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1)
#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1)
#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2)
#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7)
#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1)
#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2)
#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7)
#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1)
#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2)
#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7)
#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1)
#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2)
#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7)
#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1)
#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2)
#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7)
#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1)
#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2)
#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7)
#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1)
#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2)
#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7)
#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1)
#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2)
#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7)
#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1)
#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1)
#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1)
#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2)
#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5)
#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6)
#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1)
#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2)
#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5)
#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6)
#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1)
#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2)
#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5)
#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6)
#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1)
#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2)
#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5)
#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6)
#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1)
#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2)
#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5)
#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6)
#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1)
#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2)
#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6)
#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7)
#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1)
#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2)
#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6)
#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7)
#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1)
#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2)
#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6)
#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7)
#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1)
#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2)
#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6)
#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7)
#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1)
#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2)
#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7)
#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1)
#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2)
#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7)
#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1)
#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7)
#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1)
#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3)
#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7)
#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1)
#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2)
#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3)
#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4)
#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5)
#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7)
#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1)
#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7)
#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1)
#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2)
#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3)
#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7)
#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1)
#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2)
#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3)
#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4)
#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5)
#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7)
#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1)
#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1)
#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7)
#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1)
#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2)
#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3)
#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5)
#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7)
#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1)
#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2)
#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3)
#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5)
#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7)
#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1)
#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1)
#endif /* __DTS_MT8173_PINFUNC_H */
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8173.dtsi
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linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Ben Ho <ben.ho@mediatek.com>
* Erin Lo <erin.lo@mediatek.com>
*/
/dts-v1/;
#include "mt8183.dtsi"
#include "mt6358.dtsi"
/ {
model = "MediaTek MT8183 evaluation board";
chassis-type = "embedded";
compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
thermistor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;
pulldown-ohm = <0>;
io-channels = <&auxadc 0>;
};
};
&auxadc {
status = "okay";
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
status = "okay";
clock-frequency = <100000>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_1>;
status = "okay";
clock-frequency = <100000>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_2>;
status = "okay";
clock-frequency = <100000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_3>;
status = "okay";
clock-frequency = <100000>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_4>;
status = "okay";
clock-frequency = <1000000>;
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_5>;
status = "okay";
clock-frequency = <1000000>;
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-hw-reset;
no-sdio;
no-sd;
hs400-ds-delay = <0x12814>;
vmmc-supply = <&mt6358_vemc_reg>;
vqmmc-supply = <&mt6358_vio18_reg>;
assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
non-removable;
};
&mmc1 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_uhs>;
bus-width = <4>;
max-frequency = <200000000>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
cap-sdio-irq;
no-mmc;
no-sd;
vmmc-supply = <&mt6358_vmch_reg>;
vqmmc-supply = <&mt6358_vmc_reg>;
keep-power-in-suspend;
wakeup-source;
non-removable;
};
&mt6358_vgpu_reg {
regulator-min-microvolt = <625000>;
regulator-max-microvolt = <900000>;
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
regulator-coupled-max-spread = <100000>;
};
&mt6358_vsram_gpu_reg {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-coupled-with = <&mt6358_vgpu_reg>;
regulator-coupled-max-spread = <100000>;
};
&pio {
i2c_pins_0: i2c0-pins {
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
};
};
i2c_pins_1: i2c1-pins {
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
};
};
i2c_pins_2: i2c2-pins {
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
};
};
i2c_pins_3: i2c3-pins {
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
};
};
i2c_pins_4: i2c4-pins {
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
};
};
i2c_pins_5: i2c5-pins {
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
};
};
spi_pins_0: spi0-pins {
pins_spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_SPI0_CSB>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
<PINMUX_GPIO88__FUNC_SPI0_CLK>;
bias-disable;
};
};
mmc0_pins_default: mmc0-default-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO122__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up;
};
pins_clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
bias-pull-down;
};
pins_rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO122__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins_ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins_rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-up;
};
};
mmc1_pins_default: mmc1-default-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
input-enable;
bias-pull-up;
};
pins_clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
bias-pull-down;
};
pins_pmu {
pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
<PINMUX_GPIO166__FUNC_GPIO166>;
output-high;
};
};
mmc1_pins_uhs: mmc1-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
drive-strength = <MTK_DRIVE_6mA>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
input-enable;
};
};
spi_pins_1: spi1-pins {
pins_spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
<PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
bias-disable;
};
};
spi_pins_2: spi2-pins {
pins_spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>,
<PINMUX_GPIO94__FUNC_SPI2_MI>;
bias-disable;
};
};
spi_pins_3: spi3-pins {
pins_spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
<PINMUX_GPIO24__FUNC_SPI3_CLK>;
bias-disable;
};
};
spi_pins_4: spi4-pins {
pins_spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
<PINMUX_GPIO20__FUNC_SPI4_CLK>;
bias-disable;
};
};
spi_pins_5: spi5-pins {
pins_spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,
<PINMUX_GPIO16__FUNC_SPI5_CLK>;
bias-disable;
};
};
pwm_pins_1: pwm1-pins {
pins_pwm {
pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
};
};
};
&pmic {
interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
};
&mfg {
domain-supply = <&mt6358_vgpu_reg>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_0>;
mediatek,pad-select = <0>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_1>;
mediatek,pad-select = <0>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_2>;
mediatek,pad-select = <0>;
status = "okay";
};
&spi3 {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_3>;
mediatek,pad-select = <0>;
status = "okay";
};
&spi4 {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_4>;
mediatek,pad-select = <0>;
status = "okay";
};
&spi5 {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_5>;
mediatek,pad-select = <0>;
status = "okay";
};
&cci {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu1 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu2 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu3 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu4 {
proc-supply = <&mt6358_vproc11_reg>;
};
&cpu5 {
proc-supply = <&mt6358_vproc11_reg>;
};
&cpu6 {
proc-supply = <&mt6358_vproc11_reg>;
};
&cpu7 {
proc-supply = <&mt6358_vproc11_reg>;
};
&uart0 {
status = "okay";
};
&pwm1 {
status = "okay";
pinctrl-0 = <&pwm_pins_1>;
pinctrl-names = "default";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) da7219-max98357a sound card.
*
* Copyright 2019 Google LLC.
*/
#include "mt8183-kukui-audio-da7219.dtsi"
#include "mt8183-kukui-audio-max98357a.dtsi"
&sound {
compatible = "mediatek,mt8183_da7219_max98357";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) da7219-rt1015p sound card.
*
* Copyright 2020 Google LLC.
*/
#include "mt8183-kukui-audio-da7219.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"
&sound {
compatible = "mediatek,mt8183_da7219_rt1015p";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for da7219.
*
* Copyright 2020 Google LLC.
*/
&i2c5 {
da7219: da7219@1a {
pinctrl-names = "default";
pinctrl-0 = <&da7219_pins>;
compatible = "dlg,da7219";
reg = <0x1a>;
interrupts-extended = <&pio 165 IRQ_TYPE_LEVEL_LOW>;
dlg,micbias-lvl = <2600>;
dlg,mic-amp-in-sel = "diff";
VDD-supply = <&pp1800_alw>;
VDDMIC-supply = <&pp3300_alw>;
VDDIO-supply = <&pp1800_alw>;
status = "okay";
da7219_aad {
dlg,adc-1bit-rpt = <1>;
dlg,btn-avg = <4>;
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
dlg,jack-det-rate = "32_64";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;
dlg,d-b-btn-thr = <0x16>;
dlg,b-c-btn-thr = <0x21>;
dlg,c-mic-btn-thr = <0x3E>;
};
};
};
&pio {
da7219_pins: da7219-pins {
pins-intn {
pinmux = <PINMUX_GPIO165__FUNC_GPIO165>;
input-enable;
bias-pull-up;
};
};
};
&sound {
mediatek,headset-codec = <&da7219>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for max98357a.
*
* Copyright 2020 Google LLC.
*/
/ {
max98357a: max98357a {
compatible = "maxim,max98357a";
sdmode-gpios = <&pio 175 0>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for rt1015p.
*
* Copyright 2020 Google LLC.
*/
/ {
rt1015p: rt1015p {
compatible = "realtek,rt1015p";
sdb-gpios = <&pio 175 0>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) ts3a227e-max98357a sound card.
*
* Copyright 2020 Google LLC.
*/
#include "mt8183-kukui-audio-max98357a.dtsi"
#include "mt8183-kukui-audio-ts3a227e.dtsi"
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card.
*
* Copyright 2021 Google LLC.
*/
#include "mt8183-kukui-audio-ts3a227e.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for ts3a227e.
*
* Copyright 2019 Google LLC.
*/
&i2c5 {
ts3a227e: ts3a227e@3b {
pinctrl-names = "default";
pinctrl-0 = <&ts3a227e_pins>;
compatible = "ti,ts3a227e";
reg = <0x3b>;
interrupts-extended = <&pio 157 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
&pio {
ts3a227e_pins: ts3a227e-pins {
pins1 {
pinmux = <PINMUX_GPIO157__FUNC_GPIO157>;
input-enable;
bias-pull-up;
};
};
};
&sound {
mediatek,headset-codec = <&ts3a227e>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google burnet board";
chassis-type = "convertible";
compatible = "google,burnet", "mediatek,mt8183";
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&i2c0 {
touchscreen@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <200>;
hid-descr-addr = <0x0020>;
};
};
&i2c2 {
i2c-scl-internal-delay-ns = <4100>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google cozmo board";
chassis-type = "laptop";
compatible = "google,cozmo", "mediatek,mt8183";
};
&i2c_tunnel {
google,remote-bus = <0>;
};
&i2c2 {
i2c-scl-internal-delay-ns = <25000>;
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_COZMO";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-da7219-max98357a.dtsi"
/ {
model = "Google damu board";
chassis-type = "convertible";
compatible = "google,damu", "mediatek,mt8183";
};
&touchscreen {
compatible = "elan,ekth6a12nay";
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
vcc33-supply = <&pp3300_alw>;
vccio-supply = <&pp1800_alw>;
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_DAMU";
};
&i2c2 {
i2c-scl-internal-delay-ns = <20000>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "Google fennel sku1 board";
chassis-type = "convertible";
compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
pwmleds {
compatible = "pwm-leds";
keyboard_backlight: led-0 {
label = "cros_ec::kbd_backlight";
pwms = <&cros_ec_pwm 0>;
max-brightness = <1023>;
};
};
};
&cros_ec_pwm {
status = "okay";
};
&touchscreen {
compatible = "elan,ekth6a12nay";
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
vcc33-supply = <&pp3300_alw>;
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "Google fennel sku6 board";
chassis-type = "convertible";
compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
};
&touchscreen {
compatible = "elan,ekth6a12nay";
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
vcc33-supply = <&pp3300_alw>;
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
/ {
model = "Google fennel sku7 board";
chassis-type = "convertible";
compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";
};
&touchscreen {
compatible = "elan,ekth6a12nay";
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
vcc33-supply = <&pp3300_alw>;
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c2 {
i2c-scl-internal-delay-ns = <21500>;
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
/ {
model = "Google fennel14 sku2 board";
chassis-type = "laptop";
compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "Google fennel14 sku0 board";
chassis-type = "laptop";
compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google juniper sku16 board";
chassis-type = "convertible";
compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_JUNIPER";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google kappa board";
chassis-type = "laptop";
compatible = "google,kappa", "mediatek,mt8183";
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google kenzo sku17 board";
chassis-type = "laptop";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "Google makomo sku0 board";
chassis-type = "laptop";
compatible = "google,makomo-sku0", "google,makomo", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <6>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
/ {
model = "Google makomo sku1 board";
chassis-type = "laptop";
compatible = "google,makomo-sku1", "google,makomo", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <6>;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google pico board";
chassis-type = "convertible";
compatible = "google,pico-sku1", "google,pico", "mediatek,mt8183";
};
&i2c_tunnel {
google,remote-bus = <0>;
};
&i2c2 {
i2c-scl-internal-delay-ns = <25000>;
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google pico6 board";
chassis-type = "convertible";
compatible = "google,pico-sku2", "google,pico", "mediatek,mt8183";
bt_wakeup: bt-wakeup {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_wakeup>;
event-wobt {
label = "Wake on BT";
gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
};
&i2c_tunnel {
google,remote-bus = <0>;
};
&i2c2 {
i2c-scl-internal-delay-ns = <25000>;
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&wifi_wakeup_event {
gpios = <&pio 113 GPIO_ACTIVE_LOW>;
};
&wifi_pwrseq {
post-power-on-delay-ms = <50>;
/* Toggle WIFI_ENABLE to reset the chip. */
reset-gpios = <&pio 8 GPIO_ACTIVE_LOW>;
};
&wifi_pins_pwrseq {
pins-wifi-enable {
pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
};
};
&mmc1_pins_default {
pins-cmd-dat {
drive-strength = <6>;
};
pins-clk {
drive-strength = <6>;
};
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <6>;
};
};
&mmc1 {
bluetooth@2 {
reg = <2>;
compatible = "mediatek,mt7921s-bluetooth";
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_reset>;
reset-gpios = <&pio 120 GPIO_ACTIVE_LOW>;
};
};
&pio {
bt_pins_wakeup: bt-pins-wakeup {
pins-bt-wakeup {
pinmux = <PINMUX_GPIO42__FUNC_GPIO42>;
input-enable;
};
};
bt_pins_reset: bt-pins-reset {
pins-bt-reset {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
output-high;
};
};
};
/delete-node/ &bluetooth;
/delete-node/ &bt_pins;
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
#include "mt8183-kukui-audio-da7219-max98357a.dtsi"
/ {
model = "Google willow board sku0";
chassis-type = "laptop";
compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google willow board sku1";
chassis-type = "laptop";
compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_JUNIPER";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
#include "mt8183-kukui.dtsi"
/* Must come after mt8183-kukui.dtsi to modify cros_ec */
#include <arm/cros-ec-keyboard.dtsi>
/ {
pp1000_mipibrdg: pp1000-mipibrdg {
compatible = "regulator-fixed";
regulator-name = "pp1000_mipibrdg";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pp1000_mipibrdg_en>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 54 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp1800_alw>;
};
pp1800_mipibrdg: pp1800-mipibrdg {
compatible = "regulator-fixed";
regulator-name = "pp1800_mipibrdg";
pinctrl-names = "default";
pinctrl-0 = <&pp1800_mipibrdg_en>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp1800_alw>;
};
pp3300_panel: pp3300-panel {
compatible = "regulator-fixed";
regulator-name = "pp3300_panel";
pinctrl-names = "default";
pinctrl-0 = <&pp3300_panel_pins>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 35 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_alw>;
};
pp3300_mipibrdg: pp3300-mipibrdg {
compatible = "regulator-fixed";
regulator-name = "pp3300_mipibrdg";
pinctrl-names = "default";
pinctrl-0 = <&pp3300_mipibrdg_en>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 37 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_alw>;
};
volume_buttons: volume-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&volume_button_pins>;
button-volume-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <100>;
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
button-volume-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <100>;
gpios = <&pio 5 GPIO_ACTIVE_LOW>;
};
};
};
&cros_ec {
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
status = "disabled";
};
};
&dsi_out {
remote-endpoint = <&anx7625_in>;
};
&i2c0 {
status = "okay";
touchscreen: touchscreen@10 {
compatible = "elan,ekth3500";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <100000>;
anx_bridge: anx7625@58 {
compatible = "analogix,anx7625";
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&anx7625_pins>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1000_mipibrdg>;
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&pp3300_mipibrdg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
anx7625_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
anx7625_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
aux-bus {
panel: panel {
compatible = "edp-panel";
power-supply = <&pp3300_panel>;
backlight = <&backlight_lcd0>;
port {
panel_in: endpoint {
remote-endpoint = <&anx7625_out>;
};
};
};
};
};
};
&i2c_tunnel {
google,remote-bus = <2>;
};
&pio {
/* 192 lines */
gpio-line-names =
"SPI_AP_EC_CS_L",
"SPI_AP_EC_MOSI",
"SPI_AP_EC_CLK",
"I2S3_DO",
"USB_PD_INT_ODL",
"",
"",
"",
"",
"IT6505_HPD_L",
"I2S3_TDM_D3",
"SOC_I2C6_1V8_SCL",
"SOC_I2C6_1V8_SDA",
"DPI_D0",
"DPI_D1",
"DPI_D2",
"DPI_D3",
"DPI_D4",
"DPI_D5",
"DPI_D6",
"DPI_D7",
"DPI_D8",
"DPI_D9",
"DPI_D10",
"DPI_D11",
"DPI_HSYNC",
"DPI_VSYNC",
"DPI_DE",
"DPI_CK",
"AP_MSDC1_CLK",
"AP_MSDC1_DAT3",
"AP_MSDC1_CMD",
"AP_MSDC1_DAT0",
"AP_MSDC1_DAT2",
"AP_MSDC1_DAT1",
"",
"",
"",
"",
"",
"",
"OTG_EN",
"DRVBUS",
"DISP_PWM",
"DSI_TE",
"LCM_RST_1V8",
"AP_CTS_WIFI_RTS",
"AP_RTS_WIFI_CTS",
"SOC_I2C5_1V8_SCL",
"SOC_I2C5_1V8_SDA",
"SOC_I2C3_1V8_SCL",
"SOC_I2C3_1V8_SDA",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"SOC_I2C1_1V8_SDA",
"SOC_I2C0_1V8_SDA",
"SOC_I2C0_1V8_SCL",
"SOC_I2C1_1V8_SCL",
"AP_SPI_H1_MISO",
"AP_SPI_H1_CS_L",
"AP_SPI_H1_MOSI",
"AP_SPI_H1_CLK",
"I2S5_BCK",
"I2S5_LRCK",
"I2S5_DO",
"BOOTBLOCK_EN_L",
"MT8183_KPCOL0",
"SPI_AP_EC_MISO",
"UART_DBG_TX_AP_RX",
"UART_AP_TX_DBG_RX",
"I2S2_MCK",
"I2S2_BCK",
"CLK_5M_WCAM",
"CLK_2M_UCAM",
"I2S2_LRCK",
"I2S2_DI",
"SOC_I2C2_1V8_SCL",
"SOC_I2C2_1V8_SDA",
"SOC_I2C4_1V8_SCL",
"SOC_I2C4_1V8_SDA",
"",
"SCL8",
"SDA8",
"FCAM_PWDN_L",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"",
"",
"",
"",
"",
"",
/*
* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
* call it BIOS_FLASH_WP_R_L.
*/
"AP_FLASH_WP_L",
"EC_AP_INT_ODL",
"IT6505_INT_ODL",
"H1_INT_OD_L",
"",
"",
"",
"",
"",
"",
"",
"AP_SPI_FLASH_MISO",
"AP_SPI_FLASH_CS_L",
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_CLK",
"DA7219_IRQ",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"";
pp1000_mipibrdg_en: pp1000-mipibrdg-en-pins {
pins1 {
pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
output-low;
};
};
pp1800_mipibrdg_en: pp1800-mipibrdg-en-pins {
pins1 {
pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
output-low;
};
};
pp3300_panel_pins: pp3300-panel-pins {
panel_3v3_enable: pins-panel-en {
pinmux = <PINMUX_GPIO35__FUNC_GPIO35>;
output-low;
};
};
ppvarp_lcd_en: ppvarp-lcd-en-pins {
pins1 {
pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
output-low;
};
};
ppvarn_lcd_en: ppvarn-lcd-en-pins {
pins1 {
pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
output-low;
};
};
anx7625_pins: anx7625-pins {
pins1 {
pinmux = <PINMUX_GPIO45__FUNC_GPIO45>,
<PINMUX_GPIO73__FUNC_GPIO73>;
output-low;
};
pins2 {
pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
input-enable;
bias-pull-up;
};
};
touchscreen_pins: touchscreen-pins {
pins-intn {
pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
input-enable;
bias-pull-up;
};
pins-rst {
pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
output-high;
};
};
trackpad_pins: trackpad-pins {
pins-intn {
pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
input-enable;
bias-disable; /* pulled externally */
};
};
pp3300_mipibrdg_en: pp3300-mipibrdg-en-pins {
pins1 {
pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
output-low;
};
};
volume_button_pins: volume-button-pins {
pins-voldn {
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
input-enable;
bias-pull-up;
};
pins-volup {
pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
input-enable;
bias-pull-up;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
+38
View File
@@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"
/ {
model = "MediaTek kakadu board sku22";
chassis-type = "tablet";
compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
"google,kakadu", "mediatek,mt8183";
};
&i2c0 {
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
};
&panel {
compatible = "boe,tv105wum-nw0";
};
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
+33
View File
@@ -0,0 +1,33 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "MediaTek kakadu board";
chassis-type = "tablet";
compatible = "google,kakadu-rev3", "google,kakadu-rev2",
"google,kakadu", "mediatek,mt8183";
};
&i2c0 {
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
};
&panel {
compatible = "boe,tv105wum-nw0";
};
linux-7.2.3/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
+406
View File
@@ -0,0 +1,406 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Google LLC
*/
#include "mt8183-kukui.dtsi"
#include <dt-bindings/input/gpio-keys.h>
/ {
ppvarn_lcd: ppvarn-lcd {
compatible = "regulator-fixed";
regulator-name = "ppvarn_lcd";
pinctrl-names = "default";
pinctrl-0 = <&ppvarn_lcd_en>;
enable-active-high;
gpio = <&pio 66 GPIO_ACTIVE_HIGH>;
};
ppvarp_lcd: ppvarp-lcd {
compatible = "regulator-fixed";
regulator-name = "ppvarp_lcd";
pinctrl-names = "default";
pinctrl-0 = <&ppvarp_lcd_en>;
enable-active-high;
gpio = <&pio 166 GPIO_ACTIVE_HIGH>;
};
pp1800_lcd: pp1800-lcd {
compatible = "regulator-fixed";
regulator-name = "pp1800_lcd";
pinctrl-names = "default";
pinctrl-0 = <&pp1800_lcd_en>;
enable-active-high;
gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pen_eject>;
switch-pen-insert {
label = "Pen Insert";
/* Insert = low, eject = high */
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
linux,code = <SW_PEN_INSERTED>;
linux,input-type = <EV_SW>;
wakeup-event-action = <EV_ACT_DEASSERTED>;
wakeup-source;
};
};
};
&bluetooth {
firmware-name = "nvm_00440302_i2s_eu.bin";
};
&dsi0 {
#address-cells = <1>;
#size-cells = <0>;
panel: panel@0 {
/* compatible will be set in board dts */
reg = <0>;
enable-gpios = <&pio 45 0>;
pinctrl-names = "default";
pinctrl-0 = <&panel_pins_default>;
avdd-supply = <&ppvarn_lcd>;
avee-supply = <&ppvarp_lcd>;
pp1800-supply = <&pp1800_lcd>;
backlight = <&backlight_lcd0>;
rotation = <270>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&dsi_out {
remote-endpoint = <&panel_in>;
};
&i2c0 {
status = "okay";
};
&mt6358_vcama2_reg {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
vcc-supply = <&mt6358_vcama2_reg>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};
};
&mipi_tx0 {
drive-strength-microamp = <5800>;
};
&pio {
/* 192 lines */
gpio-line-names =
"SPI_AP_EC_CS_L",
"SPI_AP_EC_MOSI",
"SPI_AP_EC_CLK",
"I2S3_DO",
"USB_PD_INT_ODL",
"",
"",
"",
"",
"IT6505_HPD_L",
"I2S3_TDM_D3",
"SOC_I2C6_1V8_SCL",
"SOC_I2C6_1V8_SDA",
"DPI_D0",
"DPI_D1",
"DPI_D2",
"DPI_D3",
"DPI_D4",
"DPI_D5",
"DPI_D6",
"DPI_D7",
"DPI_D8",
"DPI_D9",
"DPI_D10",
"DPI_D11",
"DPI_HSYNC",
"DPI_VSYNC",
"DPI_DE",
"DPI_CK",
"AP_MSDC1_CLK",
"AP_MSDC1_DAT3",
"AP_MSDC1_CMD",
"AP_MSDC1_DAT0",
"AP_MSDC1_DAT2",
"AP_MSDC1_DAT1",
"",
"",
"",
"",
"",
"",
"OTG_EN",
"DRVBUS",
"DISP_PWM",
"DSI_TE",
"LCM_RST_1V8",
"AP_CTS_WIFI_RTS",
"AP_RTS_WIFI_CTS",
"SOC_I2C5_1V8_SCL",
"SOC_I2C5_1V8_SDA",
"SOC_I2C3_1V8_SCL",
"SOC_I2C3_1V8_SDA",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"SOC_I2C1_1V8_SDA",
"SOC_I2C0_1V8_SDA",
"SOC_I2C0_1V8_SCL",
"SOC_I2C1_1V8_SCL",
"AP_SPI_H1_MISO",
"AP_SPI_H1_CS_L",
"AP_SPI_H1_MOSI",
"AP_SPI_H1_CLK",
"I2S5_BCK",
"I2S5_LRCK",
"I2S5_DO",
"BOOTBLOCK_EN_L",
"MT8183_KPCOL0",
"SPI_AP_EC_MISO",
"UART_DBG_TX_AP_RX",
"UART_AP_TX_DBG_RX",
"I2S2_MCK",
"I2S2_BCK",
"CLK_5M_WCAM",
"CLK_2M_UCAM",
"I2S2_LRCK",
"I2S2_DI",
"SOC_I2C2_1V8_SCL",
"SOC_I2C2_1V8_SDA",
"SOC_I2C4_1V8_SCL",
"SOC_I2C4_1V8_SDA",
"",
"SCL8",
"SDA8",
"FCAM_PWDN_L",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"I2S_PMIC",
"",
"",
"",
"",
"",
"",
/*
* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
* call it BIOS_FLASH_WP_R_L.
*/
"AP_FLASH_WP_L",
"EC_AP_INT_ODL",
"IT6505_INT_ODL",
"H1_INT_OD_L",
"",
"",
"",
"",
"",
"",
"",
"AP_SPI_FLASH_MISO",
"AP_SPI_FLASH_CS_L",
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_CLK",
"DA7219_IRQ",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"";
ppvarp_lcd_en: ppvarp-lcd-en-pins {
pins1 {
pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
output-low;
};
};
ppvarn_lcd_en: ppvarn-lcd-en-pins {
pins1 {
pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
output-low;
};
};
pp1800_lcd_en: pp1800-lcd-en-pins {
pins1 {
pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
output-low;
};
};
open_touch: opentouch-pins {
pins-intn {
pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
input-enable;
bias-pull-up;
};
pins-rst {
pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
/*
* The pen driver doesn't currently support driving
* this reset line. By specifying output-high here
* we're relying on the fact that this pin has a default
* pulldown at boot (which makes sure the pen was in
* reset if it was powered) and then we set it high here
* to take it out of reset. Better would be if the pen
* driver could control this and we could remove
* "output-high" here.
*/
output-high;
};
};
pen_eject: pen-pins {
pins-eject {
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
input-enable;
/* External pull-up. */
bias-disable;
};
};
};
&cros_ec {
cbas {
compatible = "google,cros-cbas";
};
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_KAKADU";
};
&panel {
status = "okay";
/* compatible will be set in board dts */
};

Some files were not shown because too many files have changed in this diff Show More