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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm64/boot/dts/renesas/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-beacon-rzg2h-kit.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb
r8a77951-salvator-x-panel-aa104xd12-dtbs := r8a77951-salvator-x.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb
r8a77951-salvator-xs-panel-aa104xd12-dtbs := r8a77951-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb
r8a77960-salvator-x-panel-aa104xd12-dtbs := r8a77960-salvator-x.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs.dtb
r8a77960-salvator-xs-panel-aa104xd12-dtbs := r8a77960-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
r8a77961-salvator-xs-panel-aa104xd12-dtbs := r8a77961-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
r8a77965-salvator-x-panel-aa104xd12-dtbs := r8a77965-salvator-x.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb
r8a77965-salvator-xs-panel-aa104xd12-dtbs := r8a77965-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779md-geist.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtbo
r8a77970-eagle-function-expansion-dtbs := r8a77970-eagle.dtb r8a77970-eagle-function-expansion.dtbo
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980a-condor-i.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
r8a77990-ebisu-panel-aa104xd12-dtbs := r8a77990-ebisu.dtb draak-ebisu-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
r8a77995-draak-panel-aa104xd12-dtbs := r8a77995-draak.dtb draak-ebisu-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-cpu.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += white-hawk-ard-audio-da7212.dtbo
r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb
r8a779g2-white-hawk-single-ard-audio-da7212-dtbs := r8a779g2-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb
DTC_FLAGS_r8a779g3-sparrow-hawk += -Wno-spi_bus_bridge
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo
r8a779g3-sparrow-hawk-camera-j1-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo
r8a779g3-sparrow-hawk-camera-j1-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo
r8a779g3-sparrow-hawk-camera-j2-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo
r8a779g3-sparrow-hawk-camera-j2-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-argon40.dtbo
r8a779g3-sparrow-hawk-fan-argon40-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-argon40.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-argon40.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo
r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtbo
r8a779g3-sparrow-hawk-olimex-dsi-hdmi-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo
r8a779g3-sparrow-hawk-rpi-display-2-5in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
r8a779g3-sparrow-hawk-rpi-display-2-7in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtbo
r8a779g3-sparrow-hawk-ws-display-13in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-ws-display-13in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb
r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb
dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb
dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h2-gray-hawk-single.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-salvator-xs.dtb
r8a779m3-salvator-xs-panel-aa104xd12-dtbs := r8a779m3-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
r8a779m5-salvator-xs-panel-aa104xd12-dtbs := r8a779m5-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo
r9a07g043u11-smarc-cru-csi-ov5645-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtb
r9a07g043u11-smarc-du-adv7513-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-du-adv7513.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo
r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtbo
r9a09g047e57-smarc-cru-csi-ov5645-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtb
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
dtb-$(CONFIG_ARCH_R9A09G056) += rzv2-evk-cn15-emmc.dtbo
r9a09g056n48-rzv2n-evk-cn15-emmc-dtbs := r9a09g056n48-rzv2n-evk.dtb rzv2-evk-cn15-emmc.dtbo
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk-cn15-emmc.dtb
dtb-$(CONFIG_ARCH_R9A09G056) += rzv2-evk-cn15-sd.dtbo
r9a09g056n48-rzv2n-evk-cn15-sd-dtbs := r9a09g056n48-rzv2n-evk.dtb rzv2-evk-cn15-sd.dtbo
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk-cn15-sd.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += rzv2-evk-cn15-emmc.dtbo
r9a09g057h44-rzv2h-evk-cn15-emmc-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-emmc.dtbo
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-emmc.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += rzv2-evk-cn15-sd.dtbo
r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-sd.dtbo
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip-pixpaper.dtbo
r9a09g057h48-kakip-pixpaper-dtbs := r9a09g057h48-kakip.dtb r9a09g057h48-kakip-pixpaper.dtbo
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip-pixpaper.dtb
dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb
dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb
dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
linux-7.2.3/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
+94
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@@ -0,0 +1,94 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the AISTARVISION MIPI Adapter V2.1
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/ {
ov5645_vdddo_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ov5645_vdda_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ov5645_vddd_1v5: 1p5v {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
imx219_vana_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vana";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
imx219_vdig_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdig";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
imx219_vddl_1v2: 1p2v {
compatible = "regulator-fixed";
regulator-name = "camera_vddl";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
osc25250_clk: osc25250_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&MIPI_OV5645_PARENT_I2C {
ov5645: ov5645@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
clocks = <&osc25250_clk>;
vdddo-supply = <&ov5645_vdddo_1v8>;
vdda-supply = <&ov5645_vdda_2v8>;
vddd-supply = <&ov5645_vddd_1v5>;
port {
ov5645_ep: endpoint {
};
};
};
};
&MIPI_IMX219_PARENT_I2C {
imx219: imx219@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&osc25250_clk>;
VANA-supply = <&imx219_vana_2v8>;
VDIG-supply = <&imx219_vdig_1v8>;
VDDL-supply = <&imx219_vddl_1v2>;
port {
imx219_ep: endpoint {
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/versaclock.h>
/ {
backlight_dpi: backlight-dpi {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>;
pwms = <&pwm0 0 25000>;
brightness-levels = <0 25 33 50 63 75 88 100>;
default-brightness-level = <6>;
};
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
keys {
compatible = "gpio-keys";
key-1 { /* S19 */
gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
label = "Up";
wakeup-source;
debounce-interval = <20>;
};
key-2 { /*S20 */
gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LEFT>;
label = "Left";
wakeup-source;
debounce-interval = <20>;
};
key-3 { /* S21 */
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
label = "Down";
wakeup-source;
debounce-interval = <20>;
};
key-4 { /* S22 */
gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RIGHT>;
label = "Right";
wakeup-source;
debounce-interval = <20>;
};
key-5 { /* S23 */
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
label = "Center";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led0 {
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
label = "LED0";
linux,default-trigger = "heartbeat";
};
led1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
led3 {
gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
};
rgb {
/* Different LCD with compatible timings */
compatible = "rocktech,rk070er9427";
backlight = <&backlight_dpi>;
enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd>;
port {
rgb_panel: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "audio-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "lcd_panel_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_cam0: regulator-cam0 {
compatible = "regulator-fixed";
regulator-name = "reg_cam0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_cam1: regulator-cam1 {
compatible = "regulator-fixed";
regulator-name = "reg_cam1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
};
sound_card {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0>, <&rsnd_port1>;
widgets = "Microphone", "Mic Jack",
"Line", "Line In Jack",
"Headphone", "Headphone Jack";
mic-det-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
routing = "Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN3R", "MICBIAS",
"Mic Jack", "IN3R";
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
/* External DU dot clocks */
x302_clk: x302-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x304_clk: x304-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
};
&audio_clk_b {
clock-frequency = <22579200>;
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
renesas,can-clock-select = <0x0>;
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
renesas,can-clock-select = <0x0>;
status = "okay";
};
&du {
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&rgb_panel>;
};
};
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&ehci1 {
status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&hdmi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
gpio_exp2: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp3: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp4: gpio@23 {
compatible = "onnn,pca9654";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
versaclock6_bb: clock-controller@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
idt,shutdown = <0>;
idt,output-enable-active = <0>;
assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
<&versaclock6_bb 3>, <&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24576000>,
<24576000>;
OUT1 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <100>;
};
OUT2 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <100>;
};
OUT3 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <3300000>;
idt,slew-percent = <100>;
};
OUT4 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <3300000>;
idt,slew-percent = <100>;
};
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
&i2c5 {
status = "okay";
clock-frequency = <400000>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&versaclock6_bb 3>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:Default */
0x0000 /* 3:Default */
0x0000 /* 4:Default */
0x0000 /* 5:Default */
>;
port {
wm8962_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
};
};
};
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
interrupts-extended = <&gpio5 9 IRQ_TYPE_EDGE_RISING>;
wakeup-source;
};
hd3ss3220@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
gpio_exp1: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
"backlight-enable", "Touch_shdwn",
"LCD_H_pol", "lcd_V_pol";
};
};
&msiof1 {
pinctrl-0 = <&msiof1_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&ohci1 {
status = "okay";
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pfc {
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp";
function = "du";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
led_pins: leds {
/* GP_0_4 , AVS1, AVS2, GP_7_3 */
pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3";
bias-pull-down;
};
msiof1_pins: msiof1 {
groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g";
function = "msiof1";
};
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a";
function = "audio_clk";
};
usb0_pins: usb0 {
mux {
groups = "usb0";
function = "usb0";
};
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
};
usb30_pins: usb30 {
mux {
groups = "usb30";
function = "usb30";
};
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
/* Reference versaclock instead of audio_clk_a */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&versaclock6_bb 4>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_MOD 922>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
reg = <0>;
rsnd_endpoint0: endpoint {
remote-endpoint = <&wm8962_endpoint>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi1>, <&dvc1>, <&src1>;
capture = <&ssi0>;
};
};
rsnd_port1: port@1 {
reg = <0x01>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&rwdt {
status = "okay";
timeout-sec = <60>;
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif5 {
pinctrl-0 = <&scif5_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&ssi1 {
shared-pin;
};
&tmu0 {
status = "okay";
};
&tmu1 {
status = "okay";
};
&tmu2 {
status = "okay";
};
&tmu3 {
status = "okay";
};
&tmu4 {
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&usb3_phy0 {
status = "okay";
};
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
&xhci0
{
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/versaclock.h>
/ {
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc_32k: osc_32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
wlan_pwrseq: wlan_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
clocks = <&osc_32k>;
clock-names = "ext_clock";
post-power-on-delay-ms = <80>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
clock-names = "fck", "refclk";
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640";
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gpio6 {
usb-hub-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
clocks = <&osc_32k>;
clock-names = "extclk";
max-speed = <4000000>;
};
};
&hscif2 {
status = "okay";
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
};
&i2c4 {
status = "okay";
clock-frequency = <100000>;
pca9654: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"i2c4_20_0",
"wl_reg_on",
"bt_reg_on",
"i2c4_20_3",
"i2c4_20_4",
"bt_dev_wake",
"i2c4_20_6",
"i2c4_20_7";
};
pca9654_lte: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"i2c4_21_0",
"zoe_pwr_on",
"zoe_extint",
"zoe_reset_n",
"sara_reset",
"i2c4_21_5",
"sara_pwr_off",
"sara_networking_status";
};
eeprom@50 {
compatible = "microchip,24c64", "atmel,24c64";
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x50>;
};
rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
versaclock5: versaclock-som@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
idt,shutdown = <0>;
idt,output-enable-active = <0>;
/* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
assigned-clocks = <&versaclock5 1>,
<&versaclock5 2>,
<&versaclock5 3>,
<&versaclock5 4>;
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
OUT1 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <100>;
};
OUT2 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <100>;
};
OUT3 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <100>;
};
OUT4 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <3300000>;
idt,slew-percent = <100>;
};
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
hscif2_pins: hscif2 {
groups = "hscif2_data_a";
function = "hscif2";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif5_pins: scif5 {
groups = "scif5_data_a";
function = "scif5";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
};
&scif_clk {
clock-frequency = <14745600>;
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&sdhi2 {
pinctrl-names = "default";
pinctrl-0 = <&sdhi2_pins>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
mmc-pwrseq = <&wlan_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupts-extended = <&gpio1 27 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
&usb2_clksel {
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
<&versaclock5 3>, <&usb3s0_clk>;
status = "okay";
};
&usb3s0_clk {
clock-frequency = <100000000>;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/cat875.dtsi
+65
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/ {
model = "Silicon Linux sub board for CAT874 (CAT875)";
aliases {
ethernet0 = &avb;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915";
reg = <0>;
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&pciec0 {
status = "okay";
};
&pfc {
avb_pins: avb {
mux {
groups = "avb_mii";
function = "avb";
};
};
can0_pins: can0 {
groups = "can0_data";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/condor-common.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor board with R-Car V3H
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
port@0 {
csi41_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out1>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
clock-frequency = <400000>;
io_expander0: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander1: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
bootph-all;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
gmsl1: gmsl-deserializer@4a {
compatible = "maxim,max9286";
reg = <0x4a>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso
+10
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree overlay for the AA104XD12 panel connected to LVDS1 on a Draak or
* Ebisu board
*
* Copyright 2021 Ideas on Board Oy
*/
#define RENESAS_LVDS_OUTPUT lvds1
#include "panel-aa104xd12.dtsi"
linux-7.2.3/arch/arm64/boot/dts/renesas/draak.dtsi
+756
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Draak board
*
* Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas Draak board";
compatible = "renesas,draak";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
composite-in {
compatible = "composite-video-connector";
port {
composite_con_in: endpoint {
remote-endpoint = <&adv7180_in>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&adv7612_in>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW56-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW56-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW56-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW56-4";
wakeup-source;
debounce-interval = <20>;
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
sound_card: sound {
compatible = "audio-graph-card";
dais = <&rsnd_port0 /* ak4613 */
/* HDMI is not yet supported */
>;
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
x19_clk: x19 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&audio_clk_b {
/*
* X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
* and R-Car Sound uses AUDIO_CLKB.
* Note is that schematic indicates VI4_FIELD conection only
* not AUDIO_CLKB at SoC page.
* And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
* SW60 should be 1-2.
*/
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio5 19 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Draak board, however, TX clock internal delay mode
* isn't supported on R-Car D3(e). Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "host";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hsusb {
dr_mode = "host";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 0>; /* audio_clkout */
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
port {
ak4613_endpoint: endpoint {
remote-endpoint = <&rsnd_for_ak4613>;
};
};
};
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* HDMI is the default selection, leave CVBS
* not connected here.
*/
};
};
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
reg-names = "main", "edid", "cec", "packet";
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&reg_1p8v>;
dvdd-supply = <&reg_1p8v>;
pvdd-supply = <&reg_1p8v>;
dvdd-3v-supply = <&reg_3p3v>;
bgvdd-supply = <&reg_1p8v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-decoder@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* HDMI is the default selection, link it to
* VIN4 here.
*/
adv7612_out: endpoint {
remote-endpoint = <&vin4_in>;
};
};
};
};
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
bootph-all;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "host";
status = "okay";
};
&pfc {
avb0_pins: avb {
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
};
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data_a";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
keys_pins: keys {
pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
bias-pull-up;
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
rpc_pins: rpc {
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
"rpc_int";
function = "rpc";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
sdhi2_pins: sd2 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clk_a", "audio_clk_b",
"audio_clkout", "audio_clkout1";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
vin4_pins: vin4 {
groups = "vin4_data24", "vin4_sync", "vin4_clk";
function = "vin4";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&cs2000>, <&audio_clk_b>,
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
ports {
rsnd_port0: port {
rsnd_for_ak4613: endpoint {
remote-endpoint = <&ak4613_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_for_ak4613>;
frame-master = <&rsnd_for_ak4613>;
playback = <&ssi3>, <&src5>, <&dvc0>;
capture = <&ssi4>, <&src6>, <&dvc1>;
};
};
};
};
&rpc {
pinctrl-0 = <&rpc_pins>;
pinctrl-names = "default";
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&sdhi2 {
/* used for on-board eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&ssi4 {
shared-pin;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
renesas,no-otg-pins;
status = "okay";
};
&vin4 {
pinctrl-0 = <&vin4_pins>;
pinctrl-names = "default";
status = "okay";
ports {
port {
vin4_in: endpoint {
pclk-sample = <0>;
hsync-active = <0>;
vsync-active = <0>;
remote-endpoint = <&adv7612_out>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/ebisu.dtsi
+935
View File
@@ -0,0 +1,935 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Ebisu/Ebisu-4D board
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas Ebisu board";
compatible = "renesas,ebisu";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
};
pcie_usb_refclk: clk-x7 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cvbs-in {
compatible = "composite-video-connector";
label = "CVBS IN";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
label = "HDMI IN";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW4-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW4-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW4-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW4-4";
wakeup-source;
debounce-interval = <20>;
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS_CN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rsnd-ak4613";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
x13_clk: x13 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Ebisu board, however, TX clock internal delay mode
* isn't supported on R-Car E3(e). Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
/* Please only enable canfd or can0 */
/* status = "okay"; */
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
/* Please only enable canfd or can0 */
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x13_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
status = "okay";
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupts-extended = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupts-extended = <&gpio1 1 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&reg_1p8v>;
dvdd-supply = <&reg_1p8v>;
pvdd-supply = <&reg_1p8v>;
dvdd-3v-supply = <&reg_3p3v>;
bgvdd-supply = <&reg_1p8v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
pcie_usb_clk: clk@68 {
compatible = "renesas,9fgv0841";
reg = <0x68>;
clocks = <&pcie_usb_refclk>;
#clock-cells = <1>;
};
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
interrupts-extended = <&gpio0 7 IRQ_TYPE_LEVEL_LOW>,
<&gpio0 17 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "intrq1", "intrq2";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
};
};
&i2c3 {
status = "okay";
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&i2c_dvfs {
bootph-all;
status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0x1>;
rohm,rstbmode-level;
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
bootph-all;
};
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&pcie_bus_clk {
status = "disabled";
};
&pciec0 {
clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>;
status = "okay";
};
&pciec0_rp {
/*
* This configuration is valid for SW49 in OFF position,
* which means the PCIe signals are routed to the PCIe slot
* and U11 9FGV0841 PCIe clock generator output 3 supplies
* clock to the PCIe slot.
*
* In case the SW49 is set to ON position, which means the
* PCIe signals are routed to the EX BT/WLAN expansion port,
* and U11 9FGV0841 PCIe clock generator output 4 supplies
* clock to the port, change clocks below to:
* clocks = <&pcie_usb_clk 4>;
*/
clocks = <&pcie_usb_clk 3>;
};
&pfc {
avb_pins: avb {
groups = "avb_link", "avb_mii";
function = "avb";
};
can0_pins: can0 {
groups = "can0_data";
function = "can0";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
bias-pull-up;
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
};
pwm5_pins: pwm5 {
groups = "pwm5_a";
function = "pwm5";
};
rpc_pins: rpc {
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
"rpc_int";
function = "rpc";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout1_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
usb0_pins: usb {
groups = "usb0_b", "usb0_id";
function = "usb0";
};
usb30_pins: usb30 {
groups = "usb30";
function = "usb30";
};
};
&pwm3 {
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm5 {
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
rcar_sound,dai {
dai0 {
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
};
&rpc {
pinctrl-0 = <&rpc_pins>;
pinctrl-names = "default";
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi3 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&ssi1 {
shared-pin;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb3_phy0 {
clocks = <&pcie_usb_clk 6>;
status = "okay";
};
&usb3s0_clk {
status = "disabled";
};
&usb3_peri0 {
phys = <&usb3_phy0>;
phy-names = "usb";
companion = <&xhci0>;
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi
+868
View File
@@ -0,0 +1,868 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the Gray Hawk Single board
*
* Copyright (C) 2023 Renesas Electronics Corp.
* Copyright (C) 2024-2025 Glider bv
*/
/*
* [How to use Sound]
*
* Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
* at the same time. You need to switch the direction which is controlled
* by the GP0_01 pin via amixer.
*
* Playback (CN9500)
* > amixer set "MUX" "Playback" // for GP0_01
* > amixer set "DAC 1" 85%
* > aplay xxx.wav
*
* Capture (CN9501)
* > amixer set "MUX" "Capture" // for GP0_01
* > amixer set "Mic 1" 80%
* > amixer set "ADC 1" on
* > amixer set 'ADC 1' 80%
* > arecord xxx hoge.wav
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/media/video-interfaces.h>
/ {
model = "Renesas Gray Hawk Single board";
compatible = "renesas,gray-hawk-single";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
serial0 = &hscif0;
serial1 = &hscif2;
ethernet0 = &avb0;
ethernet1 = &avb1;
ethernet2 = &avb2;
};
can_transceiver0: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
max-bitrate = <5000000>;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x1 0x80000000>;
};
pcie_clk: clk-9fgv0841-pci {
compatible = "fixed-clock";
clock-frequency = <100000000>;
#clock-cells = <0>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out0>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sound_mux: sound-mux {
compatible = "simple-audio-mux";
mux-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
state-labels = "Playback", "Capture";
};
sound_card: sound {
compatible = "audio-graph-card2";
label = "rcar-sound";
aux-devs = <&sound_mux>; // for GP0_01
links = <&rsnd_port>; // AK4619 Audio Codec
};
};
&audio_clkin {
clock-frequency = <24576000>;
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&avb0_phy>;
tx-internal-delay-ps = <2000>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
avb0_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&avb1 {
pinctrl-0 = <&avb1_pins>;
pinctrl-names = "default";
phy-handle = <&avb1_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb1_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&avb2 {
pinctrl-0 = <&avb2_pins>;
pinctrl-names = "default";
phy-handle = <&avb2_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb2_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
phys = <&can_transceiver0>;
};
channel1 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96724_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi41_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96724_out1>;
};
};
};
};
&dsi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gpio1 {
audio-power-hog {
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "Audio-Power";
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
bootph-all;
uart-has-rtscts;
status = "okay";
};
&hscif2 {
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander_a: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
interrupts-extended = <&gpio0 0 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
io_expander_b: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander_c: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
reg = <0x52>;
pagesize = <8>;
};
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board-id";
reg = <0x53>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out0: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
gmsl0: gmsl-deserializer@4e {
compatible = "maxim,max96724";
reg = <0x4e>;
enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96724_out0: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
gmsl1: gmsl-deserializer@4f {
compatible = "maxim,max96724";
reg = <0x4f>;
enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96724_out1: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
codec@10 {
compatible = "asahi-kasei,ak4619";
reg = <0x10>;
clocks = <&rcar_sound>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
ak4619_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint>;
};
};
};
};
&isp0 {
status = "okay";
};
&isp1 {
status = "okay";
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pcie0_clkref {
compatible = "gpio-gate-clock";
clocks = <&pcie_clk>;
enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
/delete-property/ clock-frequency;
};
&pciec0 {
reset-gpios = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
avb1_pins: avb1 {
mux {
groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
"avb1_txcrefclk";
function = "avb1";
};
link {
groups = "avb1_link";
bias-disable;
};
mdio {
groups = "avb1_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb1_rgmii";
drive-strength = <24>;
bias-disable;
};
};
avb2_pins: avb2 {
mux {
groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
"avb2_txcrefclk";
function = "avb2";
};
link {
groups = "avb2_link";
bias-disable;
};
mdio {
groups = "avb2_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb2_rgmii";
drive-strength = <24>;
bias-disable;
};
};
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
hscif2_pins: hscif2 {
groups = "hscif2_data", "hscif2_ctrl";
function = "hscif2";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
irq0_pins: irq0_pins {
groups = "intc_ex_irq0_a";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_5_0", "GP_5_1", "GP_5_2";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
scif_clk2_pins: scif-clk2 {
groups = "scif_clk2";
function = "scif_clk2";
};
sound_clk_pins: sound_clk {
groups = "audio_clkin", "audio_clkout";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi_ctrl", "ssi_data";
function = "ssi";
};
};
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>, <&sound_pins>;
pinctrl-names = "default";
status = "okay";
/* audio_clkout */
clock-frequency = <12288000>;
ports {
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&ak4619_endpoint>;
bitclock-master;
frame-master;
/* see above [How to use Sound] */
playback = <&ssi0>;
capture = <&ssi0>;
};
};
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1200000>;
read-only;
};
user@1200000 {
reg = <0x1200000 0x2e00000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};
&scif_clk2 {
clock-frequency = <24000000>;
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
&vin08 {
status = "okay";
};
&vin09 {
status = "okay";
};
&vin10 {
status = "okay";
};
&vin11 {
status = "okay";
};
&vin12 {
status = "okay";
};
&vin13 {
status = "okay";
};
&vin14 {
status = "okay";
};
&vin15 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/hihope-common.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led2 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
led3 {
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
led4 {
gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sound_card: sound {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port>;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
x302_clk: x302-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x304_clk: x304-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&du {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gpio6 {
usb1-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-low;
line-name = "usb1-reset";
};
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint>;
};
};
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
idt,shutdown = <0>;
idt,output-enable-active = <1>;
};
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
ovc {
pins = "GP_6_27";
bias-pull-up;
};
};
usb30_pins: usb30 {
groups = "usb30";
function = "usb30";
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi2 {
status = "okay";
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
interrupts-extended = <&gpio2 5 IRQ_TYPE_LEVEL_HIGH>;
};
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
&usb_extal_clk {
clock-frequency = <50000000>;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_peri0 {
phys = <&usb3_phy0>;
phy-names = "usb";
companion = <&xhci0>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3s0_clk {
clock-frequency = <100000000>;
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/hihope-rev2.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] main board Rev.2.0 common
* parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include "hihope-common.dtsi"
/ {
leds {
compatible = "gpio-leds";
bt_active_led {
label = "blue:bt";
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
wlan_active_led {
label = "yellow:wlan";
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
};
wlan_en_reg: regulator-wlan_en {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio_expander 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&hscif0 {
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>;
};
};
&i2c4 {
gpio_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&pfc {
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a";
function = "audio_clk";
};
};
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
playback = <&ssi2>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include "hihope-common.dtsi"
/ {
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
wlan_en_reg: regulator-wlan_en {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
x1801_clk: x1801-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&hscif0 {
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
cs2000: clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x1801_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&pfc {
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
/*
* Update <audio_clk_b> to <cs2000>
* Switch SW2404 should be at position 1 so that clock from
* CS2000 is connected to AUDIO_CLKB_A
*/
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_MOD 922>;
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
playback = <&ssi2>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#define MIPI_OV5645_PARENT_I2C i2c2
#define MIPI_IMX219_PARENT_I2C i2c3
#include "aistarvision-mipi-adapter-2.1.dtsi"
&csi20 {
status = "okay";
ports {
port@0 {
csi20_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&ov5645_ep>;
};
};
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&imx219_ep>;
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
};
&imx219 {
port {
imx219_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
remote-endpoint = <&csi40_in>;
};
};
};
&ov5645 {
enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
port {
ov5645_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi20_in>;
};
};
};
&pfc {
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
};
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/ {
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-hog {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&pfc {
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/ {
aliases {
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <1800>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915";
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&pciec0 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common file for the AA104XD12 panel connected to Renesas R-Car Gen3 boards.
*
* Copyright (C) 2014 Renesas Electronics Corp.
*/
/dts-v1/;
/plugin/;
&{/} {
panel {
compatible = "mitsubishi,aa104xd12", "panel-lvds";
backlight = <&backlight>;
width-mm = <210>;
height-mm = <158>;
data-mapping = "jeida-18";
panel-timing {
/* 1024x768 @65Hz */
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hsync-len = <136>;
hfront-porch = <20>;
hback-porch = <160>;
vfront-porch = <3>;
vback-porch = <29>;
vsync-len = <6>;
};
port {
lvds_panel_in: endpoint {
remote-endpoint = <&lvds_panel_out>;
};
};
};
};
&RENESAS_LVDS_OUTPUT {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_panel_out: endpoint {
remote-endpoint = <&lvds_panel_in>;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "beacon-renesom-som.dtsi"
#include "beacon-renesom-baseboard.dtsi"
/ {
model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
serial3 = &scif0;
serial4 = &hscif2;
serial5 = &scif5;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M board
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774a1-hihope-rzg2m-ex.dts"
#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board";
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
};
/*
* On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode.
* HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and
* imx219 as the imx219 endpoint driver supports only 2 lane mode.
*/
&csi40 {
status = "disabled";
};
&imx219 {
status = "disabled";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
* sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
"renesas,r8a774a1";
};
/* SW43 should be OFF, if in ON state SATA port will be activated */
&pciec1 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.2.0 sub board connected to an
* Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-rev2-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.2.0 connected to sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m-rev2.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M (Rev.2.0) with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
"renesas,r8a774a1";
};
/* SW43 should be OFF, if in ON state SATA port will be activated */
&pciec1 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.2.0 main board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "hihope-rev2.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M main board (Rev.2.0) based on r8a774a1";
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2M main board based on r8a774a1";
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "beacon-renesom-som.dtsi"
#include "beacon-renesom-baseboard.dtsi"
/ {
model = "Beacon Embedded Works RZ/G2N Development Kit";
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
serial3 = &scif0;
serial4 = &hscif2;
serial5 = &scif5;
serial6 = &scif4;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 with sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N board
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1-hihope-rzg2n-ex.dts"
#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N with sub board connected with aistarvision-mipi-v2-adapter board";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
* sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
&sata {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.2.0 with sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-rev2-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.2.0 connected to sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n-rev2.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N (Rev.2.0) with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N Rev.2.0 main board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-rev2.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N main board (Rev.2.0) based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774c0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/display/tda998x.h>
/ {
model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
compatible = "si-linux,cat874", "renesas,r8a774c0";
aliases {
serial0 = &scif2;
serial1 = &hscif2;
mmc0 = &sdhi0;
mmc1 = &sdhi3;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&tda19988_out>;
};
};
};
leds {
compatible = "gpio-leds";
led0 {
gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
label = "LED0";
};
led1 {
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2 {
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
led3 {
gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "CAT874 HDMI sound";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&tda19988>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
wlan_en_reg: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <70000>;
gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
x13_clk: x13 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x13_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&tda19988_in>;
};
};
};
};
&ehci0 {
dr_mode = "host";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hscif2 {
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
hd3ss3220@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
tda19988: tda19988@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
interrupts-extended = <&gpio1 1 IRQ_TYPE_LEVEL_LOW>;
video-ports = <0x234501>;
#sound-dai-cells = <0>;
audio-ports = <TDA998x_I2S 0x03>;
clocks = <&rcar_sound 1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tda19988_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
tda19988_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@32 {
compatible = "epson,rx8571";
reg = <0x32>;
};
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "host";
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
};
&pfc {
du_pins: du {
groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp",
"du_clk_in_0";
function = "du";
};
hscif2_pins: hscif2 {
groups = "hscif2_data_a", "hscif2_ctrl_a";
function = "hscif2";
};
i2c1_pins: i2c1 {
groups = "i2c1_b";
function = "i2c1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
sound_clk_pins: sound_clk {
groups = "audio_clkout1_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data";
function = "ssi";
};
usb30_pins: usb30 {
groups = "usb30", "usb30_id";
function = "usb30";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
rcar_sound,dai {
dai0 {
playback = <&ssi0>, <&src0>, <&dvc0>;
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi3 {
status = "okay";
pinctrl-0 = <&sdhi3_pins>;
pinctrl-names = "default";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
interrupts-extended = <&gpio1 0 IRQ_TYPE_LEVEL_HIGH>;
};
};
&usb2_phy0 {
renesas,no-otg-pins;
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874),
* connected to an Advantech IDK-2121WR 21.5" LVDS panel
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774c0-ek874.dts"
/ {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&reg_12p0v>;
enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
panel-lvds {
compatible = "advantech,idk-2121wr", "panel-lvds";
width-mm = <476>;
height-mm = <268>;
data-mapping = "vesa-24";
panel-timing {
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
hsync-len = <44>;
hfront-porch = <88>;
hback-porch = <148>;
vfront-porch = <4>;
vback-porch = <36>;
vsync-len = <5>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
panel_in0: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
panel_in1: endpoint {
remote-endpoint = <&lvds1_out>;
};
};
};
};
};
&gpio0 {
/*
* When GP0_17 is low LVDS[01] are connected to the LVDS connector
* When GP0_17 is high LVDS[01] are connected to the LT8918L
*/
lvds-connector-en-hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&panel_in0>;
};
};
};
};
&lvds1 {
status = "okay";
clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds1_out: endpoint {
remote-endpoint = <&panel_in1>;
};
};
};
};
&pfc {
pwm5_pins: pwm5 {
groups = "pwm5_a";
function = "pwm5";
};
};
&pwm5 {
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774c0-ek874.dts"
#define MIPI_OV5645_PARENT_I2C i2c3
#define MIPI_IMX219_PARENT_I2C i2c3
#include "aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-adapter board";
compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
};
&i2c3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&ov5645_ep>;
};
};
};
};
&ov5645 {
enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
port {
ov5645_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
&imx219 {
port {
imx219_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
/* uncomment remote-endpoint property to tie imx219 to
* CSI2 also make sure remote-endpoint for ov5645 camera
* is commented and remote endpoint phandle in csi40_in
* is imx219_ep
*/
/* remote-endpoint = <&csi40_in>; */
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774c0-cat874.dts"
#include "cat875.dtsi"
/ {
model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
/dts-v1/;
#include "r8a774e1.dtsi"
#include "beacon-renesom-som.dtsi"
#include "beacon-renesom-baseboard.dtsi"
/ {
model = "Beacon Embedded Works RZ/G2H Development Kit";
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
serial3 = &scif0;
serial4 = &hscif2;
serial5 = &scif5;
serial6 = &scif4;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H sub board connected
* to an Advantech IDK-1110WR 10.1" LVDS panel
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774e1-hihope-rzg2h-ex.dts"
#include "hihope-rzg2-ex-lvds.dtsi"
#include "rzg2-advantech-idk-1110wr-panel.dtsi"
&lvds0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H board
* connected with aistarvision-mipi-v2-adapter board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774e1-hihope-rzg2h-ex.dts"
#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H with sub board connected with aistarvision-mipi-v2-adapter board";
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774e1-hihope-rzg2h.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
&sata {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H main board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774e1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77951.dtsi"
#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a77951";
compatible = "renesas,salvator-x", "renesas,r8a7795";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+
*
* Copyright (C) 2015-2017 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77951.dtsi"
#include "salvator-xs.dtsi"
/ {
model = "Renesas Salvator-X 2nd version board based on r8a77951";
compatible = "renesas,salvator-xs", "renesas,r8a7795";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&versaclock6 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB Kingfisher board with R-Car H3 ES2.0+
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
#include "r8a77951-ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas H3ULCB Kingfisher board based on r8a77951";
compatible = "shimafuji,kingfisher", "renesas,h3ulcb",
"renesas,r8a7795";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES2.0+
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77951.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas H3ULCB board based on r8a77951";
compatible = "renesas,h3ulcb", "renesas,r8a7795";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 4>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77951.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car M3-W
*
* Copyright (C) 2016 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77960.dtsi"
#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a77960";
compatible = "renesas,salvator-x", "renesas,r8a7796";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W
*
* Copyright (C) 2015-2017 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77960.dtsi"
#include "salvator-xs.dtsi"
/ {
model = "Renesas Salvator-X 2nd version board based on r8a77960";
compatible = "renesas,salvator-xs", "renesas,r8a7796";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB Kingfisher board with R-Car M3-W
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
#include "r8a77960-ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas M3ULCB Kingfisher board based on r8a77960";
compatible = "shimafuji,kingfisher", "renesas,m3ulcb",
"renesas,r8a7796";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77960.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas M3ULCB board based on r8a77960";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77960.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77961.dtsi"
#include "salvator-xs.dtsi"
/ {
model = "Renesas Salvator-X 2nd version board based on r8a77961";
compatible = "renesas,salvator-xs", "renesas,r8a77961";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB Kingfisher board with R-Car M3-W+
*
* Copyright (C) 2020 Eugeniu Rosca <rosca.eugeniu@gmail.com>
*/
#include "r8a77961-ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas M3ULCB Kingfisher board based on r8a77961";
compatible = "shimafuji,kingfisher", "renesas,m3ulcb",
"renesas,r8a77961";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W+
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77961.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas M3ULCB board based on r8a77961";
compatible = "renesas,m3ulcb", "renesas,r8a77961";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77961.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car M3-N
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
*/
/dts-v1/;
#include "r8a77965.dtsi"
#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a77965";
compatible = "renesas,salvator-x", "renesas,r8a77965";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N
*
* Copyright (C) 2017 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77965.dtsi"
#include "salvator-xs.dtsi"
/ {
model = "Renesas Salvator-X 2nd version board based on r8a77965";
compatible = "renesas,salvator-xs", "renesas,r8a77965";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3NULCB Kingfisher board with R-Car M3-N
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#include "r8a77965-ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas M3NULCB Kingfisher board based on r8a77965";
compatible = "shimafuji,kingfisher", "renesas,m3nulcb",
"renesas,r8a77965";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77965.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas M3NULCB board based on r8a77965";
compatible = "renesas,m3nulcb", "renesas,r8a77965";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77965.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Eagle V3M Function expansion board.
*
* Copyright (C) 2024 Niklas Söderlund <niklas.soderlund@ragnatech.se>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* CN4 */
/* Eagle: SW18 set to OFF */
cvbs-in-cn4 {
compatible = "composite-video-connector";
label = "CVBS IN CN4";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
/* CN2 */
/* Eagle: SW35 set 5, 6 and 8 to OFF */
hdmi-in-cn2 {
compatible = "hdmi-connector";
label = "HDMI IN CN2";
type = "a";
port {
hdmi_in_con2: endpoint {
remote-endpoint = <&adv7612_in>;
};
};
};
/* CN3 */
/* Eagle: SW18 set to OFF */
hdmi-in-cn3 {
compatible = "hdmi-connector";
label = "HDMI IN CN3";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
};
/* Disconnect MAX9286 GMSL I2C. */
&i2c3 {
status = "disabled";
};
/* Connect expansion board I2C. */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
gpio@27 {
compatible = "onnn,pca9654";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
vin0-adv7612-en-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-high;
line-name = "VIN0_ADV7612_ENn";
};
};
hdmi-decoder@4c {
compatible = "adi,adv7612";
reg = <0x4c>, <0x50>, <0x52>, <0x54>, <0x56>, <0x58>;
reg-names = "main", "afe", "rep", "edid", "hdmi", "cp";
interrupts-extended = <&gpio3 2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_in_con2>;
};
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0_in>;
};
};
};
};
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70 0x71 0x72 0x73 0x74 0x75
0x60 0x61 0x62 0x63 0x64 0x65>;
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
interrupts-extended = <&gpio3 3 IRQ_TYPE_LEVEL_LOW>,
<&gpio3 4 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "intrq1", "intrq2";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
};
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&d3p3>;
vqmmc-supply = <&d1p8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&pfc {
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
vin0_pins_parallel: vin0 {
groups = "vin0_data12", "vin0_sync", "vin0_clk", "vin0_clkenb";
function = "vin0";
};
};
&vin0 {
status = "okay";
pinctrl-0 = <&vin0_pins_parallel>;
pinctrl-names = "default";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vin0_in: endpoint {
pclk-sample = <0>;
hsync-active = <0>;
vsync-active = <0>;
remote-endpoint = <&adv7612_out>;
};
};
};
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Eagle board with R-Car V3M
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77970.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Eagle board based on r8a77970";
compatible = "renesas,eagle", "renesas,r8a77970";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &scif0;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
d1p8: regulator-fixed {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d3p3: regulator-fixed {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3p3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1p8>;
dvdd-supply = <&d1p8>;
pvdd-supply = <&d1p8>;
dvdd-3v-supply = <&d3p3>;
bgvdd-supply = <&d1p8>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c3_pins: i2c3 {
groups = "i2c3_a";
function = "i2c3";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3M Starter Kit board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77970.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas V3M Starter Kit board";
compatible = "renesas,v3msk", "renesas,r8a77970";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc_d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc5_clk: osc5-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc_d1_8v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC_D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc_d3_3v: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC_D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_vddq_vin0: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "VCC_VDDQ_VIN0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc5_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc_d1_8v>;
dvdd-supply = <&vcc_d1_8v>;
pvdd-supply = <&vcc_d1_8v>;
bgvdd-supply = <&vcc_d1_8v>;
dvdd-3v-supply = <&vcc_d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_d3_3v>;
vqmmc-supply = <&vcc_vddq_vin0>;
bus-width = <8>;
non-removable;
status = "okay";
};
&pfc {
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
mmc_pins: mmc_3_3v {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77970.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor board with R-Car V3H
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77980.dtsi"
#include "condor-common.dtsi"
/ {
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3H Starter Kit board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77980.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas V3H Starter Kit board";
compatible = "renesas,v3hsk", "renesas,r8a77980";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc3v3_d5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
osc1_clk: osc1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc1v8_d4: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC1V8_D4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc3v3_d5: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_D5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc1v8_d4>;
dvdd-supply = <&vcc1v8_d4>;
pvdd-supply = <&vcc1v8_d4>;
bgvdd-supply = <&vcc1v8_d4>;
dvdd-3v-supply = <&vcc3v3_d5>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&pfc {
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
/* Firmware should reserve it but sadly doesn't */
&swdt {
status = "reserved";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77980.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor-I board on r8a77980A (ES2.0)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77980a.dtsi"
#include "condor-common.dtsi"
/ {
model = "Renesas Condor-I board based on r8a77980A (ES2.0)";
compatible = "renesas,condor-i", "renesas,r8a77980a", "renesas,r8a77980";
};
&mmc0 {
mmc-hs400-1_8v;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77980a.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the R-Car V3H2 (R8A77980A) SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a77980.dtsi"
/ {
compatible = "renesas,r8a77980a", "renesas,r8a77980";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Ebisu/Ebisu-4D board with R-Car E3
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77990.dtsi"
#include "ebisu.dtsi"
/ {
model = "Renesas Ebisu board based on r8a77990";
compatible = "renesas,ebisu", "renesas,r8a77990";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77990.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Draak board with R-Car D3
*
* Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*/
/dts-v1/;
#include "r8a77995.dtsi"
#include "draak.dtsi"
/ {
model = "Renesas Draak board based on r8a77995";
compatible = "renesas,draak", "renesas,r8a77995";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a77995.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "r8a779a0.dtsi"
/ {
model = "Renesas Falcon CPU board";
compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio6 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x80000000>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
&dsi0 {
status = "okay";
ports {
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
&i2c6 {
pinctrl-0 = <&i2c6_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
i2c6_pins: i2c6 {
groups = "i2c6";
function = "i2c6";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_6_18", "GP_6_19", "GP_6_20";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0xcc0000>;
read-only;
};
user@cc0000 {
reg = <0xcc0000 0x3340000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
bootph-all;
uart-has-rtscts;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CSI/DSI sub-board
*
* Copyright (C) 2021 Glider bv
*/
#include <dt-bindings/media/video-interfaces.h>
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out0>;
};
};
};
};
&csi42 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi42_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out1>;
};
};
};
};
&csi43 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi43_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out2>;
};
};
};
};
&i2c0 {
pca9654_a: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
pca9654_b: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
pca9654_c: gpio@23 {
compatible = "onnn,pca9654";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
reg = <0x52>;
pagesize = <8>;
};
};
&i2c1 {
gmsl0: gmsl-deserializer@49 {
compatible = "maxim,max96712";
reg = <0x49>;
enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out0: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
gmsl1: gmsl-deserializer@4b {
compatible = "maxim,max96712";
reg = <0x4b>;
enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out1: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
remote-endpoint = <&csi42_in>;
};
};
};
};
gmsl2: gmsl-deserializer@6b {
compatible = "maxim,max96712";
reg = <0x6b>;
enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out2: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
remote-endpoint = <&csi43_in>;
};
};
};
};
};
&isp0 {
status = "okay";
};
&isp2 {
status = "okay";
};
&isp3 {
status = "okay";
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
&vin16 {
status = "okay";
};
&vin17 {
status = "okay";
};
&vin18 {
status = "okay";
};
&vin19 {
status = "okay";
};
&vin20 {
status = "okay";
};
&vin21 {
status = "okay";
};
&vin22 {
status = "okay";
};
&vin23 {
status = "okay";
};
&vin24 {
status = "okay";
};
&vin25 {
status = "okay";
};
&vin26 {
status = "okay";
};
&vin27 {
status = "okay";
};
&vin28 {
status = "okay";
};
&vin29 {
status = "okay";
};
&vin30 {
status = "okay";
};
&vin31 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon Ethernet sub-board
*
* Copyright (C) 2021 Glider bv
*/
/ {
aliases {
ethernet1 = &avb1;
ethernet2 = &avb2;
ethernet3 = &avb3;
ethernet4 = &avb4;
ethernet5 = &avb5;
};
};
&avb1 {
pinctrl-0 = <&avb1_pins>;
pinctrl-names = "default";
phy-handle = <&avb1_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb1_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <7>;
interrupts-extended = <&gpio5 16 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&avb2 {
pinctrl-0 = <&avb2_pins>;
pinctrl-names = "default";
phy-handle = <&avb2_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb2_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <7>;
interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&avb3 {
pinctrl-0 = <&avb3_pins>;
pinctrl-names = "default";
phy-handle = <&avb3_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb3_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <7>;
interrupts-extended = <&gpio7 16 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&avb4 {
pinctrl-0 = <&avb4_pins>;
pinctrl-names = "default";
phy-handle = <&avb4_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb4_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <7>;
interrupts-extended = <&gpio8 16 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&avb5 {
pinctrl-0 = <&avb5_pins>;
pinctrl-names = "default";
phy-handle = <&avb5_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <4000>;
avb5_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <7>;
interrupts-extended = <&gpio9 16 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c0 {
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board-id";
reg = <0x53>;
pagesize = <8>;
};
};
&pfc {
avb1_pins: avb1 {
mux {
groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
"avb1_txcrefclk";
function = "avb1";
};
link {
groups = "avb1_link";
bias-disable;
};
mdio {
groups = "avb1_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb1_rgmii";
drive-strength = <24>;
bias-disable;
};
};
avb2_pins: avb2 {
mux {
groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
"avb2_txcrefclk";
function = "avb2";
};
link {
groups = "avb2_link";
bias-disable;
};
mdio {
groups = "avb2_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb2_rgmii";
drive-strength = <24>;
bias-disable;
};
};
avb3_pins: avb3 {
mux {
groups = "avb3_link", "avb3_mdio", "avb3_rgmii",
"avb3_txcrefclk";
function = "avb3";
};
link {
groups = "avb3_link";
bias-disable;
};
mdio {
groups = "avb3_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb3_rgmii";
drive-strength = <24>;
bias-disable;
};
};
avb4_pins: avb4 {
mux {
groups = "avb4_link", "avb4_mdio", "avb4_rgmii",
"avb4_txcrefclk";
function = "avb4";
};
link {
groups = "avb4_link";
bias-disable;
};
mdio {
groups = "avb4_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb4_rgmii";
drive-strength = <24>;
bias-disable;
};
};
avb5_pins: avb5 {
mux {
groups = "avb5_link", "avb5_mdio", "avb5_rgmii",
"avb5_txcrefclk";
function = "avb5";
};
link {
groups = "avb5_link";
bias-disable;
};
mdio {
groups = "avb5_mdio";
drive-strength = <24>;
bias-disable;
};
rgmii {
groups = "avb5_rgmii";
drive-strength = <24>;
bias-disable;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779a0-falcon-cpu.dtsi"
#include "r8a779a0-falcon-csi-dsi.dtsi"
#include "r8a779a0-falcon-ethernet.dtsi"
/ {
model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
ethernet0 = &avb0;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio4 16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
channel1 {
status = "okay";
};
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};
&pfc {
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the Spider CPU board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "r8a779f0.dtsi"
/ {
model = "Renesas Spider CPU board";
compatible = "renesas,spider-cpu", "renesas,r8a779f0";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &hscif0;
serial1 = &scif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:1843200n8";
};
leds {
compatible = "gpio-leds";
led-7 {
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <7>;
};
led-8 {
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <8>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
rc21012_pci: clk-rc21012-pci {
compatible = "fixed-clock";
clock-frequency = <100000000>;
#clock-cells = <0>;
};
rc21012_ufs: clk-rc21012-ufs {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
bootph-all;
uart-has-rtscts;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gpio_exp_20: gpio@20 {
compatible = "ti,tca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
rc21012-gpio2-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-high;
};
};
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
/*
* This board also has a microSD slot which we will not support upstream
* because we cannot directly switch voltages in software.
*/
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pcie0_clkref {
compatible = "gpio-gate-clock";
clocks = <&rc21012_pci>;
enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
/delete-property/ clock-frequency;
};
&pciec0 {
reset-gpios = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};
&ufs {
status = "okay";
};
&ufs30_clk {
compatible = "gpio-gate-clock";
clocks = <&rc21012_ufs>;
enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>;
/delete-property/ clock-frequency;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Spider Ethernet sub-board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/ {
aliases {
ethernet0 = &rswitch_port0;
ethernet1 = &rswitch_port1;
ethernet2 = &rswitch_port2;
};
};
&eth_serdes {
status = "okay";
};
&i2c4 {
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board";
reg = <0x52>;
pagesize = <8>;
};
};
&pfc {
tsn0_pins: tsn0 {
groups = "tsn0_mdio_b", "tsn0_link_b";
function = "tsn0";
power-source = <1800>;
};
tsn1_pins: tsn1 {
groups = "tsn1_mdio_b", "tsn1_link_b";
function = "tsn1";
power-source = <1800>;
};
tsn2_pins: tsn2 {
groups = "tsn2_mdio_b", "tsn2_link_b";
function = "tsn2";
power-source = <1800>;
};
};
&rswitch {
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rswitch_port0 {
reg = <0>;
phy-handle = <&u101>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
u101: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port1 {
reg = <1>;
phy-handle = <&u201>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
u201: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port2 {
reg = <2>;
phy-handle = <&u301>;
phy-mode = "sgmii";
phys = <&eth_serdes 2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
u301: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the Spider CPU and BreakOut boards
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779f0-spider-cpu.dtsi"
#include "r8a779f0-spider-ethernet.dtsi"
/ {
model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0";
};
&i2c4 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the R-Car S4 Starter Kit board
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "r8a779f4.dtsi"
/ {
model = "R-Car S4 Starter Kit board";
compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &hscif0;
serial1 = &hscif1;
ethernet0 = &rswitch_port0;
ethernet1 = &rswitch_port1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
/* The last 512MB is reserved for CR. */
reg = <0x0 0x48000000 0x0 0x58000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
vcc_sdhi: regulator-vcc-sdhi {
compatible = "regulator-fixed";
regulator-name = "SDHI Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&eth_serdes {
status = "okay";
};
&extal_clk {
clock-frequency = <20000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
bootph-all;
uart-has-rtscts;
status = "okay";
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&i2c5 {
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "st,24c16", "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
};
};
&mmc0 {
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi>;
cd-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data", "hscif1_ctrl";
function = "hscif1";
};
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
sd_pins: sd {
groups = "mmc_data4", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
tsn0_pins: tsn0 {
groups = "tsn0_mdio_b", "tsn0_link_b";
function = "tsn0";
drive-strength = <18>;
power-source = <3300>;
};
tsn1_pins: tsn1 {
groups = "tsn1_mdio_b", "tsn1_link_b";
function = "tsn1";
drive-strength = <18>;
power-source = <3300>;
};
};
&rswitch {
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rswitch_port0 {
reg = <0>;
phy-handle = <&ic99>;
phy-mode = "sgmii";
phys = <&eth_serdes 0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic99: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rswitch_port1 {
reg = <1>;
phy-handle = <&ic102>;
phy-mode = "sgmii";
phys = <&eth_serdes 1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ic102: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};
&ufs {
status = "okay";
};
&ufs30_clk {
clock-frequency = <38400000>;
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779f4.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the R-Car S4-8 (R8A779F4) SoC
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#include "r8a779f0.dtsi"
/ {
compatible = "renesas,r8a779f4", "renesas,r8a779f0";
};
&fuse {
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
ufs_tune: calib@144 {
reg = <0x144 0x08>;
};
};
};
&ufs {
nvmem-cells = <&ufs_tune>;
nvmem-cell-names = "calibration";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the standalone R-Car V4H White Hawk CPU board
*
* Copyright (C) 2023 Glider bv
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
/ {
model = "Renesas White Hawk CPU board based on r8a779g0";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H White Hawk CPU board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a779g0.dtsi"
#include "white-hawk-cpu-common.dtsi"
/ {
model = "Renesas White Hawk CPU board";
compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
#include "white-hawk-common.dtsi"
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
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linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board
*
* Copyright (C) 2023 Glider bv
*/
/dts-v1/;
#include "r8a779g2.dtsi"
#include "white-hawk-single.dtsi"
/ {
model = "Renesas White Hawk Single board based on r8a779g2";
compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
"renesas,r8a779g0";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g2.dtsi
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H (R8A779G2) SoC
*
* Copyright (C) 2023 Glider bv
*/
#include "r8a779g0.dtsi"
/ {
compatible = "renesas,r8a779g2", "renesas,r8a779g0";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for an IMX219 camera sensor on connector J1 on R-Car V4H
* ES3.0 Sparrow Hawk board.
*
* Copyright 2025 Renesas Electronics Corp.
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
&{/} {
clk_cam_j1: clk-cam-j1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
/* Page 29 / CSI_IF_CN / J1 */
reg_cam_j1: reg-cam-j1 {
compatible = "regulator-fixed";
regulator-name = "cam-J1";
enable-active-high;
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
cam@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&clk_cam_j1>;
VANA-supply = <&reg_cam_j1>;
VDIG-supply = <&reg_cam_j1>;
VDDL-supply = <&reg_cam_j1>;
orientation = <2>;
rotation = <0>;
port {
imx219_j1_out: endpoint {
clock-noncontinuous;
link-frequencies = /bits/ 64 <456000000>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
};
/* Page 29 / CSI_IF_CN */
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&imx219_j1_out>;
};
};
};
};
&isp0 {
status = "okay";
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for an IMX462 camera sensor on connector J1 on R-Car V4H
* ES3.0 Sparrow Hawk board.
*
* Copyright 2025 Renesas Electronics Corp.
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
&{/} {
clk_cam_j1: clk-cam-j1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <37125000>;
};
/* Page 29 / CSI_IF_CN / J1 */
reg_cam_j1: reg-cam-j1 {
compatible = "regulator-fixed";
regulator-name = "cam-J1";
enable-active-high;
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
cam@1a {
compatible = "sony,imx462lqr";
reg = <0x1a>;
clocks = <&clk_cam_j1>;
clock-names = "xclk";
clock-frequency = <37125000>;
vdddo-supply = <&reg_cam_j1>;
vdda-supply = <&reg_cam_j1>;
vddd-supply = <&reg_cam_j1>;
orientation = <2>;
rotation = <0>;
port {
imx462_j1_out: endpoint {
link-frequencies = /bits/ 64 <222750000 148500000>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
/* Page 29 / CSI_IF_CN */
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&imx462_j1_out>;
};
};
};
};
&isp0 {
status = "okay";
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso
+116
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for an IMX219 camera sensor on connector J2 on R-Car V4H
* ES3.0 Sparrow Hawk board.
*
* Copyright 2025 Renesas Electronics Corp.
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
&{/} {
clk_cam_j2: clk-cam-j2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
/* Page 29 / CSI_IF_CN / J2 */
reg_cam_j2: reg-cam-j2 {
compatible = "regulator-fixed";
regulator-name = "cam-J2";
enable-active-high;
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
cam@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&clk_cam_j2>;
VANA-supply = <&reg_cam_j2>;
VDIG-supply = <&reg_cam_j2>;
VDDL-supply = <&reg_cam_j2>;
orientation = <2>;
rotation = <0>;
port {
imx219_j2_out: endpoint {
clock-noncontinuous;
link-frequencies = /bits/ 64 <456000000>;
data-lanes = <1 2>;
remote-endpoint = <&csi41_in>;
};
};
};
};
/* Page 29 / CSI_IF_CN */
&csi41 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi41_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&imx219_j2_out>;
};
};
};
};
&isp1 {
status = "okay";
};
&vin08 {
status = "okay";
};
&vin09 {
status = "okay";
};
&vin10 {
status = "okay";
};
&vin11 {
status = "okay";
};
&vin12 {
status = "okay";
};
&vin13 {
status = "okay";
};
&vin14 {
status = "okay";
};
&vin15 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso
+117
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for an IMX462 camera sensor on connector J2 on R-Car V4H
* ES3.0 Sparrow Hawk board.
*
* Copyright 2025 Renesas Electronics Corp.
* Copyright 2025 Niklas Söderlund <niklas.soderlund@ragnatech.se>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
&{/} {
clk_cam_j2: clk-cam-j2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <37125000>;
};
/* Page 29 / CSI_IF_CN / J2 */
reg_cam_j2: reg-cam-j2 {
compatible = "regulator-fixed";
regulator-name = "cam-J2";
enable-active-high;
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
cam@1a {
compatible = "sony,imx462lqr";
reg = <0x1a>;
clocks = <&clk_cam_j2>;
clock-names = "xclk";
clock-frequency = <37125000>;
vdddo-supply = <&reg_cam_j2>;
vdda-supply = <&reg_cam_j2>;
vddd-supply = <&reg_cam_j2>;
orientation = <2>;
rotation = <0>;
port {
imx462_j2_out: endpoint {
link-frequencies = /bits/ 64 <222750000 148500000>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
};
/* Page 29 / CSI_IF_CN */
&csi41 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi41_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&imx462_j2_out>;
};
};
};
};
&isp1 {
status = "okay";
};
&vin08 {
status = "okay";
};
&vin09 {
status = "okay";
};
&vin10 {
status = "okay";
};
&vin11 {
status = "okay";
};
&vin12 {
status = "okay";
};
&vin13 {
status = "okay";
};
&vin14 {
status = "okay";
};
&vin15 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the Argon40 HAT blower fan on connector CN7
* on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*
* Example usage:
*
* # Localize hwmon sysfs directory that matches the PWM fan,
* # enable the PWM fan, and configure the fan speed manually.
* r8a779g3-sparrow-hawk$ ls -1 /sys/devices/platform/pwm-fan-ext/hwmon/hwmon?/pwm?_enable
* /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1_enable
*
* # Select mode 2 , enable fan PWM and regulator and keep them enabled.
* # For details, see Linux Documentation/hwmon/pwm-fan.rst
* r8a779g3-sparrow-hawk$ echo 2 > /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1_enable
*
* # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed .
* # Fan speed 101 is about 2/5 of the PWM fan speed:
* r8a779g3-sparrow-hawk$ echo 101 > /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1
*/
/dts-v1/;
/plugin/;
&{/} {
pwm-fan-ext {
compatible = "pwm-fan";
#cooling-cells = <2>;
/* PWM period: 33us ~= 30 kHz */
pwms = <&pwmhat 0 33334 0>;
/* Available cooling levels */
cooling-levels = <0 50 100 150 200 255>;
fan-shutdown-percent = <100>;
};
};
/* Page 31 / IO_CN */
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
status = "okay";
pwmhat: pwm@1a {
compatible = "argon40,fan-hat";
reg = <0x1a>;
#pwm-cells = <3>;
};
};

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