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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm64/boot/dts/sprd/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
sp9860g-1h10.dtb \
sp9863a-1h10.dtb \
ums512-1h10.dtb \
ums9620-2h10.dtb
linux-7.2.3/arch/arm64/boot/dts/sprd/sc2731.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SC2731 PMIC dts file
*
* Copyright (C) 2018, Spreadtrum Communications Inc.
*/
&adi_bus {
sc2731_pmic: pmic@0 {
compatible = "sprd,sc2731";
reg = <0>;
spi-max-frequency = <26000000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
charger@0 {
compatible = "sprd,sc2731-charger";
reg = <0x0>;
monitored-battery = <&bat>;
};
led-controller@200 {
compatible = "sprd,sc2731-bltc";
reg = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
label = "red";
reg = <0x0>;
};
led@1 {
label = "green";
reg = <0x1>;
};
led@2 {
label = "blue";
reg = <0x2>;
};
};
rtc@280 {
compatible = "sprd,sc2731-rtc";
reg = <0x280>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <2>;
};
pmic_eic: gpio@300 {
compatible = "sprd,sc2731-eic";
reg = <0x300>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
efuse@380 {
compatible = "sprd,sc2731-efuse";
reg = <0x380>;
#address-cells = <1>;
#size-cells = <1>;
hwlocks = <&hwlock 12>;
fgu_calib: calib@6 {
reg = <0x6 0x2>;
bits = <0 9>;
};
adc_big_scale: calib@24 {
reg = <0x24 0x2>;
};
adc_small_scale: calib@26 {
reg = <0x26 0x2>;
};
};
pmic_adc: adc@480 {
compatible = "sprd,sc2731-adc";
reg = <0x480>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <0>;
#io-channel-cells = <1>;
hwlocks = <&hwlock 4>;
nvmem-cell-names = "big_scale_calib", "small_scale_calib";
nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
};
pmic_fgu: fuel-gauge@a00 {
compatible = "sprd,sc2731-fgu";
reg = <0xa00>;
battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
io-channels = <&pmic_adc 3>, <&pmic_adc 6>;
io-channel-names = "bat-temp", "charge-vol";
nvmem-cell-names = "fgu_calib";
nvmem-cells = <&fgu_calib>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <4>;
status = "disabled";
};
vibrator@ec8 {
compatible = "sprd,sc2731-vibrator";
reg = <0xec8>;
};
regulators {
compatible = "sprd,sc2731-regulator";
vddarm0: BUCK_CPU0 {
regulator-name = "vddarm0";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1996875>;
regulator-ramp-delay = <25000>;
regulator-always-on;
};
vddarm1: BUCK_CPU1 {
regulator-name = "vddarm1";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1996875>;
regulator-ramp-delay = <25000>;
regulator-always-on;
};
dcdcrf: BUCK_RF {
regulator-name = "dcdcrf";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2196875>;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <100>;
regulator-always-on;
};
vddcama0: LDO_CAMA0 {
regulator-name = "vddcama0";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
};
vddcama1: LDO_CAMA1 {
regulator-name = "vddcama1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddcammot: LDO_CAMMOT {
regulator-name = "vddcammot";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddvldo: LDO_VLDO {
regulator-name = "vddvldo";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddemmccore: LDO_EMMCCORE {
regulator-name = "vddemmccore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
regulator-boot-on;
};
vddsdcore: LDO_SDCORE {
regulator-name = "vddsdcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddsdio: LDO_SDIO {
regulator-name = "vddsdio";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddwifipa: LDO_WIFIPA {
regulator-name = "vddwifipa";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddusb33: LDO_USB33 {
regulator-name = "vddusb33";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddcamd0: LDO_CAMD0 {
regulator-name = "vddcamd0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1793750>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddcamd1: LDO_CAMD1 {
regulator-name = "vddcamd1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1793750>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddcon: LDO_CON {
regulator-name = "vddcon";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1793750>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddcamio: LDO_CAMIO {
regulator-name = "vddcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1793750>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
};
vddsram: LDO_SRAM {
regulator-name = "vddsram";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1793750>;
regulator-enable-ramp-delay = <100>;
regulator-ramp-delay = <25000>;
regulator-always-on;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sc9836-openphone.dts
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// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Spreadtrum SC9836 openphone board DTS file
*
* Copyright (C) 2014, Spreadtrum Communications Inc.
*/
/dts-v1/;
#include "sc9836.dtsi"
/ {
model = "Spreadtrum SC9836 Openphone Board";
compatible = "sprd,sc9836-openphone", "sprd,sc9836";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x20000000>;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sc9836.dtsi
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// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Spreadtrum SC9836 SoC DTS file
*
* Copyright (C) 2014, Spreadtrum Communications Inc.
*/
#include "sharkl64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "sprd,sc9836";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
etf@10003000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x10003000 0 0x1000>;
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
in-ports {
port {
etf_in: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
funnel@10001000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint = <&etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
port@4 {
reg = <4>;
funnel_in_port4: endpoint {
remote-endpoint = <&stm_out>;
};
};
/* Other input ports aren't connected to anyone */
};
};
etm@10440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x10440000 0 0x1000>;
cpu = <&cpu0>;
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
etm@10540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x10540000 0 0x1000>;
cpu = <&cpu1>;
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
etm@10640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x10640000 0 0x1000>;
cpu = <&cpu2>;
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint = <&funnel_in_port2>;
};
};
};
};
etm@10740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x10740000 0 0x1000>;
cpu = <&cpu3>;
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out: endpoint {
remote-endpoint = <&funnel_in_port3>;
};
};
};
};
stm@10006000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x10006000 0 0x1000>,
<0 0x01000000 0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&clk26mhz>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel_in_port4>;
};
};
};
};
gic: interrupt-controller@12001000 {
compatible = "arm,gic-400";
reg = <0 0x12001000 0 0x1000>,
<0 0x12002000 0 0x2000>,
<0 0x12004000 0 0x2000>,
<0 0x12006000 0 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_on = <0xc4000003>;
cpu_off = <0x84000002>;
cpu_suspend = <0xc4000001>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sc9860.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SC9860 SoC
*
* Copyright (C) 2016, Spreadtrum Communications Inc.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "whale2.dtsi"
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU0: cpu@530000 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530000>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU1: cpu@530001 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530001>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU2: cpu@530002 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530002>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU3: cpu@530003 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530003>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU4: cpu@530100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530100>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU5: cpu@530101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530101>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU6: cpu@530102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530102>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
CPU7: cpu@530103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x530103>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
};
idle-states {
entry-method = "psci";
CORE_PD: cpu-pd {
compatible = "arm,idle-state";
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2500>;
local-timer-stop;
arm,psci-suspend-param = <0x00010002>;
};
CLUSTER_PD: cluster-pd {
compatible = "arm,idle-state";
entry-latency-us = <1000>;
exit-latency-us = <1000>;
min-residency-us = <3000>;
local-timer-stop;
arm,psci-suspend-param = <0x01010003>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>,
<&CPU1>,
<&CPU2>,
<&CPU3>,
<&CPU4>,
<&CPU5>,
<&CPU6>,
<&CPU7>;
};
soc {
gic: interrupt-controller@12001000 {
compatible = "arm,gic-400";
reg = <0 0x12001000 0 0x1000>,
<0 0x12002000 0 0x2000>,
<0 0x12004000 0 0x2000>,
<0 0x12006000 0 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_HIGH)>;
};
ap_clk: clock-controller@20000000 {
compatible = "sprd,sc9860-ap-clk";
reg = <0 0x20000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>,
<&pmu_gate 0>;
#clock-cells = <1>;
};
aon_prediv: aon-prediv@402d0000 {
compatible = "sprd,sc9860-aon-prediv";
reg = <0 0x402d0000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>,
<&pmu_gate 0>;
#clock-cells = <1>;
};
aonsecure_clk: clock-controller@40880000 {
compatible = "sprd,sc9860-aonsecure-clk";
reg = <0 0x40880000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>;
#clock-cells = <1>;
};
gpu_clk: clock-controller@60200000 {
compatible = "sprd,sc9860-gpu-clk";
reg = <0 0x60200000 0 0x400>;
clocks = <&pll 0>;
#clock-cells = <1>;
};
vsp_clk: clock-controller@61000000 {
compatible = "sprd,sc9860-vsp-clk";
reg = <0 0x61000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>;
#clock-cells = <1>;
};
cam_clk: clock-controller@62000000 {
compatible = "sprd,sc9860-cam-clk";
reg = <0 0x62000000 0 0x4000>;
clocks = <&ext_26m>, <&pll 0>;
#clock-cells = <1>;
};
disp_clk: clock-controller@63000000 {
compatible = "sprd,sc9860-disp-clk";
reg = <0 0x63000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>;
#clock-cells = <1>;
};
funnel@10001000 { /* SoC Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
soc_funnel_out_port: endpoint {
remote-endpoint = <&etb_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
soc_funnel_in_port0: endpoint {
remote-endpoint =
<&main_funnel_out_port>;
};
};
port@4 {
reg = <4>;
soc_funnel_in_port1: endpoint {
remote-endpoint =
<&stm_out_port>;
};
};
};
};
etb@10003000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x10003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in: endpoint {
remote-endpoint =
<&soc_funnel_out_port>;
};
};
};
};
stm@10006000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x10006000 0 0x1000>,
<0 0x01000000 0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_port: endpoint {
remote-endpoint =
<&soc_funnel_in_port1>;
};
};
};
};
funnel@11001000 { /* Cluster0 Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x11001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
cluster0_funnel_out_port: endpoint {
remote-endpoint =
<&cluster0_etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster0_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
cluster0_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
cluster0_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@4 {
reg = <4>;
cluster0_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
};
};
funnel@11002000 { /* Cluster1 Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x11002000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
cluster1_funnel_out_port: endpoint {
remote-endpoint =
<&cluster1_etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster1_funnel_in_port0: endpoint {
remote-endpoint = <&etm4_out>;
};
};
port@1 {
reg = <1>;
cluster1_funnel_in_port1: endpoint {
remote-endpoint = <&etm5_out>;
};
};
port@2 {
reg = <2>;
cluster1_funnel_in_port2: endpoint {
remote-endpoint = <&etm6_out>;
};
};
port@3 {
reg = <3>;
cluster1_funnel_in_port3: endpoint {
remote-endpoint = <&etm7_out>;
};
};
};
};
etf@11003000 { /* ETF on Cluster0 */
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x11003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
cluster0_etf_out: endpoint {
remote-endpoint =
<&main_funnel_in_port0>;
};
};
};
in-ports {
port {
cluster0_etf_in: endpoint {
remote-endpoint =
<&cluster0_funnel_out_port>;
};
};
};
};
etf@11004000 { /* ETF on Cluster1 */
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x11004000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
cluster1_etf_out: endpoint {
remote-endpoint =
<&main_funnel_in_port1>;
};
};
};
in-ports {
port {
cluster1_etf_in: endpoint {
remote-endpoint =
<&cluster1_funnel_out_port>;
};
};
};
};
funnel@11005000 { /* Main Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x11005000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
main_funnel_out_port: endpoint {
remote-endpoint =
<&soc_funnel_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
main_funnel_in_port0: endpoint {
remote-endpoint =
<&cluster0_etf_out>;
};
};
port@1 {
reg = <1>;
main_funnel_in_port1: endpoint {
remote-endpoint =
<&cluster1_etf_out>;
};
};
};
};
etm@11440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11440000 0 0x1000>;
cpu = <&CPU0>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&cluster0_funnel_in_port0>;
};
};
};
};
etm@11540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11540000 0 0x1000>;
cpu = <&CPU1>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&cluster0_funnel_in_port1>;
};
};
};
};
etm@11640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11640000 0 0x1000>;
cpu = <&CPU2>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&cluster0_funnel_in_port2>;
};
};
};
};
etm@11740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11740000 0 0x1000>;
cpu = <&CPU3>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&cluster0_funnel_in_port3>;
};
};
};
};
etm@11840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11840000 0 0x1000>;
cpu = <&CPU4>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm4_out: endpoint {
remote-endpoint =
<&cluster1_funnel_in_port0>;
};
};
};
};
etm@11940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11940000 0 0x1000>;
cpu = <&CPU5>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm5_out: endpoint {
remote-endpoint =
<&cluster1_funnel_in_port1>;
};
};
};
};
etm@11a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11a40000 0 0x1000>;
cpu = <&CPU6>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm6_out: endpoint {
remote-endpoint =
<&cluster1_funnel_in_port2>;
};
};
};
};
etm@11b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x11b40000 0 0x1000>;
cpu = <&CPU7>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm7_out: endpoint {
remote-endpoint =
<&cluster1_funnel_in_port3>;
};
};
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sc9863a.dtsi
+589
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@@ -0,0 +1,589 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Unisoc SC9863A SoC DTS file
*
* Copyright (C) 2019, Unisoc Inc.
*/
#include <dt-bindings/clock/sprd,sc9863a-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sharkl3.dtsi"
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
};
idle-states {
entry-method = "psci";
CORE_PD: cpu-pd {
compatible = "arm,idle-state";
entry-latency-us = <4000>;
exit-latency-us = <4000>;
min-residency-us = <10000>;
local-timer-stop;
arm,psci-suspend-param = <0x00010000>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
gic: interrupt-controller@14000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
redistributor-stride = <0x0 0x20000>; /* 128KB stride */
#redistributor-regions = <1>;
interrupt-controller;
reg = <0x0 0x14000000 0 0x20000>, /* GICD */
<0x0 0x14040000 0 0x100000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ap_clk: clock-controller@21500000 {
compatible = "sprd,sc9863a-ap-clk";
reg = <0 0x21500000 0 0x1000>;
clocks = <&ext_26m>, <&ext_32k>;
clock-names = "ext-26m", "ext-32k";
#clock-cells = <1>;
};
aon_clk: clock-controller@402d0000 {
compatible = "sprd,sc9863a-aon-clk";
reg = <0 0x402d0000 0 0x1000>;
clocks = <&ext_26m>, <&ext_32k>,
<&ext_4m>, <&rco_100m>;
clock-names = "ext-26m", "ext-32k",
"ext-4m", "rco-100m";
#clock-cells = <1>;
};
mm_clk: clock-controller@60900000 {
compatible = "sprd,sc9863a-mm-clk";
reg = <0 0x60900000 0 0x1000>;
#clock-cells = <1>;
};
funnel@10001000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_soc_out_port: endpoint {
remote-endpoint = <&etb_in>;
};
};
};
in-ports {
port {
funnel_soc_in_port: endpoint {
remote-endpoint =
<&funnel_ca55_out_port>;
};
};
};
};
etb@10003000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x10003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in: endpoint {
remote-endpoint =
<&funnel_soc_out_port>;
};
};
};
};
funnel@12001000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x12001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_little_out_port: endpoint {
remote-endpoint =
<&etf_little_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_little_in_port0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_little_in_port1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
funnel_little_in_port2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
funnel_little_in_port3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
};
};
etf@12002000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x12002000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etf_little_out: endpoint {
remote-endpoint =
<&funnel_ca55_in_port0>;
};
};
};
in-ports {
port {
etf_little_in: endpoint {
remote-endpoint =
<&funnel_little_out_port>;
};
};
};
};
etf@12003000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x12003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etf_big_out: endpoint {
remote-endpoint =
<&funnel_ca55_in_port1>;
};
};
};
in-ports {
port {
etf_big_in: endpoint {
remote-endpoint =
<&funnel_big_out_port>;
};
};
};
};
funnel@12004000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x12004000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_ca55_out_port: endpoint {
remote-endpoint =
<&funnel_soc_in_port>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_ca55_in_port0: endpoint {
remote-endpoint =
<&etf_little_out>;
};
};
port@1 {
reg = <1>;
funnel_ca55_in_port1: endpoint {
remote-endpoint =
<&etf_big_out>;
};
};
};
};
funnel@12005000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x12005000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_big_out_port: endpoint {
remote-endpoint =
<&etf_big_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_big_in_port0: endpoint {
remote-endpoint = <&etm4_out>;
};
};
port@1 {
reg = <1>;
funnel_big_in_port1: endpoint {
remote-endpoint = <&etm5_out>;
};
};
port@2 {
reg = <2>;
funnel_big_in_port2: endpoint {
remote-endpoint = <&etm6_out>;
};
};
port@3 {
reg = <3>;
funnel_big_in_port3: endpoint {
remote-endpoint = <&etm7_out>;
};
};
};
};
etm@13040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13040000 0 0x1000>;
cpu = <&CPU0>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&funnel_little_in_port0>;
};
};
};
};
etm@13140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13140000 0 0x1000>;
cpu = <&CPU1>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&funnel_little_in_port1>;
};
};
};
};
etm@13240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13240000 0 0x1000>;
cpu = <&CPU2>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&funnel_little_in_port2>;
};
};
};
};
etm@13340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13340000 0 0x1000>;
cpu = <&CPU3>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&funnel_little_in_port3>;
};
};
};
};
etm@13440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13440000 0 0x1000>;
cpu = <&CPU4>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm4_out: endpoint {
remote-endpoint =
<&funnel_big_in_port0>;
};
};
};
};
etm@13540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13540000 0 0x1000>;
cpu = <&CPU5>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm5_out: endpoint {
remote-endpoint =
<&funnel_big_in_port1>;
};
};
};
};
etm@13640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13640000 0 0x1000>;
cpu = <&CPU6>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm6_out: endpoint {
remote-endpoint =
<&funnel_big_in_port2>;
};
};
};
};
etm@13740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x13740000 0 0x1000>;
cpu = <&CPU7>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm7_out: endpoint {
remote-endpoint =
<&funnel_big_in_port3>;
};
};
};
};
ahb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
sdio0: mmc@20300000 {
compatible = "sprd,sdhci-r11";
reg = <0 0x20300000 0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&aon_clk CLK_SDIO0_2X>,
<&apahb_gate CLK_SDIO0_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
assigned-clock-parents = <&rpll CLK_RPLL_390M>;
bus-width = <4>;
no-sdio;
no-mmc;
};
sdio3: mmc@20600000 {
compatible = "sprd,sdhci-r11";
reg = <0 0x20600000 0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&aon_clk CLK_EMMC_2X>,
<&apahb_gate CLK_EMMC_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&aon_clk CLK_EMMC_2X>;
assigned-clock-parents = <&rpll CLK_RPLL_390M>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
cap-mmc-hw-reset;
};
};
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sharkl3.dtsi
+242
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@@ -0,0 +1,242 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Unisoc Sharkl3 platform DTS file
*
* Copyright (C) 2019, Unisoc Inc.
*/
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ap_ahb_regs: syscon@20e00000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x20e00000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x20e00000 0x4000>;
apahb_gate: apahb-gate@0 {
compatible = "sprd,sc9863a-apahb-gate";
reg = <0x0 0x1020>;
#clock-cells = <1>;
};
};
pmu_regs: syscon@402b0000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x402b0000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x402b0000 0x4000>;
pmu_gate: pmu-gate@0 {
compatible = "sprd,sc9863a-pmu-gate";
reg = <0 0x1200>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
aon_apb_regs: syscon@402e0000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x402e0000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x402e0000 0x4000>;
aonapb_gate: aonapb-gate@0 {
compatible = "sprd,sc9863a-aonapb-gate";
reg = <0 0x1100>;
#clock-cells = <1>;
};
};
anlg_phy_g2_regs: syscon@40353000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x40353000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40353000 0x3000>;
pll: pll@0 {
compatible = "sprd,sc9863a-pll";
reg = <0 0x100>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
anlg_phy_g4_regs: syscon@40359000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x40359000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40359000 0x3000>;
mpll: mpll@0 {
compatible = "sprd,sc9863a-mpll";
reg = <0 0x100>;
#clock-cells = <1>;
};
};
anlg_phy_g5_regs: syscon@4035c000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x4035c000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x4035c000 0x3000>;
rpll: rpll@0 {
compatible = "sprd,sc9863a-rpll";
reg = <0 0x100>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
anlg_phy_g7_regs: syscon@40363000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x40363000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40363000 0x3000>;
dpll: dpll@0 {
compatible = "sprd,sc9863a-dpll";
reg = <0 0x100>;
#clock-cells = <1>;
};
};
mm_ahb_regs: syscon@60800000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x60800000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x60800000 0x3000>;
mm_gate: mm-gate@0 {
compatible = "sprd,sc9863a-mm-gate";
reg = <0 0x1100>;
#clock-cells = <1>;
};
};
ap_apb_regs: syscon@71300000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x71300000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x71300000 0x4000>;
apapb_gate: apapb-gate@0 {
compatible = "sprd,sc9863a-apapb-gate";
reg = <0 0x1000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x70000000 0x10000000>;
uart0: serial@0 {
compatible = "sprd,sc9863a-uart",
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart1: serial@100000 {
compatible = "sprd,sc9863a-uart",
"sprd,sc9836-uart";
reg = <0x100000 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart2: serial@200000 {
compatible = "sprd,sc9863a-uart",
"sprd,sc9836-uart";
reg = <0x200000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart3: serial@300000 {
compatible = "sprd,sc9863a-uart",
"sprd,sc9836-uart";
reg = <0x300000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart4: serial@400000 {
compatible = "sprd,sc9863a-uart",
"sprd,sc9836-uart";
reg = <0x400000 0x100>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
};
};
ext_26m: ext-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
ext_32k: ext-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
ext_4m: ext-4m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <4000000>;
clock-output-names = "ext-4m";
};
rco_100m: rco-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "rco-100m";
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sharkl64.dtsi
+64
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// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Spreadtrum Sharkl64 platform DTS file
*
* Copyright (C) 2014, Spreadtrum Communications Inc.
*/
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
uart0: serial@70000000 {
compatible = "sprd,sc9836-uart";
reg = <0 0x70000000 0 0x100>;
interrupts = <0 2 0xf04>;
clocks = <&clk26mhz>;
status = "disabled";
};
uart1: serial@70100000 {
compatible = "sprd,sc9836-uart";
reg = <0 0x70100000 0 0x100>;
interrupts = <0 3 0xf04>;
clocks = <&clk26mhz>;
status = "disabled";
};
uart2: serial@70200000 {
compatible = "sprd,sc9836-uart";
reg = <0 0x70200000 0 0x100>;
interrupts = <0 4 0xf04>;
clocks = <&clk26mhz>;
status = "disabled";
};
uart3: serial@70300000 {
compatible = "sprd,sc9836-uart";
reg = <0 0x70300000 0 0x100>;
interrupts = <0 5 0xf04>;
clocks = <&clk26mhz>;
status = "disabled";
};
};
};
clk26mhz: clk26mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SP9860g board
*
* Copyright (C) 2017, Spreadtrum Communications Inc.
*/
/dts-v1/;
#include "sc9860.dtsi"
#include "sc2731.dtsi"
/ {
model = "Spreadtrum SP9860G 3GFHD Board";
compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
aliases {
serial0 = &uart0; /* for Bluetooth */
serial1 = &uart1; /* UART console */
serial2 = &uart2; /* Reserved */
serial3 = &uart3; /* for GPS */
spi0 = &adi_bus;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x60000000>,
<0x1 0x80000000 0 0x60000000>;
};
chosen {
stdout-path = "serial1:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
debounce-interval = <2>;
wakeup-source;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
debounce-interval = <2>;
wakeup-source;
};
key-power {
label = "Power Key";
linux,code = <KEY_POWER>;
gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
debounce-interval = <2>;
wakeup-source;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
bat: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <1900000>;
charge-term-current-microamp = <120000>;
constant-charge-voltage-max-microvolt = <4350000>;
factory-internal-resistance-micro-ohms = <250000>;
ocv-capacity-celsius = <20>;
ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
<4022000 85>, <3983000 80>, <3949000 75>,
<3917000 70>, <3889000 65>, <3864000 60>,
<3835000 55>, <3805000 50>, <3787000 45>,
<3777000 40>, <3773000 35>, <3770000 30>,
<3765000 25>, <3752000 20>, <3724000 15>,
<3680000 10>, <3605000 5>, <3400000 0>;
};
};
&pmic_fgu {
monitored-battery = <&bat>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Unisoc SP9863A-1h10 boards DTS file
*
* Copyright (C) 2019, Unisoc Inc.
*/
/dts-v1/;
#include "sc9863a.dtsi"
/ {
model = "Spreadtrum SP9863A-1H10 Board";
compatible = "sprd,sp9863a-1h10", "sprd,sc9863a";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
chosen {
stdout-path = "serial1:115200n8";
bootargs = "earlycon";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/sprd/ums512-1h10.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Unisoc UMS512-1h10 boards DTS file
*
* Copyright (C) 2021, Unisoc Inc.
*/
/dts-v1/;
#include "ums512.dtsi"
/ {
model = "Unisoc UMS512-1H10 Board";
compatible = "sprd,ums512-1h10", "sprd,ums512";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
/* SD card */
&sdio0 {
bus-width = <4>;
no-sdio;
no-mmc;
sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>;
sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>;
sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>;
sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>;
sd-uhs-sdr104;
sd-uhs-sdr50;
};
/* EMMC storage */
&sdio3 {
status = "okay";
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
cap-mmc-hw-reset;
};
linux-7.2.3/arch/arm64/boot/dts/sprd/ums512.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Unisoc UMS512 SoC DTS file
*
* Copyright (C) 2021, Unisoc Inc.
*/
#include <dt-bindings/clock/sprd,ums512-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a75";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a75";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
};
};
idle-states {
entry-method = "psci";
CORE_PD: cpu-pd {
compatible = "arm,idle-state";
entry-latency-us = <4000>;
exit-latency-us = <4000>;
min-residency-us = <10000>;
local-timer-stop;
arm,psci-suspend-param = <0x00010000>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
pmu-a75 {
compatible = "arm,cortex-a75-pmu";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU6>, <&CPU7>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@12000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x12000000 0 0x20000>, /* GICD */
<0x0 0x12040000 0 0x100000>; /* GICR */
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
redistributor-stride = <0x0 0x20000>; /* 128KB stride */
#redistributor-regions = <1>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ap_ahb_regs: syscon@20100000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x20100000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x20100000 0x4000>;
apahb_gate: clock-controller@0 {
compatible = "sprd,ums512-apahb-gate";
reg = <0x0 0x3000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
pub_apb_regs: syscon@31050000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x31050000 0 0x9000>;
};
top_dvfs_apb_regs: syscon@322a0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x322a0000 0 0x8000>;
};
ap_intc0_regs: syscon@32310000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32310000 0 0x1000>;
};
ap_intc1_regs: syscon@32320000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32320000 0 0x1000>;
};
ap_intc2_regs: syscon@32330000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32330000 0 0x1000>;
};
ap_intc3_regs: syscon@32340000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32340000 0 0x1000>;
};
ap_intc4_regs: syscon@32350000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32350000 0 0x1000>;
};
ap_intc5_regs: syscon@32360000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32360000 0 0x1000>;
};
anlg_phy_g0_regs: syscon@32390000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x32390000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x32390000 0x3000>;
dpll0: clock-controller@0 {
compatible = "sprd,ums512-g0-pll";
reg = <0x0 0x100>;
#clock-cells = <1>;
};
};
anlg_phy_g2_regs: syscon@323b0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x323b0000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x323b0000 0x3000>;
mpll1: clock-controller@0 {
compatible = "sprd,ums512-g2-pll";
reg = <0x0 0x100>;
#clock-cells = <1>;
};
};
anlg_phy_g3_regs: syscon@323c0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x323c0000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x323c0000 0x3000>;
pll1: clock-controller@0 {
compatible = "sprd,ums512-g3-pll";
reg = <0x0 0x3000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
anlg_phy_gc_regs: syscon@323e0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x323e0000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x323e0000 0x3000>;
pll2: clock-controller@0 {
compatible = "sprd,ums512-gc-pll";
reg = <0x0 0x100>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
anlg_phy_g10_regs: syscon@323f0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x323f0000 0 0x3000>;
};
aon_apb_regs: syscon@327d0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x327d0000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x327d0000 0x3000>;
aonapb_gate: clock-controller@0 {
compatible = "sprd,ums512-aon-gate";
reg = <0x0 0x3000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
pmu_apb_regs: syscon@327e0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x327e0000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x327e0000 0x3000>;
pmu_gate: clock-controller@0 {
compatible = "sprd,ums512-pmu-gate";
reg = <0x0 0x3000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
audcp_apb_regs: syscon@3350d000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x3350d000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x3350d000 0x1000>;
audcpapb_gate: clock-controller@0 {
compatible = "sprd,ums512-audcpapb-gate";
reg = <0x0 0x300>;
#clock-cells = <1>;
};
};
audcp_ahb_regs: syscon@335e0000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x335e0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x335e0000 0x1000>;
audcpahb_gate: clock-controller@0 {
compatible = "sprd,ums512-audcpahb-gate";
reg = <0x0 0x300>;
#clock-cells = <1>;
};
};
gpu_apb_regs: syscon@60100000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x60100000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x60100000 0x3000>;
gpu_clk: clock-controller@0 {
compatible = "sprd,ums512-gpu-clk";
clocks = <&ext_26m>;
clock-names = "ext-26m";
reg = <0x0 0x100>;
#clock-cells = <1>;
};
};
gpu_dvfs_apb_regs: syscon@60110000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x60110000 0 0x3000>;
};
mm_ahb_regs: syscon@62200000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x62200000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x62200000 0x3000>;
mm_gate: clock-controller@0 {
compatible = "sprd,ums512-mm-gate-clk";
reg = <0x0 0x3000>;
#clock-cells = <1>;
};
};
ap_apb_regs: syscon@71000000 {
compatible = "sprd,ums512-glbregs", "syscon",
"simple-mfd";
reg = <0 0x71000000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x71000000 0x3000>;
apapb_gate: clock-controller@0 {
compatible = "sprd,ums512-apapb-gate";
reg = <0x0 0x3000>;
#clock-cells = <1>;
};
};
ap_clk: clock-controller@20200000 {
compatible = "sprd,ums512-ap-clk";
reg = <0 0x20200000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
aon_clk: clock-controller@32080000 {
compatible = "sprd,ums512-aonapb-clk";
reg = <0 0x32080000 0 0x1000>;
clocks = <&ext_26m>, <&ext_32k>,
<&ext_4m>, <&rco_100m>;
clock-names = "ext-26m", "ext-32k",
"ext-4m", "rco-100m";
#clock-cells = <1>;
};
mm_clk: clock-controller@62100000 {
compatible = "sprd,ums512-mm-clk";
reg = <0 0x62100000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
/* SoC Funnel */
funnel@3c002000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x3c002000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_soc_out_port: endpoint {
remote-endpoint = <&etb_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
funnel_soc_in_port: endpoint {
remote-endpoint =
<&funnel_corinth_out_port>;
};
};
};
};
/* SoC ETF */
soc_etb: etb@3c003000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x3c003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in: endpoint {
remote-endpoint =
<&funnel_soc_out_port>;
};
};
};
};
/* AP-CPU Funnel for core3/4/5/7 */
funnel@3e001000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x3e001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_corinth_lit_out_port: endpoint {
remote-endpoint =
<&corinth_etf_lit_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_core_in_port3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
port@1 {
reg = <1>;
funnel_core_in_port4: endpoint {
remote-endpoint = <&etm4_out>;
};
};
port@2 {
reg = <2>;
funnel_core_in_port5: endpoint {
remote-endpoint = <&etm5_out>;
};
};
port@3 {
reg = <3>;
funnel_core_in_port7: endpoint {
remote-endpoint = <&etm7_out>;
};
};
};
};
/* AP-CPU ETF for little cores */
etf@3e002000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x3e002000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
corinth_etf_lit_out: endpoint {
remote-endpoint =
<&funnel_corinth_from_lit_in_port>;
};
};
};
in-ports {
port {
corinth_etf_lit_in: endpoint {
remote-endpoint =
<&funnel_corinth_lit_out_port>;
};
};
};
};
/* AP-CPU ETF for big cores */
etf@3e003000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x3e003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
corinth_etf_big_out: endpoint {
remote-endpoint =
<&funnel_corinth_from_big_in_port>;
};
};
};
in-ports {
port {
corinth_etf_big_in: endpoint {
remote-endpoint =
<&funnel_corinth_big_out_port>;
};
};
};
};
/* Funnel to SoC */
funnel@3e004000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x3e004000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_corinth_out_port: endpoint {
remote-endpoint =
<&funnel_soc_in_port>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_corinth_from_lit_in_port: endpoint {
remote-endpoint = <&corinth_etf_lit_out>;
};
};
port@1 {
reg = <1>;
funnel_corinth_from_big_in_port: endpoint {
remote-endpoint = <&corinth_etf_big_out>;
};
};
};
};
/* AP-CPU Funnel for core0/1/2/6 */
funnel@3e005000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x3e005000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_corinth_big_out_port: endpoint {
remote-endpoint = <&corinth_etf_big_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_core_in_port0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_core_in_port1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
funnel_core_in_port2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
funnel_core_in_port6: endpoint {
remote-endpoint = <&etm6_out>;
};
};
};
};
etm0: etm@3f040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f040000 0 0x1000>;
cpu = <&CPU0>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&funnel_core_in_port0>;
};
};
};
};
etm1: etm@3f140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f140000 0 0x1000>;
cpu = <&CPU1>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&funnel_core_in_port1>;
};
};
};
};
etm2: etm@3f240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f240000 0 0x1000>;
cpu = <&CPU2>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&funnel_core_in_port2>;
};
};
};
};
etm3: etm@3f340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f340000 0 0x1000>;
cpu = <&CPU3>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&funnel_core_in_port3>;
};
};
};
};
etm4: etm@3f440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f440000 0 0x1000>;
cpu = <&CPU4>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm4_out: endpoint {
remote-endpoint =
<&funnel_core_in_port4>;
};
};
};
};
etm5: etm@3f540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f540000 0 0x1000>;
cpu = <&CPU5>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm5_out: endpoint {
remote-endpoint =
<&funnel_core_in_port5>;
};
};
};
};
etm6: etm@3f640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f640000 0 0x1000>;
cpu = <&CPU6>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm6_out: endpoint {
remote-endpoint =
<&funnel_core_in_port6>;
};
};
};
};
etm7: etm@3f740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f740000 0 0x1000>;
cpu = <&CPU7>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
out-ports {
port {
etm7_out: endpoint {
remote-endpoint =
<&funnel_core_in_port7>;
};
};
};
};
apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x70000000 0x10000000>;
uart0: serial@0 {
compatible = "sprd,ums512-uart",
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart1: serial@100000 {
compatible = "sprd,ums512-uart",
"sprd,sc9836-uart";
reg = <0x100000 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
sdio0: mmc@1100000 {
compatible = "sprd,sdhci-r11";
reg = <0x1100000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk CLK_SDIO0_2X>,
<&apapb_gate CLK_SDIO0_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
assigned-clock-parents = <&pll1 CLK_RPLL>;
status = "disabled";
};
sdio3: mmc@1400000 {
compatible = "sprd,sdhci-r11";
reg = <0x1400000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk CLK_EMMC_2X>,
<&apapb_gate CLK_EMMC_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&ap_clk CLK_EMMC_2X>;
assigned-clock-parents = <&pll1 CLK_RPLL>;
status = "disabled";
};
};
aon: bus@32000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x32000000 0x1000000>;
adi_bus: spi@100000 {
compatible = "sprd,ums512-adi";
reg = <0x100000 0x100000>;
#address-cells = <1>;
#size-cells = <0>;
sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
<17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
<35 0x19b8>, <39 0x19ac>;
};
};
};
ext_26m: clk-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
ext_32k: clk-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
ext_4m: clk-4m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <4000000>;
clock-output-names = "ext-4m";
};
rco_100m: clk-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "rco-100m";
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/ums9620-2h10.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Unisoc UMS9620-2h10 board DTS file
*
* Copyright (C) 2023, Unisoc Inc.
*/
/dts-v1/;
#include "ums9620.dtsi"
/ {
model = "Unisoc UMS9620-2H10 Board";
compatible = "sprd,ums9620-2h10", "sprd,ums9620";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
chosen {
stdout-path = "serial1:921600n8";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/sprd/ums9620.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Unisoc UMS9620 DTS file
*
* Copyright (C) 2023, Unisoc Inc.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&LIT_CORE_PD>;
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&LIT_CORE_PD>;
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&LIT_CORE_PD>;
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&LIT_CORE_PD>;
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&BIG_CORE_PD>;
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&BIG_CORE_PD>;
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&BIG_CORE_PD>;
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&BIG_CORE_PD>;
};
};
idle-states {
entry-method = "psci";
LIT_CORE_PD: cpu-pd-lit {
compatible = "arm,idle-state";
entry-latency-us = <1000>;
exit-latency-us = <500>;
min-residency-us = <2500>;
local-timer-stop;
arm,psci-suspend-param = <0x00010000>;
};
BIG_CORE_PD: cpu-pd-big {
compatible = "arm,idle-state";
entry-latency-us = <4000>;
exit-latency-us = <4000>;
min-residency-us = <10000>;
local-timer-stop;
arm,psci-suspend-param = <0x00010000>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
soc: soc {
compatible = "simple-bus";
ranges;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@12000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x12000000 0 0x20000>, /* GICD */
<0x0 0x12040000 0 0x100000>; /* GICR */
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
redistributor-stride = <0x0 0x20000>; /* 128KB stride */
#redistributor-regions = <1>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apb@20200000 {
compatible = "simple-bus";
ranges = <0 0 0x20200000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
uart0: serial@0 {
compatible = "sprd,ums9620-uart",
"sprd,sc9836-uart";
reg = <0 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
uart1: serial@10000 {
compatible = "sprd,ums9620-uart",
"sprd,sc9836-uart";
reg = <0x10000 0x100>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_26m>;
status = "disabled";
};
};
};
ext_26m: clk-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
ext_4m: clk-4m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <4000000>;
clock-output-names = "ext-4m";
};
ext_32k: clk-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
rco_100m: clk-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "rco-100m";
};
dphy_312m5: dphy-312m5 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <312500000>;
clock-output-names = "dphy-312m5";
};
dphy_416m7: dphy-416m7 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <416700000>;
clock-output-names = "dphy-416m7";
};
};
linux-7.2.3/arch/arm64/boot/dts/sprd/whale2.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum Whale2 platform peripherals
*
* Copyright (C) 2016, Spreadtrum Communications Inc.
*/
#include <dt-bindings/clock/sprd,sc9860-clk.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apahb_gate: clock-controller@20210000 {
reg = <0 0x20210000 0 0x10000>;
compatible = "sprd,sc9860-apahb-gate";
clocks = <&aon_prediv 0>;
#clock-cells = <1>;
};
pmu_gate: clock-controller@402b0000 {
reg = <0 0x402b0000 0 0x10000>;
compatible = "sprd,sc9860-pmu-gate";
clocks = <&ext_26m>;
#clock-cells = <1>;
};
aon_gate: clock-controller@402e0000 {
reg = <0 0x402e0000 0 0x10000>;
compatible = "sprd,sc9860-aon-gate";
clocks = <&aon_prediv 0>;
#clock-cells = <1>;
};
pll: clock-controller@40400000 {
reg = <0 0x40400000 0 0x10000>;
compatible = "sprd,sc9860-pll";
clocks = <&pmu_gate 0>;
#clock-cells = <1>;
};
agcp_gate: clock-controller@415e0000 {
reg = <0 0x415e0000 0 0x1000000>;
compatible = "sprd,sc9860-agcp-gate";
clocks = <&aon_prediv 0>;
#clock-cells = <1>;
};
vsp_gate: clock-controller@61100000 {
reg = <0 0x61100000 0 0x10000>;
compatible = "sprd,sc9860-vsp-gate";
clocks = <&vsp_clk 0>;
#clock-cells = <1>;
};
cam_gate: clock-controller@62100000 {
reg = <0 0x62100000 0 0x10000>;
compatible = "sprd,sc9860-cam-gate";
clocks = <&cam_clk 0>;
#clock-cells = <1>;
};
disp_gate: clock-controller@63100000 {
reg = <0 0x63100000 0 0x10000>;
compatible = "sprd,sc9860-disp-gate";
clocks = <&disp_clk 0>;
#clock-cells = <1>;
};
apapb_gate: clock-controller@70b00000 {
reg = <0 0x70b00000 0 0x40000>;
compatible = "sprd,sc9860-apapb-gate";
clocks = <&ap_clk 0>;
#clock-cells = <1>;
};
apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x70000000 0x10000000>;
uart0: serial@0 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apapb_gate CLK_UART0_EB>,
<&ap_clk CLK_UART0>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
uart1: serial@100000 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x100000 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apapb_gate CLK_UART1_EB>,
<&ap_clk CLK_UART1>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
uart2: serial@200000 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x200000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apapb_gate CLK_UART2_EB>,
<&ap_clk CLK_UART2>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
uart3: serial@300000 {
compatible = "sprd,sc9860-uart",
"sprd,sc9836-uart";
reg = <0x300000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apapb_gate CLK_UART3_EB>,
<&ap_clk CLK_UART3>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
};
ahb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ap_dma: dma-controller@20100000 {
compatible = "sprd,sc9860-dma";
reg = <0 0x20100000 0 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
/* For backwards compatibility: */
#dma-channels = <32>;
dma-channels = <32>;
clocks = <&apahb_gate CLK_DMA_EB>;
clock-names = "enable";
};
sdio3: mmc@50430000 {
compatible = "sprd,sdhci-r11";
reg = <0 0x50430000 0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&aon_prediv CLK_EMMC_2X>,
<&apahb_gate CLK_EMMC_EB>,
<&aon_gate CLK_EMMC_2X_EN>;
clock-names = "sdio", "enable", "2x_enable";
assigned-clocks = <&aon_prediv CLK_EMMC_2X>;
assigned-clock-parents = <&clk_l0_409m6>;
sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
vmmc-supply = <&vddemmccore>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
cap-mmc-hw-reset;
mmc-hs400-enhanced-strobe;
mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
};
};
aon-bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
adi_bus: spi@40030000 {
compatible = "sprd,sc9860-adi";
reg = <0 0x40030000 0 0x10000>;
hwlocks = <&hwlock 0>;
hwlock-names = "adi";
#address-cells = <1>;
#size-cells = <0>;
};
timer@40050000 {
compatible = "sprd,sc9860-timer";
reg = <0 0x40050000 0 0x20>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ext_32k>;
};
timer@40050020 {
compatible = "sprd,sc9860-suspend-timer";
reg = <0 0x40050020 0 0x20>;
clocks = <&ext_32k>;
};
hwlock: hwspinlock@40500000 {
compatible = "sprd,hwspinlock-r3p0";
reg = <0 0x40500000 0 0x1000>;
#hwlock-cells = <1>;
clocks = <&aon_gate CLK_SPLK_EB>;
clock-names = "enable";
};
eic_debounce: gpio@40210000 {
compatible = "sprd,sc9860-eic-debounce";
reg = <0 0x40210000 0 0x80>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_latch: gpio@40210080 {
compatible = "sprd,sc9860-eic-latch";
reg = <0 0x40210080 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_async: gpio@402100a0 {
compatible = "sprd,sc9860-eic-async";
reg = <0 0x402100a0 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_sync: gpio@402100c0 {
compatible = "sprd,sc9860-eic-sync";
reg = <0 0x402100c0 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
ap_gpio: gpio@40280000 {
compatible = "sprd,sc9860-gpio";
reg = <0 0x40280000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
pin_controller: pinctrl@402a0000 {
compatible = "sprd,sc9860-pinctrl";
reg = <0 0x402a0000 0 0x10000>;
};
watchdog@40310000 {
compatible = "sprd,sp9860-wdt";
reg = <0 0x40310000 0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <12>;
clocks = <&aon_gate CLK_APCPU_WDG_EB>,
<&aon_gate CLK_AP_WDG_RTC_EB>;
clock-names = "enable", "rtc_enable";
};
};
agcp-bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
agcp_dma: dma-controller@41580000 {
compatible = "sprd,sc9860-dma";
reg = <0 0x41580000 0 0x4000>;
#dma-cells = <1>;
/* For backwards compatibility: */
#dma-channels = <32>;
dma-channels = <32>;
clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
clock-names = "enable", "ashb_eb";
};
};
};
ext_32k: ext_32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
ext_26m: ext_26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
ext_rco_100m: ext_rco_100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "ext-rco-100m";
};
clk_l0_409m6: clk_l0_409m6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <409600000>;
clock-output-names = "ext-409m6";
};
};