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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/arm64/boot/dts/xilinx/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1275-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb
zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb
zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb
zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb
zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb
zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb
zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb
zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb
zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb
zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb
zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb
zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb
zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb
zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb
linux-7.2.3/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Avnet Ultra96 rev1
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp-zcu100-revC.dts"
/ {
model = "Avnet Ultra96 Rev1";
compatible = "avnet,ultra96-rev1", "avnet,ultra96",
"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
"xlnx,zynqmp";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal NET fixed clock
*
* (C) Copyright 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/ {
clk60: clk60 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
};
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk150: clk150 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <150000000>;
};
clk160: clk160 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <160000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
clk250: clk250 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
clk300: clk300 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
clk450: clk450 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <450000000>;
};
clk1200: clk1200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1200000000>;
};
firmware {
versal_net_firmware: versal-net-firmware {
compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
bootph-all;
method = "smc";
};
};
};
&adma0 {
clocks = <&clk450>, <&clk450>;
};
&adma1 {
clocks = <&clk450>, <&clk450>;
};
&adma2 {
clocks = <&clk450>, <&clk450>;
};
&adma3 {
clocks = <&clk450>, <&clk450>;
};
&adma4 {
clocks = <&clk450>, <&clk450>;
};
&adma5 {
clocks = <&clk450>, <&clk450>;
};
&adma6 {
clocks = <&clk450>, <&clk450>;
};
&adma7 {
clocks = <&clk450>, <&clk450>;
};
&can0 {
clocks = <&clk160>, <&clk160>;
};
&can1 {
clocks = <&clk160>, <&clk160>;
};
&gem0 {
clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
};
&gem1 {
clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
};
&gpio0 {
clocks = <&clk100>;
};
&gpio1 {
clocks = <&clk100>;
};
&i2c0 {
clocks = <&clk100>;
};
&i2c1 {
clocks = <&clk100>;
};
&i3c0 {
clocks = <&clk100>;
};
&i3c1 {
clocks = <&clk100>;
};
&ospi {
clocks = <&clk200>;
};
&qspi {
clocks = <&clk300>, <&clk300>;
};
&rtc {
/* Nothing */
};
&sdhci0 {
clocks = <&clk200>, <&clk200>, <&clk1200>;
};
&sdhci1 {
clocks = <&clk200>, <&clk200>, <&clk1200>;
};
&serial0 {
clocks = <&clk100>, <&clk100>;
};
&serial1 {
clocks = <&clk100>, <&clk100>;
};
&spi0 {
clocks = <&clk200>, <&clk200>;
};
&spi1 {
clocks = <&clk200>, <&clk200>;
};
&ttc0 {
clocks = <&clk150>;
};
&usb0 {
clocks = <&clk60>, <&clk60>;
};
&dwc3_0 {
clocks = <&clk60>;
};
&usb1 {
clocks = <&clk60>, <&clk60>;
};
&dwc3_1 {
clocks = <&clk60>;
};
&wwdt0 {
clocks = <&clk150>;
};
&wwdt1 {
clocks = <&clk150>;
};
&wwdt2 {
clocks = <&clk150>;
};
&wwdt3 {
clocks = <&clk150>;
};
&lpd_wwdt0 {
clocks = <&clk150>;
};
&lpd_wwdt1 {
clocks = <&clk150>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal Net VNX board revA
*
* (C) Copyright 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "versal-net.dtsi"
#include "versal-net-clk.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
model = "Xilinx Versal NET VNX revA";
dma-coherent;
memory: memory@0 {
reg = <0 0 0 0x80000000>;
device_type = "memory";
};
memory_hi: memory@800000000 {
reg = <8 0 3 0x80000000>;
device_type = "memory";
};
memory_hi2: memory@50000000000 {
reg = <0x500 0 4 0>;
device_type = "memory";
};
chosen {
bootargs = "console=ttyAMA1,115200n8";
stdout-path = "serial1:115200n8";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rsc_tbl_carveout: rproc@bbf14000 {
reg = <0 0xbbf14000 0 0x1000>;
no-map;
};
rpu0vdev0vring0: rpu0vdev0vring0@bbf15000 {
reg = <0 0xbbf15000 0 0x1000>;
no-map;
};
rpu0vdev0vring1: rpu0vdev0vring1@bbf16000 {
reg = <0 0xbbf16000 0 0x1000>;
no-map;
};
rpu0vdev0buffer: rpu0vdev0buffer@bbf17000 {
reg = <0 0xbbf17000 0 0xD000>;
no-map;
};
reserve_others: reserveothers@0 {
reg = <0 0x0 0 0x1c200000>;
no-map;
};
pdi_update: pdiupdate@1c200000 {
reg = <0 0x1c200000 0 0x6000000>;
no-map;
};
reserve_optee_atf: reserveopteeatf@22200000 {
reg = <0 0x22200000 0 0x4100000>;
no-map;
};
};
};
&gem1 {
status = "okay";
iommus = <&smmu 0x235>;
phy-handle = <&phy>;
phy-mode = "rmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@4 {
reg = <4>;
};
};
};
&ospi {
num-cs = <2>;
iommus = <&smmu 0x245>;
#address-cells = <1>;
#size-cells = <0>;
};
&sdhci1 {
status = "okay";
iommus = <&smmu 0x243>;
non-removable;
disable-wp;
no-sd;
no-sdio;
cap-mmc-hw-reset;
bus-width = <8>;
no-1-8-v;
};
&serial1 {
status = "okay";
};
&smmu {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/versal-net.dtsi
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linux-7.2.3/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2018 Xilinx, Inc.
*
*/
#ifndef _XLNX_ZYNQMP_CLK_H
#define _XLNX_ZYNQMP_CLK_H
#define IOPLL 0
#define RPLL 1
#define APLL 2
#define DPLL 3
#define VPLL 4
#define IOPLL_TO_FPD 5
#define RPLL_TO_FPD 6
#define APLL_TO_LPD 7
#define DPLL_TO_LPD 8
#define VPLL_TO_LPD 9
#define ACPU 10
#define ACPU_HALF 11
#define DBF_FPD 12
#define DBF_LPD 13
#define DBG_TRACE 14
#define DBG_TSTMP 15
#define DP_VIDEO_REF 16
#define DP_AUDIO_REF 17
#define DP_STC_REF 18
#define GDMA_REF 19
#define DPDMA_REF 20
#define DDR_REF 21
#define SATA_REF 22
#define PCIE_REF 23
#define GPU_REF 24
#define GPU_PP0_REF 25
#define GPU_PP1_REF 26
#define TOPSW_MAIN 27
#define TOPSW_LSBUS 28
#define GTGREF0_REF 29
#define LPD_SWITCH 30
#define LPD_LSBUS 31
#define USB0_BUS_REF 32
#define USB1_BUS_REF 33
#define USB3_DUAL_REF 34
#define USB0 35
#define USB1 36
#define CPU_R5 37
#define CPU_R5_CORE 38
#define CSU_SPB 39
#define CSU_PLL 40
#define PCAP 41
#define IOU_SWITCH 42
#define GEM_TSU_REF 43
#define GEM_TSU 44
#define GEM0_TX 45
#define GEM1_TX 46
#define GEM2_TX 47
#define GEM3_TX 48
#define GEM0_RX 49
#define GEM1_RX 50
#define GEM2_RX 51
#define GEM3_RX 52
#define QSPI_REF 53
#define SDIO0_REF 54
#define SDIO1_REF 55
#define UART0_REF 56
#define UART1_REF 57
#define SPI0_REF 58
#define SPI1_REF 59
#define NAND_REF 60
#define I2C0_REF 61
#define I2C1_REF 62
#define CAN0_REF 63
#define CAN1_REF 64
#define CAN0 65
#define CAN1 66
#define DLL_REF 67
#define ADMA_REF 68
#define TIMESTAMP_REF 69
#define AMS_REF 70
#define PL0_REF 71
#define PL1_REF 72
#define PL2_REF 73
#define PL3_REF 74
#define WDT 75
#define IOPLL_INT 76
#define IOPLL_PRE_SRC 77
#define IOPLL_HALF 78
#define IOPLL_INT_MUX 79
#define IOPLL_POST_SRC 80
#define RPLL_INT 81
#define RPLL_PRE_SRC 82
#define RPLL_HALF 83
#define RPLL_INT_MUX 84
#define RPLL_POST_SRC 85
#define APLL_INT 86
#define APLL_PRE_SRC 87
#define APLL_HALF 88
#define APLL_INT_MUX 89
#define APLL_POST_SRC 90
#define DPLL_INT 91
#define DPLL_PRE_SRC 92
#define DPLL_HALF 93
#define DPLL_INT_MUX 94
#define DPLL_POST_SRC 95
#define VPLL_INT 96
#define VPLL_PRE_SRC 97
#define VPLL_HALF 98
#define VPLL_INT_MUX 99
#define VPLL_POST_SRC 100
#define CAN0_MIO 101
#define CAN1_MIO 102
#define ACPU_FULL 103
#define GEM0_REF 104
#define GEM1_REF 105
#define GEM2_REF 106
#define GEM3_REF 107
#define GEM0_REF_UNG 108
#define GEM1_REF_UNG 109
#define GEM2_REF_UNG 110
#define GEM3_REF_UNG 111
#define LPD_WDT 112
#endif /* _XLNX_ZYNQMP_CLK_H */
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "xlnx-zynqmp-clk.h"
/ {
pss_ref_clk: pss-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333000>;
clock-output-names = "pss_ref_clk";
};
video_clk: video-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "video_clk";
};
pss_alt_ref_clk: pss-alt-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "pss_alt_ref_clk";
};
gt_crx_ref_clk: gt-crx-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
clock-output-names = "gt_crx_ref_clk";
};
aux_ref_clk: aux-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "aux_ref_clk";
};
};
&zynqmp_firmware {
zynqmp_clk: clock-controller {
bootph-all;
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
<&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
"aux_ref_clk", "gt_crx_ref_clk";
};
};
&can0 {
clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&can1 {
clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&cpu0 {
clocks = <&zynqmp_clk ACPU>;
};
&cpu0_debug {
clocks = <&zynqmp_clk DBF_FPD>;
};
&cpu1_debug {
clocks = <&zynqmp_clk DBF_FPD>;
};
&cpu2_debug {
clocks = <&zynqmp_clk DBF_FPD>;
};
&cpu3_debug {
clocks = <&zynqmp_clk DBF_FPD>;
};
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan2 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan3 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan4 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan5 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan6 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan7 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan8 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gpu {
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan2 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan3 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan4 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan5 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan6 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan7 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan8 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&nand0 {
clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gem0 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gpio {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&i2c0 {
clocks = <&zynqmp_clk I2C0_REF>;
};
&i2c1 {
clocks = <&zynqmp_clk I2C1_REF>;
};
&pcie {
clocks = <&zynqmp_clk PCIE_REF>;
};
&qspi {
clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&sata {
clocks = <&zynqmp_clk SATA_REF>;
};
&sdhci0 {
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO0_REF>;
};
&sdhci1 {
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO1_REF>;
};
&spi0 {
clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&spi1 {
clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&ttc0 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc1 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc2 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc3 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk UART0_REF>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk UART1_REF>;
};
&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_0 {
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_1 {
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {
clocks = <&zynqmp_clk WDT>;
};
&lpd_watchdog {
clocks = <&zynqmp_clk LPD_WDT>;
};
&xilinx_ams {
clocks = <&zynqmp_clk AMS_REF>;
};
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
};
&zynqmp_dpsub {
clocks = <&zynqmp_clk TOPSW_LSBUS>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>;
assigned-clocks = <&zynqmp_clk DP_STC_REF>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for KD240 revA Carrier Card
*
* Copyright (C) 2021 - 2022, Xilinx, Inc.
* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/dts-v1/;
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sk-kd240-rev1",
"xlnx,zynqmp-sk-kd240-revB",
"xlnx,zynqmp-sk-kd240-revA",
"xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
model = "ZynqMP KD240 revA/B/1";
aliases {
ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
clk_26: clock2 { /* u17 - USB */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk_25_0: clock4 { /* u92/u91 - GEM2 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clk_25_1: clock5 { /* u92/u91 - GEM3 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&can0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u3: ina260@40 { /* u3 */
compatible = "ti,ina260";
label = "ina260-u14";
reg = <0x40>;
};
slg7xl45106: gpio@11 { /* u13 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "",
"SD_RESET_B", "USB0_HUB_RESET_B",
"", "PS_GEM0_RESET_B",
"", "";
};
hub: usb-hub@2d { /* u36 */
compatible = "microchip,usb5744";
reg = <0x2d>;
};
};
/* USB 3.0 */
&psgtr {
status = "okay";
/* usb */
clocks = <&clk_26>;
clock-names = "ref2";
};
&usb0 { /* mio52 - mio63 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub_3_0>;
i2c-bus = <&hub>;
reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub_2_0>;
i2c-bus = <&hub>;
reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
};
&gem1 { /* mdio mio50/51 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
assigned-clock-rates = <250000000>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@8 { /* Adin u31 */
#phy-cells = <1>;
compatible = "ethernet-phy-id0283.bc30";
reg = <8>;
adi,rx-internal-delay-ps = <2000>;
adi,tx-internal-delay-ps = <2000>;
adi,fifo-depth-bits = <8>;
reset-assert-us = <10>;
reset-deassert-us = <5000>;
reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
};
};
};
/* 2 more ethernet phys u32@2 and u34@3 */
&pinctrl0 { /* required by spec */
status = "okay";
pinctrl_can0_default: can0-default {
mux {
function = "can0";
groups = "can0_16_grp";
};
conf {
groups = "can0_16_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO66";
bias-pull-up;
};
conf-tx {
pins = "MIO67";
bias-pull-up;
drive-strength = <4>;
};
};
pinctrl_uart0_default: uart0-default {
conf {
groups = "uart0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO70";
bias-high-impedance;
};
conf-tx {
pins = "MIO71";
bias-disable;
};
mux {
groups = "uart0_17_grp";
function = "uart0";
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem1_default: gem1-default {
conf {
groups = "ethernet1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO45", "MIO46", "MIO47", "MIO48";
bias-disable;
low-power-disable;
};
conf-bootstrap {
pins = "MIO44", "MIO49";
bias-disable;
output-enable;
low-power-disable;
};
conf-tx {
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
output-enable;
low-power-enable;
};
conf-mdio {
groups = "mdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
function = "mdio1";
groups = "mdio1_0_grp";
};
mux {
function = "ethernet1";
groups = "ethernet1_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_usb1_default: usb1-default {
conf {
groups = "usb1_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb1_0_grp";
function = "usb1";
};
};
};
&uart0 {
status = "okay";
rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
linux,rs485-enabled-at-boot-time;
rs485-rts-delay = <10 10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
assigned-clock-rates = <100000000>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&zynqmp_dpsub {
status = "disabled";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
+448
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for KR260 revA Carrier Card
*
* (C) Copyright 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/dts-v1/;
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sk-kr260-revA",
"xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
model = "ZynqMP KR260 revA";
aliases {
ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
clk_27: clock0 { /* u86 - DP */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
clk_125: si5332-0 { /* u17 - GEM0/1 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk_74: si5332-5 { /* u17 - SLVC-EC */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
clk_26: si5332-2 { /* u17 - USB */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk_156: si5332-3 { /* u17 - SFP+ */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <156250000>;
};
clk_25_0: si5332-1 { /* u17 - GEM2 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clk_25_1: si5332-4 { /* u17 - GEM3 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
label = "ina260-u14";
reg = <0x40>;
};
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
"SD_RESET_B", "USB0_HUB_RESET_B",
"USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
"PS_GEM1_RESET_B", "";
};
i2c-mux@74 { /* u18 */
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
usbhub_i2c0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
hub_1: usb-hub@2d {
compatible = "microchip,usb5744";
reg = <0x2d>;
};
};
usbhub_i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
hub_2: usb-hub@2d {
compatible = "microchip,usb5744";
reg = <0x2d>;
};
};
/* Bus 2/3 are not connected */
};
/* si5332@6a - u17 - clock-generator */
};
/* GEM SGMII/DP and USB 3.0 */
&psgtr {
status = "okay";
/* gem0/1, dp, usb */
clocks = <&clk_125>, <&clk_27>, <&clk_26>;
clock-names = "ref0", "ref1", "ref2";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
};
&usb0 { /* mio52 - mio63 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub_3_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub_2_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
};
&usb1 { /* mio64 - mio75 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub1_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub1_3_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub1_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub1_2_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
};
&gem0 { /* mdio mio50/51 */
status = "okay";
phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
assigned-clock-rates = <250000000>;
};
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 { /* u81 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <4>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <300>;
reset-deassert-us = <280>;
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@8 { /* u36 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <8>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-deassert-us = <280>;
reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
};
};
};
/* gem2/gem3 via PL with phys u79@2 and u80@3 */
&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem1_default: gem1-default {
conf {
groups = "ethernet1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO44", "MIO46", "MIO48";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
output-enable;
low-power-disable;
};
conf-tx {
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
output-enable;
low-power-enable;
};
conf-mdio {
groups = "mdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
function = "mdio1";
groups = "mdio1_0_grp";
};
mux {
function = "ethernet1";
groups = "ethernet1_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_usb1_default: usb1-default {
conf {
groups = "usb1_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb1_0_grp";
function = "usb1";
};
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for KR260 revB Carrier Card (A03 revision)
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/dts-v1/;
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sk-kr260-revB",
"xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
model = "ZynqMP KR260 revB";
aliases {
ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
clk_125: clock0 { /* u87 - GEM0/1 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk_27: clock1 { /* u86 - DP */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
clk_26: clock2 { /* u89 - USB */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk_156: clock3 { /* u90 - SFP+ */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <156250000>;
};
clk_25_0: clock4 { /* u92/u91 - GEM2 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clk_25_1: clock5 { /* u92/u91 - GEM3 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clk_74: clock6 { /* u88 - SLVC-EC */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
label = "ina260-u14";
reg = <0x40>;
};
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
"SD_RESET_B", "USB0_HUB_RESET_B",
"USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
"PS_GEM1_RESET_B", "";
};
i2c-mux@74 { /* u18 */
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
usbhub_i2c0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
hub_1: usb-hub@2d {
compatible = "microchip,usb5744";
reg = <0x2d>;
};
};
usbhub_i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
hub_2: usb-hub@2d {
compatible = "microchip,usb5744";
reg = <0x2d>;
};
};
/* Bus 2/3 are not connected */
};
/* si5332@6a - u17 - clock-generator */
};
/* GEM SGMII/DP and USB 3.0 */
&psgtr {
status = "okay";
/* gem0/1, dp, usb */
clocks = <&clk_125>, <&clk_27>, <&clk_26>;
clock-names = "ref0", "ref1", "ref2";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
};
&usb0 { /* mio52 - mio63 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub_3_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub_2_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
};
&usb1 { /* mio64 - mio75 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub1_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub1_3_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub1_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub1_2_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
};
&gem0 { /* mdio mio50/51 */
status = "okay";
phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
assigned-clock-rates = <250000000>;
};
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 { /* u81 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <4>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <300>;
reset-deassert-us = <280>;
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@8 { /* u36 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <8>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-deassert-us = <280>;
reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
};
};
};
/* gem2/gem3 via PL with phys u79@2 and u80@3 */
&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem1_default: gem1-default {
conf {
groups = "ethernet1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO44", "MIO46", "MIO48";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
output-enable;
low-power-disable;
};
conf-tx {
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
output-enable;
low-power-enable;
};
conf-mdio {
groups = "mdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
function = "mdio1";
groups = "mdio1_0_grp";
};
mux {
function = "ethernet1";
groups = "ethernet1_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_usb1_default: usb1-default {
conf {
groups = "usb1_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb1_0_grp";
function = "usb1";
};
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+405
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* SD level shifter:
* "A" - A01 board un-modified (NXP)
* "Y" - A01 board modified with legacy interposer (Nexperia)
* "Z" - A01 board modified with Diode interposer
*
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/dts-v1/;
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sk-kv260-revA",
"xlnx,zynqmp-sk-kv260-revY",
"xlnx,zynqmp-sk-kv260-revZ",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
model = "ZynqMP KV260 revA";
aliases {
ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
};
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332-1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332-2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332-3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332-4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332-5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
label = "ina260-u14";
reg = <0x40>;
};
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
/* DP/USB 3.0 and SATA */
&psgtr {
status = "okay";
/* pcie, usb3, sata */
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
clock-names = "ref0", "ref1", "ref2";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
};
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
};
&sdhci1 { /* on CC with tuned parameters */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
/*
* SD 3.0 requires level shifter and this property
* should be removed if the board has level shifter and
* need to work in UHS mode
*/
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
assigned-clock-rates = <187498123>;
bus-width = <4>;
};
&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-deassert-us = <280>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
};
};
};
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem3_default: gem3-default {
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO72", "MIO74";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
output-enable;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
output-enable;
low-power-enable;
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_sdhci1_default: sdhci1-default {
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/dts-v1/;
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sk-kv260-rev2",
"xlnx,zynqmp-sk-kv260-rev1",
"xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
model = "ZynqMP KV260 revB";
aliases {
ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
};
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332-1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332-2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332-3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332-4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332-5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
label = "ina260-u14";
reg = <0x40>;
};
hub: usb-hub@2d {
compatible = "microchip,usb5744";
reg = <0x2d>;
};
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
/* DP/USB 3.0 */
&psgtr {
status = "okay";
/* pcie, usb3, sata */
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
clock-names = "ref0", "ref1", "ref2";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
};
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
#address-cells = <1>;
#size-cells = <0>;
/* 2.0 hub on port 1 */
hub_2_0: hub@1 {
compatible = "usb424,2744";
reg = <1>;
peer-hub = <&hub_3_0>;
i2c-bus = <&hub>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
/* 3.0 hub on port 2 */
hub_3_0: hub@2 {
compatible = "usb424,5744";
reg = <2>;
peer-hub = <&hub_2_0>;
i2c-bus = <&hub>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
};
&sdhci1 { /* on CC with tuned parameters */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
/*
* SD 3.0 requires level shifter and this property
* should be removed if the board has level shifter and
* need to work in UHS mode
*/
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
clk-phase-sd-hs = <126>, <60>;
clk-phase-uhs-sdr25 = <120>, <60>;
clk-phase-uhs-ddr50 = <126>, <48>;
assigned-clock-rates = <187498123>;
bus-width = <4>;
};
&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
assigned-clock-rates = <250000000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-deassert-us = <280>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
};
};
};
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem3_default: gem3-default {
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO72", "MIO74";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
output-enable;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
output-enable;
low-power-enable;
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_sdhci1_default: sdhci1-default {
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts
+23
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SM-K24 RevA
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2022, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-sm-k26-revA.dts"
/ {
model = "ZynqMP SM-K24 RevA/B/1";
compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB",
"xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
"xlnx,zynqmp";
memory@0 {
device_type = "memory"; /* 2GB */
reg = <0 0 0 0x80000000>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP SM-K26 Rev2/1/B/A";
compatible = "xlnx,zynqmp-sm-k26-rev2",
"xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
"xlnx,zynqmp";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
nvmem1 = &eeprom_cc;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
spi1 = &spi0;
spi2 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial1:115200n8";
};
memory@0 {
device_type = "memory"; /* 4GB */
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pmu_region: pmu@7ff00000 {
reg = <0x0 0x7ff00000 0x0 0x100000>;
no-map;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
key-fwuen {
label = "fwuen";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
ds35-led {
label = "heartbeat";
gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
ds36-led {
label = "vbus_det";
gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
pwm_fan: pwm-fan {
compatible = "pwm-fan";
status = "okay";
pwms = <&ttc0 2 40000 1>;
};
};
&modepin_gpio {
label = "modepin";
};
&ttc0 {
status = "okay";
#pwm-cells = <3>;
};
&uart1 { /* MIO36/MIO37 */
status = "okay";
};
&pinctrl0 {
status = "okay";
pinctrl_sdhci0_default: sdhci0-default {
conf {
groups = "sdio0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
};
};
&qspi { /* MIO 0-5 - U143 */
status = "okay";
spi_flash: flash@0 { /* MT25QU512A */
compatible = "jedec,spi-nor"; /* 64MB */
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>; /* 40MHz */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Image Selector";
reg = <0x0 0x80000>; /* 512KB */
read-only;
lock;
};
partition@80000 {
label = "Image Selector Golden";
reg = <0x80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@100000 {
label = "Persistent Register";
reg = <0x100000 0x20000>; /* 128KB */
};
partition@120000 {
label = "Persistent Register Backup";
reg = <0x120000 0x20000>; /* 128KB */
};
partition@140000 {
label = "Open_1";
reg = <0x140000 0xC0000>; /* 768KB */
};
partition@200000 {
label = "Image A (FSBL, PMU, ATF, U-Boot)";
reg = <0x200000 0xD00000>; /* 13MB */
};
partition@f00000 {
label = "ImgSel Image A Catch";
reg = <0xF00000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@f80000 {
label = "Image B (FSBL, PMU, ATF, U-Boot)";
reg = <0xF80000 0xD00000>; /* 13MB */
};
partition@1c80000 {
label = "ImgSel Image B Catch";
reg = <0x1C80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@1d00000 {
label = "Open_2";
reg = <0x1D00000 0x100000>; /* 1MB */
};
partition@1e00000 {
label = "Recovery Image";
reg = <0x1E00000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2000000 {
label = "Recovery Image Backup";
reg = <0x2000000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2200000 {
label = "U-Boot storage variables";
reg = <0x2200000 0x20000>; /* 128KB */
};
partition@2220000 {
label = "U-Boot storage variables backup";
reg = <0x2220000 0x20000>; /* 128KB */
};
partition@2240000 {
label = "SHA256";
reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
read-only;
lock;
};
partition@2280000 {
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22a0000 {
label = "User";
reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
};
};
};
};
&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
non-removable;
disable-wp;
no-sd;
no-sdio;
cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
assigned-clock-rates = <187498123>;
};
&spi1 { /* MIO6, 9-11 */
status = "okay";
label = "TPM";
num-cs = <1>;
tpm@0 { /* slm9670 - U144 */
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <18500000>;
};
};
&i2c1 {
status = "okay";
bootph-all;
clock-frequency = <400000>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x50>;
/* WP pin EE_WP_EN connected to slg7x644092@68 */
};
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x51>;
};
/* da9062@30 - u170 - also at address 0x31 */
/* da9131@33 - u167 */
da9131: pmic@33 {
compatible = "dlg,da9131";
reg = <0x33>;
regulators {
da9131_buck1: buck1 {
regulator-name = "da9131_buck1";
regulator-boot-on;
regulator-always-on;
};
da9131_buck2: buck2 {
regulator-name = "da9131_buck2";
regulator-boot-on;
regulator-always-on;
};
};
};
/* da9130@32 - u166 */
da9130: pmic@32 {
compatible = "dlg,da9130";
reg = <0x32>;
regulators {
da9130_buck1: buck1 {
regulator-name = "da9130_buck1";
regulator-boot-on;
regulator-always-on;
};
};
};
/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
/*
* stdp4320 - u27 FW has below two issues to be fixed in next board revision.
* Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
* Address conflict with slg7x644091@70 making both the devices NOT accessible.
* With the FW fix, stdp4320 should respond to address 0x73 only.
*/
/* slg7x644092@68 - u169 */
/* Also connected via JA1C as C23/C24 */
};
&gpio {
status = "okay";
gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
"QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
"SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
"I2C1_SDA", "", "", "", "", /* 25 - 29 */
"", "", "", "", "", /* 30 - 34 */
"", "", "", "", "", /* 35 - 39 */
"", "", "", "", "", /* 40 - 44 */
"", "", "", "", "", /* 45 - 49 */
"", "", "", "", "", /* 50 - 54 */
"", "", "", "", "", /* 55 - 59 */
"", "", "", "", "", /* 60 - 64 */
"", "", "", "", "", /* 65 - 69 */
"", "", "", "", "", /* 70 - 74 */
"", "", "", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
"", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"", "", "", "", "", /* 110 - 114 */
"", "", "", "", "", /* 115 - 119 */
"", "", "", "", "", /* 120 - 124 */
"", "", "", "", "", /* 125 - 129 */
"", "", "", "", "", /* 130 - 134 */
"", "", "", "", "", /* 135 - 139 */
"", "", "", "", "", /* 140 - 144 */
"", "", "", "", "", /* 145 - 149 */
"", "", "", "", "", /* 150 - 154 */
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 173 */
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&rtc {
status = "okay";
};
&lpd_dma_chan1 {
status = "okay";
};
&lpd_dma_chan2 {
status = "okay";
};
&lpd_dma_chan3 {
status = "okay";
};
&lpd_dma_chan4 {
status = "okay";
};
&lpd_dma_chan5 {
status = "okay";
};
&lpd_dma_chan6 {
status = "okay";
};
&lpd_dma_chan7 {
status = "okay";
};
&lpd_dma_chan8 {
status = "okay";
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gpu {
status = "okay";
};
&lpd_watchdog {
status = "okay";
};
&watchdog0 {
status = "okay";
};
&cpu_opp_table {
opp00 {
opp-hz = /bits/ 64 <1333333333>;
};
opp01 {
opp-hz = /bits/ 64 <666666666>;
};
opp02 {
opp-hz = /bits/ 64 <444444444>;
};
opp03 {
opp-hz = /bits/ 64 <333333333>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SMK-K24 RevA
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2022, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-sm-k24-revA.dts"
/ {
model = "ZynqMP SMK-K24 RevA";
compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24",
"xlnx,zynqmp";
};
&sdhci0 {
status = "disabled";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-sm-k26-revA.dts"
/ {
model = "ZynqMP SMK-K26 Rev2/1/B/A";
compatible = "xlnx,zynqmp-smk-k26-rev2",
"xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
"xlnx,zynqmp";
};
&sdhci0 {
status = "disabled";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZC1232
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1232 RevA";
compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&dcc {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZC1254
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1254 RevA";
compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&dcc {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
i2c0 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
clock_si5338_0: clk27 { /* u55 SI5338-GM */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_si5338_3: clk150 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <150000000>;
};
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */
reg = <0x55>;
};
};
&pinctrl0 {
status = "okay";
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_9_grp";
function = "i2c1";
};
conf {
groups = "i2c1_9_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_36_grp", "gpio0_37_grp";
function = "gpio0";
};
conf {
groups = "gpio0_36_grp", "gpio0_37_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_8_grp";
function = "uart0";
};
conf {
groups = "uart0_8_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO34";
bias-high-impedance;
};
conf-tx {
pins = "MIO35";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
conf {
groups = "sdio0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio0_cd_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "sdio0_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio0_wp_0_grp";
function = "sdio0_wp";
};
conf-wp {
groups = "sdio0_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio1_wp_0_grp";
function = "sdio1_wp";
};
conf-wp {
groups = "sdio1_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_gpio_default: gpio-default {
mux {
function = "gpio0";
groups = "gpio0_38_grp";
};
conf {
groups = "gpio0_38_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
};
&psgtr {
status = "okay";
/* dp, usb3, sata */
clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* eMMC */
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem2;
i2c0 = &i2c0;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
};
&can1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem2 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};
&gpio {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* IRQ not connected */
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&nand0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand0_default>;
nand@0 {
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-0";
};
nand@1 {
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-1";
};
};
&pinctrl0 {
status = "okay";
pinctrl_can0_default: can0-default {
mux {
function = "can0";
groups = "can0_9_grp";
};
conf {
groups = "can0_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO38";
bias-high-impedance;
};
conf-tx {
pins = "MIO39";
bias-disable;
};
};
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_8_grp";
};
conf {
groups = "can1_8_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO33";
bias-high-impedance;
};
conf-tx {
pins = "MIO32";
bias-disable;
};
};
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_1_grp";
function = "i2c0";
};
conf {
groups = "i2c0_1_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_6_grp", "gpio0_7_grp";
function = "gpio0";
};
conf {
groups = "gpio0_6_grp", "gpio0_7_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_10_grp";
function = "uart0";
};
conf {
groups = "uart0_10_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO42";
bias-high-impedance;
};
conf-tx {
pins = "MIO43";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO41";
bias-high-impedance;
};
conf-tx {
pins = "MIO40";
bias-disable;
};
};
pinctrl_usb1_default: usb1-default {
mux {
groups = "usb1_0_grp";
function = "usb1";
};
conf {
groups = "usb1_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_gem2_default: gem2-default {
mux {
function = "ethernet2";
groups = "ethernet2_0_grp";
};
conf {
groups = "ethernet2_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
"MIO63";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
"MIO57";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio2";
groups = "mdio2_0_grp";
};
conf-mdio {
groups = "mdio2_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_nand0_default: nand0-default {
mux {
groups = "nand0_0_grp";
function = "nand0";
};
conf {
groups = "nand0_0_grp";
bias-pull-up;
};
mux-ce {
groups = "nand0_ce_0_grp";
function = "nand0_ce";
};
conf-ce {
groups = "nand0_ce_0_grp";
bias-pull-up;
};
mux-rb {
groups = "nand0_rb_0_grp";
function = "nand0_rb";
};
conf-rb {
groups = "nand0_rb_0_grp";
bias-pull-up;
};
mux-dqs {
groups = "nand0_dqs_0_grp";
function = "nand0_dqs";
};
conf-dqs {
groups = "nand0_dqs_0_grp";
bias-pull-up;
};
};
pinctrl_spi0_default: spi0-default {
mux {
groups = "spi0_0_grp";
function = "spi0";
};
conf {
groups = "spi0_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
"spi0_ss_2_grp";
function = "spi0_ss";
};
conf-cs {
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
"spi0_ss_2_grp";
bias-disable;
};
};
pinctrl_spi1_default: spi1-default {
mux {
groups = "spi1_3_grp";
function = "spi1";
};
conf {
groups = "spi1_3_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
"spi1_ss_11_grp";
function = "spi1_ss";
};
conf-cs {
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
"spi1_ss_11_grp";
bias-disable;
};
};
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
spi0_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf080", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
partition@0 {
label = "spi0-data";
reg = <0x0 0x100000>;
};
};
};
&spi1 {
status = "okay";
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
spi1_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <20000000>;
reg = <0>;
partition@0 {
label = "spi1-data";
reg = <0x0 0x84000>;
};
};
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_si5338_3: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};
};
&gpio {
status = "okay";
};
/* just eeprom here */
&i2c0 {
status = "okay";
clock-frequency = <400000>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* IRQ not connected */
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
/* eeprom24c02 and SE98A temp chip pca9306 */
&i2c1 {
status = "okay";
clock-frequency = <400000>;
};
/* MT29F64G08AECDBJ4-6 */
&nand0 {
status = "okay";
num-cs = <2>;
};
&psgtr {
status = "okay";
/* usb3, sata */
clocks = <&clock_si5338_2>, <&clock_si5338_3>;
clock-names = "ref2", "ref3";
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
};
&sdhci1 { /* emmc with some settings */
status = "okay";
};
/* main */
&uart0 {
status = "okay";
};
/* DB9 */
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
phy-names = "usb3-phy";
phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm018-dc4";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem0;
ethernet1 = &gem1;
ethernet2 = &gem2;
ethernet3 = &gem3;
i2c0 = &i2c0;
i2c1 = &i2c1;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&lpd_dma_chan1 {
status = "okay";
};
&lpd_dma_chan2 {
status = "okay";
};
&lpd_dma_chan3 {
status = "okay";
};
&lpd_dma_chan4 {
status = "okay";
};
&lpd_dma_chan5 {
status = "okay";
};
&lpd_dma_chan6 {
status = "okay";
};
&lpd_dma_chan7 {
status = "okay";
};
&lpd_dma_chan8 {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
};
};
};
&gem1 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy7>;
};
&gem2 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy3>;
};
&gem3 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy8>;
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&watchdog0 {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem1;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem1 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&gpio {
status = "okay";
};
&i2c0 {
status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_18_grp";
function = "i2c0";
};
conf {
groups = "i2c0_18_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_74_grp", "gpio0_75_grp";
function = "gpio0";
};
conf {
groups = "gpio0_74_grp", "gpio0_75_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_19_grp";
function = "i2c1";
};
conf {
groups = "i2c1_19_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_76_grp", "gpio0_77_grp";
function = "gpio0";
};
conf {
groups = "gpio0_76_grp", "gpio0_77_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_17_grp";
function = "uart0";
};
conf {
groups = "uart0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70";
bias-high-impedance;
};
conf-tx {
pins = "MIO71";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_18_grp";
function = "uart1";
};
conf {
groups = "uart1_18_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO73";
bias-high-impedance;
};
conf-tx {
pins = "MIO72";
bias-disable;
};
};
pinctrl_gem1_default: gem1-default {
mux {
function = "ethernet1";
groups = "ethernet1_0_grp";
};
conf {
groups = "ethernet1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
"MIO49";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
"MIO43";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio1";
groups = "mdio1_0_grp";
};
conf-mdio {
groups = "mdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
conf {
groups = "sdio0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio0_cd_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "sdio0_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-wp {
groups = "sdio0_wp_0_grp";
function = "sdio0_wp";
};
conf-wp {
groups = "sdio0_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_watchdog0_default: watchdog0-default {
mux-clk {
groups = "swdt0_clk_1_grp";
function = "swdt0_clk";
};
conf-clk {
groups = "swdt0_clk_1_grp";
bias-pull-up;
};
mux-rst {
groups = "swdt0_rst_1_grp";
function = "swdt0_rst";
};
conf-rst {
groups = "swdt0_rst_1_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc0_default: ttc0-default {
mux-clk {
groups = "ttc0_clk_0_grp";
function = "ttc0_clk";
};
conf-clk {
groups = "ttc0_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc0_wav_0_grp";
function = "ttc0_wav";
};
conf-wav {
groups = "ttc0_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc1_default: ttc1-default {
mux-clk {
groups = "ttc1_clk_0_grp";
function = "ttc1_clk";
};
conf-clk {
groups = "ttc1_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc1_wav_0_grp";
function = "ttc1_wav";
};
conf-wav {
groups = "ttc1_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc2_default: ttc2-default {
mux-clk {
groups = "ttc2_clk_0_grp";
function = "ttc2_clk";
};
conf-clk {
groups = "ttc2_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc2_wav_0_grp";
function = "ttc2_wav";
};
conf-wav {
groups = "ttc2_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_ttc3_default: ttc3-default {
mux-clk {
groups = "ttc3_clk_0_grp";
function = "ttc3_clk";
};
conf-clk {
groups = "ttc3_clk_0_grp";
bias-pull-up;
};
mux-wav {
groups = "ttc3_wav_0_grp";
function = "ttc3_wav";
};
conf-wav {
groups = "ttc3_wav_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
};
};
};
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
no-1-8-v;
xlnx,mio-bank = <0>;
};
&ttc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc0_default>;
};
&ttc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc1_default>;
};
&ttc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc2_default>;
};
&ttc3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ttc3_default>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&watchdog0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog0_default>;
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
+627
View File
@@ -0,0 +1,627 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU100 RevC";
compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
aliases {
i2c0 = &i2c1;
rtc0 = &rtc;
serial0 = &uart1;
serial1 = &uart0;
serial2 = &dcc;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
switch-4 {
label = "sw4";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
autorepeat;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
<&xilinx_ams 9>, <&xilinx_ams 10>,
<&xilinx_ams 11>, <&xilinx_ams 12>;
};
leds {
compatible = "gpio-leds";
led-ds2 {
label = "ds2";
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-ds3 {
label = "ds3";
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx"; /* WLAN tx */
default-state = "off";
};
led-ds4 {
label = "ds4";
gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0rx"; /* WLAN rx */
default-state = "off";
};
led-ds5 {
label = "ds5";
gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
};
led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
label = "vbus_det";
gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
wmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
regulator-name = "wmmcsdio_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
post-power-on-delay-ms = <10>;
};
ina226 {
compatible = "iio-hwmon";
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
si5335_0: si5335-0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5335_1: si5335-1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&dcc {
status = "okay";
};
&gpio {
status = "okay";
gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
"I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
"SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
"SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
"PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
"VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
"DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
"", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
"GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
"GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
"USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
"", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
i2c-mux@75 { /* u11 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2csw_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
label = "LS-I2C0";
};
i2csw_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
label = "LS-I2C1";
};
i2csw_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
label = "HS-I2C2";
};
i2csw_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
label = "HS-I2C3";
};
i2csw_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
pmic: pmic@5e { /* Custom TI PMIC u33 */
compatible = "ti,tps65086";
reg = <0x5e>;
interrupt-parent = <&gpio>;
interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
};
};
i2csw_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* PS_PMBUS */
u35: ina226@40 { /* u35 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
reg = <0x40>;
shunt-resistor = <10000>;
/* MIO31 is alert which should be routed to PMUFW */
};
};
i2csw_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/*
* Not Connected
*/
};
i2csw_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
/*
* usb5744 (DNP) - U5
* 100kHz - this is default freq for us
*/
};
};
};
&pinctrl0 {
status = "okay";
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_1_grp";
function = "i2c1";
};
conf {
groups = "i2c1_1_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_4_grp", "gpio0_5_grp";
function = "gpio0";
};
conf {
groups = "gpio0_4_grp", "gpio0_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_3_grp";
function = "sdio0";
};
conf {
groups = "sdio0_3_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio0_cd_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "sdio0_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_2_grp";
function = "sdio1";
};
conf {
groups = "sdio1_2_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_spi0_default: spi0-default {
mux {
groups = "spi0_3_grp";
function = "spi0";
};
conf {
groups = "spi0_3_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi0_ss_9_grp";
function = "spi0_ss";
};
conf-cs {
groups = "spi0_ss_9_grp";
bias-disable;
};
};
pinctrl_spi1_default: spi1-default {
mux {
groups = "spi1_0_grp";
function = "spi1";
};
conf {
groups = "spi1_0_grp";
bias-disable;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cs {
groups = "spi1_ss_0_grp";
function = "spi1_ss";
};
conf-cs {
groups = "spi1_ss_0_grp";
bias-disable;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_0_grp";
function = "uart0";
};
conf {
groups = "uart0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO3";
bias-high-impedance;
};
conf-tx {
pins = "MIO2";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_0_grp";
function = "uart1";
};
conf {
groups = "uart1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO1";
bias-high-impedance;
};
conf-tx {
pins = "MIO0";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_usb1_default: usb1-default {
mux {
groups = "usb1_0_grp";
function = "usb1";
};
conf {
groups = "usb1_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO64", "MIO65", "MIO67";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
};
&psgtr {
status = "okay";
/* usb3, dp */
clocks = <&si5335_0>, <&si5335_1>;
clock-names = "ref0", "ref1";
};
&rtc {
status = "okay";
};
/* SD0 only supports 3.3V, no level shifter */
&sdhci0 {
status = "okay";
no-1-8-v;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
xlnx,mio-bank = <0>;
};
&sdhci1 {
status = "okay";
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <0>;
non-removable;
disable-wp;
no-sd;
no-sdio;
cap-mmc-hw-reset;
cap-power-off-card;
mmc-pwrseq = <&sdio_pwrseq>;
vqmmc-supply = <&wmmcsdio_fixed>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wifi@2 {
compatible = "ti,wl1831";
reg = <2>;
interrupt-parent = <&gpio>;
interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
};
};
&spi0 { /* Low Speed connector */
status = "okay";
label = "LS-SPI0";
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
};
&spi1 { /* High Speed connector */
status = "okay";
label = "HS-SPI1";
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
bluetooth {
compatible = "ti,wl1831-st";
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
/delete-property/ reset-gpios;
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
maximum-speed = "super-speed";
};
&watchdog0 {
status = "okay";
};
&ams_ps {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-revB.dts"
/ {
model = "ZynqMP ZCU102 Rev1.0";
compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
&rproc_split {
status = "okay";
};
&rproc_lockstep {
status = "disabled";
};
&eeprom {
#address-cells = <1>;
#size-cells = <1>;
board_sn: board-sn@0 {
reg = <0x0 0x14>;
};
eth_mac: eth-mac@20 {
reg = <0x20 0x6>;
};
board_name: board-name@d0 {
reg = <0xd0 0x6>;
};
board_revision: board-revision@e0 {
reg = <0xe0 0x3>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.1
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-rev1.0.dts"
/ {
model = "ZynqMP ZCU102 Rev1.1";
compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
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linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include "zynqmp-zcu102-revA.dts"
/ {
model = "ZynqMP ZCU102 RevB";
compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
&gem3 {
phy-handle = <&phyc>;
mdio: mdio {
phyc: ethernet-phy@c {
#phy-cells = <0x1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
/* Cleanup from RevA */
/delete-node/ ethernet-phy@21;
};
};
/* Fix collision with u61 */
&i2c0 {
i2c-mux@75 {
i2c@2 {
max15303@1b { /* u8 */
compatible = "maxim,max15303";
reg = <0x1b>;
};
/delete-node/ max15303@20;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU104 RevA";
compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
i2c0 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&can1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/*
* IIC_EEPROM 1kB memory which uses 256B blocks
* where every block has different address.
* 0 - 256B address 0x54
* 256B - 512B address 0x55
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
eeprom: eeprom@54 { /* u23 */
compatible = "atmel,24c08";
reg = <0x54>;
#address-cells = <1>;
#size-cells = <1>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* 8T49N287 - u182 */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
compatible = "infineon,irps5401";
reg = <0x43>; /* pmbus / i2c 0x13 */
};
irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
compatible = "infineon,irps5401";
reg = <0x44>; /* pmbus / i2c 0x14 */
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - IRPS5401_ALERT_B
* 1 - HDMI_8T49N241_INT_ALM
* 2 - MAX6643_OT_B
* 3 - MAX6643_FANFAIL_B
* 5 - IIC_MUX_RESET_B
* 6 - GEM3_EXP_RESET_B
* 7 - FMC_LPC_PRSNT_M2C_B
* 4, 10 - 17 - not connected
*/
};
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
/* 3, 6 not connected */
};
};
&pinctrl0 {
status = "okay";
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
drive-strength = <12>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
&watchdog0 {
status = "okay";
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU104 RevC";
compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
i2c0 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
ina226 {
compatible = "iio-hwmon";
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&can1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - IRPS5401_ALERT_B
* 1 - HDMI_8T49N241_INT_ALM
* 2 - MAX6643_OT_B
* 3 - MAX6643_FANFAIL_B
* 5 - IIC_MUX_RESET_B
* 6 - GEM3_EXP_RESET_B
* 7 - FMC_LPC_PRSNT_M2C_B
* 4, 10 - 17 - not connected
*/
};
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/*
* IIC_EEPROM 1kB memory which uses 256B blocks
* where every block has different address.
* 0 - 256B address 0x54
* 256B - 512B address 0x55
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
eeprom: eeprom@54 { /* u23 */
compatible = "atmel,24c08";
reg = <0x54>;
#address-cells = <1>;
#size-cells = <1>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* 8T49N287 - u182 */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
compatible = "infineon,irps5401";
reg = <0x43>; /* pmbus / i2c 0x13 */
};
irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
compatible = "infineon,irps5401";
reg = <0x44>; /* pmbus / i2c 0x14 */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
u183: ina226@40 { /* u183 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
reg = <0x40>;
shunt-resistor = <5000>;
};
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
/* 4, 6 not connected */
};
};
&pinctrl0 {
status = "okay";
pinctrl_can1_default: can1-default {
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
drive-strength = <12>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
&watchdog0 {
status = "okay";
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+1051
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linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU111 RevA";
compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
/* Another 4GB connected to PL */
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
switch-19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
ina226-u67 {
compatible = "iio-hwmon";
io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
};
ina226-u59 {
compatible = "iio-hwmon";
io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
};
ina226-u61 {
compatible = "iio-hwmon";
io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
};
ina226-u60 {
compatible = "iio-hwmon";
io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
};
ina226-u64 {
compatible = "iio-hwmon";
io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
};
ina226-u69 {
compatible = "iio-hwmon";
io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
};
ina226-u66 {
compatible = "iio-hwmon";
io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u63 {
compatible = "iio-hwmon";
io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
};
ina226-u3 {
compatible = "iio-hwmon";
io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
};
ina226-u71 {
compatible = "iio-hwmon";
io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u73 {
compatible = "iio-hwmon";
io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
type = "full-size";
port {
dpcon_in: endpoint {
remote-endpoint = <&dpsub_dp_out>;
};
};
};
};
&dcc {
status = "okay";
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
};
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u22: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller; /* interrupt not connected */
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - MAX6643_OT_B
* 1 - MAX6643_FANFAIL_B
* 2 - MIO26_PMU_INPUT_LS
* 4 - SFP_SI5382_INT_ALM
* 5 - IIC_MUX_RESET_B
* 6 - GEM3_EXP_RESET_B
* 10 - FMCP_HSPC_PRSNT_M2C_B
* 11 - CLK_SPI_MUX_SEL0
* 12 - CLK_SPI_MUX_SEL1
* 16 - IRPS5401_ALERT_B
* 17 - INA226_PMBUS_ALERT
* 3, 7, 13-15 - not connected
*/
};
i2c-mux@75 { /* u23 */
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* PS_PMBUS */
/* PMBUS_ALERT done via pca9544 */
u67: ina226@40 { /* u67 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u67";
reg = <0x40>;
shunt-resistor = <2000>;
};
u59: ina226@41 { /* u59 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u59";
reg = <0x41>;
shunt-resistor = <5000>;
};
u61: ina226@42 { /* u61 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u61";
reg = <0x42>;
shunt-resistor = <5000>;
};
u60: ina226@43 { /* u60 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u60";
reg = <0x43>;
shunt-resistor = <5000>;
};
u64: ina226@45 { /* u64 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u64";
reg = <0x45>;
shunt-resistor = <5000>;
};
u69: ina226@46 { /* u69 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u69";
reg = <0x46>;
shunt-resistor = <2000>;
};
u66: ina226@47 { /* u66 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u66";
reg = <0x47>;
shunt-resistor = <5000>;
};
u65: ina226@48 { /* u65 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u65";
reg = <0x48>;
shunt-resistor = <5000>;
};
u63: ina226@49 { /* u63 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u63";
reg = <0x49>;
shunt-resistor = <5000>;
};
u3: ina226@4a { /* u3 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u3";
reg = <0x4a>;
shunt-resistor = <5000>;
};
u71: ina226@4b { /* u71 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u71";
reg = <0x4b>;
shunt-resistor = <5000>;
};
u77: ina226@4c { /* u77 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u77";
reg = <0x4c>;
shunt-resistor = <5000>;
};
u73: ina226@4d { /* u73 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u73";
reg = <0x4d>;
shunt-resistor = <5000>;
};
u79: ina226@4e { /* u79 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u79";
reg = <0x4e>;
shunt-resistor = <5000>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* NC */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
compatible = "infineon,irps5401";
reg = <0x43>;
};
irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
compatible = "infineon,irps5401";
reg = <0x44>;
};
irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
compatible = "infineon,irps5401";
reg = <0x45>;
};
/* u68 IR38064 +0 */
/* u70 IR38060 +1 */
/* u74 IR38060 +2 */
/* u75 IR38060 +6 */
/* J19 header too */
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* SYSMON */
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { /* u26 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/*
* IIC_EEPROM 1kB memory which uses 256B blocks
* where every block has different address.
* 0 - 256B address 0x54
* 256B - 512B address 0x55
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
eeprom: eeprom@54 { /* u88 */
compatible = "atmel,24c08";
reg = <0x54>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u46 */
compatible = "silabs,si5341";
reg = <0x36>;
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
si570_1: clock-generator@5d { /* USER SI570 - u47 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <300000000>;
clock-frequency = <300000000>;
clock-output-names = "si570_user";
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* SI5382 - u48 */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
sc18is603: spi@2f { /* sc18is602 - u93 */
compatible = "nxp,sc18is603";
reg = <0x2f>;
/* 4 gpios for CS not handled by driver */
/*
* USB2ANY cable or
* LMK04208 - u90 or
* LMX2594 - u102 or
* LMX2594 - u103 or
* LMX2594 - u104
*/
};
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* FMC connector */
};
/* 7 NC */
};
i2c-mux@75 {
compatible = "nxp,pca9548"; /* u27 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* FMCP_HSPC_IIC */
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* NC */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* SYSMON */
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* SFP3 */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* SFP2 */
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* SFP1 */
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
/* SFP0 */
};
};
};
&pinctrl0 {
status = "okay";
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_3_grp";
function = "i2c0";
};
conf {
groups = "i2c0_3_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
conf {
groups = "gpio0_14_grp", "gpio0_15_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_default: i2c1-default {
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp", "gpio0_17_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_uart0_default: uart0-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
drive-strength = <12>;
slew-rate = <SLEW_RATE_FAST>;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
"MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
"MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
};
pinctrl_sdhci1_default: sdhci1-default {
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
};
pinctrl_gpio_default: gpio-default {
mux {
function = "gpio0";
groups = "gpio0_22_grp", "gpio0_23_grp";
};
conf {
groups = "gpio0_22_grp", "gpio0_23_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-msp {
function = "gpio0";
groups = "gpio0_13_grp", "gpio0_38_grp";
};
conf-msp {
groups = "gpio0_13_grp", "gpio0_38_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-pull-up {
pins = "MIO22";
bias-pull-up;
};
conf-pull-none {
pins = "MIO13", "MIO23", "MIO38";
bias-disable;
};
};
};
&psgtr {
status = "okay";
/* nc, dp, usb3, sata */
clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
disable-wp;
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts
+58
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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZCU1275 RevA";
compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&dcc {
status = "okay";
};
&gpio {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+1342
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