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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/csky/abiv2/inc/abi/cacheflush.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ABI_CSKY_CACHEFLUSH_H
#define __ABI_CSKY_CACHEFLUSH_H
/* Keep includes the same across arches. */
#include <linux/mm.h>
/*
* The cache doesn't need to be flushed when TLB entries change when
* the cache is mapped to physical memory, not virtual memory
*/
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define PG_dcache_clean PG_arch_1
static inline void flush_dcache_folio(struct folio *folio)
{
if (test_bit(PG_dcache_clean, &folio->flags.f))
clear_bit(PG_dcache_clean, &folio->flags.f);
}
#define flush_dcache_folio flush_dcache_folio
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
static inline void flush_dcache_page(struct page *page)
{
flush_dcache_folio(page_folio(page));
}
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start, end) cache_wbinv_range(start, end)
void flush_icache_mm_range(struct mm_struct *mm,
unsigned long start, unsigned long end);
void flush_icache_deferred(struct mm_struct *mm);
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vmap_early(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
memcpy(dst, src, len); \
if (vma->vm_flags & VM_EXEC) { \
dcache_wb_range((unsigned long)dst, \
(unsigned long)dst + len); \
flush_icache_mm_range(current->mm, \
(unsigned long)dst, \
(unsigned long)dst + len); \
} \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
#endif /* __ABI_CSKY_CACHEFLUSH_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/ckmmu.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_CSKY_CKMMUV2_H
#define __ASM_CSKY_CKMMUV2_H
#include <abi/reg_ops.h>
#include <asm/barrier.h>
static inline int read_mmu_index(void)
{
return mfcr("cr<0, 15>");
}
static inline void write_mmu_index(int value)
{
mtcr("cr<0, 15>", value);
}
static inline int read_mmu_entrylo0(void)
{
return mfcr("cr<2, 15>");
}
static inline int read_mmu_entrylo1(void)
{
return mfcr("cr<3, 15>");
}
static inline void write_mmu_pagemask(int value)
{
mtcr("cr<6, 15>", value);
}
static inline int read_mmu_entryhi(void)
{
return mfcr("cr<4, 15>");
}
static inline void write_mmu_entryhi(int value)
{
mtcr("cr<4, 15>", value);
}
static inline unsigned long read_mmu_msa0(void)
{
return mfcr("cr<30, 15>");
}
static inline void write_mmu_msa0(unsigned long value)
{
mtcr("cr<30, 15>", value);
}
static inline unsigned long read_mmu_msa1(void)
{
return mfcr("cr<31, 15>");
}
static inline void write_mmu_msa1(unsigned long value)
{
mtcr("cr<31, 15>", value);
}
/*
* TLB operations.
*/
static inline void tlb_probe(void)
{
mtcr("cr<8, 15>", 0x80000000);
}
static inline void tlb_read(void)
{
mtcr("cr<8, 15>", 0x40000000);
}
static inline void tlb_invalid_all(void)
{
#ifdef CONFIG_CPU_HAS_TLBI
sync_is();
asm volatile(
"tlbi.alls \n"
"sync.i \n"
:
:
: "memory");
#else
mtcr("cr<8, 15>", 0x04000000);
#endif
}
static inline void local_tlb_invalid_all(void)
{
#ifdef CONFIG_CPU_HAS_TLBI
sync_is();
asm volatile(
"tlbi.all \n"
"sync.i \n"
:
:
: "memory");
#else
tlb_invalid_all();
#endif
}
static inline void tlb_invalid_indexed(void)
{
mtcr("cr<8, 15>", 0x02000000);
}
#define NOP32 ".long 0x4820c400\n"
static inline void setup_pgd(pgd_t *pgd, int asid)
{
#ifdef CONFIG_CPU_HAS_TLBI
sync_is();
#else
mb();
#endif
asm volatile(
#ifdef CONFIG_CPU_HAS_TLBI
"mtcr %1, cr<28, 15> \n"
#endif
"mtcr %1, cr<29, 15> \n"
"mtcr %0, cr< 4, 15> \n"
".rept 64 \n"
NOP32
".endr \n"
:
:"r"(asid), "r"(__pa(pgd) | BIT(0))
:"memory");
}
static inline pgd_t *get_pgd(void)
{
return __va(mfcr("cr<29, 15>") & ~BIT(0));
}
#endif /* __ASM_CSKY_CKMMUV2_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/elf.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ABI_CSKY_ELF_H
#define __ABI_CSKY_ELF_H
/* The member sort in array pr_reg[x] is defined by GDB. */
#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \
pr_reg[0] = regs->pc; \
pr_reg[1] = regs->a1; \
pr_reg[2] = regs->a0; \
pr_reg[3] = regs->sr; \
pr_reg[4] = regs->a2; \
pr_reg[5] = regs->a3; \
pr_reg[6] = regs->regs[0]; \
pr_reg[7] = regs->regs[1]; \
pr_reg[8] = regs->regs[2]; \
pr_reg[9] = regs->regs[3]; \
pr_reg[10] = regs->regs[4]; \
pr_reg[11] = regs->regs[5]; \
pr_reg[12] = regs->regs[6]; \
pr_reg[13] = regs->regs[7]; \
pr_reg[14] = regs->regs[8]; \
pr_reg[15] = regs->regs[9]; \
pr_reg[16] = regs->usp; \
pr_reg[17] = regs->lr; \
pr_reg[18] = regs->exregs[0]; \
pr_reg[19] = regs->exregs[1]; \
pr_reg[20] = regs->exregs[2]; \
pr_reg[21] = regs->exregs[3]; \
pr_reg[22] = regs->exregs[4]; \
pr_reg[23] = regs->exregs[5]; \
pr_reg[24] = regs->exregs[6]; \
pr_reg[25] = regs->exregs[7]; \
pr_reg[26] = regs->exregs[8]; \
pr_reg[27] = regs->exregs[9]; \
pr_reg[28] = regs->exregs[10]; \
pr_reg[29] = regs->exregs[11]; \
pr_reg[30] = regs->exregs[12]; \
pr_reg[31] = regs->exregs[13]; \
pr_reg[32] = regs->exregs[14]; \
pr_reg[33] = regs->tls; \
} while (0);
#endif /* __ABI_CSKY_ELF_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/entry.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_CSKY_ENTRY_H
#define __ASM_CSKY_ENTRY_H
#include <asm/setup.h>
#include <abi/regdef.h>
#define LSAVE_PC 8
#define LSAVE_PSR 12
#define LSAVE_A0 24
#define LSAVE_A1 28
#define LSAVE_A2 32
#define LSAVE_A3 36
#define LSAVE_A4 40
#define LSAVE_A5 44
#define KSPTOUSP
#define USPTOKSP
#define usp cr<14, 1>
.macro SAVE_ALL epc_inc
subi sp, 152
stw tls, (sp, 0)
stw lr, (sp, 4)
RD_MEH lr
WR_MEH lr
mfcr lr, epc
movi tls, \epc_inc
add lr, tls
stw lr, (sp, 8)
mfcr lr, epsr
stw lr, (sp, 12)
btsti lr, 31
bf 1f
addi lr, sp, 152
br 2f
1:
mfcr lr, usp
2:
stw lr, (sp, 16)
stw a0, (sp, 20)
stw a0, (sp, 24)
stw a1, (sp, 28)
stw a2, (sp, 32)
stw a3, (sp, 36)
addi sp, 40
stm r4-r13, (sp)
addi sp, 40
stm r16-r30, (sp)
#ifdef CONFIG_CPU_HAS_HILO
mfhi lr
stw lr, (sp, 60)
mflo lr
stw lr, (sp, 64)
mfcr lr, cr14
stw lr, (sp, 68)
#endif
subi sp, 80
.endm
.macro RESTORE_ALL
ldw tls, (sp, 0)
ldw lr, (sp, 4)
ldw a0, (sp, 8)
mtcr a0, epc
ldw a0, (sp, 12)
mtcr a0, epsr
btsti a0, 31
ldw a0, (sp, 16)
mtcr a0, usp
mtcr a0, ss0
#ifdef CONFIG_CPU_HAS_HILO
ldw a0, (sp, 140)
mthi a0
ldw a0, (sp, 144)
mtlo a0
ldw a0, (sp, 148)
mtcr a0, cr14
#endif
ldw a0, (sp, 24)
ldw a1, (sp, 28)
ldw a2, (sp, 32)
ldw a3, (sp, 36)
addi sp, 40
ldm r4-r13, (sp)
addi sp, 40
ldm r16-r30, (sp)
addi sp, 72
bf 1f
mfcr sp, ss0
1:
rte
.endm
.macro SAVE_REGS_FTRACE
subi sp, 152
stw tls, (sp, 0)
stw lr, (sp, 4)
mfcr lr, psr
stw lr, (sp, 12)
addi lr, sp, 152
stw lr, (sp, 16)
stw a0, (sp, 20)
stw a0, (sp, 24)
stw a1, (sp, 28)
stw a2, (sp, 32)
stw a3, (sp, 36)
addi sp, 40
stm r4-r13, (sp)
addi sp, 40
stm r16-r30, (sp)
#ifdef CONFIG_CPU_HAS_HILO
mfhi lr
stw lr, (sp, 60)
mflo lr
stw lr, (sp, 64)
mfcr lr, cr14
stw lr, (sp, 68)
#endif
subi sp, 80
.endm
.macro RESTORE_REGS_FTRACE
ldw tls, (sp, 0)
#ifdef CONFIG_CPU_HAS_HILO
ldw a0, (sp, 140)
mthi a0
ldw a0, (sp, 144)
mtlo a0
ldw a0, (sp, 148)
mtcr a0, cr14
#endif
ldw a0, (sp, 24)
ldw a1, (sp, 28)
ldw a2, (sp, 32)
ldw a3, (sp, 36)
addi sp, 40
ldm r4-r13, (sp)
addi sp, 40
ldm r16-r30, (sp)
addi sp, 72
.endm
.macro SAVE_SWITCH_STACK
subi sp, 64
stm r4-r11, (sp)
stw lr, (sp, 32)
stw r16, (sp, 36)
stw r17, (sp, 40)
stw r26, (sp, 44)
stw r27, (sp, 48)
stw r28, (sp, 52)
stw r29, (sp, 56)
stw r30, (sp, 60)
#ifdef CONFIG_CPU_HAS_HILO
subi sp, 16
mfhi lr
stw lr, (sp, 0)
mflo lr
stw lr, (sp, 4)
mfcr lr, cr14
stw lr, (sp, 8)
#endif
.endm
.macro RESTORE_SWITCH_STACK
#ifdef CONFIG_CPU_HAS_HILO
ldw lr, (sp, 0)
mthi lr
ldw lr, (sp, 4)
mtlo lr
ldw lr, (sp, 8)
mtcr lr, cr14
addi sp, 16
#endif
ldm r4-r11, (sp)
ldw lr, (sp, 32)
ldw r16, (sp, 36)
ldw r17, (sp, 40)
ldw r26, (sp, 44)
ldw r27, (sp, 48)
ldw r28, (sp, 52)
ldw r29, (sp, 56)
ldw r30, (sp, 60)
addi sp, 64
.endm
/* MMU registers operators. */
.macro RD_MIR rx
mfcr \rx, cr<0, 15>
.endm
.macro RD_MEH rx
mfcr \rx, cr<4, 15>
.endm
.macro RD_MCIR rx
mfcr \rx, cr<8, 15>
.endm
.macro RD_PGDR rx
mfcr \rx, cr<29, 15>
.endm
.macro RD_PGDR_K rx
mfcr \rx, cr<28, 15>
.endm
.macro WR_MEH rx
mtcr \rx, cr<4, 15>
.endm
.macro WR_MCIR rx
mtcr \rx, cr<8, 15>
.endm
#ifdef CONFIG_PAGE_OFFSET_80000000
#define MSA_SET cr<30, 15>
#define MSA_CLR cr<31, 15>
#endif
#ifdef CONFIG_PAGE_OFFSET_A0000000
#define MSA_SET cr<31, 15>
#define MSA_CLR cr<30, 15>
#endif
.macro SETUP_MMU
/* Init psr and enable ee */
lrw r6, DEFAULT_PSR_VALUE
mtcr r6, psr
psrset ee
/* Invalid I/Dcache BTB BHT */
movi r6, 7
lsli r6, 16
addi r6, (1<<4) | 3
mtcr r6, cr17
/* Invalid all TLB */
bgeni r6, 26
mtcr r6, cr<8, 15> /* Set MCIR */
/* Check MMU on/off */
mfcr r6, cr18
btsti r6, 0
bt 1f
/* MMU off: setup mapping tlb entry */
movi r6, 0
mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
grs r6, 1f /* Get current pa by PC */
bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
andn r6, r7
mtcr r6, cr<4, 15> /* Set MEH */
mov r8, r6
movi r7, 0x00000006
or r8, r7
mtcr r8, cr<2, 15> /* Set MEL0 */
movi r7, 0x00001006
or r8, r7
mtcr r8, cr<3, 15> /* Set MEL1 */
bgeni r8, 28
mtcr r8, cr<8, 15> /* Set MCIR to write TLB */
br 2f
1:
/*
* MMU on: use origin MSA value from bootloader
*
* cr<30/31, 15> MSA register format:
* 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* BA Reserved SH WA B SO SEC C D V
*/
mfcr r6, MSA_SET /* Get MSA */
2:
lsri r6, 29
lsli r6, 29
addi r6, 0x1ce
mtcr r6, MSA_SET /* Set MSA */
movi r6, 0
mtcr r6, MSA_CLR /* Clr MSA */
/* enable MMU */
mfcr r6, cr18
bseti r6, 0
mtcr r6, cr18
jmpi 3f /* jump to va */
3:
.endm
#endif /* __ASM_CSKY_ENTRY_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/fpu.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_CSKY_FPU_H
#define __ASM_CSKY_FPU_H
#include <asm/sigcontext.h>
#include <asm/ptrace.h>
int fpu_libc_helper(struct pt_regs *regs);
void fpu_fpe(struct pt_regs *regs);
static inline void init_fpu(void) { mtcr("cr<1, 2>", 0); }
void save_to_user_fp(struct user_fp *user_fp);
void restore_from_user_fp(struct user_fp *user_fp);
/*
* Define the fesr bit for fpe handle.
*/
#define FPE_ILLE (1 << 16) /* Illegal instruction */
#define FPE_FEC (1 << 7) /* Input float-point arithmetic exception */
#define FPE_IDC (1 << 5) /* Input denormalized exception */
#define FPE_IXC (1 << 4) /* Inexact exception */
#define FPE_UFC (1 << 3) /* Underflow exception */
#define FPE_OFC (1 << 2) /* Overflow exception */
#define FPE_DZC (1 << 1) /* Divide by zero exception */
#define FPE_IOC (1 << 0) /* Invalid operation exception */
#define FPE_REGULAR_EXCEPTION (FPE_IXC | FPE_UFC | FPE_OFC | FPE_DZC | FPE_IOC)
#ifdef CONFIG_OPEN_FPU_IDE
#define IDE_STAT (1 << 5)
#else
#define IDE_STAT 0
#endif
#ifdef CONFIG_OPEN_FPU_IXE
#define IXE_STAT (1 << 4)
#else
#define IXE_STAT 0
#endif
#ifdef CONFIG_OPEN_FPU_UFE
#define UFE_STAT (1 << 3)
#else
#define UFE_STAT 0
#endif
#ifdef CONFIG_OPEN_FPU_OFE
#define OFE_STAT (1 << 2)
#else
#define OFE_STAT 0
#endif
#ifdef CONFIG_OPEN_FPU_DZE
#define DZE_STAT (1 << 1)
#else
#define DZE_STAT 0
#endif
#ifdef CONFIG_OPEN_FPU_IOE
#define IOE_STAT (1 << 0)
#else
#define IOE_STAT 0
#endif
#endif /* __ASM_CSKY_FPU_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/page.h
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/* SPDX-License-Identifier: GPL-2.0 */
static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
struct page *page)
{
copy_page(to, from);
}
linux-7.2.3/arch/csky/abiv2/inc/abi/pgtable-bits.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_CSKY_PGTABLE_BITS_H
#define __ASM_CSKY_PGTABLE_BITS_H
/* implemented in software */
#define _PAGE_ACCESSED (1<<7)
#define _PAGE_READ (1<<8)
#define _PAGE_WRITE (1<<9)
#define _PAGE_PRESENT (1<<10)
#define _PAGE_MODIFIED (1<<11)
/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
#define _PAGE_SWP_EXCLUSIVE (1<<7)
/* implemented in hardware */
#define _PAGE_GLOBAL (1<<0)
#define _PAGE_VALID (1<<1)
#define _PAGE_DIRTY (1<<2)
#define _PAGE_SO (1<<5)
#define _PAGE_BUF (1<<6)
#define _PAGE_CACHE (1<<3)
#define _CACHE_MASK _PAGE_CACHE
#define _CACHE_CACHED (_PAGE_CACHE | _PAGE_BUF)
#define _CACHE_UNCACHED (0)
#define _PAGE_PROT_NONE _PAGE_WRITE
/*
* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
* are !pte_none() && !pte_present().
*
* Format of swap PTE:
* bit 0: _PAGE_GLOBAL (zero)
* bit 1: _PAGE_VALID (zero)
* bit 2 - 6: swap type
* bit 7: exclusive marker
* bit 8: swap offset[0]
* bit 9: _PAGE_WRITE (zero)
* bit 10: _PAGE_PRESENT (zero)
* bit 11 - 31: swap offset[1 - 21]
*/
#define __swp_type(x) (((x).val >> 2) & 0x1f)
#define __swp_offset(x) ((((x).val >> 8) & 0x1) | \
(((x).val >> 10) & 0x3ffffe))
#define __swp_entry(type, offset) ((swp_entry_t) { \
((type & 0x1f) << 2) | \
((offset & 0x1) << 8) | \
((offset & 0x3ffffe) << 10)})
#endif /* __ASM_CSKY_PGTABLE_BITS_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/reg_ops.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ABI_REG_OPS_H
#define __ABI_REG_OPS_H
#include <asm/reg_ops.h>
static inline unsigned int mfcr_hint(void)
{
return mfcr("cr31");
}
static inline unsigned int mfcr_ccr2(void)
{
return mfcr("cr23");
}
#endif /* __ABI_REG_OPS_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/regdef.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_CSKY_REGDEF_H
#define __ASM_CSKY_REGDEF_H
#ifdef __ASSEMBLER__
#define syscallid r7
#else
#define syscallid "r7"
#endif
#define regs_syscallid(regs) regs->regs[3]
#define regs_fp(regs) regs->regs[4]
/*
* PSR format:
* | 31 | 30-24 | 23-16 | 15 14 | 13-10 | 9 | 8-0 |
* S VEC TM MM
*
* S: Super Mode
* VEC: Exception Number
* TM: Trace Mode
* MM: Memory unaligned addr access
*/
#define DEFAULT_PSR_VALUE 0x80000200
#define SYSTRACE_SAVENUM 5
#define TRAP0_SIZE 4
#endif /* __ASM_CSKY_REGDEF_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/string.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ABI_CSKY_STRING_H
#define __ABI_CSKY_STRING_H
#define __HAVE_ARCH_MEMCMP
extern int memcmp(const void *, const void *, __kernel_size_t);
#define __HAVE_ARCH_MEMCPY
extern void *memcpy(void *, const void *, __kernel_size_t);
#define __HAVE_ARCH_MEMMOVE
extern void *memmove(void *, const void *, __kernel_size_t);
#define __HAVE_ARCH_MEMSET
extern void *memset(void *, int, __kernel_size_t);
#define __HAVE_ARCH_STRCMP
extern int strcmp(const char *, const char *);
#define __HAVE_ARCH_STRCPY
extern char *strcpy(char *, const char *);
#define __HAVE_ARCH_STRLEN
extern __kernel_size_t strlen(const char *);
#endif /* __ABI_CSKY_STRING_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/switch_context.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ABI_CSKY_PTRACE_H
#define __ABI_CSKY_PTRACE_H
struct switch_stack {
#ifdef CONFIG_CPU_HAS_HILO
unsigned long rhi;
unsigned long rlo;
unsigned long cr14;
unsigned long pad;
#endif
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long r11;
unsigned long r15;
unsigned long r16;
unsigned long r17;
unsigned long r26;
unsigned long r27;
unsigned long r28;
unsigned long r29;
unsigned long r30;
};
#endif /* __ABI_CSKY_PTRACE_H */
linux-7.2.3/arch/csky/abiv2/inc/abi/vdso.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ABI_CSKY_VDSO_H
#define __ABI_CSKY_VDSO_H
/* movi r7, 173 */
#define SET_SYSCALL_ID .long 0x008bea07
#endif /* __ABI_CSKY_VDSO_H */