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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/mips/boot/dts/mscc/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_SOC_VCOREIII) += \
jaguar2_pcb110.dtb \
jaguar2_pcb111.dtb \
jaguar2_pcb118.dtb \
luton_pcb091.dtb \
ocelot_pcb120.dtb \
ocelot_pcb123.dtb \
serval_pcb105.dtb \
serval_pcb106.dtb
linux-7.2.3/arch/mips/boot/dts/mscc/jaguar2.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,jr2";
aliases {
serial0 = &uart0;
serial1 = &uart2;
gpio0 = &gpio;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb: ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@70000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};
intc: interrupt-controller@70000070 {
compatible = "mscc,jaguar2-icpu-intr";
reg = <0x70000070 0x94>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@70100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@70100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
gpio: pinctrl@71010038 {
compatible = "mscc,jaguar2-pinctrl";
reg = <0x71010038 0x90>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 64>;
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_24", "GPIO_25";
function = "uart2";
};
cs1_pins: cs1-pins {
pins = "GPIO_16";
function = "si";
};
cs2_pins: cs2-pins {
pins = "GPIO_17";
function = "si";
};
cs3_pins: cs3-pins {
pins = "GPIO_18";
function = "si";
};
i2c_pins: i2c-pins {
pins = "GPIO_14", "GPIO_15";
function = "twi";
};
i2c2_pins: i2c2-pins {
pins = "GPIO_28", "GPIO_29";
function = "twi2";
};
};
i2c0: i2c@70100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
status = "disabled";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x70100400 0x100>, <0x700001b8 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clock-frequency = <100000>;
clocks = <&ahb_clk>;
};
i2c2: i2c@70100c00 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
status = "disabled";
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
reg = <0x70100c00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clock-frequency = <100000>;
clocks = <&ahb_clk>;
};
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/jaguar2_common.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
#include "jaguar2.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-sda-hold-time-ns = <300>;
};
linux-7.2.3/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
compatible = "mscc,jr2-pcb110", "mscc,jr2";
aliases {
i2c0 = &i2c0;
i2c108 = &i2c108;
i2c109 = &i2c109;
i2c110 = &i2c110;
i2c111 = &i2c111;
i2c112 = &i2c112;
i2c113 = &i2c113;
i2c114 = &i2c114;
i2c115 = &i2c115;
i2c116 = &i2c116;
i2c117 = &i2c117;
i2c118 = &i2c118;
i2c119 = &i2c119;
i2c120 = &i2c120;
i2c121 = &i2c121;
i2c122 = &i2c122;
i2c123 = &i2c123;
i2c124 = &i2c124;
i2c125 = &i2c125;
i2c126 = &i2c126;
i2c127 = &i2c127;
i2c128 = &i2c128;
i2c129 = &i2c129;
i2c130 = &i2c130;
i2c131 = &i2c131;
i2c149 = &i2c149;
i2c150 = &i2c150;
i2c151 = &i2c151;
i2c152 = &i2c152;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c149", "i2c150", "i2c151", "i2c152", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_pins_i>;
i2c149: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c150: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c152: i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
i2c0_emux: i2c0-emux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH
&gpio 52 GPIO_ACTIVE_HIGH
&gpio 53 GPIO_ACTIVE_HIGH
&gpio 58 GPIO_ACTIVE_HIGH
&gpio 59 GPIO_ACTIVE_HIGH>;
idle-state = <0x0>;
i2c108: i2c@10 {
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c109: i2c@11 {
reg = <0x11>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c110: i2c@12 {
reg = <0x12>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c111: i2c@13 {
reg = <0x13>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c112: i2c@14 {
reg = <0x14>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c113: i2c@15 {
reg = <0x15>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c114: i2c@16 {
reg = <0x16>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c115: i2c@17 {
reg = <0x17>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c116: i2c@8 {
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c117: i2c@9 {
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c118: i2c@a {
reg = <0xa>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c119: i2c@b {
reg = <0xb>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c120: i2c@c {
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c121: i2c@d {
reg = <0xd>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c122: i2c@e {
reg = <0xe>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c123: i2c@f {
reg = <0xf>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
synce_pins: synce-pins {
// GPIO 16 == SI_nCS1
pins = "GPIO_16";
function = "si";
};
synce_builtin_pins: synce-builtin-pins {
// GPIO 49 == SI_nCS13
pins = "GPIO_49";
function = "si";
};
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};
&i2c0 {
i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c124: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c125: i2c@1 {
/* FMC B */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c126: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c127: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
i2c-mux@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c128: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c129: i2c@1 {
/* FMC B */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c130: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c131: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
/ {
model = "Jaguar2 Cu48 PCB111 Reference Board";
compatible = "mscc,jr2-pcb111", "mscc,jr2";
aliases {
i2c0 = &i2c0;
i2c149 = &i2c149;
i2c150 = &i2c150;
i2c151 = &i2c151;
i2c152 = &i2c152;
i2c203 = &i2c203;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
pinctrl-5 = <&i2cmux_pins_i>;
i2c149: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c150: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c152: i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c203: i2c@4 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
synce_builtin_pins: synce-builtin-pins {
// GPIO 49 == SI_nCS13
pins = "GPIO_49";
function = "si";
};
cpld_pins: cpld-pins {
// GPIO 50 == SI_nCS14
pins = "GPIO_50";
function = "si";
};
cpld_fifo_pins: synce-builtin-pins {
// GPIO 51 == SI_nCS15
pins = "GPIO_51";
function = "si";
};
};
&gpio {
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
/ {
model = "Jaguar2/Aquantia PCB118 Reference Board";
compatible = "mscc,jr2-pcb118", "mscc,jr2";
aliases {
i2c150 = &i2c150;
i2c151 = &i2c151;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c150", "i2c151", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_pins_i>;
i2c150: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_16";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1-pins {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/luton.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020 Microsemi Corporation */
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,luton";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <416666666>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb@60000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x60000000 0x20000000>;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@10000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x10000000 0x2c>;
};
intc: interrupt-controller@10000084 {
compatible = "mscc,luton-icpu-intr";
reg = <0x10000084 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@10100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x10100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c0: i2c@10100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x10100400 0x100>, <0x100002a4 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11>;
clocks = <&ahb_clk>;
status = "disabled";
};
gpio: pinctrl@70068 {
compatible = "mscc,luton-pinctrl";
reg = <0x70068 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 32>;
interrupt-controller;
interrupts = <13>;
#interrupt-cells = <2>;
i2c_pins: i2c-pins {
pins = "GPIO_5", "GPIO_6";
function = "twi";
};
uart_pins: uart-pins {
pins = "GPIO_30", "GPIO_31";
function = "uart";
};
};
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/luton_pcb091.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
/dts-v1/;
#include "luton.dtsi"
/ {
model = "Luton10 PCB091 Reference Board";
compatible = "mscc,luton-pcb091", "mscc,luton";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-sda-hold-time-ns = <300>;
};
linux-7.2.3/arch/mips/boot/dts/mscc/ocelot.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2017 Microsemi Corporation */
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,ocelot";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x70000000 0x2000000>;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@0 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x0 0x2c>;
};
intc: interrupt-controller@70 {
compatible = "mscc,ocelot-icpu-intr";
reg = <0x70 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c: i2c@100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x100400 0x100>, <0x198 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clocks = <&ahb_clk>;
status = "disabled";
};
uart2: serial@100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
spi: spi@101000 {
compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x101000 0x100>, <0x3c 0x18>;
interrupts = <9>;
clocks = <&ahb_clk>;
status = "disabled";
};
switch@1010000 {
compatible = "mscc,vsc7514-switch";
reg = <0x1010000 0x10000>,
<0x1030000 0x10000>,
<0x1080000 0x100>,
<0x10e0000 0x10000>,
<0x11e0000 0x100>,
<0x11f0000 0x100>,
<0x1200000 0x100>,
<0x1210000 0x100>,
<0x1220000 0x100>,
<0x1230000 0x100>,
<0x1240000 0x100>,
<0x1250000 0x100>,
<0x1260000 0x100>,
<0x1270000 0x100>,
<0x1280000 0x100>,
<0x1800000 0x80000>,
<0x1880000 0x10000>,
<0x1040000 0x10000>,
<0x1050000 0x10000>,
<0x1060000 0x10000>,
<0x1a0 0x1c4>;
reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
"port2", "port3", "port4", "port5", "port6",
"port7", "port8", "port9", "port10", "qsys",
"ana", "s0", "s1", "s2", "fdma";
interrupts = <18 21 22 16>;
interrupt-names = "ptp_rdy", "xtr", "inj", "fdma";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port0: port@0 {
reg = <0>;
status = "disabled";
};
port1: port@1 {
reg = <1>;
status = "disabled";
};
port2: port@2 {
reg = <2>;
status = "disabled";
};
port3: port@3 {
reg = <3>;
status = "disabled";
};
port4: port@4 {
reg = <4>;
status = "disabled";
};
port5: port@5 {
reg = <5>;
status = "disabled";
};
port6: port@6 {
reg = <6>;
status = "disabled";
};
port7: port@7 {
reg = <7>;
status = "disabled";
};
port8: port@8 {
reg = <8>;
status = "disabled";
};
port9: port@9 {
reg = <9>;
status = "disabled";
};
port10: port@10 {
reg = <10>;
status = "disabled";
};
};
};
reset@1070008 {
compatible = "mscc,ocelot-chip-reset";
reg = <0x1070008 0x4>;
};
gpio: pinctrl@1070034 {
compatible = "mscc,ocelot-pinctrl";
reg = <0x1070034 0x68>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
interrupt-controller;
interrupts = <13>;
#interrupt-cells = <2>;
i2c_pins: i2c-pins {
pins = "GPIO_16", "GPIO_17";
function = "twi";
};
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim";
};
};
mdio0: mdio@107009c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x107009c 0x24>, <0x10700f0 0x8>;
interrupts = <14>;
status = "disabled";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
mdio1: mdio@10700c0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
pinctrl-0 = <&miim1_pins>;
status = "disabled";
};
hsio: syscon@10d0000 {
compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
reg = <0x10d0000 0x10000>;
serdes: serdes {
compatible = "mscc,vsc7514-serdes";
#phy-cells = <2>;
};
};
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2017 Microsemi Corporation */
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy-ocelot-serdes.h>
#include "ocelot.dtsi"
/ {
compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0e000000>;
};
};
&gpio {
phy_int_pins: phy-int-pins {
pins = "GPIO_4";
function = "gpio";
};
phy_load_save_pins: phy-load-save-pins {
pins = "GPIO_10";
function = "ptp2";
};
};
&mdio0 {
status = "okay";
};
&mdio1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
phy7: ethernet-phy@0 {
reg = <0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
phy6: ethernet-phy@1 {
reg = <1>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
phy5: ethernet-phy@2 {
reg = <2>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
phy4: ethernet-phy@3 {
reg = <3>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpio>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
};
&port0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
phy-mode = "internal";
};
&port4 {
status = "okay";
phy-handle = <&phy7>;
phy-mode = "sgmii";
phys = <&serdes 4 SERDES1G(2)>;
};
&port5 {
status = "okay";
phy-handle = <&phy4>;
phy-mode = "sgmii";
phys = <&serdes 5 SERDES1G(5)>;
};
&port6 {
status = "okay";
phy-handle = <&phy6>;
phy-mode = "sgmii";
phys = <&serdes 6 SERDES1G(3)>;
};
&port9 {
status = "okay";
phy-handle = <&phy5>;
phy-mode = "sgmii";
phys = <&serdes 9 SERDES1G(4)>;
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
linux-7.2.3/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2017 Microsemi Corporation */
/dts-v1/;
#include "ocelot.dtsi"
/ {
compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0e000000>;
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&spi {
status = "okay";
flash@0 {
compatible = "macronix,mx25l25635f", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
status = "okay";
};
&mdio0 {
status = "okay";
};
&port0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
phy-mode = "internal";
};
linux-7.2.3/arch/mips/boot/dts/mscc/serval.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,serval";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
gpio0 = &gpio;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <416666666>;
};
ahb_clk: ahb-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cpu_clk>;
clock-div = <2>;
clock-mult = <1>;
};
ahb: ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@70000000 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};
intc: interrupt-controller@70000070 {
compatible = "mscc,serval-icpu-intr";
reg = <0x70000070 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@70100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@70100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x70100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
gpio: pinctrl@71070034 {
compatible = "mscc,serval-pinctrl";
reg = <0x71070034 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
function = "sg0";
};
i2c_pins: i2c-pins {
pins = "GPIO_6", "GPIO_7";
function = "twi";
};
uart_pins: uart-pins {
pins = "GPIO_26", "GPIO_27";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_13", "GPIO_14";
function = "uart2";
};
cs1_pins: cs1-pins {
pins = "GPIO_8";
function = "si";
};
irqext0_pins: irqext0-pins {
pins = "GPIO_28";
function = "irq0";
};
irqext1_pins: irqext1-pins {
pins = "GPIO_29";
function = "irq1";
};
};
i2c0: i2c@70100400 {
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
status = "disabled";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
reg = <0x70100400 0x100>, <0x70000190 0x8>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clock-frequency = <100000>;
clocks = <&ahb_clk>;
};
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/serval_common.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microsemi Corporation
*/
#include "serval.dtsi"
/ {
aliases {
serial0 = &uart0;
i2c104 = &i2c104;
i2c105 = &i2c105;
i2c106 = &i2c106;
i2c107 = &i2c107;
i2c108 = &i2c108;
i2c109 = &i2c109;
};
chosen {
stdout-path = "serial0:115200n8";
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c104", "i2c105", "i2c106", "i2c107",
"i2c108", "i2c109", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_4>;
pinctrl-5 = <&i2cmux_5>;
pinctrl-6 = <&i2cmux_pins_i>;
i2c104: i2c_sfp0@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c105: i2c_sfp1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c106: i2c_sfp2@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c107: i2c_sfp3@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c108: i2c_sfp4@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c109: i2c_sfp5@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&gpio {
i2c_pins: i2c-pins {
pins = "GPIO_7"; /* No "default" scl for i2c0 */
function = "twi";
};
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
"GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0-pins {
pins = "GPIO_11";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1-pins {
pins = "GPIO_12";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3-pins {
pins = "GPIO_19";
function = "twi_scl_m";
output-high;
};
i2cmux_4: i2cmux-4-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_5: i2cmux-5-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};
&i2c0 {
status = "okay";
i2c-sda-hold-time-ns = <300>;
};
linux-7.2.3/arch/mips/boot/dts/mscc/serval_pcb105.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "serval_common.dtsi"
/ {
model = "Serval PCB105 Reference Board";
compatible = "mscc,serval-pcb105", "mscc,serval";
aliases {
};
};
linux-7.2.3/arch/mips/boot/dts/mscc/serval_pcb106.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "serval_common.dtsi"
/ {
model = "Serval PCB106 Reference Board";
compatible = "mscc,serval-pcb106", "mscc,serval";
aliases {
};
};