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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/mips/include/asm/Kbuild
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# SPDX-License-Identifier: GPL-2.0
# MIPS headers
generated-y += syscall_table_n32.h
generated-y += syscall_table_n64.h
generated-y += syscall_table_o32.h
generated-y += unistd_nr_n32.h
generated-y += unistd_nr_n64.h
generated-y += unistd_nr_o32.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
generic-y += parport.h
generic-y += qrwlock.h
generic-y += qspinlock.h
generic-y += ring_buffer.h
generic-y += user.h
generic-y += text-patching.h
linux-7.2.3/arch/mips/include/asm/abi.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2005 MIPS Technologies, Inc.
*/
#ifndef _ASM_ABI_H
#define _ASM_ABI_H
#include <linux/signal_types.h>
#include <asm/signal.h>
#include <asm/siginfo.h>
#include <asm/vdso.h>
struct mips_abi {
int (* const setup_frame)(void *sig_return, struct ksignal *ksig,
struct pt_regs *regs, sigset_t *set);
int (* const setup_rt_frame)(void *sig_return, struct ksignal *ksig,
struct pt_regs *regs, sigset_t *set);
const unsigned long restart;
unsigned off_sc_fpregs;
unsigned off_sc_fpc_csr;
unsigned off_sc_used_math;
struct mips_vdso_image *vdso;
};
#endif /* _ASM_ABI_H */
linux-7.2.3/arch/mips/include/asm/addrspace.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
*/
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
#include <spaces.h>
/*
* Configure language
*/
#ifdef __ASSEMBLER__
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
#define _CONST64_(x) x
#else
#define _ATYPE_ __PTRDIFF_TYPE__
#define _ATYPE32_ int
#define _ATYPE64_ __s64
#ifdef CONFIG_64BIT
#define _CONST64_(x) x ## L
#else
#define _CONST64_(x) x ## LL
#endif
#endif
/*
* 32-bit MIPS address spaces
*/
#ifdef __ASSEMBLER__
#define _ACAST32_
#define _ACAST64_
#else
#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
#endif
/*
* Returns the kernel segment base of a given address
*/
#define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000))
/*
* Gives the size of each kernel segment
*/
#define CSEGX_SIZE 0x20000000
/*
* Returns the physical address of a CKSEGx / XKPHYS address
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
_CONST64_(0x0000ffffffffffff))
#ifdef CONFIG_64BIT
/*
* Memory segments (64bit kernel mode addresses)
* The compatibility segments use the full 64-bit sign extended value. Note
* the R8000 doesn't have them so don't reference these in generic MIPS code.
*/
#define XKUSEG _CONST64_(0x0000000000000000)
#define XKSSEG _CONST64_(0x4000000000000000)
#define XKPHYS _CONST64_(0x8000000000000000)
#define XKSEG _CONST64_(0xc000000000000000)
#define CKSEG0 _CONST64_(0xffffffff80000000)
#define CKSEG1 _CONST64_(0xffffffffa0000000)
#define CKSSEG _CONST64_(0xffffffffc0000000)
#define CKSEG3 _CONST64_(0xffffffffe0000000)
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
#else
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/*
* Map an address to a certain kernel segment
*/
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/*
* Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
*/
#define KUSEG 0x00000000
#define KSEG0 0x80000000
#define KSEG1 0xa0000000
#define KSEG2 0xc0000000
#define KSEG3 0xe0000000
#define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
#endif
/*
* Cache modes for XKPHYS address conversion macros
*/
#define K_CALG_COH_EXCL1_NOL2 0
#define K_CALG_COH_SHRL1_NOL2 1
#define K_CALG_UNCACHED 2
#define K_CALG_NONCOHERENT 3
#define K_CALG_COH_EXCL 4
#define K_CALG_COH_SHAREABLE 5
#define K_CALG_NOTUSED 6
#define K_CALG_UNCACHED_ACCEL 7
/*
* 64-bit address conversions
*/
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
/*
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
* R8000 implements most with its 48-bit physical address space.
*/
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#endif /* _ASM_ADDRSPACE_H */
linux-7.2.3/arch/mips/include/asm/amon.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Imagination Technologies Ltd.
*
* Arbitrary Monitor Support (AMON)
*/
int amon_cpu_avail(int cpu);
int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp,
unsigned long gp, unsigned long a0);
linux-7.2.3/arch/mips/include/asm/arch_hweight.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#ifndef _ASM_ARCH_HWEIGHT_H
#define _ASM_ARCH_HWEIGHT_H
#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
#include <asm/types.h>
static inline unsigned int __arch_hweight32(unsigned int w)
{
return __builtin_popcount(w);
}
static inline unsigned int __arch_hweight16(unsigned int w)
{
return __builtin_popcount(w & 0xffff);
}
static inline unsigned int __arch_hweight8(unsigned int w)
{
return __builtin_popcount(w & 0xff);
}
static inline unsigned long __arch_hweight64(__u64 w)
{
return __builtin_popcountll(w);
}
#else
#include <asm-generic/bitops/arch_hweight.h>
#endif
#endif /* _ASM_ARCH_HWEIGHT_H */
linux-7.2.3/arch/mips/include/asm/asm-eva.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2014 Imagination Technologies Ltd.
*
*/
#ifndef __ASM_ASM_EVA_H
#define __ASM_ASM_EVA_H
#ifndef __ASSEMBLER__
/* Kernel variants */
#define kernel_cache(op, base) "cache " op ", " base "\n"
#define kernel_pref(hint, base) "pref " hint ", " base "\n"
#define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
#define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
#define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
#define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n"
#define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n"
#define kernel_lh(reg, addr) "lh " reg ", " addr "\n"
#define kernel_lb(reg, addr) "lb " reg ", " addr "\n"
#define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n"
#define kernel_sw(reg, addr) "sw " reg ", " addr "\n"
#define kernel_swl(reg, addr) "swl " reg ", " addr "\n"
#define kernel_swr(reg, addr) "swr " reg ", " addr "\n"
#define kernel_sh(reg, addr) "sh " reg ", " addr "\n"
#define kernel_sb(reg, addr) "sb " reg ", " addr "\n"
#ifdef CONFIG_32BIT
/*
* No 'sd' or 'ld' instructions in 32-bit but the code will
* do the correct thing
*/
#define kernel_sd(reg, addr) user_sw(reg, addr)
#define kernel_ld(reg, addr) user_lw(reg, addr)
#else
#define kernel_sd(reg, addr) "sd " reg", " addr "\n"
#define kernel_ld(reg, addr) "ld " reg", " addr "\n"
#endif /* CONFIG_32BIT */
#ifdef CONFIG_EVA
#define __BUILD_EVA_INSN(insn, reg, addr) \
" .set push\n" \
" .set mips0\n" \
" .set eva\n" \
" "insn" "reg", "addr "\n" \
" .set pop\n"
#define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base)
#define user_pref(hint, base) __BUILD_EVA_INSN("prefe", hint, base)
#define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr)
#define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr)
#define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr)
#define user_lwl(reg, addr) __BUILD_EVA_INSN("lwle", reg, addr)
#define user_lwr(reg, addr) __BUILD_EVA_INSN("lwre", reg, addr)
#define user_lh(reg, addr) __BUILD_EVA_INSN("lhe", reg, addr)
#define user_lb(reg, addr) __BUILD_EVA_INSN("lbe", reg, addr)
#define user_lbu(reg, addr) __BUILD_EVA_INSN("lbue", reg, addr)
/* No 64-bit EVA instruction for loading double words */
#define user_ld(reg, addr) user_lw(reg, addr)
#define user_sw(reg, addr) __BUILD_EVA_INSN("swe", reg, addr)
#define user_swl(reg, addr) __BUILD_EVA_INSN("swle", reg, addr)
#define user_swr(reg, addr) __BUILD_EVA_INSN("swre", reg, addr)
#define user_sh(reg, addr) __BUILD_EVA_INSN("she", reg, addr)
#define user_sb(reg, addr) __BUILD_EVA_INSN("sbe", reg, addr)
/* No 64-bit EVA instruction for storing double words */
#define user_sd(reg, addr) user_sw(reg, addr)
#else
#define user_cache(op, base) kernel_cache(op, base)
#define user_pref(hint, base) kernel_pref(hint, base)
#define user_ll(reg, addr) kernel_ll(reg, addr)
#define user_sc(reg, addr) kernel_sc(reg, addr)
#define user_lw(reg, addr) kernel_lw(reg, addr)
#define user_lwl(reg, addr) kernel_lwl(reg, addr)
#define user_lwr(reg, addr) kernel_lwr(reg, addr)
#define user_lh(reg, addr) kernel_lh(reg, addr)
#define user_lb(reg, addr) kernel_lb(reg, addr)
#define user_lbu(reg, addr) kernel_lbu(reg, addr)
#define user_sw(reg, addr) kernel_sw(reg, addr)
#define user_swl(reg, addr) kernel_swl(reg, addr)
#define user_swr(reg, addr) kernel_swr(reg, addr)
#define user_sh(reg, addr) kernel_sh(reg, addr)
#define user_sb(reg, addr) kernel_sb(reg, addr)
#ifdef CONFIG_32BIT
#define user_sd(reg, addr) kernel_sw(reg, addr)
#define user_ld(reg, addr) kernel_lw(reg, addr)
#else
#define user_sd(reg, addr) kernel_sd(reg, addr)
#define user_ld(reg, addr) kernel_ld(reg, addr)
#endif /* CONFIG_32BIT */
#endif /* CONFIG_EVA */
#else /* __ASSEMBLER__ */
#define kernel_cache(op, base) cache op, base
#define kernel_pref(hint, base) pref hint, base
#define kernel_ll(reg, addr) ll reg, addr
#define kernel_sc(reg, addr) sc reg, addr
#define kernel_lw(reg, addr) lw reg, addr
#define kernel_lwl(reg, addr) lwl reg, addr
#define kernel_lwr(reg, addr) lwr reg, addr
#define kernel_lh(reg, addr) lh reg, addr
#define kernel_lb(reg, addr) lb reg, addr
#define kernel_lbu(reg, addr) lbu reg, addr
#define kernel_sw(reg, addr) sw reg, addr
#define kernel_swl(reg, addr) swl reg, addr
#define kernel_swr(reg, addr) swr reg, addr
#define kernel_sh(reg, addr) sh reg, addr
#define kernel_sb(reg, addr) sb reg, addr
#ifdef CONFIG_32BIT
/*
* No 'sd' or 'ld' instructions in 32-bit but the code will
* do the correct thing
*/
#define kernel_sd(reg, addr) user_sw(reg, addr)
#define kernel_ld(reg, addr) user_lw(reg, addr)
#else
#define kernel_sd(reg, addr) sd reg, addr
#define kernel_ld(reg, addr) ld reg, addr
#endif /* CONFIG_32BIT */
#ifdef CONFIG_EVA
#define __BUILD_EVA_INSN(insn, reg, addr) \
.set push; \
.set mips0; \
.set eva; \
insn reg, addr; \
.set pop;
#define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base)
#define user_pref(hint, base) __BUILD_EVA_INSN(prefe, hint, base)
#define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr)
#define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr)
#define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr)
#define user_lwl(reg, addr) __BUILD_EVA_INSN(lwle, reg, addr)
#define user_lwr(reg, addr) __BUILD_EVA_INSN(lwre, reg, addr)
#define user_lh(reg, addr) __BUILD_EVA_INSN(lhe, reg, addr)
#define user_lb(reg, addr) __BUILD_EVA_INSN(lbe, reg, addr)
#define user_lbu(reg, addr) __BUILD_EVA_INSN(lbue, reg, addr)
/* No 64-bit EVA instruction for loading double words */
#define user_ld(reg, addr) user_lw(reg, addr)
#define user_sw(reg, addr) __BUILD_EVA_INSN(swe, reg, addr)
#define user_swl(reg, addr) __BUILD_EVA_INSN(swle, reg, addr)
#define user_swr(reg, addr) __BUILD_EVA_INSN(swre, reg, addr)
#define user_sh(reg, addr) __BUILD_EVA_INSN(she, reg, addr)
#define user_sb(reg, addr) __BUILD_EVA_INSN(sbe, reg, addr)
/* No 64-bit EVA instruction for loading double words */
#define user_sd(reg, addr) user_sw(reg, addr)
#else
#define user_cache(op, base) kernel_cache(op, base)
#define user_pref(hint, base) kernel_pref(hint, base)
#define user_ll(reg, addr) kernel_ll(reg, addr)
#define user_sc(reg, addr) kernel_sc(reg, addr)
#define user_lw(reg, addr) kernel_lw(reg, addr)
#define user_lwl(reg, addr) kernel_lwl(reg, addr)
#define user_lwr(reg, addr) kernel_lwr(reg, addr)
#define user_lh(reg, addr) kernel_lh(reg, addr)
#define user_lb(reg, addr) kernel_lb(reg, addr)
#define user_lbu(reg, addr) kernel_lbu(reg, addr)
#define user_sw(reg, addr) kernel_sw(reg, addr)
#define user_swl(reg, addr) kernel_swl(reg, addr)
#define user_swr(reg, addr) kernel_swr(reg, addr)
#define user_sh(reg, addr) kernel_sh(reg, addr)
#define user_sb(reg, addr) kernel_sb(reg, addr)
#ifdef CONFIG_32BIT
#define user_sd(reg, addr) kernel_sw(reg, addr)
#define user_ld(reg, addr) kernel_lw(reg, addr)
#else
#define user_sd(reg, addr) kernel_sd(reg, addr)
#define user_ld(reg, addr) kernel_ld(reg, addr)
#endif /* CONFIG_32BIT */
#endif /* CONFIG_EVA */
#endif /* __ASSEMBLER__ */
#endif /* __ASM_ASM_EVA_H */
linux-7.2.3/arch/mips/include/asm/asm-offsets.h
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#include <generated/asm-offsets.h>
linux-7.2.3/arch/mips/include/asm/asm-prototypes.h
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/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/checksum.h>
#include <asm/page.h>
#include <asm/fpu.h>
#include <asm-generic/asm-prototypes.h>
#include <linux/uaccess.h>
#include <asm/ftrace.h>
#include <asm/mmu_context.h>
extern void clear_page_cpu(void *page);
extern void copy_page_cpu(void *to, void *from);
linux-7.2.3/arch/mips/include/asm/asm.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
#include <asm/sgidefs.h>
#include <asm/asm-eva.h>
#include <asm/isa-rev.h>
#ifndef __VDSO__
/*
* Emit CFI data in .debug_frame sections, not .eh_frame sections.
* We don't do DWARF unwinding at runtime, so only the offline DWARF
* information is useful to anyone. Note we should change this if we
* ever decide to enable DWARF unwinding at runtime.
*/
#define CFI_SECTIONS .cfi_sections .debug_frame
#else
/*
* For the vDSO, emit both runtime unwind information and debug
* symbols for the .dbg file.
*/
#define CFI_SECTIONS
#endif
#ifdef __ASSEMBLER__
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
CFI_SECTIONS; \
.globl symbol; \
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, 0, ra; \
.cfi_startproc; \
.insn
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
CFI_SECTIONS; \
.globl symbol; \
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, framesize, rpc; \
.cfi_startproc; \
.insn
/*
* END - mark end of function
*/
#define END(function) \
.cfi_endproc; \
.end function; \
.size function, .-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol, @function; \
symbol: .insn
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
#define ASM_PANIC(msg) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
jal panic; \
9: b 9b; \
.set pop; \
TEXT(msg)
/*
* Print formatted string
*/
#ifdef CONFIG_PRINTK
#define ASM_PRINT(string) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
jal _printk; \
.set pop; \
TEXT(string)
#else
#define ASM_PRINT(string)
#endif
#endif /* __ASSEMBLER__ */
/*
* Stack alignment
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define ALSZ 7
#define ALMASK ~7
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define ALSZ 15
#define ALMASK ~15
#endif
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#ifdef __mips64
#define SZREG 8
#else
#define SZREG 4
#endif
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define REG_S sd
#define REG_L ld
#define REG_SUBU dsubu
#define REG_ADDU daddu
#endif
/*
* How to add/sub/load/store/shift C int variables.
*/
#if (_MIPS_SZINT == 32)
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
#endif
#if (_MIPS_SZINT == 64)
#define INT_ADD dadd
#define INT_ADDU daddu
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_SUB dsub
#define INT_SUBU dsubu
#define INT_L ld
#define INT_S sd
#define INT_SLL dsll
#define INT_SLLV dsllv
#define INT_SRL dsrl
#define INT_SRLV dsrlv
#define INT_SRA dsra
#define INT_SRAV dsrav
#endif
/*
* How to add/sub/load/store/shift C long variables.
*/
#if (_MIPS_SZLONG == 32)
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_LL ll
#define LONG_SC sc
#define LONG_S sw
#define LONG_SP swp
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG_INS ins
#define LONG_EXT ext
#ifdef __ASSEMBLER__
#define LONG .word
#endif
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
#endif
#if (_MIPS_SZLONG == 64)
#define LONG_ADD dadd
#define LONG_ADDU daddu
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_LL lld
#define LONG_SC scd
#define LONG_S sd
#define LONG_SP sdp
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#define LONG_INS dins
#define LONG_EXT dext
#ifdef __ASSEMBLER__
#define LONG .dword
#endif
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3
#endif
/*
* How to add/sub/load/store/shift pointers.
*/
#if (_MIPS_SZPTR == 32)
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_LI li
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR_WD .word
#define PTRSIZE 4
#define PTRLOG 2
#endif
#if (_MIPS_SZPTR == 64)
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
#define PTR_LA dla
#define PTR_LI dli
#define PTR_SLL dsll
#define PTR_SLLV dsllv
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
#define PTR_SCALESHIFT 3
#define PTR_WD .dword
#define PTRSIZE 8
#define PTRLOG 3
#endif
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define MFC0 dmfc0
#define MTC0 dmtc0
#endif
#define SSNOP sll zero, zero, 1
/*
* Using a branch-likely instruction to check the result of an sc instruction
* works around a bug present in R10000 CPUs prior to revision 3.0 that could
* cause ll-sc sequences to execute non-atomically.
*/
#ifdef CONFIG_WAR_R10000_LLSC
# define SC_BEQZ beqzl
#elif !defined(CONFIG_CC_HAS_BROKEN_INLINE_COMPAT_BRANCH) && MIPS_ISA_REV >= 6
# define SC_BEQZ beqzc
#else
# define SC_BEQZ beqz
#endif
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
#else
#define R10KCBARRIER(addr)
#endif
#endif /* __ASM_ASM_H */
linux-7.2.3/arch/mips/include/asm/asmmacro-32.h
+91
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* asmmacro.h: Assembler macros to make things easier to read.
*
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
* Copyright (C) 1998, 1999, 2003 Ralf Baechle
*/
#ifndef _ASM_ASMMACRO_32_H
#define _ASM_ASMMACRO_32_H
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_single thread tmp=t0
.set push
.set hardfloat
cfc1 \tmp, fcr31
s.d $f0, THREAD_FPR0(\thread)
s.d $f2, THREAD_FPR2(\thread)
s.d $f4, THREAD_FPR4(\thread)
s.d $f6, THREAD_FPR6(\thread)
s.d $f8, THREAD_FPR8(\thread)
s.d $f10, THREAD_FPR10(\thread)
s.d $f12, THREAD_FPR12(\thread)
s.d $f14, THREAD_FPR14(\thread)
s.d $f16, THREAD_FPR16(\thread)
s.d $f18, THREAD_FPR18(\thread)
s.d $f20, THREAD_FPR20(\thread)
s.d $f22, THREAD_FPR22(\thread)
s.d $f24, THREAD_FPR24(\thread)
s.d $f26, THREAD_FPR26(\thread)
s.d $f28, THREAD_FPR28(\thread)
s.d $f30, THREAD_FPR30(\thread)
sw \tmp, THREAD_FCR31(\thread)
.set pop
.endm
.macro fpu_restore_single thread tmp=t0
.set push
.set hardfloat
lw \tmp, THREAD_FCR31(\thread)
l.d $f0, THREAD_FPR0(\thread)
l.d $f2, THREAD_FPR2(\thread)
l.d $f4, THREAD_FPR4(\thread)
l.d $f6, THREAD_FPR6(\thread)
l.d $f8, THREAD_FPR8(\thread)
l.d $f10, THREAD_FPR10(\thread)
l.d $f12, THREAD_FPR12(\thread)
l.d $f14, THREAD_FPR14(\thread)
l.d $f16, THREAD_FPR16(\thread)
l.d $f18, THREAD_FPR18(\thread)
l.d $f20, THREAD_FPR20(\thread)
l.d $f22, THREAD_FPR22(\thread)
l.d $f24, THREAD_FPR24(\thread)
l.d $f26, THREAD_FPR26(\thread)
l.d $f28, THREAD_FPR28(\thread)
l.d $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.set pop
.endm
.macro cpu_save_nonscratch thread
LONG_S s0, THREAD_REG16(\thread)
LONG_S s1, THREAD_REG17(\thread)
LONG_S s2, THREAD_REG18(\thread)
LONG_S s3, THREAD_REG19(\thread)
LONG_S s4, THREAD_REG20(\thread)
LONG_S s5, THREAD_REG21(\thread)
LONG_S s6, THREAD_REG22(\thread)
LONG_S s7, THREAD_REG23(\thread)
LONG_S sp, THREAD_REG29(\thread)
LONG_S fp, THREAD_REG30(\thread)
.endm
.macro cpu_restore_nonscratch thread
LONG_L s0, THREAD_REG16(\thread)
LONG_L s1, THREAD_REG17(\thread)
LONG_L s2, THREAD_REG18(\thread)
LONG_L s3, THREAD_REG19(\thread)
LONG_L s4, THREAD_REG20(\thread)
LONG_L s5, THREAD_REG21(\thread)
LONG_L s6, THREAD_REG22(\thread)
LONG_L s7, THREAD_REG23(\thread)
LONG_L sp, THREAD_REG29(\thread)
LONG_L fp, THREAD_REG30(\thread)
LONG_L ra, THREAD_REG31(\thread)
.endm
#endif /* _ASM_ASMMACRO_32_H */
linux-7.2.3/arch/mips/include/asm/asmmacro-64.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* asmmacro.h: Assembler macros to make things easier to read.
*
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
* Copyright (C) 1998, 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_ASMMACRO_64_H
#define _ASM_ASMMACRO_64_H
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro cpu_save_nonscratch thread
LONG_S s0, THREAD_REG16(\thread)
LONG_S s1, THREAD_REG17(\thread)
LONG_S s2, THREAD_REG18(\thread)
LONG_S s3, THREAD_REG19(\thread)
LONG_S s4, THREAD_REG20(\thread)
LONG_S s5, THREAD_REG21(\thread)
LONG_S s6, THREAD_REG22(\thread)
LONG_S s7, THREAD_REG23(\thread)
LONG_S sp, THREAD_REG29(\thread)
LONG_S fp, THREAD_REG30(\thread)
.endm
.macro cpu_restore_nonscratch thread
LONG_L s0, THREAD_REG16(\thread)
LONG_L s1, THREAD_REG17(\thread)
LONG_L s2, THREAD_REG18(\thread)
LONG_L s3, THREAD_REG19(\thread)
LONG_L s4, THREAD_REG20(\thread)
LONG_L s5, THREAD_REG21(\thread)
LONG_L s6, THREAD_REG22(\thread)
LONG_L s7, THREAD_REG23(\thread)
LONG_L sp, THREAD_REG29(\thread)
LONG_L fp, THREAD_REG30(\thread)
LONG_L ra, THREAD_REG31(\thread)
.endm
#endif /* _ASM_ASMMACRO_64_H */
linux-7.2.3/arch/mips/include/asm/asmmacro.h
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@@ -0,0 +1,664 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
*/
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H
#include <asm/hazards.h>
#include <asm/asm-offsets.h>
#include <asm/msa.h>
#ifdef CONFIG_32BIT
#include <asm/asmmacro-32.h>
#endif
#ifdef CONFIG_64BIT
#include <asm/asmmacro-64.h>
#endif
/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
#undef fp
/*
* Helper macros for generating raw instruction encodings.
*/
#ifdef CONFIG_CPU_MICROMIPS
.macro insn32_if_mm enc
.insn
.hword ((\enc) >> 16)
.hword ((\enc) & 0xffff)
.endm
.macro insn_if_mips enc
.endm
#else
.macro insn32_if_mm enc
.endm
.macro insn_if_mips enc
.insn
.word (\enc)
.endm
#endif
#ifdef CONFIG_CPU_HAS_DIEI
.macro local_irq_enable
ei
irq_enable_hazard
.endm
.macro local_irq_disable
di
irq_disable_hazard
.endm
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
mtc0 \reg, CP0_STATUS
irq_enable_hazard
.endm
.macro local_irq_disable reg=t0
#ifdef CONFIG_PREEMPTION
lw \reg, TI_PRE_COUNT($28)
addi \reg, \reg, 1
sw \reg, TI_PRE_COUNT($28)
#endif
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
xori \reg, \reg, 1
mtc0 \reg, CP0_STATUS
irq_disable_hazard
#ifdef CONFIG_PREEMPTION
lw \reg, TI_PRE_COUNT($28)
addi \reg, \reg, -1
sw \reg, TI_PRE_COUNT($28)
#endif
.endm
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro fpu_save_16even thread tmp=t0
.set push
.set hardfloat
cfc1 \tmp, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
sdc1 $f4, THREAD_FPR4(\thread)
sdc1 $f6, THREAD_FPR6(\thread)
sdc1 $f8, THREAD_FPR8(\thread)
sdc1 $f10, THREAD_FPR10(\thread)
sdc1 $f12, THREAD_FPR12(\thread)
sdc1 $f14, THREAD_FPR14(\thread)
sdc1 $f16, THREAD_FPR16(\thread)
sdc1 $f18, THREAD_FPR18(\thread)
sdc1 $f20, THREAD_FPR20(\thread)
sdc1 $f22, THREAD_FPR22(\thread)
sdc1 $f24, THREAD_FPR24(\thread)
sdc1 $f26, THREAD_FPR26(\thread)
sdc1 $f28, THREAD_FPR28(\thread)
sdc1 $f30, THREAD_FPR30(\thread)
sw \tmp, THREAD_FCR31(\thread)
.set pop
.endm
.macro fpu_save_16odd thread
.set push
.set mips64r2
.set fp=64
.set hardfloat
sdc1 $f1, THREAD_FPR1(\thread)
sdc1 $f3, THREAD_FPR3(\thread)
sdc1 $f5, THREAD_FPR5(\thread)
sdc1 $f7, THREAD_FPR7(\thread)
sdc1 $f9, THREAD_FPR9(\thread)
sdc1 $f11, THREAD_FPR11(\thread)
sdc1 $f13, THREAD_FPR13(\thread)
sdc1 $f15, THREAD_FPR15(\thread)
sdc1 $f17, THREAD_FPR17(\thread)
sdc1 $f19, THREAD_FPR19(\thread)
sdc1 $f21, THREAD_FPR21(\thread)
sdc1 $f23, THREAD_FPR23(\thread)
sdc1 $f25, THREAD_FPR25(\thread)
sdc1 $f27, THREAD_FPR27(\thread)
sdc1 $f29, THREAD_FPR29(\thread)
sdc1 $f31, THREAD_FPR31(\thread)
.set pop
.endm
.macro fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
sll \tmp, \status, 5
bgez \tmp, 10f
fpu_save_16odd \thread
10:
#endif
fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
.set push
.set hardfloat
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
ldc1 $f4, THREAD_FPR4(\thread)
ldc1 $f6, THREAD_FPR6(\thread)
ldc1 $f8, THREAD_FPR8(\thread)
ldc1 $f10, THREAD_FPR10(\thread)
ldc1 $f12, THREAD_FPR12(\thread)
ldc1 $f14, THREAD_FPR14(\thread)
ldc1 $f16, THREAD_FPR16(\thread)
ldc1 $f18, THREAD_FPR18(\thread)
ldc1 $f20, THREAD_FPR20(\thread)
ldc1 $f22, THREAD_FPR22(\thread)
ldc1 $f24, THREAD_FPR24(\thread)
ldc1 $f26, THREAD_FPR26(\thread)
ldc1 $f28, THREAD_FPR28(\thread)
ldc1 $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.set pop
.endm
.macro fpu_restore_16odd thread
.set push
.set mips64r2
.set fp=64
.set hardfloat
ldc1 $f1, THREAD_FPR1(\thread)
ldc1 $f3, THREAD_FPR3(\thread)
ldc1 $f5, THREAD_FPR5(\thread)
ldc1 $f7, THREAD_FPR7(\thread)
ldc1 $f9, THREAD_FPR9(\thread)
ldc1 $f11, THREAD_FPR11(\thread)
ldc1 $f13, THREAD_FPR13(\thread)
ldc1 $f15, THREAD_FPR15(\thread)
ldc1 $f17, THREAD_FPR17(\thread)
ldc1 $f19, THREAD_FPR19(\thread)
ldc1 $f21, THREAD_FPR21(\thread)
ldc1 $f23, THREAD_FPR23(\thread)
ldc1 $f25, THREAD_FPR25(\thread)
ldc1 $f27, THREAD_FPR27(\thread)
ldc1 $f29, THREAD_FPR29(\thread)
ldc1 $f31, THREAD_FPR31(\thread)
.set pop
.endm
.macro fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
sll \tmp, \status, 5
bgez \tmp, 10f # 16 register mode?
fpu_restore_16odd \thread
10:
#endif
fpu_restore_16even \thread \tmp
.endm
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
.macro _EXT rd, rs, p, s
ext \rd, \rs, \p, \s
.endm
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
.macro _EXT rd, rs, p, s
srl \rd, \rs, \p
andi \rd, \rd, (1 << \s) - 1
.endm
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
/*
* Temporary until all gas have MT ASE support
*/
.macro DMT reg=0
insn_if_mips 0x41600bc1 | (\reg << 16)
insn32_if_mm 0x0000057C | (\reg << 21)
.endm
.macro EMT reg=0
insn_if_mips 0x41600be1 | (\reg << 16)
insn32_if_mm 0x0000257C | (\reg << 21)
.endm
.macro DVPE reg=0
insn_if_mips 0x41600001 | (\reg << 16)
insn32_if_mm 0x0000157C | (\reg << 21)
.endm
.macro EVPE reg=0
insn_if_mips 0x41600021 | (\reg << 16)
insn32_if_mm 0x0000357C | (\reg << 21)
.endm
.macro MFTR rs=0, rt=0, u=0, sel=0
insn_if_mips 0x41000000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
insn32_if_mm 0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
.endm
.macro MTTR rt=0, rs=0, u=0, sel=0
insn_if_mips 0x41800000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
insn32_if_mm 0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
.endm
#ifdef TOOLCHAIN_SUPPORTS_MSA
.macro _cfcmsa rd, cs
.set push
.set mips32r2
.set fp=64
.set msa
cfcmsa \rd, $\cs
.set pop
.endm
.macro _ctcmsa cd, rs
.set push
.set mips32r2
.set fp=64
.set msa
ctcmsa $\cd, \rs
.set pop
.endm
.macro ld_b wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
ld.b $w\wd, \off(\base)
.set pop
.endm
.macro ld_h wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
ld.h $w\wd, \off(\base)
.set pop
.endm
.macro ld_w wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
ld.w $w\wd, \off(\base)
.set pop
.endm
.macro ld_d wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
ld.d $w\wd, \off(\base)
.set pop
.endm
.macro st_b wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
st.b $w\wd, \off(\base)
.set pop
.endm
.macro st_h wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
st.h $w\wd, \off(\base)
.set pop
.endm
.macro st_w wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
st.w $w\wd, \off(\base)
.set pop
.endm
.macro st_d wd, off, base
.set push
.set mips32r2
.set fp=64
.set msa
st.d $w\wd, \off(\base)
.set pop
.endm
.macro copy_s_w ws, n
.set push
.set mips32r2
.set fp=64
.set msa
copy_s.w $1, $w\ws[\n]
.set pop
.endm
.macro copy_s_d ws, n
.set push
.set mips64r2
.set fp=64
.set msa
copy_s.d $1, $w\ws[\n]
.set pop
.endm
.macro insert_w wd, n
.set push
.set mips32r2
.set fp=64
.set msa
insert.w $w\wd[\n], $1
.set pop
.endm
.macro insert_d wd, n
.set push
.set mips64r2
.set fp=64
.set msa
insert.d $w\wd[\n], $1
.set pop
.endm
#else
/*
* Temporary until all toolchains in use include MSA support.
*/
.macro _cfcmsa rd, cs
.set push
.set noat
.set hardfloat
insn_if_mips 0x787e0059 | (\cs << 11)
insn32_if_mm 0x587e0056 | (\cs << 11)
move \rd, $1
.set pop
.endm
.macro _ctcmsa cd, rs
.set push
.set noat
.set hardfloat
move $1, \rs
insn_if_mips 0x783e0819 | (\cd << 6)
insn32_if_mm 0x583e0816 | (\cd << 6)
.set pop
.endm
.macro ld_b wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000820 | (\wd << 6)
insn32_if_mm 0x58000807 | (\wd << 6)
.set pop
.endm
.macro ld_h wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000821 | (\wd << 6)
insn32_if_mm 0x58000817 | (\wd << 6)
.set pop
.endm
.macro ld_w wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000822 | (\wd << 6)
insn32_if_mm 0x58000827 | (\wd << 6)
.set pop
.endm
.macro ld_d wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000823 | (\wd << 6)
insn32_if_mm 0x58000837 | (\wd << 6)
.set pop
.endm
.macro st_b wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000824 | (\wd << 6)
insn32_if_mm 0x5800080f | (\wd << 6)
.set pop
.endm
.macro st_h wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000825 | (\wd << 6)
insn32_if_mm 0x5800081f | (\wd << 6)
.set pop
.endm
.macro st_w wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000826 | (\wd << 6)
insn32_if_mm 0x5800082f | (\wd << 6)
.set pop
.endm
.macro st_d wd, off, base
.set push
.set noat
.set hardfloat
PTR_ADDU $1, \base, \off
insn_if_mips 0x78000827 | (\wd << 6)
insn32_if_mm 0x5800083f | (\wd << 6)
.set pop
.endm
.macro copy_s_w ws, n
.set push
.set noat
.set hardfloat
insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
.set pop
.endm
.macro copy_s_d ws, n
.set push
.set noat
.set hardfloat
insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
.set pop
.endm
.macro insert_w wd, n
.set push
.set noat
.set hardfloat
insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
.set pop
.endm
.macro insert_d wd, n
.set push
.set noat
.set hardfloat
insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
.set pop
.endm
#endif
#ifdef TOOLCHAIN_SUPPORTS_MSA
#define FPR_BASE_OFFS THREAD_FPR0
#define FPR_BASE $1
#else
#define FPR_BASE_OFFS 0
#define FPR_BASE \thread
#endif
.macro msa_save_all thread
.set push
.set noat
#ifdef TOOLCHAIN_SUPPORTS_MSA
PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
.set hardfloat
_cfcmsa $1, MSA_CSR
sw $1, THREAD_MSA_CSR(\thread)
.set pop
.endm
.macro msa_restore_all thread
.set push
.set noat
.set hardfloat
lw $1, THREAD_MSA_CSR(\thread)
_ctcmsa MSA_CSR, $1
#ifdef TOOLCHAIN_SUPPORTS_MSA
PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
.set pop
.endm
#undef FPR_BASE_OFFS
#undef FPR_BASE
.macro msa_init_upper wd
#ifdef CONFIG_64BIT
insert_d \wd, 1
#else
insert_w \wd, 2
insert_w \wd, 3
#endif
.endm
.macro msa_init_all_upper
.set push
.set noat
.set hardfloat
not $1, zero
msa_init_upper 0
msa_init_upper 1
msa_init_upper 2
msa_init_upper 3
msa_init_upper 4
msa_init_upper 5
msa_init_upper 6
msa_init_upper 7
msa_init_upper 8
msa_init_upper 9
msa_init_upper 10
msa_init_upper 11
msa_init_upper 12
msa_init_upper 13
msa_init_upper 14
msa_init_upper 15
msa_init_upper 16
msa_init_upper 17
msa_init_upper 18
msa_init_upper 19
msa_init_upper 20
msa_init_upper 21
msa_init_upper 22
msa_init_upper 23
msa_init_upper 24
msa_init_upper 25
msa_init_upper 26
msa_init_upper 27
msa_init_upper 28
msa_init_upper 29
msa_init_upper 30
msa_init_upper 31
.set pop
.endm
#endif /* _ASM_ASMMACRO_H */
linux-7.2.3/arch/mips/include/asm/atomic.h
+258
View File
@@ -0,0 +1,258 @@
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*
* But use these as seldom as possible since they are much more slower
* than regular operations.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
*/
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H
#include <linux/irqflags.h>
#include <linux/types.h>
#include <asm/asm.h>
#include <asm/barrier.h>
#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/cmpxchg.h>
#include <asm/sync.h>
#define ATOMIC_OPS(pfx, type) \
static __always_inline type arch_##pfx##_read(const pfx##_t *v) \
{ \
return READ_ONCE(v->counter); \
} \
\
static __always_inline void arch_##pfx##_set(pfx##_t *v, type i) \
{ \
WRITE_ONCE(v->counter, i); \
} \
ATOMIC_OPS(atomic, int)
#ifdef CONFIG_64BIT
# define ATOMIC64_INIT(i) { (i) }
ATOMIC_OPS(atomic64, s64)
#endif
#define ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
static __inline__ void arch_##pfx##_##op(type i, pfx##_t * v) \
{ \
type temp; \
\
if (!kernel_uses_llsc) { \
unsigned long flags; \
\
raw_local_irq_save(flags); \
v->counter c_op i; \
raw_local_irq_restore(flags); \
return; \
} \
\
__asm__ __volatile__( \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " #ll " %0, %1 # " #pfx "_" #op " \n" \
" " #asm_op " %0, %2 \n" \
" " #sc " %0, %1 \n" \
"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
" .set pop \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i) : __LLSC_CLOBBER); \
}
#define ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
static __inline__ type \
arch_##pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
{ \
type temp, result; \
\
if (!kernel_uses_llsc) { \
unsigned long flags; \
\
raw_local_irq_save(flags); \
result = v->counter; \
result c_op i; \
v->counter = result; \
raw_local_irq_restore(flags); \
return result; \
} \
\
__asm__ __volatile__( \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " #ll " %1, %2 # " #pfx "_" #op "_return\n" \
" " #asm_op " %0, %1, %3 \n" \
" " #sc " %0, %2 \n" \
"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
" .set pop \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i) : __LLSC_CLOBBER); \
\
return result; \
}
#define ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc) \
static __inline__ type \
arch_##pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
{ \
int temp, result; \
\
if (!kernel_uses_llsc) { \
unsigned long flags; \
\
raw_local_irq_save(flags); \
result = v->counter; \
v->counter c_op i; \
raw_local_irq_restore(flags); \
return result; \
} \
\
__asm__ __volatile__( \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " #ll " %1, %2 # " #pfx "_fetch_" #op "\n" \
" " #asm_op " %0, %1, %3 \n" \
" " #sc " %0, %2 \n" \
"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
" .set pop \n" \
" move %0, %1 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i) : __LLSC_CLOBBER); \
\
return result; \
}
#undef ATOMIC_OPS
#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
ATOMIC_OPS(atomic, add, int, +=, addu, ll, sc)
ATOMIC_OPS(atomic, sub, int, -=, subu, ll, sc)
#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
#ifdef CONFIG_64BIT
ATOMIC_OPS(atomic64, add, s64, +=, daddu, lld, scd)
ATOMIC_OPS(atomic64, sub, s64, -=, dsubu, lld, scd)
# define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
# define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
# define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
# define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
#endif /* CONFIG_64BIT */
#undef ATOMIC_OPS
#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
ATOMIC_OPS(atomic, and, int, &=, and, ll, sc)
ATOMIC_OPS(atomic, or, int, |=, or, ll, sc)
ATOMIC_OPS(atomic, xor, int, ^=, xor, ll, sc)
#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
#ifdef CONFIG_64BIT
ATOMIC_OPS(atomic64, and, s64, &=, and, lld, scd)
ATOMIC_OPS(atomic64, or, s64, |=, or, lld, scd)
ATOMIC_OPS(atomic64, xor, s64, ^=, xor, lld, scd)
# define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
# define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
# define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
#endif
#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP
/*
* atomic_sub_if_positive - conditionally subtract integer from atomic variable
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
* Atomically test @v and subtract @i if @v is greater or equal than @i.
* The function returns the old value of @v minus @i.
*/
#define ATOMIC_SIP_OP(pfx, type, op, ll, sc) \
static __inline__ type arch_##pfx##_sub_if_positive(type i, pfx##_t * v) \
{ \
type temp, result; \
\
smp_mb__before_atomic(); \
\
if (!kernel_uses_llsc) { \
unsigned long flags; \
\
raw_local_irq_save(flags); \
result = v->counter; \
result -= i; \
if (result >= 0) \
v->counter = result; \
raw_local_irq_restore(flags); \
smp_mb__after_atomic(); \
return result; \
} \
\
__asm__ __volatile__( \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " #ll " %1, %2 # atomic_sub_if_positive\n" \
" .set pop \n" \
" " #op " %0, %1, %3 \n" \
" move %1, %0 \n" \
" bltz %0, 2f \n" \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " #sc " %1, %2 \n" \
" " __stringify(SC_BEQZ) " %1, 1b \n" \
"2: " __SYNC(full, loongson3_war) " \n" \
" .set pop \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i) \
: __LLSC_CLOBBER); \
\
/* \
* In the Loongson3 workaround case we already have a \
* completion barrier at 2: above, which is needed due to the \
* bltz that can branch to code outside of the LL/SC loop. As \
* such, we don't need to emit another barrier here. \
*/ \
if (__SYNC_loongson3_war == 0) \
smp_mb__after_atomic(); \
\
return result; \
}
ATOMIC_SIP_OP(atomic, int, subu, ll, sc)
#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(1, v)
#ifdef CONFIG_64BIT
ATOMIC_SIP_OP(atomic64, s64, dsubu, lld, scd)
#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(1, v)
#endif
#undef ATOMIC_SIP_OP
#endif /* _ASM_ATOMIC_H */
linux-7.2.3/arch/mips/include/asm/barrier.h
+142
View File
@@ -0,0 +1,142 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H
#include <asm/addrspace.h>
#include <asm/sync.h>
static inline void __sync(void)
{
asm volatile(__SYNC(full, always) ::: "memory");
}
static inline void rmb(void)
{
asm volatile(__SYNC(rmb, always) ::: "memory");
}
#define rmb rmb
static inline void wmb(void)
{
asm volatile(__SYNC(wmb, always) ::: "memory");
}
#define wmb wmb
#define fast_mb() __sync()
#define __fast_iob() \
__asm__ __volatile__( \
".set push\n\t" \
".set noreorder\n\t" \
"lw $0,%0\n\t" \
"nop\n\t" \
".set pop" \
: /* no output */ \
: "m" (*(int *)CKSEG1) \
: "memory")
#ifdef CONFIG_CPU_CAVIUM_OCTEON
# define fast_iob() do { } while (0)
#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
# ifdef CONFIG_SGI_IP28
# define fast_iob() \
__asm__ __volatile__( \
".set push\n\t" \
".set noreorder\n\t" \
"lw $0,%0\n\t" \
"sync\n\t" \
"lw $0,%0\n\t" \
".set pop" \
: /* no output */ \
: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
: "memory")
# else
# define fast_iob() \
do { \
__sync(); \
__fast_iob(); \
} while (0)
# endif
#endif /* CONFIG_CPU_CAVIUM_OCTEON */
#ifdef CONFIG_CPU_HAS_WB
#include <asm/wbflush.h>
#define mb() wbflush()
#define iob() wbflush()
#else /* !CONFIG_CPU_HAS_WB */
#define mb() fast_mb()
#define iob() fast_iob()
#endif /* !CONFIG_CPU_HAS_WB */
#if defined(CONFIG_WEAK_ORDERING)
# define __smp_mb() __sync()
# define __smp_rmb() rmb()
# define __smp_wmb() wmb()
#else
# define __smp_mb() barrier()
# define __smp_rmb() barrier()
# define __smp_wmb() barrier()
#endif
/*
* When LL/SC does imply order, it must also be a compiler barrier to avoid the
* compiler from reordering where the CPU will not. When it does not imply
* order, the compiler is also free to reorder across the LL/SC loop and
* ordering will be done by smp_llsc_mb() and friends.
*/
#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
# define __WEAK_LLSC_MB sync
# define smp_llsc_mb() \
__asm__ __volatile__(__stringify(__WEAK_LLSC_MB) : : :"memory")
# define __LLSC_CLOBBER
#else
# define __WEAK_LLSC_MB
# define smp_llsc_mb() do { } while (0)
# define __LLSC_CLOBBER "memory"
#endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define smp_mb__before_llsc() smp_wmb()
#define __smp_mb__before_llsc() __smp_wmb()
/* Cause previous writes to become visible on all CPUs as soon as possible */
#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
".set arch=octeon\n\t" \
"syncw\n\t" \
".set pop" : : : "memory")
#else
#define smp_mb__before_llsc() smp_llsc_mb()
#define __smp_mb__before_llsc() smp_llsc_mb()
#define nudge_writes() mb()
#endif
/*
* In the Loongson3 LL/SC workaround case, all of our LL/SC loops already have
* a completion barrier immediately preceding the LL instruction. Therefore we
* can skip emitting a barrier from __smp_mb__before_atomic().
*/
#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
# define __smp_mb__before_atomic()
#else
# define __smp_mb__before_atomic() __smp_mb__before_llsc()
#endif
#define __smp_mb__after_atomic() smp_llsc_mb()
static inline void sync_ginv(void)
{
asm volatile(__SYNC(ginv, always));
}
#include <asm-generic/barrier.h>
#endif /* __ASM_BARRIER_H */
linux-7.2.3/arch/mips/include/asm/bcache.h
+87
View File
@@ -0,0 +1,87 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1997, 1999 by Ralf Baechle
* Copyright (c) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_BCACHE_H
#define _ASM_BCACHE_H
#include <linux/types.h>
/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
chipset implemented caches. On machines with other CPUs the CPU does the
cache thing itself. */
struct bcache_ops {
void (*bc_enable)(void);
void (*bc_disable)(void);
void (*bc_wback_inv)(unsigned long page, unsigned long size);
void (*bc_inv)(unsigned long page, unsigned long size);
void (*bc_prefetch_enable)(void);
void (*bc_prefetch_disable)(void);
bool (*bc_prefetch_is_enabled)(void);
};
extern void indy_sc_init(void);
#ifdef CONFIG_BOARD_SCACHE
extern struct bcache_ops *bcops;
static inline void bc_enable(void)
{
bcops->bc_enable();
}
static inline void bc_disable(void)
{
bcops->bc_disable();
}
static inline void bc_wback_inv(unsigned long page, unsigned long size)
{
bcops->bc_wback_inv(page, size);
}
static inline void bc_inv(unsigned long page, unsigned long size)
{
bcops->bc_inv(page, size);
}
static inline void bc_prefetch_enable(void)
{
if (bcops->bc_prefetch_enable)
bcops->bc_prefetch_enable();
}
static inline void bc_prefetch_disable(void)
{
if (bcops->bc_prefetch_disable)
bcops->bc_prefetch_disable();
}
static inline bool bc_prefetch_is_enabled(void)
{
if (bcops->bc_prefetch_is_enabled)
return bcops->bc_prefetch_is_enabled();
return false;
}
#else /* !defined(CONFIG_BOARD_SCACHE) */
/* Not R4000 / R4400 / R4600 / R5000. */
#define bc_enable() do { } while (0)
#define bc_disable() do { } while (0)
#define bc_wback_inv(page, size) do { } while (0)
#define bc_inv(page, size) do { } while (0)
#define bc_prefetch_enable() do { } while (0)
#define bc_prefetch_disable() do { } while (0)
#define bc_prefetch_is_enabled() 0
#endif /* !defined(CONFIG_BOARD_SCACHE) */
#endif /* _ASM_BCACHE_H */
linux-7.2.3/arch/mips/include/asm/bitops.h
+483
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@@ -0,0 +1,483 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
* Copyright (c) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <linux/bits.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/asm.h>
#include <asm/barrier.h>
#include <asm/byteorder.h> /* sigh ... */
#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/sgidefs.h>
#define __bit_op(mem, insn, inputs...) do { \
unsigned long __temp; \
\
asm volatile( \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " __stringify(LONG_LL) " %0, %1 \n" \
" " insn " \n" \
" " __stringify(LONG_SC) " %0, %1 \n" \
" " __stringify(SC_BEQZ) " %0, 1b \n" \
" .set pop \n" \
: "=&r"(__temp), "+" GCC_OFF_SMALL_ASM()(mem) \
: inputs \
: __LLSC_CLOBBER); \
} while (0)
#define __test_bit_op(mem, ll_dst, insn, inputs...) ({ \
unsigned long __orig, __temp; \
\
asm volatile( \
" .set push \n" \
" .set " MIPS_ISA_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " __stringify(LONG_LL) " " ll_dst ", %2\n" \
" " insn " \n" \
" " __stringify(LONG_SC) " %1, %2 \n" \
" " __stringify(SC_BEQZ) " %1, 1b \n" \
" .set pop \n" \
: "=&r"(__orig), "=&r"(__temp), \
"+" GCC_OFF_SMALL_ASM()(mem) \
: inputs \
: __LLSC_CLOBBER); \
\
__orig; \
})
/*
* These are the "slower" versions of the functions and are in bitops.c.
* These functions call raw_local_irq_{save,restore}().
*/
void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
int __mips_test_and_set_bit_lock(unsigned long nr,
volatile unsigned long *addr);
int __mips_test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr);
int __mips_test_and_change_bit(unsigned long nr,
volatile unsigned long *addr);
bool __mips_xor_is_negative_byte(unsigned long mask,
volatile unsigned long *addr);
/*
* set_bit - Atomically set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* This function is atomic and may not be reordered. See __set_bit()
* if you do not require the atomic guarantees.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
{
volatile unsigned long *m = &addr[BIT_WORD(nr)];
int bit = nr % BITS_PER_LONG;
if (!kernel_uses_llsc) {
__mips_set_bit(nr, addr);
return;
}
if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit) && (bit >= 16)) {
__bit_op(*m, __stringify(LONG_INS) " %0, %3, %2, 1", "i"(bit), "r"(~0));
return;
}
__bit_op(*m, "or\t%0, %2", "ir"(BIT(bit)));
}
/*
* clear_bit - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* clear_bit() is atomic and may not be reordered. However, it does
* not contain a memory barrier, so if it is used for locking purposes,
* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
* in order to ensure changes are visible on other processors.
*/
static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
{
volatile unsigned long *m = &addr[BIT_WORD(nr)];
int bit = nr % BITS_PER_LONG;
if (!kernel_uses_llsc) {
__mips_clear_bit(nr, addr);
return;
}
if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit)) {
__bit_op(*m, __stringify(LONG_INS) " %0, $0, %2, 1", "i"(bit));
return;
}
__bit_op(*m, "and\t%0, %2", "ir"(~BIT(bit)));
}
/*
* clear_bit_unlock - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* clear_bit() is atomic and implies release semantics before the memory
* operation. It can be used for an unlock.
*/
static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
{
smp_mb__before_atomic();
clear_bit(nr, addr);
}
/*
* change_bit - Toggle a bit in memory
* @nr: Bit to change
* @addr: Address to start counting from
*
* change_bit() is atomic and may not be reordered.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
{
volatile unsigned long *m = &addr[BIT_WORD(nr)];
int bit = nr % BITS_PER_LONG;
if (!kernel_uses_llsc) {
__mips_change_bit(nr, addr);
return;
}
__bit_op(*m, "xor\t%0, %2", "ir"(BIT(bit)));
}
/*
* test_and_set_bit_lock - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and implies acquire ordering semantics
* after the memory operation.
*/
static inline int test_and_set_bit_lock(unsigned long nr,
volatile unsigned long *addr)
{
volatile unsigned long *m = &addr[BIT_WORD(nr)];
int bit = nr % BITS_PER_LONG;
unsigned long res, orig;
if (!kernel_uses_llsc) {
res = __mips_test_and_set_bit_lock(nr, addr);
} else {
orig = __test_bit_op(*m, "%0",
"or\t%1, %0, %3",
"ir"(BIT(bit)));
res = (orig & BIT(bit)) != 0;
}
smp_llsc_mb();
return res;
}
/*
* test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
smp_mb__before_atomic();
return test_and_set_bit_lock(nr, addr);
}
/*
* test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
volatile unsigned long *m = &addr[BIT_WORD(nr)];
int bit = nr % BITS_PER_LONG;
unsigned long res, orig;
smp_mb__before_atomic();
if (!kernel_uses_llsc) {
res = __mips_test_and_clear_bit(nr, addr);
} else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
res = __test_bit_op(*m, "%1",
__stringify(LONG_EXT) " %0, %1, %3, 1;"
__stringify(LONG_INS) " %1, $0, %3, 1",
"i"(bit));
} else {
orig = __test_bit_op(*m, "%0",
"or\t%1, %0, %3;"
"xor\t%1, %1, %3",
"ir"(BIT(bit)));
res = (orig & BIT(bit)) != 0;
}
smp_llsc_mb();
return res;
}
/*
* test_and_change_bit - Change a bit and return its old value
* @nr: Bit to change
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
volatile unsigned long *m = &addr[BIT_WORD(nr)];
int bit = nr % BITS_PER_LONG;
unsigned long res, orig;
smp_mb__before_atomic();
if (!kernel_uses_llsc) {
res = __mips_test_and_change_bit(nr, addr);
} else {
orig = __test_bit_op(*m, "%0",
"xor\t%1, %0, %3",
"ir"(BIT(bit)));
res = (orig & BIT(bit)) != 0;
}
smp_llsc_mb();
return res;
}
static inline bool xor_unlock_is_negative_byte(unsigned long mask,
volatile unsigned long *p)
{
unsigned long orig;
bool res;
smp_mb__before_atomic();
if (!kernel_uses_llsc) {
res = __mips_xor_is_negative_byte(mask, p);
} else {
orig = __test_bit_op(*p, "%0",
"xor\t%1, %0, %3",
"ir"(mask));
res = (orig & BIT(7)) != 0;
}
smp_llsc_mb();
return res;
}
#undef __bit_op
#undef __test_bit_op
#include <asm-generic/bitops/non-atomic.h>
/*
* __clear_bit_unlock - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* __clear_bit() is non-atomic and implies release semantics before the memory
* operation. It can be used for an unlock if no other CPUs can concurrently
* modify other bits in the word.
*/
static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
{
smp_mb__before_llsc();
__clear_bit(nr, addr);
nudge_writes();
}
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
static __always_inline __attribute_const__ unsigned long __fls(unsigned long word)
{
int num;
if (BITS_PER_LONG == 32 && !__builtin_constant_p(word) &&
__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
__asm__(
" .set push \n"
" .set "MIPS_ISA_LEVEL" \n"
" clz %0, %1 \n"
" .set pop \n"
: "=r" (num)
: "r" (word));
return 31 - num;
}
if (BITS_PER_LONG == 64 && !__builtin_constant_p(word) &&
__builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
__asm__(
" .set push \n"
" .set "MIPS_ISA_LEVEL" \n"
" dclz %0, %1 \n"
" .set pop \n"
: "=r" (num)
: "r" (word));
return 63 - num;
}
num = BITS_PER_LONG - 1;
#if BITS_PER_LONG == 64
if (!(word & (~0ul << 32))) {
num -= 32;
word <<= 32;
}
#endif
if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
num -= 16;
word <<= 16;
}
if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
num -= 8;
word <<= 8;
}
if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
num -= 4;
word <<= 4;
}
if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
num -= 2;
word <<= 2;
}
if (!(word & (~0ul << (BITS_PER_LONG-1))))
num -= 1;
return num;
}
/*
* __ffs - find first bit in word.
* @word: The word to search
*
* Returns 0..SZLONG-1
* Undefined if no bit exists, so code should check against 0 first.
*/
static __always_inline __attribute_const__ unsigned long __ffs(unsigned long word)
{
return __fls(word & -word);
}
/*
* fls - find last bit set.
* @word: The word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static inline __attribute_const__ int fls(unsigned int x)
{
int r;
if (!__builtin_constant_p(x) &&
__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
__asm__(
" .set push \n"
" .set "MIPS_ISA_LEVEL" \n"
" clz %0, %1 \n"
" .set pop \n"
: "=r" (x)
: "r" (x));
return 32 - x;
}
r = 32;
if (!x)
return 0;
if (!(x & 0xffff0000u)) {
x <<= 16;
r -= 16;
}
if (!(x & 0xff000000u)) {
x <<= 8;
r -= 8;
}
if (!(x & 0xf0000000u)) {
x <<= 4;
r -= 4;
}
if (!(x & 0xc0000000u)) {
x <<= 2;
r -= 2;
}
if (!(x & 0x80000000u)) {
x <<= 1;
r -= 1;
}
return r;
}
#include <asm-generic/bitops/fls64.h>
/*
* ffs - find first bit set.
* @word: The word to search
*
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the below ffz (man ffs).
*/
static inline __attribute_const__ int ffs(int word)
{
if (!word)
return 0;
return fls(word & -word);
}
#include <asm-generic/bitops/ffz.h>
#ifdef __KERNEL__
#include <asm-generic/bitops/sched.h>
#include <asm/arch_hweight.h>
#include <asm-generic/bitops/const_hweight.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic.h>
#endif /* __KERNEL__ */
#endif /* _ASM_BITOPS_H */
linux-7.2.3/arch/mips/include/asm/bitrev.h
+31
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@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __MIPS_ASM_BITREV_H__
#define __MIPS_ASM_BITREV_H__
#include <linux/swab.h>
static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x)
{
u32 ret;
asm("bitswap %0, %1" : "=r"(ret) : "r"(__swab32(x)));
return ret;
}
static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x)
{
u16 ret;
asm("bitswap %0, %1" : "=r"(ret) : "r"(__swab16(x)));
return ret;
}
static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x)
{
u8 ret;
asm("bitswap %0, %1" : "=r"(ret) : "r"(x));
return ret;
}
#endif /* __MIPS_ASM_BITREV_H__ */
linux-7.2.3/arch/mips/include/asm/bmips-spaces.h
+8
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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_BMIPS_SPACES_H
#define __ASM_BMIPS_SPACES_H
/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
#endif /* __ASM_BMIPS_SPACES_H */
linux-7.2.3/arch/mips/include/asm/bmips.h
+129
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@@ -0,0 +1,129 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
*
* Definitions for BMIPS processors
*/
#ifndef _ASM_BMIPS_H
#define _ASM_BMIPS_H
#include <linux/compiler.h>
#include <linux/linkage.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <asm/hazards.h>
/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
(unsigned long) \
((read_c0_brcm_cbr() >> 18) << 18)))
#define BMIPS_RAC_CONFIG 0x00000000
#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
#define BMIPS_RAC_CONFIG_1 0x00000008
#define BMIPS_L2_CONFIG 0x0000000c
#define BMIPS_LMB_CONTROL 0x0000001c
#define BMIPS_SYSTEM_BASE 0x00000020
#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
#define BMIPS_PERF_CONTROL_0 0x00020004
#define BMIPS_PERF_CONTROL_1 0x00020008
#define BMIPS_PERF_COUNTER_0 0x00020010
#define BMIPS_PERF_COUNTER_1 0x00020014
#define BMIPS_PERF_COUNTER_2 0x00020018
#define BMIPS_PERF_COUNTER_3 0x0002001c
#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
#define BMIPS_NMI_RESET_VEC 0x80000000
#define BMIPS_WARM_RESTART_VEC 0x80000380
#define ZSCM_REG_BASE 0x97000000
#if !defined(__ASSEMBLER__)
#include <linux/cpumask.h>
#include <asm/r4kcache.h>
#include <asm/smp-ops.h>
extern const struct plat_smp_ops bmips43xx_smp_ops;
extern const struct plat_smp_ops bmips5000_smp_ops;
static inline int register_bmips_smp_ops(void)
{
#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
switch (current_cpu_type()) {
case CPU_BMIPS32:
case CPU_BMIPS3300:
return register_up_smp_ops();
case CPU_BMIPS4350:
case CPU_BMIPS4380:
register_smp_ops(&bmips43xx_smp_ops);
break;
case CPU_BMIPS5000:
register_smp_ops(&bmips5000_smp_ops);
break;
default:
return -ENODEV;
}
return 0;
#else
return -ENODEV;
#endif
}
extern char bmips_reset_nmi_vec[];
extern char bmips_reset_nmi_vec_end[];
extern char bmips_smp_movevec[];
extern char bmips_smp_int_vec[];
extern char bmips_smp_int_vec_end[];
extern void __iomem *bmips_cbr_addr;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
extern unsigned long bmips_tp1_irqs;
extern void bmips_ebase_setup(void);
extern asmlinkage void plat_wired_tlb_setup(void);
extern void bmips_cpu_setup(void);
static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
{
unsigned long ret;
barrier();
cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
__sync();
_ssnop();
_ssnop();
_ssnop();
_ssnop();
_ssnop();
_ssnop();
_ssnop();
ret = read_c0_ddatalo();
_ssnop();
return ret;
}
static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
{
write_c0_ddatalo(data);
_ssnop();
_ssnop();
_ssnop();
cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
_ssnop();
_ssnop();
_ssnop();
barrier();
}
#endif /* !defined(__ASSEMBLER__) */
#endif /* _ASM_BMIPS_H */
linux-7.2.3/arch/mips/include/asm/bootinfo.h
+189
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@@ -0,0 +1,189 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 2003 by Ralf Baechle
* Copyright (C) 1995, 1996 Andreas Busse
* Copyright (C) 1995, 1996 Stoned Elipot
* Copyright (C) 1995, 1996 Paul M. Antoine.
* Copyright (C) 2009 Zhang Le
*/
#ifndef _ASM_BOOTINFO_H
#define _ASM_BOOTINFO_H
#include <linux/types.h>
#include <asm/setup.h>
/*
* The MACH_ IDs are sort of equivalent to PCI product IDs. As such the
* numbers do not necessarily reflect technical relations or similarities
* between systems.
*/
/*
* Valid machtype values for group unknown
*/
#define MACH_UNKNOWN 0 /* whatever... */
/*
* Valid machtype for group DEC
*/
#define MACH_DSUNKNOWN 0
#define MACH_DS23100 1 /* DECstation 2100 or 3100 */
#define MACH_DS5100 2 /* DECsystem 5100 */
#define MACH_DS5000_200 3 /* DECstation 5000/200 */
#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */
#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */
#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */
#define MACH_DS5400 7 /* DECsystem 5400 */
#define MACH_DS5500 8 /* DECsystem 5500 */
#define MACH_DS5800 9 /* DECsystem 5800 */
#define MACH_DS5900 10 /* DECsystem 5900 */
/*
* Valid machtype for group Mikrotik
*/
#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
/*
* Valid machtype for Loongson family
*/
enum loongson2ef_machine_type {
MACH_LOONGSON_UNKNOWN,
MACH_LEMOTE_FL2E,
MACH_LEMOTE_FL2F,
MACH_LEMOTE_ML2F7,
MACH_LEMOTE_YL2F89,
MACH_DEXXON_GDIUM2F10,
MACH_LEMOTE_NAS,
MACH_LEMOTE_LL2F,
MACH_LOONGSON_END
};
/*
* Valid machtype for group INGENIC
*/
enum ingenic_machine_type {
MACH_INGENIC_UNKNOWN,
MACH_INGENIC_JZ4720,
MACH_INGENIC_JZ4725,
MACH_INGENIC_JZ4725B,
MACH_INGENIC_JZ4730,
MACH_INGENIC_JZ4740,
MACH_INGENIC_JZ4750,
MACH_INGENIC_JZ4755,
MACH_INGENIC_JZ4760,
MACH_INGENIC_JZ4760B,
MACH_INGENIC_JZ4770,
MACH_INGENIC_JZ4775,
MACH_INGENIC_JZ4780,
MACH_INGENIC_X1000,
MACH_INGENIC_X1000E,
MACH_INGENIC_X1830,
MACH_INGENIC_X2000,
MACH_INGENIC_X2000E,
MACH_INGENIC_X2000H,
MACH_INGENIC_X2100,
};
extern char *system_type;
const char *get_system_type(void);
extern unsigned long mips_machtype;
extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
extern void prom_init(void);
extern void prom_free_prom_memory(void);
extern void prom_cleanup(void);
extern void free_init_pages(const char *what,
unsigned long begin, unsigned long end);
extern void (*free_init_pages_eva)(void *begin, void *end);
/*
* Initial kernel command line, usually setup by prom_init()
*/
extern char arcs_cmdline[COMMAND_LINE_SIZE];
/*
* Registers a0, a1, a2 and a3 as passed to the kernel entry by firmware
*/
extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
#ifdef CONFIG_USE_OF
#include <linux/libfdt.h>
#include <linux/of_fdt.h>
extern char __appended_dtb[];
static inline void *get_fdt(void)
{
if (IS_ENABLED(CONFIG_MIPS_RAW_APPENDED_DTB) ||
IS_ENABLED(CONFIG_MIPS_ELF_APPENDED_DTB))
if (fdt_magic(&__appended_dtb) == FDT_MAGIC)
return &__appended_dtb;
if (fw_arg0 == -2) /* UHI interface */
return (void *)fw_arg1;
if (IS_ENABLED(CONFIG_BUILTIN_DTB))
if (&__dtb_start != &__dtb_end)
return &__dtb_start;
return NULL;
}
#endif
/*
* Platform memory detection hook called by arch_mem_init()
*/
extern void plat_mem_setup(void);
#ifdef CONFIG_SWIOTLB
/*
* Optional platform hook to call swiotlb_setup().
*/
extern void plat_swiotlb_setup(void);
#else
static inline void plat_swiotlb_setup(void) {}
#endif /* CONFIG_SWIOTLB */
#ifdef CONFIG_USE_OF
/**
* plat_get_fdt() - Return a pointer to the platform's device tree blob
*
* This function provides a platform independent API to get a pointer to the
* flattened device tree blob. The interface between bootloader and kernel
* is not consistent across platforms so it is necessary to provide this
* API such that common startup code can locate the FDT.
*
* This is used by the KASLR code to get command line arguments and random
* seed from the device tree. Any platform wishing to use KASLR should
* provide this API and select SYS_SUPPORTS_RELOCATABLE.
*
* Return: Pointer to the flattened device tree blob.
*/
extern void *plat_get_fdt(void);
#ifdef CONFIG_RELOCATABLE
/**
* plat_fdt_relocated() - Update platform's information about relocated dtb
*
* This function provides a platform-independent API to set platform's
* information about relocated DTB if it needs to be moved due to kernel
* relocation occurring at boot.
*/
void plat_fdt_relocated(void *new_location);
#endif /* CONFIG_RELOCATABLE */
#endif /* CONFIG_USE_OF */
#endif /* _ASM_BOOTINFO_H */
linux-7.2.3/arch/mips/include/asm/branch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
*/
#ifndef _ASM_BRANCH_H
#define _ASM_BRANCH_H
#include <asm/cpu-features.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/inst.h>
extern int __isa_exception_epc(struct pt_regs *regs);
extern int __compute_return_epc(struct pt_regs *regs);
extern int __compute_return_epc_for_insn(struct pt_regs *regs,
union mips_instruction insn);
extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
/*
* microMIPS bitfields
*/
#define MM_POOL32A_MINOR_MASK 0x3f
#define MM_POOL32A_MINOR_SHIFT 0x6
#define MM_MIPS32_COND_FC 0x30
int isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc);
extern int __mm_isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc);
static inline int mm_isBranchInstr(struct pt_regs *regs,
struct mm_decoded_insn dec_insn, unsigned long *contpc)
{
if (!cpu_has_mmips)
return 0;
return __mm_isBranchInstr(regs, dec_insn, contpc);
}
static inline int delay_slot(struct pt_regs *regs)
{
return regs->cp0_cause & CAUSEF_BD;
}
static inline void clear_delay_slot(struct pt_regs *regs)
{
regs->cp0_cause &= ~CAUSEF_BD;
}
static inline void set_delay_slot(struct pt_regs *regs)
{
regs->cp0_cause |= CAUSEF_BD;
}
static inline unsigned long exception_epc(struct pt_regs *regs)
{
if (likely(!delay_slot(regs)))
return regs->cp0_epc;
if (get_isa16_mode(regs->cp0_epc))
return __isa_exception_epc(regs);
return regs->cp0_epc + 4;
}
#define BRANCH_LIKELY_TAKEN 0x0001
static inline int compute_return_epc(struct pt_regs *regs)
{
if (get_isa16_mode(regs->cp0_epc)) {
if (cpu_has_mmips)
return __microMIPS_compute_return_epc(regs);
if (cpu_has_mips16)
return __MIPS16e_compute_return_epc(regs);
} else if (!delay_slot(regs)) {
regs->cp0_epc += 4;
return 0;
}
return __compute_return_epc(regs);
}
static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
union mips16e_instruction *inst)
{
if (likely(!delay_slot(regs))) {
if (inst->ri.opcode == MIPS16e_extend_op) {
regs->cp0_epc += 4;
return 0;
}
regs->cp0_epc += 2;
return 0;
}
return __MIPS16e_compute_return_epc(regs);
}
#endif /* _ASM_BRANCH_H */
linux-7.2.3/arch/mips/include/asm/break.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 2003 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef __ASM_BREAK_H
#define __ASM_BREAK_H
#ifdef __UAPI_ASM_BREAK_H
#error "Error: Do not directly include <uapi/asm/break.h>"
#endif
#include <uapi/asm/break.h>
/*
* Break codes used internally to the kernel.
*/
#define BRK_KDB 513 /* Used in KDB_ENTER() */
#define BRK_MEMU 514 /* Used by FPU emulator */
#define BRK_KPROBE_BP 515 /* Kprobe break */
#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
#define BRK_MULOVF 1023 /* Multiply overflow */
#endif /* __ASM_BREAK_H */
linux-7.2.3/arch/mips/include/asm/bug.h
+44
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_BUG_H
#define __ASM_BUG_H
#include <linux/compiler.h>
#include <asm/sgidefs.h>
#ifdef CONFIG_BUG
#include <asm/break.h>
static inline void __noreturn BUG(void)
{
__asm__ __volatile__("break %0" : : "i" (BRK_BUG));
unreachable();
}
#define HAVE_ARCH_BUG
#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
static inline void __BUG_ON(unsigned long condition)
{
if (__builtin_constant_p(condition)) {
if (condition)
BUG();
else
return;
}
__asm__ __volatile__("tne $0, %0, %1"
: : "r" (condition), "i" (BRK_BUG));
}
#define BUG_ON(C) __BUG_ON((unsigned long)(C))
#define HAVE_ARCH_BUG_ON
#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
#endif
#include <asm-generic/bug.h>
#endif /* __ASM_BUG_H */
linux-7.2.3/arch/mips/include/asm/bugs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2007 Maciej W. Rozycki
*/
#ifndef _ASM_BUGS_H
#define _ASM_BUGS_H
#include <linux/bug.h>
#include <linux/smp.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
extern int daddiu_bug;
extern void check_bugs64_early(void);
extern void check_bugs32(void);
extern void check_bugs64(void);
static inline int r4k_daddiu_bug(void)
{
if (!IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
return 0;
WARN_ON(daddiu_bug < 0);
return daddiu_bug != 0;
}
#endif /* _ASM_BUGS_H */
linux-7.2.3/arch/mips/include/asm/cache.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
#include <kmalloc.h>
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define __read_mostly __section(".data..read_mostly")
extern void cache_noop(void);
extern void r3k_cache_init(void);
extern unsigned long r3k_cache_size(unsigned long);
extern unsigned long r3k_cache_lsize(unsigned long);
extern void r4k_cache_init(void);
extern void octeon_cache_init(void);
extern void au1x00_fixup_config_od(void);
#endif /* _ASM_CACHE_H */
linux-7.2.3/arch/mips/include/asm/cacheflush.h
+155
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
*/
#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H
/* Keep includes the same across arches. */
#include <linux/mm.h>
#include <asm/cpu-features.h>
/* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_dup mm(mm) handles cache flushing when forking
* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
* - flush_icache_range(start, end) flush a range of instructions
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
*
* MIPS specific flush operations:
*
* - flush_icache_all() flush the entire instruction cache
* - flush_data_cache_page() flushes a page from the data cache
* - __flush_icache_user_range(start, end) flushes range of user instructions
*/
/*
* This flag is used to indicate that the page pointed to by a pte
* is dirty and requires cleaning before returning it to the user.
*/
#define PG_dcache_dirty PG_arch_1
#define folio_test_dcache_dirty(folio) \
test_bit(PG_dcache_dirty, &(folio)->flags.f)
#define folio_set_dcache_dirty(folio) \
set_bit(PG_dcache_dirty, &(folio)->flags.f)
#define folio_clear_dcache_dirty(folio) \
clear_bit(PG_dcache_dirty, &(folio)->flags.f)
extern void (*flush_cache_all)(void);
extern void (*__flush_cache_all)(void);
extern void (*flush_cache_mm)(struct mm_struct *mm);
#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
extern void (*flush_cache_range)(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
void __flush_dcache_folio_pages(struct folio *folio, struct page *page, unsigned int nr);
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
static inline void flush_dcache_folio(struct folio *folio)
{
if (cpu_has_dc_aliases)
__flush_dcache_folio_pages(folio, folio_page(folio, 0),
folio_nr_pages(folio));
else if (!cpu_has_ic_fills_f_dc)
folio_set_dcache_dirty(folio);
}
#define flush_dcache_folio flush_dcache_folio
static inline void flush_dcache_page(struct page *page)
{
struct folio *folio = page_folio(page);
if (cpu_has_dc_aliases)
__flush_dcache_folio_pages(folio, page, 1);
else if (!cpu_has_ic_fills_f_dc)
folio_set_dcache_dirty(folio);
}
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define ARCH_HAS_FLUSH_ANON_PAGE
extern void __flush_anon_page(struct page *, unsigned long);
static inline void flush_anon_page(struct vm_area_struct *vma,
struct page *page, unsigned long vmaddr)
{
if (cpu_has_dc_aliases && PageAnon(page))
__flush_anon_page(page, vmaddr);
}
extern void (*flush_icache_range)(unsigned long start, unsigned long end);
extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
extern void (*__flush_icache_user_range)(unsigned long start,
unsigned long end);
extern void (*__local_flush_icache_user_range)(unsigned long start,
unsigned long end);
extern void (*__flush_cache_vmap)(void);
static inline void flush_cache_vmap(unsigned long start, unsigned long end)
{
if (cpu_has_dc_aliases)
__flush_cache_vmap();
}
#define flush_cache_vmap_early(start, end) do { } while (0)
extern void (*__flush_cache_vunmap)(void);
static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
{
if (cpu_has_dc_aliases)
__flush_cache_vunmap();
}
extern void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
extern void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
extern void (*flush_icache_all)(void);
extern void (*flush_data_cache_page)(unsigned long addr);
/* Run kernel code uncached, useful for cache probing functions. */
unsigned long run_uncached(void *func);
extern void *kmap_coherent(struct page *page, unsigned long addr);
extern void kunmap_coherent(void);
extern void *kmap_noncoherent(struct page *page, unsigned long addr);
static inline void kunmap_noncoherent(void)
{
kunmap_coherent();
}
#define ARCH_IMPLEMENTS_FLUSH_KERNEL_VMAP_RANGE 1
/*
* For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
* cache writeback and invalidate operation.
*/
extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
static inline void flush_kernel_vmap_range(void *vaddr, int size)
{
if (cpu_has_dc_aliases)
__flush_kernel_vmap_range((unsigned long) vaddr, size);
}
static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
{
if (cpu_has_dc_aliases)
__flush_kernel_vmap_range((unsigned long) vaddr, size);
}
#endif /* _ASM_CACHEFLUSH_H */
linux-7.2.3/arch/mips/include/asm/cacheops.h
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/*
* Cache operations for the cache instruction.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
*/
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
/*
* Most cache ops are split into a 2 bit field identifying the cache, and a 3
* bit field identifying the cache operation.
*/
#define CacheOp_Cache 0x03
#define CacheOp_Op 0x1c
#define Cache_I 0x00
#define Cache_D 0x01
#define Cache_T 0x02
#define Cache_V 0x02 /* Loongson-3 */
#define Cache_S 0x03
#define Index_Writeback_Inv 0x00
#define Index_Load_Tag 0x04
#define Index_Store_Tag 0x08
#define Hit_Invalidate 0x10
#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
#define Hit_Writeback 0x18
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
#define Index_Load_Tag_I (Cache_I | Index_Load_Tag)
#define Index_Load_Tag_D (Cache_D | Index_Load_Tag)
#define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
#define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
/*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D (Cache_D | 0x0c)
#define Fill_I (Cache_I | 0x14)
#define Hit_Writeback_I (Cache_I | Hit_Writeback)
#define Hit_Writeback_D (Cache_D | Hit_Writeback)
/*
* R4000SC and R4400SC-specific cacheops
*/
#define Cache_SI 0x02
#define Cache_SD 0x03
#define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv)
#define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv)
#define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag)
#define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag)
#define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag)
#define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag)
#define Create_Dirty_Excl_SD (Cache_SD | 0x0c)
#define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate)
#define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate)
#define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv)
#define Hit_Writeback_SD (Cache_SD | Hit_Writeback)
#define Hit_Set_Virtual_SI (Cache_SI | 0x1c)
#define Hit_Set_Virtual_SD (Cache_SD | 0x1c)
/*
* R5000-specific cacheops
*/
#define R5K_Page_Invalidate_S (Cache_S | 0x14)
/*
* RM7000-specific cacheops
*/
#define Page_Invalidate_T (Cache_T | 0x14)
#define Index_Store_Tag_T (Cache_T | Index_Store_Tag)
#define Index_Load_Tag_T (Cache_T | Index_Load_Tag)
/*
* R10000-specific cacheops
*
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv)
#define Index_Load_Tag_S (Cache_S | Index_Load_Tag)
#define Index_Store_Tag_S (Cache_S | Index_Store_Tag)
#define Hit_Invalidate_S (Cache_S | Hit_Invalidate)
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv)
#define Index_Load_Data_I (Cache_I | 0x18)
#define Index_Load_Data_D (Cache_D | 0x18)
#define Index_Load_Data_S (Cache_S | 0x18)
#define Index_Store_Data_I (Cache_I | 0x1c)
#define Index_Store_Data_D (Cache_D | 0x1c)
#define Index_Store_Data_S (Cache_S | 0x1c)
/*
* Loongson2-specific cacheops
*/
#define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)
/*
* Loongson3-specific cacheops
*/
#define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv)
#endif /* __ASM_CACHEOPS_H */
linux-7.2.3/arch/mips/include/asm/cachetype.h
+9
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MIPS_CACHETYPE_H
#define __ASM_MIPS_CACHETYPE_H
#include <asm/cpu-features.h>
#define cpu_dcache_is_aliasing() cpu_has_dc_aliases
#endif
linux-7.2.3/arch/mips/include/asm/cdmm.h
+109
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2014 Imagination Technologies Ltd.
*/
#ifndef __ASM_CDMM_H
#define __ASM_CDMM_H
#include <linux/device.h>
#include <linux/device-id/mips_cdmm.h>
/**
* struct mips_cdmm_device - Represents a single device on a CDMM bus.
* @dev: Driver model device object.
* @cpu: CPU which can access this device.
* @res: MMIO resource.
* @type: Device type identifier.
* @rev: Device revision number.
*/
struct mips_cdmm_device {
struct device dev;
unsigned int cpu;
struct resource res;
unsigned int type;
unsigned int rev;
};
/**
* struct mips_cdmm_driver - Represents a driver for a CDMM device.
* @drv: Driver model driver object.
* @probe Callback for probing newly discovered devices.
* @remove: Callback to remove the device.
* @shutdown: Callback on system shutdown.
* @cpu_down: Callback when the parent CPU is going down.
* Any CPU pinned threads/timers should be disabled.
* @cpu_up: Callback when the parent CPU is coming back up again.
* CPU pinned threads/timers can be restarted.
* @id_table: Table for CDMM IDs to match against.
*/
struct mips_cdmm_driver {
struct device_driver drv;
int (*probe)(struct mips_cdmm_device *);
int (*remove)(struct mips_cdmm_device *);
void (*shutdown)(struct mips_cdmm_device *);
int (*cpu_down)(struct mips_cdmm_device *);
int (*cpu_up)(struct mips_cdmm_device *);
const struct mips_cdmm_device_id *id_table;
};
/**
* mips_cdmm_phys_base() - Choose a physical base address for CDMM region.
*
* Picking a suitable physical address at which to map the CDMM region is
* platform specific, so this function can be defined by platform code to
* pick a suitable value if none is configured by the bootloader.
*
* This address must be 32kB aligned, and the region occupies a maximum of 32kB
* of physical address space which must not be used for anything else.
*
* Returns: Physical base address for CDMM region, or 0 on failure.
*/
phys_addr_t mips_cdmm_phys_base(void);
extern const struct bus_type mips_cdmm_bustype;
void __iomem *mips_cdmm_early_probe(unsigned int dev_type);
#define to_mips_cdmm_device(d) container_of(d, struct mips_cdmm_device, dev)
#define mips_cdmm_get_drvdata(d) dev_get_drvdata(&d->dev)
#define mips_cdmm_set_drvdata(d, p) dev_set_drvdata(&d->dev, p)
int mips_cdmm_driver_register(struct mips_cdmm_driver *);
void mips_cdmm_driver_unregister(struct mips_cdmm_driver *);
/*
* module_mips_cdmm_driver() - Helper macro for drivers that don't do
* anything special in module init/exit. This eliminates a lot of
* boilerplate. Each module may only use this macro once, and
* calling it replaces module_init() and module_exit()
*/
#define module_mips_cdmm_driver(__mips_cdmm_driver) \
module_driver(__mips_cdmm_driver, mips_cdmm_driver_register, \
mips_cdmm_driver_unregister)
/*
* builtin_mips_cdmm_driver() - Helper macro for drivers that don't do anything
* special in init and have no exit. This eliminates some boilerplate. Each
* driver may only use this macro once, and calling it replaces device_initcall
* (or in some cases, the legacy __initcall). This is meant to be a direct
* parallel of module_mips_cdmm_driver() above but without the __exit stuff that
* is not used for builtin cases.
*/
#define builtin_mips_cdmm_driver(__mips_cdmm_driver) \
builtin_driver(__mips_cdmm_driver, mips_cdmm_driver_register)
/* drivers/tty/mips_ejtag_fdc.c */
#ifdef CONFIG_MIPS_EJTAG_FDC_EARLYCON
int setup_early_fdc_console(void);
#else
static inline int setup_early_fdc_console(void)
{
return -ENODEV;
}
#endif
#endif /* __ASM_CDMM_H */
linux-7.2.3/arch/mips/include/asm/cevt-r4k.h
+28
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Kevin D. Kissell
*/
/*
* Definitions used for common event timer implementation
* for MIPS 4K-type processors and their MIPS MT variants.
* Avoids unsightly extern declarations in C files.
*/
#ifndef __ASM_CEVT_R4K_H
#define __ASM_CEVT_R4K_H
#include <linux/clockchips.h>
#include <asm/time.h>
DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
void mips_event_handler(struct clock_event_device *dev);
int c0_compare_int_usable(void);
irqreturn_t c0_compare_interrupt(int, void *);
extern int cp0_timer_irq_installed;
#endif /* __ASM_CEVT_R4K_H */
linux-7.2.3/arch/mips/include/asm/checksum.h
+253
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2001 Thiemo Seufer.
* Copyright (C) 2002 Maciej W. Rozycki
* Copyright (C) 2014 Imagination Technologies Ltd.
*/
#ifndef _ASM_CHECKSUM_H
#define _ASM_CHECKSUM_H
#ifdef CONFIG_GENERIC_CSUM
#include <asm-generic/checksum.h>
#else
#include <linux/in6.h>
#include <linux/uaccess.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
__wsum csum_partial(const void *buff, int len, __wsum sum);
__wsum __csum_partial_copy_from_user(const void __user *src, void *dst, int len);
__wsum __csum_partial_copy_to_user(const void *src, void __user *dst, int len);
#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
static inline
__wsum csum_and_copy_from_user(const void __user *src, void *dst, int len)
{
might_fault();
if (!access_ok(src, len))
return 0;
return __csum_partial_copy_from_user(src, dst, len);
}
/*
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
static inline
__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len)
{
might_fault();
if (!access_ok(dst, len))
return 0;
return __csum_partial_copy_to_user(src, dst, len);
}
/*
* the same as csum_partial, but copies from user space (but on MIPS
* we have just one address space, so this is identical to the above)
*/
#define _HAVE_ARCH_CSUM_AND_COPY
__wsum __csum_partial_copy_nocheck(const void *src, void *dst, int len);
static inline __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len)
{
return __csum_partial_copy_nocheck(src, dst, len);
}
/*
* Fold a partial checksum without adding pseudo headers
*/
static inline __sum16 csum_fold(__wsum csum)
{
u32 sum = (__force u32)csum;
sum += (sum << 16);
csum = (__force __wsum)(sum < (__force u32)csum);
sum >>= 16;
sum += (__force u32)csum;
return (__force __sum16)~sum;
}
#define csum_fold csum_fold
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
* By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
* Arnt Gulbrandsen.
*/
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
const unsigned int *word = iph;
const unsigned int *stop = word + ihl;
unsigned int csum;
int carry;
csum = word[0];
csum += word[1];
carry = (csum < word[1]);
csum += carry;
csum += word[2];
carry = (csum < word[2]);
csum += carry;
csum += word[3];
carry = (csum < word[3]);
csum += carry;
word += 4;
do {
csum += *word;
carry = (csum < *word);
csum += carry;
word++;
} while (word != stop);
return csum_fold(csum);
}
#define ip_fast_csum ip_fast_csum
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
__u32 len, __u8 proto,
__wsum isum)
{
const unsigned int sh32 = IS_ENABLED(CONFIG_64BIT) ? 32 : 0;
unsigned long sum = (__force unsigned long)daddr;
unsigned long tmp;
__u32 osum;
tmp = (__force unsigned long)saddr;
sum += tmp;
if (IS_ENABLED(CONFIG_32BIT))
sum += sum < tmp;
/*
* We know PROTO + LEN has the sign bit clear, so cast to a signed
* type to avoid an extraneous zero-extension where TMP is 64-bit.
*/
tmp = (__s32)(proto + len);
tmp <<= IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? 8 : 0;
sum += tmp;
if (IS_ENABLED(CONFIG_32BIT))
sum += sum < tmp;
tmp = (__force unsigned long)isum;
sum += tmp;
if (IS_ENABLED(CONFIG_32BIT)) {
sum += sum < tmp;
osum = sum;
} else if (IS_ENABLED(CONFIG_64BIT)) {
tmp = sum << sh32;
sum += tmp;
osum = sum < tmp;
osum += sum >> sh32;
} else {
BUILD_BUG();
}
return (__force __wsum)osum;
}
#define csum_tcpudp_nofold csum_tcpudp_nofold
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
const struct in6_addr *daddr,
__u32 len, __u8 proto,
__wsum sum)
{
__wsum tmp;
__asm__(
" .set push # csum_ipv6_magic\n"
" .set noreorder \n"
" .set noat \n"
" addu %0, %5 # proto (long in network byte order)\n"
" sltu $1, %0, %5 \n"
" addu %0, $1 \n"
" addu %0, %6 # csum\n"
" sltu $1, %0, %6 \n"
" lw %1, 0(%2) # four words source address\n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 4(%2) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 8(%2) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 12(%2) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 0(%3) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 4(%3) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 8(%3) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" lw %1, 12(%3) \n"
" addu %0, $1 \n"
" addu %0, %1 \n"
" sltu $1, %0, %1 \n"
" addu %0, $1 # Add final carry\n"
" .set pop"
: "=&r" (sum), "=&r" (tmp)
: "r" (saddr), "r" (daddr),
"0" (htonl(len)), "r" (htonl(proto)), "r" (sum)
: "memory");
return csum_fold(sum);
}
#include <asm-generic/checksum.h>
#endif /* CONFIG_GENERIC_CSUM */
#endif /* _ASM_CHECKSUM_H */
linux-7.2.3/arch/mips/include/asm/clocksource.h
+11
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@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Alex Smith <alex.smith@imgtec.com>
*/
#ifndef __ASM_CLOCKSOURCE_H
#define __ASM_CLOCKSOURCE_H
#include <asm/vdso/clocksource.h>
#endif /* __ASM_CLOCKSOURCE_H */
linux-7.2.3/arch/mips/include/asm/cmp.h
+10
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@@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_CMP_H
#define _ASM_CMP_H
/*
* Definitions for CMP multitasking on MIPS cores
*/
struct task_struct;
#endif /* _ASM_CMP_H */
linux-7.2.3/arch/mips/include/asm/cmpxchg.h
+326
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@@ -0,0 +1,326 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_CMPXCHG_H
#define __ASM_CMPXCHG_H
#include <linux/bug.h>
#include <linux/irqflags.h>
#include <asm/asm.h>
#include <asm/compiler.h>
#include <asm/sync.h>
/*
* These functions doesn't exist, so if they are called you'll either:
*
* - Get an error at compile-time due to __compiletime_error, if supported by
* your compiler.
*
* or:
*
* - Get an error at link-time due to the call to the missing function.
*/
extern unsigned long __cmpxchg_called_with_bad_pointer(void)
__compiletime_error("Bad argument size for cmpxchg");
extern unsigned long __cmpxchg64_unsupported(void)
__compiletime_error("cmpxchg64 not available; cpu_has_64bits may be false");
extern unsigned long __xchg_called_with_bad_pointer(void)
__compiletime_error("Bad argument size for xchg");
#define __xchg_asm(ld, st, m, val) \
({ \
__typeof(*(m)) __ret; \
\
if (kernel_uses_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set push \n" \
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " ld " %0, %2 # __xchg_asm \n" \
" .set pop \n" \
" move $1, %z3 \n" \
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
" " st " $1, %1 \n" \
"\t" __stringify(SC_BEQZ) " $1, 1b \n" \
" .set pop \n" \
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
: __LLSC_CLOBBER); \
} else { \
unsigned long __flags; \
\
raw_local_irq_save(__flags); \
__ret = *m; \
*m = val; \
raw_local_irq_restore(__flags); \
} \
\
__ret; \
})
extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
unsigned int size);
static __always_inline
unsigned long __arch_xchg(volatile void *ptr, unsigned long x, int size)
{
switch (size) {
case 1:
case 2:
return __xchg_small(ptr, x, size);
case 4:
return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
case 8:
if (!IS_ENABLED(CONFIG_64BIT))
return __xchg_called_with_bad_pointer();
return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x);
default:
return __xchg_called_with_bad_pointer();
}
}
#define arch_xchg(ptr, x) \
({ \
__typeof__(*(ptr)) __res; \
\
/* \
* In the Loongson3 workaround case __xchg_asm() already \
* contains a completion barrier prior to the LL, so we don't \
* need to emit an extra one here. \
*/ \
if (__SYNC_loongson3_war == 0) \
smp_mb__before_llsc(); \
\
__res = (__typeof__(*(ptr))) \
__arch_xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
\
smp_llsc_mb(); \
\
__res; \
})
#define __cmpxchg_asm(ld, st, m, old, new) \
({ \
__typeof(*(m)) __ret; \
\
if (kernel_uses_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set push \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: " ld " %0, %2 # __cmpxchg_asm \n" \
" bne %0, %z3, 2f \n" \
" .set pop \n" \
" move $1, %z4 \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
" " st " $1, %1 \n" \
"\t" __stringify(SC_BEQZ) " $1, 1b \n" \
" .set pop \n" \
"2: " __SYNC(full, loongson3_war) " \n" \
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
: __LLSC_CLOBBER); \
} else { \
unsigned long __flags; \
\
raw_local_irq_save(__flags); \
__ret = *m; \
if (__ret == old) \
*m = new; \
raw_local_irq_restore(__flags); \
} \
\
__ret; \
})
extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
unsigned long new, unsigned int size);
static __always_inline
unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
unsigned long new, unsigned int size)
{
switch (size) {
case 1:
case 2:
return __cmpxchg_small(ptr, old, new, size);
case 4:
return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr,
(u32)old, new);
case 8:
/* lld/scd are only available for MIPS64 */
if (!IS_ENABLED(CONFIG_64BIT))
return __cmpxchg_called_with_bad_pointer();
return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr,
(u64)old, new);
default:
return __cmpxchg_called_with_bad_pointer();
}
}
#define arch_cmpxchg_local(ptr, old, new) \
((__typeof__(*(ptr))) \
__cmpxchg((ptr), \
(unsigned long)(__typeof__(*(ptr)))(old), \
(unsigned long)(__typeof__(*(ptr)))(new), \
sizeof(*(ptr))))
#define arch_cmpxchg(ptr, old, new) \
({ \
__typeof__(*(ptr)) __res; \
\
/* \
* In the Loongson3 workaround case __cmpxchg_asm() already \
* contains a completion barrier prior to the LL, so we don't \
* need to emit an extra one here. \
*/ \
if (__SYNC_loongson3_war == 0) \
smp_mb__before_llsc(); \
\
__res = arch_cmpxchg_local((ptr), (old), (new)); \
\
/* \
* In the Loongson3 workaround case __cmpxchg_asm() already \
* contains a completion barrier after the SC, so we don't \
* need to emit an extra one here. \
*/ \
if (__SYNC_loongson3_war == 0) \
smp_llsc_mb(); \
\
__res; \
})
#ifdef CONFIG_64BIT
#define arch_cmpxchg64_local(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
arch_cmpxchg_local((ptr), (o), (n)); \
})
#define arch_cmpxchg64(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
arch_cmpxchg((ptr), (o), (n)); \
})
#else
# include <asm-generic/cmpxchg-local.h>
# define arch_cmpxchg64_local(ptr, o, n) __generic_cmpxchg64_local((ptr), (o), (n))
# ifdef CONFIG_SMP
static inline unsigned long __cmpxchg64(volatile void *ptr,
unsigned long long old,
unsigned long long new)
{
unsigned long long tmp, ret;
unsigned long flags;
/*
* The assembly below has to combine 32 bit values into a 64 bit
* register, and split 64 bit values from one register into two. If we
* were to take an interrupt in the middle of this we'd only save the
* least significant 32 bits of each register & probably clobber the
* most significant 32 bits of the 64 bit values we're using. In order
* to avoid this we must disable interrupts.
*/
local_irq_save(flags);
asm volatile(
" .set push \n"
" .set " MIPS_ISA_ARCH_LEVEL " \n"
/* Load 64 bits from ptr */
" " __SYNC(full, loongson3_war) " \n"
"1: lld %L0, %3 # __cmpxchg64 \n"
" .set pop \n"
/*
* Split the 64 bit value we loaded into the 2 registers that hold the
* ret variable.
*/
" dsra %M0, %L0, 32 \n"
" sll %L0, %L0, 0 \n"
/*
* Compare ret against old, breaking out of the loop if they don't
* match.
*/
" bne %M0, %M4, 2f \n"
" bne %L0, %L4, 2f \n"
/*
* Combine the 32 bit halves from the 2 registers that hold the new
* variable into a single 64 bit register.
*/
# if MIPS_ISA_REV >= 2
" move %L1, %L5 \n"
" dins %L1, %M5, 32, 32 \n"
# else
" dsll %L1, %L5, 32 \n"
" dsrl %L1, %L1, 32 \n"
" .set noat \n"
" dsll $at, %M5, 32 \n"
" or %L1, %L1, $at \n"
" .set at \n"
# endif
" .set push \n"
" .set " MIPS_ISA_ARCH_LEVEL " \n"
/* Attempt to store new at ptr */
" scd %L1, %2 \n"
/* If we failed, loop! */
"\t" __stringify(SC_BEQZ) " %L1, 1b \n"
"2: " __SYNC(full, loongson3_war) " \n"
" .set pop \n"
: "=&r"(ret),
"=&r"(tmp),
"=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr)
: GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr),
"r" (old),
"r" (new)
: "memory");
local_irq_restore(flags);
return ret;
}
# define arch_cmpxchg64(ptr, o, n) ({ \
unsigned long long __old = (__typeof__(*(ptr)))(o); \
unsigned long long __new = (__typeof__(*(ptr)))(n); \
__typeof__(*(ptr)) __res; \
\
/* \
* We can only use cmpxchg64 if we know that the CPU supports \
* 64-bits, ie. lld & scd. Our call to __cmpxchg64_unsupported \
* will cause a build error unless cpu_has_64bits is a \
* compile-time constant 1. \
*/ \
if (cpu_has_64bits && kernel_uses_llsc) { \
smp_mb__before_llsc(); \
__res = __cmpxchg64((ptr), __old, __new); \
smp_llsc_mb(); \
} else { \
__res = __cmpxchg64_unsupported(); \
} \
\
__res; \
})
# else /* !CONFIG_SMP */
# define arch_cmpxchg64(ptr, o, n) arch_cmpxchg64_local((ptr), (o), (n))
# endif /* !CONFIG_SMP */
#endif /* !CONFIG_64BIT */
#endif /* __ASM_CMPXCHG_H */
linux-7.2.3/arch/mips/include/asm/compat-signal.h
+29
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@@ -0,0 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_COMPAT_SIGNAL_H
#define __ASM_COMPAT_SIGNAL_H
#include <linux/bug.h>
#include <linux/compat.h>
#include <linux/compiler.h>
#include <asm/signal.h>
#include <asm/siginfo.h>
#include <linux/uaccess.h>
static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
const sigset_t *s)
{
BUILD_BUG_ON(sizeof(*d) != sizeof(*s));
BUILD_BUG_ON(_NSIG_WORDS != 2);
return put_compat_sigset(d, s, sizeof(*d));
}
static inline int __copy_conv_sigset_from_user(sigset_t *d,
const compat_sigset_t __user *s)
{
return get_compat_sigset(d, s);
}
#endif /* __ASM_COMPAT_SIGNAL_H */
linux-7.2.3/arch/mips/include/asm/compat.h
+158
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@@ -0,0 +1,158 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_COMPAT_H
#define _ASM_COMPAT_H
/*
* Architecture specific compatibility types
*/
#include <linux/thread_info.h>
#include <linux/types.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#define __compat_uid_t __compat_uid_t
typedef s32 __compat_uid_t;
typedef s32 __compat_gid_t;
typedef __compat_uid_t __compat_uid32_t;
typedef __compat_gid_t __compat_gid32_t;
#define __compat_uid32_t __compat_uid32_t
#define compat_statfs compat_statfs
#define compat_ipc64_perm compat_ipc64_perm
#define _COMPAT_NSIG 128 /* Don't ask !$@#% ... */
#define _COMPAT_NSIG_BPW 32
typedef u32 compat_sigset_word;
#define COMPAT_RLIM_INFINITY 0x7fffffffUL
#include <asm-generic/compat.h>
#define COMPAT_UTS_MACHINE "mips\0\0\0"
typedef u32 compat_nlink_t;
struct compat_stat {
compat_dev_t st_dev;
s32 st_pad1[3];
compat_ino_t st_ino;
compat_mode_t st_mode;
compat_nlink_t st_nlink;
__compat_uid_t st_uid;
__compat_gid_t st_gid;
compat_dev_t st_rdev;
s32 st_pad2[2];
compat_off_t st_size;
s32 st_pad3;
old_time32_t st_atime;
s32 st_atime_nsec;
old_time32_t st_mtime;
s32 st_mtime_nsec;
old_time32_t st_ctime;
s32 st_ctime_nsec;
s32 st_blksize;
s32 st_blocks;
s32 st_pad4[14];
};
#define __ARCH_COMPAT_FLOCK_EXTRA_SYSID s32 l_sysid;
#define __ARCH_COMPAT_FLOCK_PAD s32 pad[4];
struct compat_statfs {
int f_type;
int f_bsize;
int f_frsize;
int f_blocks;
int f_bfree;
int f_files;
int f_ffree;
int f_bavail;
compat_fsid_t f_fsid;
int f_namelen;
int f_flags;
int f_spare[5];
};
struct compat_ipc64_perm {
compat_key_t key;
__compat_uid32_t uid;
__compat_gid32_t gid;
__compat_uid32_t cuid;
__compat_gid32_t cgid;
compat_mode_t mode;
unsigned short seq;
unsigned short __pad2;
compat_ulong_t __unused1;
compat_ulong_t __unused2;
};
struct compat_semid64_ds {
struct compat_ipc64_perm sem_perm;
compat_ulong_t sem_otime;
compat_ulong_t sem_ctime;
compat_ulong_t sem_nsems;
compat_ulong_t sem_otime_high;
compat_ulong_t sem_ctime_high;
};
struct compat_msqid64_ds {
struct compat_ipc64_perm msg_perm;
#ifndef CONFIG_CPU_LITTLE_ENDIAN
compat_ulong_t msg_stime_high;
#endif
compat_ulong_t msg_stime;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
compat_ulong_t msg_stime_high;
#endif
#ifndef CONFIG_CPU_LITTLE_ENDIAN
compat_ulong_t msg_rtime_high;
#endif
compat_ulong_t msg_rtime;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
compat_ulong_t msg_rtime_high;
#endif
#ifndef CONFIG_CPU_LITTLE_ENDIAN
compat_ulong_t msg_ctime_high;
#endif
compat_ulong_t msg_ctime;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
compat_ulong_t msg_ctime_high;
#endif
compat_ulong_t msg_cbytes;
compat_ulong_t msg_qnum;
compat_ulong_t msg_qbytes;
compat_pid_t msg_lspid;
compat_pid_t msg_lrpid;
compat_ulong_t __unused4;
compat_ulong_t __unused5;
};
struct compat_shmid64_ds {
struct compat_ipc64_perm shm_perm;
compat_size_t shm_segsz;
compat_ulong_t shm_atime;
compat_ulong_t shm_dtime;
compat_ulong_t shm_ctime;
compat_pid_t shm_cpid;
compat_pid_t shm_lpid;
compat_ulong_t shm_nattch;
compat_ushort_t shm_atime_high;
compat_ushort_t shm_dtime_high;
compat_ushort_t shm_ctime_high;
compat_ushort_t __unused2;
};
/* MIPS has unusual order of fields in stack_t */
typedef struct compat_sigaltstack {
compat_uptr_t ss_sp;
compat_size_t ss_size;
int ss_flags;
} compat_stack_t;
#define compat_sigaltstack compat_sigaltstack
static inline int is_compat_task(void)
{
return test_thread_flag(TIF_32BIT_ADDR);
}
#endif /* _ASM_COMPAT_H */
linux-7.2.3/arch/mips/include/asm/compiler.h
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/*
* Copyright (C) 2004, 2007 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef _ASM_COMPILER_H
#define _ASM_COMPILER_H
/*
* With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
* compiler that a particular code path will never be hit. This allows it to be
* optimised out of the generated binary.
*
* Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
* that can lead to instructions from beyond an unreachable statement being
* incorrectly reordered into earlier delay slots if the unreachable statement
* is the only content of a case in a switch statement. This can lead to
* seemingly random behaviour, such as invalid memory accesses from incorrectly
* reordered loads or stores. See this potential GCC fix for details:
*
* https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
*
* It is unclear whether GCC 8 onwards suffer from the same issue - nothing
* relevant is mentioned in GCC 8 release notes and nothing obviously relevant
* stands out in GCC commit logs, but these newer GCC versions generate very
* different code for the testcase which doesn't exhibit the bug.
*
* GCC also handles stack allocation suboptimally when calling noreturn
* functions or calling __builtin_unreachable():
*
* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
*
* We work around both of these issues by placing a volatile asm statement,
* which GCC is prevented from reordering past, prior to __builtin_unreachable
* calls.
*
* The .insn statement is required to ensure that any branches to the
* statement, which sadly must be kept due to the asm statement, are known to
* be branches to code and satisfy linker requirements for microMIPS kernels.
*/
#undef barrier_before_unreachable
#define barrier_before_unreachable() asm volatile(".insn")
#define GCC_OFF_SMALL_ASM() "ZC"
#ifdef CONFIG_CPU_MIPSR6
#define MIPS_ISA_LEVEL "mips64r6"
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r6
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#elif defined(CONFIG_CPU_MIPSR5)
#define MIPS_ISA_LEVEL "mips64r5"
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r5
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#else
/* MIPS64 is a superset of MIPS32 */
#define MIPS_ISA_LEVEL "mips64r2"
#define MIPS_ISA_ARCH_LEVEL "arch=r4000"
#define MIPS_ISA_LEVEL_RAW mips64r2
#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
#endif /* CONFIG_CPU_MIPSR6 */
#endif /* _ASM_COMPILER_H */
linux-7.2.3/arch/mips/include/asm/cop2.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2009 Wind River Systems,
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_COP2_H
#define __ASM_COP2_H
#include <linux/notifier.h>
#if defined(CONFIG_CPU_CAVIUM_OCTEON)
extern void octeon_cop2_save(struct octeon_cop2_state *);
extern void octeon_cop2_restore(struct octeon_cop2_state *);
#define cop2_save(r) octeon_cop2_save(&(r)->thread.cp2)
#define cop2_restore(r) octeon_cop2_restore(&(r)->thread.cp2)
#define cop2_present 1
#define cop2_lazy_restore 1
#elif defined(CONFIG_CPU_LOONGSON64)
#define cop2_present 1
#define cop2_lazy_restore 1
#define cop2_save(r) do { (void)(r); } while (0)
#define cop2_restore(r) do { (void)(r); } while (0)
#else
#define cop2_present 0
#define cop2_lazy_restore 0
#define cop2_save(r) do { (void)(r); } while (0)
#define cop2_restore(r) do { (void)(r); } while (0)
#endif
enum cu2_ops {
CU2_EXCEPTION,
CU2_LWC2_OP,
CU2_LDC2_OP,
CU2_SWC2_OP,
CU2_SDC2_OP,
};
extern int register_cu2_notifier(struct notifier_block *nb);
extern int cu2_notifier_call_chain(unsigned long val, void *v);
#define cu2_notifier(fn, pri) \
({ \
static struct notifier_block fn##_nb = { \
.notifier_call = fn, \
.priority = pri \
}; \
\
register_cu2_notifier(&fn##_nb); \
})
#endif /* __ASM_COP2_H */
linux-7.2.3/arch/mips/include/asm/cpu-features.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*/
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/isa-rev.h>
#include <cpu-feature-overrides.h>
#define __ase(ase) (cpu_data[0].ases & (ase))
#define __isa(isa) (cpu_data[0].isa_level & (isa))
#define __opt(opt) (cpu_data[0].options & (opt))
/*
* Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during
* boot (typically by cpu_probe()).
*
* Note that these should only be used in cases where a kernel built for an
* older ISA *cannot* run on a CPU which supports the feature in question. For
* example this may be used for features introduced with MIPSr6, since a kernel
* built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
* for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
* MIPSr2 CPU.
*/
#define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase))
#define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt))
/*
* Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during
* boot (typically by cpu_probe()).
*
* These are for use with features that are optional up until a particular ISA
* revision & then become required.
*/
#define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase))
#define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt))
/*
* Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during
* boot (typically by cpu_probe()).
*
* These are for use with features that are optional up until a particular ISA
* revision & are then removed - ie. no longer present in any CPU implementing
* the given ISA revision.
*/
#define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase))
#define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt))
/*
* Similarly allow for ISA level checks that take into account knowledge of the
* ISA targeted by the kernel build, provided by MIPS_ISA_REV.
*/
#define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag))
#define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag))
#define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag))
#define __isa_range(ge, lt) \
((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
#define __isa_range_or_flag(ge, lt, flag) \
(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
#define __isa_range_and_ase(ge, lt, ase) \
(__isa_range(ge, lt) && __ase(ase))
/*
* SMP assumption: Options of CPU 0 are a superset of all processors.
* This is true for all known MIPS systems.
*/
#ifndef cpu_has_tlb
#define cpu_has_tlb __opt(MIPS_CPU_TLB)
#endif
#ifndef cpu_has_ftlb
#define cpu_has_ftlb __opt(MIPS_CPU_FTLB)
#endif
#ifndef cpu_has_tlbinv
#define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV)
#endif
#ifndef cpu_has_segments
#define cpu_has_segments __opt(MIPS_CPU_SEGMENTS)
#endif
#ifndef cpu_has_eva
#define cpu_has_eva __opt(MIPS_CPU_EVA)
#endif
#ifndef cpu_has_htw
#define cpu_has_htw __opt(MIPS_CPU_HTW)
#endif
#ifndef cpu_has_ldpte
#define cpu_has_ldpte __opt(MIPS_CPU_LDPTE)
#endif
#ifndef cpu_has_rixiex
#define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
#endif
#ifndef cpu_has_maar
#define cpu_has_maar __opt(MIPS_CPU_MAAR)
#endif
#ifndef cpu_has_rw_llb
#define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that
* anything that doesn't support R4000-style exceptions and interrupts is
* R3000-like. Users should still treat these two macro definitions as
* opaque.
*/
#ifndef cpu_has_3kex
#define cpu_has_3kex (!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
#endif
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache \
({ \
int __res; \
\
switch (boot_cpu_type()) { \
case CPU_CAVIUM_OCTEON: \
case CPU_CAVIUM_OCTEON_PLUS: \
case CPU_CAVIUM_OCTEON2: \
case CPU_CAVIUM_OCTEON3: \
__res = 1; \
break; \
\
default: \
__res = 0; \
} \
\
__res; \
})
#endif
/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
#ifndef cpu_has_fpu
# ifdef CONFIG_MIPS_FP_SUPPORT
# define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
# define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
# else
# define cpu_has_fpu 0
# define raw_cpu_has_fpu 0
# endif
#else
# if cpu_has_fpu
# error "Forcing `cpu_has_fpu' to non-zero is not supported"
# endif
# define raw_cpu_has_fpu cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter __opt(MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch __opt(MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce __opt(MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag __opt(MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc cpu_has_llsc
#endif
#ifndef cpu_has_guestctl0ext
#define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT)
#endif
#ifndef cpu_has_guestctl1
#define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1)
#endif
#ifndef cpu_has_guestctl2
#define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2)
#endif
#ifndef cpu_has_guestid
#define cpu_has_guestid __opt(MIPS_CPU_GUESTID)
#endif
#ifndef cpu_has_drg
#define cpu_has_drg __opt(MIPS_CPU_DRG)
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mips16e2
#define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_rixi
#define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI)
#endif
#ifndef cpu_has_mmips
# if defined(__mips_micromips)
# define cpu_has_mmips 1
# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
# define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS)
# else
# define cpu_has_mmips 0
# endif
#endif
#ifndef cpu_has_lpa
#define cpu_has_lpa __opt(MIPS_CPU_LPA)
#endif
#ifndef cpu_has_mvh
#define cpu_has_mvh __opt(MIPS_CPU_MVH)
#endif
#ifndef cpu_has_xpa
#define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
* such as the R10000 have I-Caches that snoop local stores; the embedded ones
* don't. For maintaining I-cache coherency this means we need to flush the
* D-cache all the way back to whever the I-cache does refills from, so the
* I-cache has a chance to see the new data at all. Then we have to flush the
* I-cache also.
* Note we may have been rescheduled and may no longer be running on the CPU
* that did the store so we can't optimize this into only doing the flush on
* the local CPU.
*/
#ifndef cpu_icache_snoops_remote_store
#ifdef CONFIG_SMP
#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
#else
#define cpu_icache_snoops_remote_store 1
#endif
#endif
#ifndef cpu_has_mips_1
# define cpu_has_mips_1 (MIPS_ISA_REV < 6)
#endif
#ifndef cpu_has_mips_2
# define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II)
#endif
#ifndef cpu_has_mips_3
# define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III)
#endif
#ifndef cpu_has_mips_4
# define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
#endif
#ifndef cpu_has_mips_5
# define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V)
#endif
#ifndef cpu_has_mips32r1
# define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
#endif
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips32r5
# define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
#endif
#ifndef cpu_has_mips32r6
# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 (cpu_has_64bits && \
__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 (cpu_has_64bits && \
__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
#endif
#ifndef cpu_has_mips64r5
# define cpu_has_mips64r5 (cpu_has_64bits && \
__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
#endif
#ifndef cpu_has_mips64r6
# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
#endif
/*
* Shortcuts ...
*/
#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
#define cpu_has_mips_3_4_5_64_r2_r6 \
(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
#define cpu_has_mips_4_5_64_r2_r6 \
(cpu_has_mips_4_5 | cpu_has_mips64r1 | \
cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips32r5 | cpu_has_mips32r6)
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \
cpu_has_mips64r5 | cpu_has_mips64r6)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5)
#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips32r5 | cpu_has_mips32r6 | \
cpu_has_mips64r1 | cpu_has_mips64r2 | \
cpu_has_mips64r5 | cpu_has_mips64r6)
/* MIPSR2 - MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
/*
* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
*
* Returns non-zero value if the current processor implementation requires
* an IHB instruction to deal with an instruction hazard as per MIPS R2
* architecture specification, zero otherwise.
*/
#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard \
({ \
int __res; \
\
switch (boot_cpu_type()) { \
case CPU_M14KC: \
case CPU_74K: \
case CPU_1074K: \
case CPU_PROAPTIV: \
case CPU_P5600: \
case CPU_M5150: \
case CPU_QEMU_GENERIC: \
case CPU_CAVIUM_OCTEON: \
case CPU_CAVIUM_OCTEON_PLUS: \
case CPU_CAVIUM_OCTEON2: \
case CPU_CAVIUM_OCTEON3: \
__res = 0; \
break; \
\
default: \
__res = 1; \
} \
\
__res; \
})
#endif
/*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/
#ifndef cpu_has_clo_clz
#define cpu_has_clo_clz cpu_has_mips_r
#endif
/*
* MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
* MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
* This indicates the availability of WSBH and in case of 64 bit CPUs also
* DSBH and DSHD.
*/
#ifndef cpu_has_wsbh
#define cpu_has_wsbh cpu_has_mips_r2
#endif
#ifndef cpu_has_dsp
#define cpu_has_dsp __ase(MIPS_ASE_DSP)
#endif
#ifndef cpu_has_dsp2
#define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P)
#endif
#ifndef cpu_has_dsp3
#define cpu_has_dsp3 __ase(MIPS_ASE_DSP3)
#endif
#ifndef cpu_has_loongson_mmi
#define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI)
#endif
#ifndef cpu_has_loongson_cam
#define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM)
#endif
#ifndef cpu_has_loongson_ext
#define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT)
#endif
#ifndef cpu_has_loongson_ext2
#define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2)
#endif
#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
#endif
#ifndef cpu_has_vp
#define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP)
#endif
#ifndef cpu_has_userlocal
#define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI)
#endif
#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
#endif
#ifdef CONFIG_64BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex 0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits 1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg 1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# endif
#endif
#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint __opt(MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint 0
#endif
#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic __opt(MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic 0
#endif
#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES)
#endif
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size() cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif
#ifndef cpu_tcache_line_size
#define cpu_tcache_line_size() cpu_data[0].tcache.linesz
#endif
#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits 0
#endif
#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI)
#endif
#ifndef cpu_has_vz
#define cpu_has_vz __ase(MIPS_ASE_VZ)
#endif
#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
# define cpu_has_msa __ase(MIPS_ASE_MSA)
#elif !defined(cpu_has_msa)
# define cpu_has_msa 0
#endif
#ifndef cpu_has_ufr
# define cpu_has_ufr __opt(MIPS_CPU_UFR)
#endif
#ifndef cpu_has_fre
# define cpu_has_fre __opt(MIPS_CPU_FRE)
#endif
#ifndef cpu_has_cdmm
# define cpu_has_cdmm __opt(MIPS_CPU_CDMM)
#endif
#ifndef cpu_has_small_pages
# define cpu_has_small_pages __opt(MIPS_CPU_SP)
#endif
#ifndef cpu_has_nan_legacy
#define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
#endif
#ifndef cpu_has_nan_2008
#define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
#endif
#ifndef cpu_has_ebase_wg
# define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG)
#endif
#ifndef cpu_has_badinstr
# define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
#endif
#ifndef cpu_has_badinstrp
# define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
#endif
#ifndef cpu_has_contextconfig
# define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC)
#endif
#ifndef cpu_has_perf
# define cpu_has_perf __opt(MIPS_CPU_PERF)
#endif
#ifndef cpu_has_mac2008_only
# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY)
#endif
#ifndef cpu_has_ftlbparex
# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX)
#endif
#ifndef cpu_has_gsexcex
# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX)
#endif
#ifdef CONFIG_SMP
/*
* Some systems share FTLB RAMs between threads within a core (siblings in
* kernel parlance). This means that FTLB entries may become invalid at almost
* any point when an entry is evicted due to a sibling thread writing an entry
* to the shared FTLB RAM.
*
* This is only relevant to SMP systems, and the only systems that exhibit this
* property implement MIPSr6 or higher so we constrain support for this to
* kernels that will run on such systems.
*/
# ifndef cpu_has_shared_ftlb_ram
# define cpu_has_shared_ftlb_ram \
__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
# endif
/*
* Some systems take this a step further & share FTLB entries between siblings.
* This is implemented as TLB writes happening as usual, but if an entry
* written by a sibling exists in the shared FTLB for a translation which would
* otherwise cause a TLB refill exception then the CPU will use the entry
* written by its sibling rather than triggering a refill & writing a matching
* TLB entry for itself.
*
* This is naturally only valid if a TLB entry is known to be suitable for use
* on all siblings in a CPU, and so it only takes effect when MMIDs are in use
* rather than ASIDs or when a TLB entry is marked global.
*/
# ifndef cpu_has_shared_ftlb_entries
# define cpu_has_shared_ftlb_entries \
__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
# endif
#endif /* SMP */
#ifndef cpu_has_shared_ftlb_ram
# define cpu_has_shared_ftlb_ram 0
#endif
#ifndef cpu_has_shared_ftlb_entries
# define cpu_has_shared_ftlb_entries 0
#endif
#ifdef CONFIG_MIPS_MT_SMP
# define cpu_has_mipsmt_pertccounters \
__isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
#else
# define cpu_has_mipsmt_pertccounters 0
#endif /* CONFIG_MIPS_MT_SMP */
/*
* We only enable MMID support for configurations which natively support 64 bit
* atomics because getting good performance from the allocator relies upon
* efficient atomic64_*() functions.
*/
#ifndef cpu_has_mmid
# ifdef CONFIG_GENERIC_ATOMIC64
# define cpu_has_mmid 0
# else
# define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID)
# endif
#endif
#ifndef cpu_has_mm_sysad
# define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD)
#endif
#ifndef cpu_has_mm_full
# define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL)
#endif
/*
* Guest capabilities
*/
#ifndef cpu_guest_has_conf1
#define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1))
#endif
#ifndef cpu_guest_has_conf2
#define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2))
#endif
#ifndef cpu_guest_has_conf3
#define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3))
#endif
#ifndef cpu_guest_has_conf4
#define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4))
#endif
#ifndef cpu_guest_has_conf5
#define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5))
#endif
#ifndef cpu_guest_has_conf6
#define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6))
#endif
#ifndef cpu_guest_has_conf7
#define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7))
#endif
#ifndef cpu_guest_has_fpu
#define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU)
#endif
#ifndef cpu_guest_has_watch
#define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_guest_has_contextconfig
#define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
#endif
#ifndef cpu_guest_has_segments
#define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
#endif
#ifndef cpu_guest_has_badinstr
#define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
#endif
#ifndef cpu_guest_has_badinstrp
#define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
#endif
#ifndef cpu_guest_has_htw
#define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW)
#endif
#ifndef cpu_guest_has_ldpte
#define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE)
#endif
#ifndef cpu_guest_has_mvh
#define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH)
#endif
#ifndef cpu_guest_has_msa
#define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA)
#endif
#ifndef cpu_guest_has_kscr
#define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n)))
#endif
#ifndef cpu_guest_has_rw_llb
#define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
#endif
#ifndef cpu_guest_has_perf
#define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF)
#endif
#ifndef cpu_guest_has_maar
#define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR)
#endif
#ifndef cpu_guest_has_userlocal
#define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI)
#endif
/*
* Guest dynamic capabilities
*/
#ifndef cpu_guest_has_dyn_fpu
#define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
#endif
#ifndef cpu_guest_has_dyn_watch
#define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
#endif
#ifndef cpu_guest_has_dyn_contextconfig
#define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
#endif
#ifndef cpu_guest_has_dyn_perf
#define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
#endif
#ifndef cpu_guest_has_dyn_msa
#define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
#endif
#ifndef cpu_guest_has_dyn_maar
#define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
#endif
#endif /* __ASM_CPU_FEATURES_H */
linux-7.2.3/arch/mips/include/asm/cpu-info.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2004 Maciej W. Rozycki
*/
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H
#include <linux/cache.h>
#include <linux/types.h>
#include <asm/mipsregs.h>
/*
* Descriptor for a cache
*/
struct cache_desc {
unsigned int waysize; /* Bytes per way */
unsigned short sets; /* Number of lines per set */
unsigned char ways; /* Number of ways */
unsigned char linesz; /* Size of line in bytes */
unsigned char waybit; /* Bits to select in a cache set */
unsigned char flags; /* Flags describing cache properties */
};
struct guest_info {
unsigned long ases;
unsigned long ases_dyn;
unsigned long long options;
unsigned long long options_dyn;
int tlbsize;
u8 conf;
u8 kscratch_mask;
};
/*
* Flag definitions
*/
#define MIPS_CACHE_NOT_PRESENT 0x00000001
#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
struct cpuinfo_mips {
u64 asid_cache;
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
unsigned long asid_mask;
#endif
/*
* Capability and feature descriptor structure for MIPS CPU
*/
unsigned long ases;
unsigned long long options;
unsigned int udelay_val;
unsigned int processor_id;
unsigned int fpu_id;
unsigned int fpu_csr31;
unsigned int fpu_msk31;
unsigned int msa_id;
unsigned int cputype;
int isa_level;
int tlbsize;
int tlbsizevtlb;
int tlbsizeftlbsets;
int tlbsizeftlbways;
struct cache_desc icache; /* Primary I-cache */
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc vcache; /* Victim cache, between pcache and scache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
int package;/* physical package number */
unsigned int globalnumber;
int vmbits; /* Virtual memory size in bits */
void *data; /* Additional data */
unsigned int watch_reg_count; /* Number that exist */
unsigned int watch_reg_use_cnt; /* Usable by ptrace */
#define NUM_WATCH_REGS 4
u16 watch_reg_masks[NUM_WATCH_REGS];
unsigned int kscratch_mask; /* Usable KScratch mask. */
/*
* Cache Coherency attribute for write-combine memory writes.
* (shifted by _CACHE_SHIFT)
*/
unsigned int writecombine;
/*
* Simple counter to prevent enabling HTW in nested
* htw_start/htw_stop calls
*/
unsigned int htw_seq;
/* VZ & Guest features */
struct guest_info guest;
unsigned int gtoffset_mask;
unsigned int guestid_mask;
unsigned int guestid_cache;
#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
/* CPUCFG data for this CPU, synthesized at probe time.
*
* CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
* So the only stored values are for CPUCFG selects 1-3 inclusive.
*/
u32 loongson3_cpucfg_data[3];
#endif
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
#define boot_cpu_data cpu_data[0]
extern void cpu_probe(void);
extern void cpu_report(void);
extern void cpu_disable_mmid(void);
extern const char *__cpu_name[];
#define cpu_name_string() __cpu_name[raw_smp_processor_id()]
struct seq_file;
struct notifier_block;
extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
#define proc_cpuinfo_notifier(fn, pri) \
({ \
static struct notifier_block fn##_nb = { \
.notifier_call = fn, \
.priority = pri \
}; \
\
register_proc_cpuinfo_notifier(&fn##_nb); \
})
struct proc_cpuinfo_notifier_args {
struct seq_file *m;
unsigned long n;
};
static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
{
/* Optimisation for systems where multiple clusters aren't used */
if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
return 0;
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
MIPS_GLOBALNUMBER_CLUSTER_SHF;
}
static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
{
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
MIPS_GLOBALNUMBER_CORE_SHF;
}
static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
{
/* Optimisation for systems where VP(E)s aren't used */
if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
return 0;
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
MIPS_GLOBALNUMBER_VP_SHF;
}
extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
static inline bool cpus_are_siblings(int cpua, int cpub)
{
struct cpuinfo_mips *infoa = &cpu_data[cpua];
struct cpuinfo_mips *infob = &cpu_data[cpub];
unsigned int gnuma, gnumb;
if (infoa->package != infob->package)
return false;
gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
if (gnuma != gnumb)
return false;
return true;
}
static inline unsigned long cpu_asid_inc(void)
{
return 1 << CONFIG_MIPS_ASID_SHIFT;
}
static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
{
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
return cpuinfo->asid_mask;
#endif
return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
}
static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
unsigned long asid_mask)
{
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
cpuinfo->asid_mask = asid_mask;
#endif
}
#endif /* __ASM_CPU_INFO_H */
linux-7.2.3/arch/mips/include/asm/cpu-type.h
+202
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*/
#ifndef __ASM_CPU_TYPE_H
#define __ASM_CPU_TYPE_H
#include <linux/smp.h>
#include <linux/compiler.h>
static inline int __pure __get_cpu_type(const int cpu_type)
{
switch (cpu_type) {
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
case CPU_LOONGSON2EF:
#endif
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64
case CPU_LOONGSON64:
#endif
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON32
case CPU_LOONGSON32:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
case CPU_4KC:
case CPU_ALCHEMY:
case CPU_PR4450:
#endif
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
case CPU_4KEC:
case CPU_XBURST:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
case CPU_4KSC:
case CPU_24K:
case CPU_34K:
case CPU_1004K:
case CPU_74K:
case CPU_1074K:
case CPU_M14KC:
case CPU_M14KEC:
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5
case CPU_M5150:
case CPU_P5600:
#endif
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R5) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R5) || \
defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
case CPU_QEMU_GENERIC:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
case CPU_5KC:
case CPU_5KE:
case CPU_20KC:
case CPU_25KF:
case CPU_SB1:
case CPU_SB1A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
/*
* All MIPS64 R2 processors have their own special symbols. That is,
* there currently is no pure R2 core
*/
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R6
case CPU_M6250:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
case CPU_I6400:
case CPU_I6500:
case CPU_P6600:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R3000
case CPU_R2000:
case CPU_R3000:
case CPU_R3000A:
case CPU_R3041:
case CPU_R3051:
case CPU_R3052:
case CPU_R3081:
case CPU_R3081E:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R4300
case CPU_R4300:
case CPU_R4310:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R4X00
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4200:
case CPU_R4400PC:
case CPU_R4400SC:
case CPU_R4400MC:
case CPU_R4600:
case CPU_R4700:
case CPU_R4640:
case CPU_R4650:
#endif
#ifdef CONFIG_SYS_HAS_CPU_TX49XX
case CPU_TX49XX:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R5000
case CPU_R5000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R5500
case CPU_R5500:
#endif
#ifdef CONFIG_SYS_HAS_CPU_NEVADA
case CPU_NEVADA:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R10000
case CPU_R10000:
case CPU_R12000:
case CPU_R14000:
case CPU_R16000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_RM7000
case CPU_RM7000:
case CPU_SR71000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_SB1
case CPU_SB1:
case CPU_SB1A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
case CPU_CAVIUM_OCTEON3:
#endif
#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
defined (CONFIG_SYS_HAS_CPU_MIPS32_R1)
case CPU_BMIPS32:
case CPU_BMIPS3300:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350
case CPU_BMIPS4350:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
case CPU_BMIPS4380:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
case CPU_BMIPS5000:
#endif
break;
default:
unreachable();
}
return cpu_type;
}
static inline int __pure current_cpu_type(void)
{
const int cpu_type = current_cpu_data.cputype;
return __get_cpu_type(cpu_type);
}
static inline int __pure boot_cpu_type(void)
{
const int cpu_type = cpu_data[0].cputype;
return __get_cpu_type(cpu_type);
}
#endif /* __ASM_CPU_TYPE_H */
linux-7.2.3/arch/mips/include/asm/cpu.h
+443
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* cpu.h: Values of the PRId register used to match up
* various MIPS cpu types.
*
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
* Copyright (C) 2004, 2013 Maciej W. Rozycki
*/
#ifndef _ASM_CPU_H
#define _ASM_CPU_H
#include <linux/bits.h>
/*
As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
register 15, select 0) is defined in this (backwards compatible) way:
+----------------+----------------+----------------+----------------+
| Company Options| Company ID | Processor ID | Revision |
+----------------+----------------+----------------+----------------+
31 24 23 16 15 8 7
I don't have docs for all the previous processors, but my impression is
that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
spec.
*/
#define PRID_OPT_MASK 0xff000000
/*
* Assigned Company values for bits 23:16 of the PRId register.
*/
#define PRID_COMP_MASK 0xff0000
#define PRID_COMP_LEGACY 0x000000
#define PRID_COMP_MIPS 0x010000
#define PRID_COMP_BROADCOM 0x020000
#define PRID_COMP_ALCHEMY 0x030000
#define PRID_COMP_SIBYTE 0x040000
#define PRID_COMP_SANDCRAFT 0x050000
#define PRID_COMP_NXP 0x060000
#define PRID_COMP_TOSHIBA 0x070000
#define PRID_COMP_LSI 0x080000
#define PRID_COMP_LEXRA 0x0b0000
#define PRID_COMP_NETLOGIC 0x0c0000
#define PRID_COMP_CAVIUM 0x0d0000
#define PRID_COMP_LOONGSON 0x140000
#define PRID_COMP_INGENIC_13 0x130000 /* X2000, X2100 */
#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830 */
#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
/*
* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
* register. In order to detect a certain CPU type exactly eventually
* additional registers may need to be examined.
*/
#define PRID_IMP_MASK 0xff00
/*
* These are valid when 23:16 == PRID_COMP_LEGACY
*/
#define PRID_IMP_R2000 0x0100
#define PRID_IMP_AU1_REV1 0x0100
#define PRID_IMP_AU1_REV2 0x0200
#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
#define PRID_IMP_R4000 0x0400
#define PRID_IMP_R6000A 0x0600
#define PRID_IMP_R10000 0x0900
#define PRID_IMP_R4300 0x0b00
#define PRID_IMP_VR41XX 0x0c00
#define PRID_IMP_R12000 0x0e00
#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
#define PRID_IMP_R8000 0x1000
#define PRID_IMP_PR4450 0x1200
#define PRID_IMP_R4600 0x2000
#define PRID_IMP_R4700 0x2100
#define PRID_IMP_TX39 0x2200
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
#define PRID_IMP_R5000 0x2300
#define PRID_IMP_TX49 0x2d00
#define PRID_IMP_SONIC 0x2400
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
#define PRID_IMP_RM9000 0x3400
#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
#define PRID_IMP_R5432 0x5400
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
#define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
#define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
#define PRID_IMP_UNKNOWN 0xff00
/*
* These are the PRID's for when 23:16 == PRID_COMP_MIPS
*/
#define PRID_IMP_QEMU_GENERIC 0x0000
#define PRID_IMP_4KC 0x8000
#define PRID_IMP_5KC 0x8100
#define PRID_IMP_20KC 0x8200
#define PRID_IMP_4KEC 0x8400
#define PRID_IMP_4KSC 0x8600
#define PRID_IMP_25KF 0x8800
#define PRID_IMP_5KE 0x8900
#define PRID_IMP_4KECR2 0x9000
#define PRID_IMP_4KEMPR2 0x9100
#define PRID_IMP_4KSD 0x9200
#define PRID_IMP_24K 0x9300
#define PRID_IMP_34K 0x9500
#define PRID_IMP_24KE 0x9600
#define PRID_IMP_74K 0x9700
#define PRID_IMP_1004K 0x9900
#define PRID_IMP_1074K 0x9a00
#define PRID_IMP_M14KC 0x9c00
#define PRID_IMP_M14KEC 0x9e00
#define PRID_IMP_INTERAPTIV_UP 0xa000
#define PRID_IMP_INTERAPTIV_MP 0xa100
#define PRID_IMP_PROAPTIV_UP 0xa200
#define PRID_IMP_PROAPTIV_MP 0xa300
#define PRID_IMP_P6600 0xa400
#define PRID_IMP_M5150 0xa700
#define PRID_IMP_P5600 0xa800
#define PRID_IMP_I6400 0xa900
#define PRID_IMP_M6250 0xab00
#define PRID_IMP_I6500 0xb000
/*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
*/
#define PRID_IMP_SB1 0x0100
#define PRID_IMP_SB1A 0x1100
/*
* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
*/
#define PRID_IMP_SR71000 0x0400
/*
* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
*/
#define PRID_IMP_BMIPS32_REV4 0x4000
#define PRID_IMP_BMIPS32_REV8 0x8000
#define PRID_IMP_BMIPS3300 0x9000
#define PRID_IMP_BMIPS3300_ALT 0x9100
#define PRID_IMP_BMIPS3300_BUG 0x0000
#define PRID_IMP_BMIPS43XX 0xa000
#define PRID_IMP_BMIPS5000 0x5a00
#define PRID_IMP_BMIPS5200 0x5b00
#define PRID_REV_BMIPS4380_LO 0x0040
#define PRID_REV_BMIPS4380_HI 0x006f
/*
* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
*/
#define PRID_IMP_CAVIUM_CN38XX 0x0000
#define PRID_IMP_CAVIUM_CN31XX 0x0100
#define PRID_IMP_CAVIUM_CN30XX 0x0200
#define PRID_IMP_CAVIUM_CN58XX 0x0300
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
#define PRID_IMP_CAVIUM_CN68XX 0x9100
#define PRID_IMP_CAVIUM_CN66XX 0x9200
#define PRID_IMP_CAVIUM_CN61XX 0x9300
#define PRID_IMP_CAVIUM_CNF71XX 0x9400
#define PRID_IMP_CAVIUM_CN78XX 0x9500
#define PRID_IMP_CAVIUM_CN70XX 0x9600
#define PRID_IMP_CAVIUM_CN73XX 0x9700
#define PRID_IMP_CAVIUM_CNF75XX 0x9800
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
*/
#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
#define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
/*
* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
*/
#define PRID_IMP_NETLOGIC_XLR732 0x0000
#define PRID_IMP_NETLOGIC_XLR716 0x0200
#define PRID_IMP_NETLOGIC_XLR532 0x0900
#define PRID_IMP_NETLOGIC_XLR308 0x0600
#define PRID_IMP_NETLOGIC_XLR532C 0x0800
#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
#define PRID_IMP_NETLOGIC_XLS608 0x8000
#define PRID_IMP_NETLOGIC_XLS408 0x8800
#define PRID_IMP_NETLOGIC_XLS404 0x8c00
#define PRID_IMP_NETLOGIC_XLS208 0x8e00
#define PRID_IMP_NETLOGIC_XLS204 0x8f00
#define PRID_IMP_NETLOGIC_XLS108 0xce00
#define PRID_IMP_NETLOGIC_XLS104 0xcf00
#define PRID_IMP_NETLOGIC_XLS616B 0x4000
#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
#define PRID_IMP_NETLOGIC_XLS416B 0x4400
#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
#define PRID_IMP_NETLOGIC_AU13XX 0x8000
#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
#define PRID_IMP_NETLOGIC_XLP5XX 0x1300
/*
* Particular Revision values for bits 7:0 of the PRId register.
*/
#define PRID_REV_MASK 0x00ff
/*
* Definitions for 7:0 on legacy processors
*/
#define PRID_REV_TX4927 0x0022
#define PRID_REV_TX4937 0x0030
#define PRID_REV_R4400 0x0040
#define PRID_REV_R3000A 0x0030
#define PRID_REV_R3000 0x0020
#define PRID_REV_R2000A 0x0010
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
#define PRID_REV_VR4121 0x0060
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON1 0x0020
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON2K_R1_0 0x0000
#define PRID_REV_LOONGSON2K_R1_1 0x0001
#define PRID_REV_LOONGSON2K_R1_2 0x0002
#define PRID_REV_LOONGSON2K_R1_3 0x0003
#define PRID_REV_LOONGSON3A_R1 0x0005
#define PRID_REV_LOONGSON3B_R1 0x0006
#define PRID_REV_LOONGSON3B_R2 0x0007
#define PRID_REV_LOONGSON3A_R2_0 0x0008
#define PRID_REV_LOONGSON3A_R3_0 0x0009
#define PRID_REV_LOONGSON3A_R2_1 0x000c
#define PRID_REV_LOONGSON3A_R3_1 0x000d
/*
* Older processors used to encode processor version and revision in two
* 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
* have switched to use the 8-bits as 3:3:2 bitfield with the last field as
* the patch number. *ARGH*
*/
#define PRID_REV_ENCODE_44(ver, rev) \
((ver) << 4 | (rev))
#define PRID_REV_ENCODE_332(ver, rev, patch) \
((ver) << 5 | (rev) << 2 | (patch))
/*
* FPU implementation/revision register (CP1 control register 0).
*
* +---------------------------------+----------------+----------------+
* | 0 | Implementation | Revision |
* +---------------------------------+----------------+----------------+
* 31 16 15 8 7 0
*/
#define FPIR_IMP_MASK 0xff00
#define FPIR_IMP_NONE 0x0000
#if !defined(__ASSEMBLER__)
enum cpu_type_enum {
CPU_UNKNOWN,
/*
* R2000 class processors
*/
CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
CPU_R3081, CPU_R3081E,
/*
* R4000 class processors
*/
CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000,
CPU_R12000, CPU_R14000, CPU_R16000, CPU_RM7000,
CPU_SR71000, CPU_TX49XX,
/*
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
/*
* MIPS64 class processors
*/
CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_I6500,
CPU_QEMU_GENERIC,
CPU_LAST
};
#endif /* !__ASSEMBLER__ */
/*
* ISA Level encodings
*
*/
#define MIPS_CPU_ISA_II 0x00000001
#define MIPS_CPU_ISA_III 0x00000002
#define MIPS_CPU_ISA_IV 0x00000004
#define MIPS_CPU_ISA_V 0x00000008
#define MIPS_CPU_ISA_M32R1 0x00000010
#define MIPS_CPU_ISA_M32R2 0x00000020
#define MIPS_CPU_ISA_M64R1 0x00000040
#define MIPS_CPU_ISA_M64R2 0x00000080
#define MIPS_CPU_ISA_M32R5 0x00000100
#define MIPS_CPU_ISA_M64R5 0x00000200
#define MIPS_CPU_ISA_M32R6 0x00000400
#define MIPS_CPU_ISA_M64R6 0x00000800
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6)
/*
* CPU Option encodings
*/
#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
#define MIPS_CPU_SHARED_FTLB_RAM \
BIT_ULL(54) /* CPU shares FTLB RAM with another */
#define MIPS_CPU_SHARED_FTLB_ENTRIES \
BIT_ULL(55) /* CPU shares FTLB entries with another */
#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
/*
* CPU ASE encodings
*/
#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
#define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
#define MIPS_ASE_LOONGSON_MMI 0x00000800 /* Loongson MultiMedia extensions Instructions */
#define MIPS_ASE_LOONGSON_CAM 0x00001000 /* Loongson CAM */
#define MIPS_ASE_LOONGSON_EXT 0x00002000 /* Loongson EXTensions */
#define MIPS_ASE_LOONGSON_EXT2 0x00004000 /* Loongson EXTensions R2 */
#endif /* _ASM_CPU_H */
linux-7.2.3/arch/mips/include/asm/cpufeature.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* CPU feature definitions for module loading, used by
* module_cpu_feature_match(), see uapi/asm/hwcap.h for MIPS CPU features.
*/
#ifndef __ASM_CPUFEATURE_H
#define __ASM_CPUFEATURE_H
#include <uapi/asm/hwcap.h>
#include <asm/elf.h>
#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
#define cpu_feature(x) ilog2(HWCAP_ ## x)
static inline bool cpu_have_feature(unsigned int num)
{
return elf_hwcap & (1UL << num);
}
#endif /* __ASM_CPUFEATURE_H */
linux-7.2.3/arch/mips/include/asm/debug.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
*/
#ifndef __MIPS_ASM_DEBUG_H__
#define __MIPS_ASM_DEBUG_H__
#include <linux/dcache.h>
/*
* mips_debugfs_dir corresponds to the "mips" directory at the top level
* of the DebugFS hierarchy. MIPS-specific DebugFS entries should be
* placed beneath this directory.
*/
extern struct dentry *mips_debugfs_dir;
#endif /* __MIPS_ASM_DEBUG_H__ */
linux-7.2.3/arch/mips/include/asm/dec/ecc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/ecc.h
*
* ECC handling logic definitions common to DECstation/DECsystem
* 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
* DECsystem 5900 (KN03), 5900/260 (KN05) systems.
*
* Copyright (C) 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_ECC_H
#define __ASM_MIPS_DEC_ECC_H
/*
* Error Address Register bits.
* The register is r/wc -- any write clears it.
*/
#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */
#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */
#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */
#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */
#define KN0X_EAR_RES_27 (1<<27) /* unused */
#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */
/*
* Error Syndrome Register bits.
* The register is frozen when EAR.VALID is set, otherwise it records bits
* from the last memory read. The register is r/wc -- any write clears it.
*/
#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */
#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */
#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */
#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */
#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */
#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */
#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */
#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */
#ifndef __ASSEMBLER__
#include <linux/interrupt.h>
struct pt_regs;
extern void dec_ecc_be_init(void);
extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
#endif
#endif /* __ASM_MIPS_DEC_ECC_H */
linux-7.2.3/arch/mips/include/asm/dec/interrupts.h
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/*
* Miscellaneous definitions used to initialise the interrupt vector table
* with the machine-specific interrupt routines.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997 by Paul M. Antoine.
* reworked 1998 by Harald Koerfgen.
* Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_INTERRUPTS_H
#define __ASM_DEC_INTERRUPTS_H
#include <irq.h>
#include <asm/mipsregs.h>
/*
* The list of possible system devices which provide an
* interrupt. Not all devices exist on a given system.
*/
#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
/* Ordinary interrupts */
#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */
#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */
#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */
#define DEC_IRQ_FPU 6 /* R3k FPU */
#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */
#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */
#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */
#define DEC_IRQ_PSU 11 /* power supply unit warning */
#define DEC_IRQ_RTC 12 /* DS1287 RTC */
#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */
#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */
#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */
#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */
#define DEC_IRQ_TIMER 19 /* ARC periodic timer */
#define DEC_IRQ_VIDEO 20 /* framebuffer */
/* I/O ASIC DMA interrupts */
#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */
#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */
#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */
#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */
#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */
#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */
#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */
#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */
#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */
#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */
#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */
#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */
#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */
#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */
#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */
#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */
#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */
#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */
#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */
/* TC5 & TC6 are virtual slots for KN02's onboard devices */
#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */
#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */
#define DEC_NR_INTS 41
/* Largest of cpu mask_nr tables. */
#define DEC_MAX_CPU_INTS 6
/* Largest of asic mask_nr tables. */
#define DEC_MAX_ASIC_INTS 9
/*
* CPU interrupt bits common to all systems.
*/
#define DEC_CPU_INR_FPU 7 /* R3k FPU */
#define DEC_CPU_INR_SW1 1 /* software #1 */
#define DEC_CPU_INR_SW0 0 /* software #0 */
#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
#ifndef __ASSEMBLER__
/*
* Interrupt table structures to hide differences between systems.
*/
typedef union { int i; void *p; } int_ptr;
extern int dec_interrupt[DEC_NR_INTS];
extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
extern int cpu_fpu_mask;
/*
* Common interrupt routine prototypes for all DECStations
*/
extern void kn02_io_int(void);
extern void kn02xa_io_int(void);
extern void kn03_io_int(void);
extern void asic_dma_int(void);
extern void asic_all_int(void);
extern void kn02_all_int(void);
extern void cpu_all_int(void);
extern void dec_intr_unimplemented(void);
extern void asic_intr_unimplemented(void);
#endif /* __ASSEMBLER__ */
#endif
linux-7.2.3/arch/mips/include/asm/dec/ioasic.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/ioasic.h
*
* DEC I/O ASIC access operations.
*
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_IOASIC_H
#define __ASM_DEC_IOASIC_H
#include <linux/spinlock.h>
#include <linux/types.h>
extern spinlock_t ioasic_ssr_lock;
extern volatile u32 *ioasic_base;
static inline void ioasic_write(unsigned int reg, u32 v)
{
ioasic_base[reg / 4] = v;
}
static inline u32 ioasic_read(unsigned int reg)
{
return ioasic_base[reg / 4];
}
extern void init_ioasic_irqs(int base);
extern int dec_ioasic_clocksource_init(void);
#endif /* __ASM_DEC_IOASIC_H */
linux-7.2.3/arch/mips/include/asm/dec/ioasic_addrs.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Definitions for the address map in the JUNKIO Asic
*
* Created with Information from:
*
* "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
*
* and the Mach Sources
*
* Copyright (C) 199x the Anonymous
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define IOASIC_SLOT_SIZE 0x00040000
/*
* Address ranges decoded by the I/O ASIC for onboard devices.
*/
#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */
#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */
#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */
#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */
#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */
#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */
#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */
#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
/*
* Offsets for I/O ASIC registers
* (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
*/
/* all systems */
#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */
#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */
#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */
/* except Maxine */
#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */
#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */
/* Maxine */
#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */
#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */
#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */
#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */
#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */
#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
/* all systems */
#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
/* all systems */
#define IO_REG_SSR 0x100 /* System Support Register */
#define IO_REG_SIR 0x110 /* System Interrupt Register */
#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */
#define IO_REG_SAR 0x130 /* System Address Register */
/* Maxine */
#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */
#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */
/* all systems */
#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */
#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */
#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */
/* except Maxine */
#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */
/* Maxine */
#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */
#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */
/* all systems */
#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */
#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */
#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
#define IO_REG_RES_31 0x1f0 /* unused */
/*
* The upper 16 bits of the System Support Register are a part of the
* I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
* machines. The exception is the Maxine, which makes use of the
* FLOPPY and ISDN bits (otherwise unused) and has a different SCC
* wiring.
*/
/* all systems */
#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */
#define IO_SSR_RES_27 (1<<27) /* unused */
#define IO_SSR_RES_26 (1<<26) /* unused */
#define IO_SSR_RES_25 (1<<25) /* unused */
#define IO_SSR_RES_24 (1<<24) /* unused */
#define IO_SSR_RES_23 (1<<23) /* unused */
#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */
#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */
#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */
/* except Maxine */
#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */
#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */
#define IO_SSR_RES_22 (1<<22) /* unused */
#define IO_SSR_RES_21 (1<<21) /* unused */
#define IO_SSR_RES_20 (1<<20) /* unused */
#define IO_SSR_RES_19 (1<<19) /* unused */
/* Maxine */
#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */
#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */
#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */
#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */
#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */
#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */
/*
* The lower 16 bits are system-specific. Bits 15,11:8 are common and
* defined here. The rest is defined in system-specific headers.
*/
#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */
#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */
#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */
#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */
#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */
#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
linux-7.2.3/arch/mips/include/asm/dec/ioasic_ints.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Definitions for the interrupt related bits in the I/O ASIC
* interrupt status register (and the interrupt mask register, of course)
*
* Created with Information from:
*
* "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
*
* and the Mach Sources
*
* Copyright (C) 199x the Anonymous
* Copyright (C) 2002 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_IOASIC_INTS_H
#define __ASM_DEC_IOASIC_INTS_H
/*
* The upper 16 bits are a part of the I/O ASIC's internal DMA engine
* and thus are common to all I/O ASIC machines. The exception is
* the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
* unused) and has a different SCC wiring.
*/
/* all systems */
#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */
#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */
#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */
#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */
#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */
#define IO_INR_ASC_ERR 18 /* ASC page overrun */
#define IO_INR_ASC_MERR 17 /* ASC memory read error */
#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */
/* except Maxine */
#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */
#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */
#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */
#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */
#define IO_INR_RES_23 23 /* unused */
#define IO_INR_RES_22 22 /* unused */
#define IO_INR_RES_21 21 /* unused */
#define IO_INR_RES_20 20 /* unused */
/* Maxine */
#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */
#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */
#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */
#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */
#define IO_INR_FLOPPY_ERR 23 /* FDC error */
#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */
#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */
#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */
#define IO_INR_DMA 16 /* first DMA IRQ */
/*
* The lower 16 bits are system-specific and thus defined in
* system-specific headers.
*/
#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */
#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */
#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)
#define IO_IRQ_MASK(n) (1 << (n))
#define IO_IRQ_ALL 0x0000ffff
#define IO_IRQ_DMA 0xffff0000
#endif /* __ASM_DEC_IOASIC_INTS_H */
linux-7.2.3/arch/mips/include/asm/dec/kn01.h
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/*
* Hardware info about DECstation DS2100/3100 systems (otherwise known as
* pmin/pmax or KN01).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN01_H
#define __ASM_MIPS_DEC_KN01_H
#define KN01_SLOT_BASE 0x10000000
#define KN01_SLOT_SIZE 0x01000000
/*
* Address ranges for devices.
*/
#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */
#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */
#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */
#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */
#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */
#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */
#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */
#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */
#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */
#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */
#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */
#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */
#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */
#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */
#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */
#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
/*
* Frame buffer memory address.
*/
#define KN01_VFB_MEM 0x0fc00000
/*
* CPU interrupt bits.
*/
#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */
#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */
#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */
#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */
/*
* System Control & Status Register bits.
*/
#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */
#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
#ifndef __ASSEMBLER__
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/types.h>
struct pt_regs;
extern u16 cached_kn01_csr;
extern void dec_kn01_be_init(void);
extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id);
#endif
#endif /* __ASM_MIPS_DEC_KN01_H */
linux-7.2.3/arch/mips/include/asm/dec/kn02.h
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/*
* Hardware info about DECstation 5000/200 systems (otherwise known as
* 3max or KN02).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN02_H
#define __ASM_MIPS_DEC_KN02_H
#define KN02_SLOT_BASE 0x1fc00000
#define KN02_SLOT_SIZE 0x00080000
/*
* Address ranges decoded by the "system slot" logic for onboard devices.
*/
#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */
#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */
#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */
#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */
#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */
#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */
#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */
#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
/*
* System Control & Status Register bits.
*/
#define KN02_CSR_RES_28 (0xf<<28) /* unused */
#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */
#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */
#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
/*
* CPU interrupt bits.
*/
#define KN02_CPU_INR_RES_6 6 /* unused */
#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
#define KN02_CPU_INR_RES_4 4 /* unused */
#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */
#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
/*
* CSR interrupt bits.
*/
#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */
#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */
#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */
#define KN02_CSR_INR_RES_4 4 /* unused */
#define KN02_CSR_INR_RES_3 3 /* unused */
#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */
#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */
#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */
#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
#define KN02_IRQ_LINES 8 /* number of CSR interrupts */
#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE)
#define KN02_IRQ_MASK(n) (1 << (n))
#define KN02_IRQ_ALL 0xff
#ifndef __ASSEMBLER__
#include <linux/types.h>
extern u32 cached_kn02_csr;
extern void init_kn02_irqs(int base);
#endif
#endif /* __ASM_MIPS_DEC_KN02_H */
linux-7.2.3/arch/mips/include/asm/dec/kn02ba.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn02ba.h
*
* DECstation 5000/1xx (3min or KN02-BA) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN02BA_H
#define __ASM_MIPS_DEC_KN02BA_H
#include <asm/dec/kn02xa.h> /* For common definitions. */
/*
* CPU interrupt bits.
*/
#define KN02BA_CPU_INR_HALT 6 /* HALT button */
#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */
#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */
#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */
/*
* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
*/
#define KN02BA_IO_INR_RES_15 15 /* unused */
#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
#define KN02BA_IO_INR_RES_13 13 /* unused */
#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */
#define KN02BA_IO_INR_RES_11 11 /* unused */
#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */
#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */
#define KN02BA_IO_INR_RES_3 3 /* unused */
#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */
#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */
/*
* Memory Error Register bits.
*/
#define KN02BA_MER_RES_27 (1<<27) /* unused */
/*
* Memory Size Register bits.
*/
#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */
/*
* I/O ASIC System Support Register bits.
*/
#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */
#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
#endif /* __ASM_MIPS_DEC_KN02BA_H */
linux-7.2.3/arch/mips/include/asm/dec/kn02ca.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn02ca.h
*
* Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN02CA_H
#define __ASM_MIPS_DEC_KN02CA_H
#include <asm/dec/kn02xa.h> /* For common definitions. */
/*
* CPU interrupt bits.
*/
#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */
#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */
#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */
#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */
/*
* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
*/
#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */
#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */
#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */
#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */
#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */
#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */
#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */
#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */
#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */
#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */
#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */
#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */
/*
* Memory Error Register bits.
*/
#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */
/*
* Memory Size Register bits.
*/
#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */
#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */
#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */
#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */
#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */
/*
* I/O ASIC System Support Register bits.
*/
#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */
#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */
#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */
#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */
#define KN03CA_IO_SSR_LED (1<<0) /* power LED */
#endif /* __ASM_MIPS_DEC_KN02CA_H */
linux-7.2.3/arch/mips/include/asm/dec/kn02xa.h
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/*
* Hardware info common to DECstation 5000/1xx systems (otherwise
* known as 3min or kn02ba) and Personal DECstations 5000/xx ones
* (otherwise known as maxine or kn02ca).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
*
* These are addresses which have to be known early in the boot process.
* For other addresses refer to tc.h, ioasic_addrs.h and friends.
*/
#ifndef __ASM_MIPS_DEC_KN02XA_H
#define __ASM_MIPS_DEC_KN02XA_H
#include <asm/dec/ioasic_addrs.h>
#define KN02XA_SLOT_BASE 0x1c000000
/*
* Memory control ASIC registers.
*/
#define KN02XA_MER 0x0c400000 /* memory error register */
#define KN02XA_MSR 0x0c800000 /* memory size register */
/*
* CPU control ASIC registers.
*/
#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
#define KN02XA_EAR 0x0e000004 /* error address register */
#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
/*
* Memory Error Register bits, common definitions.
* The rest is defined in system-specific headers.
*/
#define KN02XA_MER_RES_28 (0xf<<28) /* unused */
#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
#define KN02XA_MER_RES_12 (1<<12) /* unused */
#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
/*
* Memory Size Register bits, common definitions.
* The rest is defined in system-specific headers.
*/
#define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */
#define KN02XA_MSR_RES_14 (0x7<<14) /* unused */
#define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */
#define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */
/*
* Error Address Register bits.
*/
#define KN02XA_EAR_RES_29 (0x7<<29) /* unused */
#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
#ifndef __ASSEMBLER__
#include <linux/interrupt.h>
struct pt_regs;
extern void dec_kn02xa_be_init(void);
extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id);
#endif
#endif /* __ASM_MIPS_DEC_KN02XA_H */
linux-7.2.3/arch/mips/include/asm/dec/kn03.h
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/*
* Hardware info about DECstation 5000/2x0 systems (otherwise known as
* 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
* differ mechanically but are otherwise identical (both are known as
* KN03).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN03_H
#define __ASM_MIPS_DEC_KN03_H
#include <asm/dec/ecc.h>
#include <asm/dec/ioasic_addrs.h>
#define KN03_SLOT_BASE 0x1f800000
/*
* CPU interrupt bits.
*/
#define KN03_CPU_INR_HALT 6 /* HALT button */
#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
#define KN03_CPU_INR_RES_4 4 /* unused */
#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */
#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */
/*
* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
*/
#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */
#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */
#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */
#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */
#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
#define KN03_IO_INR_RTC 5 /* DS1287 RTC */
#define KN03_IO_INR_PSU 4 /* power supply unit warning */
#define KN03_IO_INR_RES_3 3 /* unused */
#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */
#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */
/*
* Memory Control Register bits.
*/
#define KN03_MCR_RES_16 (0xffff<<16) /* unused */
#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */
#define KN03_MCR_RES_11 (0x3<<12) /* unused */
#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */
#define KN03_MCR_RES_7 (0x7<<7) /* unused */
#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */
/*
* I/O ASIC System Support Register bits.
*/
#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
#define KN03_IO_SSR_RES_12 (1<<12) /* unused */
#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
#endif /* __ASM_MIPS_DEC_KN03_H */
linux-7.2.3/arch/mips/include/asm/dec/kn05.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn05.h
*
* DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
* or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
* KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
* definitions.
*
* Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
*
* WARNING! All this information is pure guesswork based on the
* ROM. It is provided here in hope it will give someone some
* food for thought. No documentation for the KN05 nor the KN04
* module has been located so far.
*/
#ifndef __ASM_MIPS_DEC_KN05_H
#define __ASM_MIPS_DEC_KN05_H
#include <asm/dec/ioasic_addrs.h>
/*
* The oncard MB (Memory Buffer) ASIC provides an additional address
* decoder. Certain address ranges within the "high" 16 slots are
* passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
* Others are handled locally. "Low" slots are always passed.
*/
#define KN4K_SLOT_BASE 0x1fc00000
#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
/*
* MB ASIC interrupt bits.
*/
#define KN4K_MB_INR_MB 4 /* ??? */
#define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */
#define KN4K_MB_INR_RES_2 2 /* unused */
#define KN4K_MB_INR_RTC 1 /* RTC */
#define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */
/*
* Bits for the MB interrupt register.
* The register appears read-only.
*/
#define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */
#define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */
/*
* Bits for the MB control & status register.
* Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
*/
#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
#define KN4K_MB_CSR_F (1<<1) /* ??? */
#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
#define KN4K_MB_CSR_OD (1<<10) /* ??? */
#define KN4K_MB_CSR_CP (1<<11) /* ??? */
#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
#define KN4K_MB_CSR_IM (1<<13) /* ??? */
#define KN4K_MB_CSR_NC (1<<14) /* ??? */
#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
#define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */
#define KN4K_MB_CSR_FW (1<<21) /* ??? */
#define KN4K_MB_CSR_W (1<<31) /* ??? */
#endif /* __ASM_MIPS_DEC_KN05_H */
linux-7.2.3/arch/mips/include/asm/dec/kn230.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn230.h
*
* DECsystem 5100 (MIPSmate or KN230) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN230_H
#define __ASM_MIPS_DEC_KN230_H
/*
* CPU interrupt bits.
*/
#define KN230_CPU_INR_HALT 6 /* HALT button */
#define KN230_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
#define KN230_CPU_INR_RTC 4 /* DS1287 RTC */
#define KN230_CPU_INR_SII 3 /* SII (DC7061) SCSI */
#define KN230_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
#define KN230_CPU_INR_DZ11 2 /* DZ11 (DC7085) serial */
#endif /* __ASM_MIPS_DEC_KN230_H */
linux-7.2.3/arch/mips/include/asm/dec/machtype.h
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/*
* Various machine type macros
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1998, 2000 Harald Koerfgen
*/
#ifndef __ASM_DEC_MACHTYPE_H
#define __ASM_DEC_MACHTYPE_H
#include <asm/bootinfo.h>
#define TURBOCHANNEL (mips_machtype == MACH_DS5000_200 || \
mips_machtype == MACH_DS5000_1XX || \
mips_machtype == MACH_DS5000_XX || \
mips_machtype == MACH_DS5000_2X0 || \
mips_machtype == MACH_DS5900)
#define IOASIC (mips_machtype == MACH_DS5000_1XX || \
mips_machtype == MACH_DS5000_XX || \
mips_machtype == MACH_DS5000_2X0 || \
mips_machtype == MACH_DS5900)
#endif
linux-7.2.3/arch/mips/include/asm/dec/prom.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/prom.h
*
* DECstation PROM interface.
*
* Copyright (C) 2002, 2026 Maciej W. Rozycki
*
* Based on arch/mips/dec/prom/prom.h by the Anonymous.
*/
#ifndef _ASM_DEC_PROM_H
#define _ASM_DEC_PROM_H
#include <linux/types.h>
#include <asm/addrspace.h>
/*
* PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
* Many of these will work for MIPSen as well!
*/
#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)
/* Prom base address */
#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */
#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */
#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */
#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6)
#define PMAX_PROM_READ PMAX_PROM_ENTRY(7)
#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10)
#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11)
#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12)
#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */
#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15)
#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17)
#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */
/*
* Magic number indicating REX PROM available on DECstation. Found in
* register a2 on transfer of control to program from PROM.
*/
#define REX_PROM_MAGIC 0x30464354
/* KN04 and KN05 are REX PROMs, so only do the check for R3k systems. */
static inline bool prom_is_rex(u32 magic)
{
return !IS_ENABLED(CONFIG_CPU_R3000) || magic == REX_PROM_MAGIC;
}
/*
* 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
* DS5000/2x0.
*/
#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */
#define REX_PROM_GETCHAR 0x24/4 /* getch() */
#define REX_PROM_GETENV 0x64/4 /* get env. variable */
#define REX_PROM_GETSYSID 0x80/4 /* get system id */
#define REX_PROM_GETTCINFO 0xa4/4
#define REX_PROM_PRINTF 0x30/4 /* printf() */
#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */
#define REX_PROM_BOOTINIT 0x54/4 /* open() */
#define REX_PROM_BOOTREAD 0x58/4 /* read() */
#define REX_PROM_CLEARCACHE 0x7c/4
/*
* Used by rex_getbitmap().
*/
typedef struct {
int pagesize;
unsigned char bitmap[];
} memmap;
/*
* Function pointers as read from a PROM's callback vector.
*/
extern int (*__rex_bootinit)(void);
extern int (*__rex_bootread)(void);
extern int (*__rex_getbitmap)(memmap *);
extern unsigned long *(*__rex_slot_address)(int);
extern void *(*__rex_gettcinfo)(void);
extern int (*__rex_getsysid)(void);
extern void (*__rex_clear_cache)(void);
extern int (*__prom_getchar)(void);
extern char *(*__prom_getenv)(char *);
extern int (*__prom_printf)(char *, ...);
extern int (*__pmax_open)(char*, int);
extern int (*__pmax_lseek)(int, long, int);
extern int (*__pmax_read)(int, void *, int);
extern int (*__pmax_close)(int);
#ifdef CONFIG_64BIT
#define O32_STK_SIZE 512
extern unsigned long o32_stk[];
/* Switch the stack if outside the 32-bit address space. */
static inline unsigned long *o32_get_stk(void)
{
long fp = (long)__builtin_frame_address(0);
return fp != (int)fp ? o32_stk + O32_STK_SIZE : NULL;
}
/*
* On MIPS64 we have to call PROM functions via a helper
* dispatcher to accommodate ABI incompatibilities.
*/
#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
__asm__(#fun " = call_o32")
int __DEC_PROM_O32(_rex_bootinit, (int (*)(void), void *));
int __DEC_PROM_O32(_rex_bootread, (int (*)(void), void *));
int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), void *, memmap *));
unsigned long *__DEC_PROM_O32(_rex_slot_address,
(unsigned long *(*)(int), void *, int));
void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void), void *));
int __DEC_PROM_O32(_rex_getsysid, (int (*)(void), void *));
void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void), void *));
int __DEC_PROM_O32(_prom_getchar, (int (*)(void), void *));
char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), void *, char *));
int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), void *, char *, ...));
#define rex_bootinit() _rex_bootinit(__rex_bootinit, NULL)
#define rex_bootread() _rex_bootread(__rex_bootread, NULL)
#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, NULL, x)
#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, NULL, x)
#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo, NULL)
#define rex_getsysid() _rex_getsysid(__rex_getsysid, NULL)
#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache, NULL)
#define prom_getchar() _prom_getchar(__prom_getchar, NULL)
#define prom_getenv(x) _prom_getenv(__prom_getenv, NULL, x)
#define prom_printf(x...) _prom_printf(__prom_printf, o32_get_stk(), x)
#else /* !CONFIG_64BIT */
/*
* On plain MIPS we just call PROM functions directly.
*/
#define rex_bootinit __rex_bootinit
#define rex_bootread __rex_bootread
#define rex_getbitmap __rex_getbitmap
#define rex_slot_address __rex_slot_address
#define rex_gettcinfo __rex_gettcinfo
#define rex_getsysid __rex_getsysid
#define rex_clear_cache __rex_clear_cache
#define prom_getchar __prom_getchar
#define prom_getenv __prom_getenv
#define prom_printf __prom_printf
#define pmax_open __pmax_open
#define pmax_lseek __pmax_lseek
#define pmax_read __pmax_read
#define pmax_close __pmax_close
#endif /* !CONFIG_64BIT */
extern void prom_meminit(u32);
extern void prom_identify_arch(u32);
extern void prom_init_cmdline(s32, s32 *, u32);
extern void register_prom_console(void);
#endif /* _ASM_DEC_PROM_H */
linux-7.2.3/arch/mips/include/asm/dec/reset.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/mips/include/asm/dec/reset.h
*
* DECstation/DECsystem halt/reset support.
*
* Copyright (C) 2026 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_RESET_H
#define __ASM_DEC_RESET_H
#include <linux/compiler_attributes.h>
void __noreturn dec_machine_restart(char *command);
void __noreturn dec_machine_halt(void);
void __noreturn dec_machine_power_off(void);
irqreturn_t dec_intr_halt(int irq, void *dev_id);
#endif /* __ASM_DEC_RESET_H */
linux-7.2.3/arch/mips/include/asm/dec/system.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/system.h
*
* Generic DECstation/DECsystem bits.
*
* Copyright (C) 2005, 2006 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_SYSTEM_H
#define __ASM_DEC_SYSTEM_H
extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
extern int dec_tc_bus;
#endif /* __ASM_DEC_SYSTEM_H */
linux-7.2.3/arch/mips/include/asm/delay.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 by Waldorf Electronics
* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki
*/
#ifndef _ASM_DELAY_H
#define _ASM_DELAY_H
#include <linux/param.h>
extern void __delay(unsigned long loops);
extern void __ndelay(unsigned long ns);
extern void __udelay(unsigned long us);
#define ndelay(ns) __ndelay(ns)
#define udelay(us) __udelay(us)
/* make sure "usecs *= ..." in udelay do not overflow. */
#if HZ >= 1000
#define MAX_UDELAY_MS 1
#elif HZ <= 200
#define MAX_UDELAY_MS 5
#else
#define MAX_UDELAY_MS (1000 / HZ)
#endif
#endif /* _ASM_DELAY_H */
linux-7.2.3/arch/mips/include/asm/div64.h
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/*
* Copyright (C) 2000, 2004, 2021 Maciej W. Rozycki
* Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_DIV64_H
#define __ASM_DIV64_H
#include <asm/bitsperlong.h>
#if BITS_PER_LONG == 32
/*
* No traps on overflows for any of these...
*/
#define do_div64_32(res, high, low, base) ({ \
unsigned long __cf, __tmp, __tmp2, __i; \
unsigned long __quot32, __mod32; \
\
__asm__( \
" .set push \n" \
" .set noat \n" \
" .set noreorder \n" \
" move %2, $0 \n" \
" move %3, $0 \n" \
" b 1f \n" \
" li %4, 0x21 \n" \
"0: \n" \
" sll $1, %0, 0x1 \n" \
" srl %3, %0, 0x1f \n" \
" or %0, $1, %5 \n" \
" sll %1, %1, 0x1 \n" \
" sll %2, %2, 0x1 \n" \
"1: \n" \
" bnez %3, 2f \n" \
" sltu %5, %0, %z6 \n" \
" bnez %5, 3f \n" \
"2: \n" \
" addiu %4, %4, -1 \n" \
" subu %0, %0, %z6 \n" \
" addiu %2, %2, 1 \n" \
"3: \n" \
" bnez %4, 0b \n" \
" srl %5, %1, 0x1f \n" \
" .set pop" \
: "=&r" (__mod32), "=&r" (__tmp), \
"=&r" (__quot32), "=&r" (__cf), \
"=&r" (__i), "=&r" (__tmp2) \
: "Jr" (base), "0" (high), "1" (low)); \
\
(res) = __quot32; \
__mod32; \
})
#define __div64_32(n, base) ({ \
unsigned long __upper, __low, __high, __radix; \
unsigned long long __quot; \
unsigned long long __div; \
unsigned long __mod; \
\
__div = (*n); \
__radix = (base); \
\
__high = __div >> 32; \
__low = __div; \
\
if (__high < __radix) { \
__upper = __high; \
__high = 0; \
} else { \
__upper = __high % __radix; \
__high /= __radix; \
} \
\
__mod = do_div64_32(__low, __upper, __low, __radix); \
\
__quot = __high; \
__quot = __quot << 32 | __low; \
(*n) = __quot; \
__mod; \
})
#endif /* BITS_PER_LONG == 32 */
#include <asm-generic/div64.h>
#endif /* __ASM_DIV64_H */
linux-7.2.3/arch/mips/include/asm/dma-direct.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _MIPS_DMA_DIRECT_H
#define _MIPS_DMA_DIRECT_H 1
dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
#endif /* _MIPS_DMA_DIRECT_H */
linux-7.2.3/arch/mips/include/asm/dma-mapping.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
#include <linux/swiotlb.h>
extern const struct dma_map_ops jazz_dma_ops;
static inline const struct dma_map_ops *get_arch_dma_ops(void)
{
#if defined(CONFIG_MACH_JAZZ)
return &jazz_dma_ops;
#else
return NULL;
#endif
}
#endif /* _ASM_DMA_MAPPING_H */
linux-7.2.3/arch/mips/include/asm/dma.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/include/asm/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
*
* NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
* and can only be used for expansion cards. Onboard DMA controllers, such
* as the R4030 on Jazz boards behave totally different!
*/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <asm/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb outb_p
#else
#define dma_outb outb
#endif
#define dma_inb inb
/*
* NOTES about DMA transfers:
*
* controller 1: channels 0-3, byte operations, ports 00-1F
* controller 2: channels 4-7, word operations, ports C0-DF
*
* - ALL registers are 8 bits only, regardless of transfer size
* - channel 4 is not used - cascades 1 into 2.
* - channels 0-3 are byte - addresses/counts are for physical bytes
* - channels 5-7 are word - addresses/counts are for physical words
* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
* - transfer count loaded to registers is 1 less than actual count
* - controller 2 offsets are all even (2x offsets for controller 1)
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
* DMA transfers are limited to the lower 16MB of _physical_ memory.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
* Address mapping for channels 0-3:
*
* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
*
* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
* the hardware level, so odd-byte transfers aren't possible).
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
* and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
#define MAX_DMA_CHANNELS 8
#endif
/*
* The maximum address in KSEG0 that we can perform a DMA transfer to on this
* platform. This describes only the PC style part of the DMA logic like on
* Deskstations or Acer PICA but not the much more versatile DMA logic used
* for the local devices on Acer PICA or Magnums.
*/
#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
#define MAX_DMA_ADDRESS PAGE_OFFSET
#else
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
#ifndef MAX_DMA32_PFN
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
#endif
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG 0x08 /* command register (w) */
#define DMA1_STAT_REG 0x08 /* status register (r) */
#define DMA1_REQ_REG 0x09 /* request register (w) */
#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
#define DMA1_MODE_REG 0x0B /* mode register (w) */
#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
#define DMA2_CMD_REG 0xD0 /* command register (w) */
#define DMA2_STAT_REG 0xD0 /* status register (r) */
#define DMA2_REQ_REG 0xD2 /* request register (w) */
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
#define DMA2_MODE_REG 0xD6 /* mode register (w) */
#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
#define DMA_ADDR_0 0x00 /* DMA address registers */
#define DMA_ADDR_1 0x02
#define DMA_ADDR_2 0x04
#define DMA_ADDR_3 0x06
#define DMA_ADDR_4 0xC0
#define DMA_ADDR_5 0xC4
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01 /* DMA count registers */
#define DMA_CNT_1 0x03
#define DMA_CNT_2 0x05
#define DMA_CNT_3 0x07
#define DMA_CNT_4 0xC2
#define DMA_CNT_5 0xC6
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_PAGE_0 0x87 /* DMA page registers */
#define DMA_PAGE_1 0x83
#define DMA_PAGE_2 0x81
#define DMA_PAGE_3 0x82
#define DMA_PAGE_5 0x8B
#define DMA_PAGE_6 0x89
#define DMA_PAGE_7 0x8A
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr, DMA1_MASK_REG);
else
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
static __inline__ void disable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(0, DMA1_CLEAR_FF_REG);
else
dma_outb(0, DMA2_CLEAR_FF_REG);
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
if (dmanr<=3)
dma_outb(mode | dmanr, DMA1_MODE_REG);
else
dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
}
/* Set only the page register bits of the transfer address.
* This is used for successive transfers when we know the contents of
* the lower 16 bits of the DMA current address register, but a 64k boundary
* may have been crossed.
*/
static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
{
switch(dmanr) {
case 0:
dma_outb(pagenr, DMA_PAGE_0);
break;
case 1:
dma_outb(pagenr, DMA_PAGE_1);
break;
case 2:
dma_outb(pagenr, DMA_PAGE_2);
break;
case 3:
dma_outb(pagenr, DMA_PAGE_3);
break;
case 5:
dma_outb(pagenr & 0xfe, DMA_PAGE_5);
break;
case 6:
dma_outb(pagenr & 0xfe, DMA_PAGE_6);
break;
case 7:
dma_outb(pagenr & 0xfe, DMA_PAGE_7);
break;
}
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
set_dma_page(dmanr, a>>16);
if (dmanr <= 3) {
dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
} else {
dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
}
}
/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
} else {
dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr<=3)? count : (count<<1);
}
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#endif /* _ASM_DMA_H */
linux-7.2.3/arch/mips/include/asm/dmi.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_DMI_H
#define _ASM_DMI_H
#include <linux/io.h>
#include <linux/memblock.h>
#define dmi_early_remap(x, l) ioremap(x, l)
#define dmi_early_unmap(x, l) iounmap(x)
#define dmi_remap(x, l) ioremap_cache(x, l)
#define dmi_unmap(x) iounmap(x)
/* MIPS initialize DMI scan before SLAB is ready, so we use memblock here */
#define dmi_alloc(l) memblock_alloc_low(l, PAGE_SIZE)
#if defined(CONFIG_MACH_LOONGSON64)
#define SMBIOS_ENTRY_POINT_SCAN_START 0xFFFE000
#endif
#endif /* _ASM_DMI_H */
linux-7.2.3/arch/mips/include/asm/ds1287.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* DS1287 timer functions.
*
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*/
#ifndef __ASM_DS1287_H
#define __ASM_DS1287_H
extern int ds1287_timer_state(void);
extern int ds1287_set_base_clock(unsigned int hz);
extern int ds1287_clockevent_init(int irq);
#endif
linux-7.2.3/arch/mips/include/asm/dsemul.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
*/
#ifndef __MIPS_ASM_DSEMUL_H__
#define __MIPS_ASM_DSEMUL_H__
#include <asm/break.h>
#include <asm/inst.h>
/* Break instruction with special math emu break code set */
#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16))
/* When used as a frame index, indicates the lack of a frame */
#define BD_EMUFRAME_NONE ((int)BIT(31))
struct mm_struct;
struct pt_regs;
struct task_struct;
/**
* mips_dsemul() - 'Emulate' an instruction from a branch delay slot
* @regs: User thread register context.
* @ir: The instruction to be 'emulated'.
* @branch_pc: The PC of the branch instruction.
* @cont_pc: The PC to continue at following 'emulation'.
*
* Emulate or execute an arbitrary MIPS instruction within the context of
* the current user thread. This is used primarily to handle instructions
* in the delay slots of emulated branch instructions, for example FP
* branch instructions on systems without an FPU.
*
* Return: Zero on success, negative if ir is a NOP, signal number on failure.
*/
extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
unsigned long branch_pc, unsigned long cont_pc);
/**
* do_dsemulret() - Return from a delay slot 'emulation' frame
* @xcp: User thread register context.
*
* Call in response to the BRK_MEMU break instruction used to return to
* the kernel from branch delay slot 'emulation' frames following a call
* to mips_dsemul(). Restores the user thread PC to the value that was
* passed as the cpc parameter to mips_dsemul().
*
* Return: True if an emulation frame was returned from, else false.
*/
#ifdef CONFIG_MIPS_FP_SUPPORT
extern bool do_dsemulret(struct pt_regs *xcp);
#else
static inline bool do_dsemulret(struct pt_regs *xcp)
{
return false;
}
#endif
/**
* dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
* @tsk: The task structure associated with the thread
*
* If the thread @tsk has a branch delay slot 'emulation' frame
* allocated to it then free that frame.
*
* Return: True if a frame was freed, else false.
*/
#ifdef CONFIG_MIPS_FP_SUPPORT
extern bool dsemul_thread_cleanup(struct task_struct *tsk);
#else
static inline bool dsemul_thread_cleanup(struct task_struct *tsk)
{
return false;
}
#endif
/**
* dsemul_thread_rollback() - Rollback from an 'emulation' frame
* @regs: User thread register context.
*
* If the current thread, whose register context is represented by @regs,
* is executing within a delay slot 'emulation' frame then exit that
* frame. The PC will be rolled back to the branch if the instruction
* that was being 'emulated' has not yet executed, or advanced to the
* continuation PC if it has.
*
* Return: True if a frame was exited, else false.
*/
#ifdef CONFIG_MIPS_FP_SUPPORT
extern bool dsemul_thread_rollback(struct pt_regs *regs);
#else
static inline bool dsemul_thread_rollback(struct pt_regs *regs)
{
return false;
}
#endif
/**
* dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
* @mm: The struct mm_struct to cleanup state for.
*
* Cleanup state for the given @mm, ensuring that any memory allocated
* for delay slot 'emulation' book-keeping is freed. This is to be called
* before @mm is freed in order to avoid memory leaks.
*/
#ifdef CONFIG_MIPS_FP_SUPPORT
extern void dsemul_mm_cleanup(struct mm_struct *mm);
#else
static inline void dsemul_mm_cleanup(struct mm_struct *mm)
{
/* no-op */
}
#endif
#endif /* __MIPS_ASM_DSEMUL_H__ */
linux-7.2.3/arch/mips/include/asm/dsp.h
+81
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2005 Mips Technologies
* Author: Chris Dearman, chris@mips.com derived from fpu.h
*/
#ifndef _ASM_DSP_H
#define _ASM_DSP_H
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/hazards.h>
#include <asm/mipsregs.h>
#define DSP_DEFAULT 0x00000000
#define DSP_MASK 0x3f
#define __enable_dsp_hazard() \
do { \
asm("_ehb"); \
} while (0)
static inline void __init_dsp(void)
{
mthi1(0);
mtlo1(0);
mthi2(0);
mtlo2(0);
mthi3(0);
mtlo3(0);
wrdsp(DSP_DEFAULT, DSP_MASK);
}
static inline void init_dsp(void)
{
if (cpu_has_dsp)
__init_dsp();
}
#define __save_dsp(tsk) \
do { \
tsk->thread.dsp.dspr[0] = mfhi1(); \
tsk->thread.dsp.dspr[1] = mflo1(); \
tsk->thread.dsp.dspr[2] = mfhi2(); \
tsk->thread.dsp.dspr[3] = mflo2(); \
tsk->thread.dsp.dspr[4] = mfhi3(); \
tsk->thread.dsp.dspr[5] = mflo3(); \
tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
} while (0)
#define save_dsp(tsk) \
do { \
if (cpu_has_dsp) \
__save_dsp(tsk); \
} while (0)
#define __restore_dsp(tsk) \
do { \
mthi1(tsk->thread.dsp.dspr[0]); \
mtlo1(tsk->thread.dsp.dspr[1]); \
mthi2(tsk->thread.dsp.dspr[2]); \
mtlo2(tsk->thread.dsp.dspr[3]); \
mthi3(tsk->thread.dsp.dspr[4]); \
mtlo3(tsk->thread.dsp.dspr[5]); \
wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
} while (0)
#define restore_dsp(tsk) \
do { \
if (cpu_has_dsp) \
__restore_dsp(tsk); \
} while (0)
#define __get_dsp_regs(tsk) \
({ \
if (tsk == current) \
__save_dsp(current); \
\
tsk->thread.dsp.dspr; \
})
#endif /* _ASM_DSP_H */
linux-7.2.3/arch/mips/include/asm/edac.h
+38
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef ASM_EDAC_H
#define ASM_EDAC_H
#include <asm/compiler.h>
/* ECC atomic, DMA, SMP and interrupt safe scrub function */
static inline void edac_atomic_scrub(void *va, u32 size)
{
unsigned long *virt_addr = va;
unsigned long temp;
u32 i;
for (i = 0; i < size / sizeof(unsigned long); i++) {
/*
* Very carefully read and write to memory atomically
* so we are interrupt, DMA and SMP safe.
*
* Intel: asm("lock; addl $0, %0"::"m"(*virt_addr));
*/
__asm__ __volatile__ (
" .set push \n"
" .set mips2 \n"
"1: ll %0, %1 # edac_atomic_scrub \n"
" addu %0, $0 \n"
" sc %0, %1 \n"
" beqz %0, 1b \n"
" .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)
: GCC_OFF_SMALL_ASM() (*virt_addr));
virt_addr++;
}
}
#endif
linux-7.2.3/arch/mips/include/asm/elf.h
+522
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Much of this is taken from binutils and GNU libc ...
*/
#ifndef _ASM_ELF_H
#define _ASM_ELF_H
#include <linux/auxvec.h>
#include <linux/fs.h>
#include <linux/mm_types.h>
#include <uapi/linux/elf.h>
#include <asm/current.h>
/* ELF header e_flags defines. */
/* MIPS architecture level. */
#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */
#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
#define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */
#define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */
/* The ABI of a file. */
#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */
#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */
#define PT_MIPS_REGINFO 0x70000000
#define PT_MIPS_RTPROC 0x70000001
#define PT_MIPS_OPTIONS 0x70000002
#define PT_MIPS_ABIFLAGS 0x70000003
/* Flags in the e_flags field of the header */
#define EF_MIPS_NOREORDER 0x00000001
#define EF_MIPS_PIC 0x00000002
#define EF_MIPS_CPIC 0x00000004
#define EF_MIPS_ABI2 0x00000020
#define EF_MIPS_OPTIONS_FIRST 0x00000080
#define EF_MIPS_32BITMODE 0x00000100
#define EF_MIPS_FP64 0x00000200
#define EF_MIPS_NAN2008 0x00000400
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_ARCH 0xf0000000
#define DT_MIPS_RLD_VERSION 0x70000001
#define DT_MIPS_TIME_STAMP 0x70000002
#define DT_MIPS_ICHECKSUM 0x70000003
#define DT_MIPS_IVERSION 0x70000004
#define DT_MIPS_FLAGS 0x70000005
#define RHF_NONE 0x00000000
#define RHF_HARDWAY 0x00000001
#define RHF_NOTPOT 0x00000002
#define RHF_SGI_ONLY 0x00000010
#define DT_MIPS_BASE_ADDRESS 0x70000006
#define DT_MIPS_CONFLICT 0x70000008
#define DT_MIPS_LIBLIST 0x70000009
#define DT_MIPS_LOCAL_GOTNO 0x7000000a
#define DT_MIPS_CONFLICTNO 0x7000000b
#define DT_MIPS_LIBLISTNO 0x70000010
#define DT_MIPS_SYMTABNO 0x70000011
#define DT_MIPS_UNREFEXTNO 0x70000012
#define DT_MIPS_GOTSYM 0x70000013
#define DT_MIPS_HIPAGENO 0x70000014
#define DT_MIPS_RLD_MAP 0x70000016
#define R_MIPS_NONE 0
#define R_MIPS_16 1
#define R_MIPS_32 2
#define R_MIPS_REL32 3
#define R_MIPS_26 4
#define R_MIPS_HI16 5
#define R_MIPS_LO16 6
#define R_MIPS_GPREL16 7
#define R_MIPS_LITERAL 8
#define R_MIPS_GOT16 9
#define R_MIPS_PC16 10
#define R_MIPS_CALL16 11
#define R_MIPS_GPREL32 12
/* The remaining relocs are defined on Irix, although they are not
in the MIPS ELF ABI. */
#define R_MIPS_UNUSED1 13
#define R_MIPS_UNUSED2 14
#define R_MIPS_UNUSED3 15
#define R_MIPS_SHIFT5 16
#define R_MIPS_SHIFT6 17
#define R_MIPS_64 18
#define R_MIPS_GOT_DISP 19
#define R_MIPS_GOT_PAGE 20
#define R_MIPS_GOT_OFST 21
/*
* The following two relocation types are specified in the MIPS ABI
* conformance guide version 1.2 but not yet in the psABI.
*/
#define R_MIPS_GOTHI16 22
#define R_MIPS_GOTLO16 23
#define R_MIPS_SUB 24
#define R_MIPS_INSERT_A 25
#define R_MIPS_INSERT_B 26
#define R_MIPS_DELETE 27
#define R_MIPS_HIGHER 28
#define R_MIPS_HIGHEST 29
/*
* The following two relocation types are specified in the MIPS ABI
* conformance guide version 1.2 but not yet in the psABI.
*/
#define R_MIPS_CALLHI16 30
#define R_MIPS_CALLLO16 31
/*
* Introduced for MIPSr6.
*/
#define R_MIPS_PC21_S2 60
#define R_MIPS_PC26_S2 61
/*
* This range is reserved for vendor specific relocations.
*/
#define R_MIPS_LOVENDOR 100
#define R_MIPS_HIVENDOR 127
#define R_MIPS_PC32 248
#define SHN_MIPS_ACCOMON 0xff00 /* Allocated common symbols */
#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */
#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */
#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */
#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */
#define SHT_MIPS_LIST 0x70000000
#define SHT_MIPS_CONFLICT 0x70000002
#define SHT_MIPS_GPTAB 0x70000003
#define SHT_MIPS_UCODE 0x70000004
#define SHT_MIPS_DEBUG 0x70000005
#define SHT_MIPS_REGINFO 0x70000006
#define SHT_MIPS_PACKAGE 0x70000007
#define SHT_MIPS_PACKSYM 0x70000008
#define SHT_MIPS_RELD 0x70000009
#define SHT_MIPS_IFACE 0x7000000b
#define SHT_MIPS_CONTENT 0x7000000c
#define SHT_MIPS_OPTIONS 0x7000000d
#define SHT_MIPS_SHDR 0x70000010
#define SHT_MIPS_FDESC 0x70000011
#define SHT_MIPS_EXTSYM 0x70000012
#define SHT_MIPS_DENSE 0x70000013
#define SHT_MIPS_PDESC 0x70000014
#define SHT_MIPS_LOCSYM 0x70000015
#define SHT_MIPS_AUXSYM 0x70000016
#define SHT_MIPS_OPTSYM 0x70000017
#define SHT_MIPS_LOCSTR 0x70000018
#define SHT_MIPS_LINE 0x70000019
#define SHT_MIPS_RFDESC 0x7000001a
#define SHT_MIPS_DELTASYM 0x7000001b
#define SHT_MIPS_DELTAINST 0x7000001c
#define SHT_MIPS_DELTACLASS 0x7000001d
#define SHT_MIPS_DWARF 0x7000001e
#define SHT_MIPS_DELTADECL 0x7000001f
#define SHT_MIPS_SYMBOL_LIB 0x70000020
#define SHT_MIPS_EVENTS 0x70000021
#define SHT_MIPS_TRANSLATE 0x70000022
#define SHT_MIPS_PIXIE 0x70000023
#define SHT_MIPS_XLATE 0x70000024
#define SHT_MIPS_XLATE_DEBUG 0x70000025
#define SHT_MIPS_WHIRL 0x70000026
#define SHT_MIPS_EH_REGION 0x70000027
#define SHT_MIPS_XLATE_OLD 0x70000028
#define SHT_MIPS_PDR_EXCEPTION 0x70000029
#define SHF_MIPS_GPREL 0x10000000
#define SHF_MIPS_MERGE 0x20000000
#define SHF_MIPS_ADDR 0x40000000
#define SHF_MIPS_STRING 0x80000000
#define SHF_MIPS_NOSTRIP 0x08000000
#define SHF_MIPS_LOCAL 0x04000000
#define SHF_MIPS_NAMES 0x02000000
#define SHF_MIPS_NODUPES 0x01000000
#define MIPS_ABI_FP_ANY 0 /* FP ABI doesn't matter */
#define MIPS_ABI_FP_DOUBLE 1 /* -mdouble-float */
#define MIPS_ABI_FP_SINGLE 2 /* -msingle-float */
#define MIPS_ABI_FP_SOFT 3 /* -msoft-float */
#define MIPS_ABI_FP_OLD_64 4 /* -mips32r2 -mfp64 */
#define MIPS_ABI_FP_XX 5 /* -mfpxx */
#define MIPS_ABI_FP_64 6 /* -mips32r2 -mfp64 */
#define MIPS_ABI_FP_64A 7 /* -mips32r2 -mfp64 -mno-odd-spreg */
struct mips_elf_abiflags_v0 {
uint16_t version; /* Version of flags structure */
uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below,
1-n otherwise */
uint8_t gpr_size; /* The size of general purpose registers */
uint8_t cpr1_size; /* The size of co-processor 1 registers */
uint8_t cpr2_size; /* The size of co-processor 2 registers */
uint8_t fp_abi; /* The floating-point ABI */
uint32_t isa_ext; /* Mask of processor-specific extensions */
uint32_t ases; /* Mask of ASEs used */
uint32_t flags1; /* Mask of general flags */
uint32_t flags2;
};
/* ELF register definitions */
#define ELF_NGREG 45
#define ELF_NFPREG 33
typedef unsigned long elf_greg_t;
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs);
void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs);
#ifdef CONFIG_32BIT
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch elf32_check_arch
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_CORE_COPY_REGS(dest, regs) \
mips_dump_regs32((u32 *)&(dest), (regs));
#endif /* CONFIG_32BIT */
#ifdef CONFIG_64BIT
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch elf64_check_arch
#define compat_elf_check_arch elf32_check_arch
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS64
#define ELF_CORE_COPY_REGS(dest, regs) \
mips_dump_regs64((u64 *)&(dest), (regs));
#endif /* CONFIG_64BIT */
/*
* These are used to set parameters in the core dumps.
*/
#ifdef __MIPSEB__
#define ELF_DATA ELFDATA2MSB
#elif defined(__MIPSEL__)
#define ELF_DATA ELFDATA2LSB
#endif
#define ELF_ARCH EM_MIPS
/*
* In order to be sure that we don't attempt to execute an O32 binary which
* requires 64 bit FP (FR=1) on a system which does not support it we refuse
* to execute any binary which has bits specified by the following macro set
* in its ELF header flags.
*/
#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
# define __MIPS_O32_FP64_MUST_BE_ZERO 0
#else
# define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64
#endif
#define mips_elf_check_machine(x) ((x)->e_machine == EM_MIPS)
#define vmcore_elf32_check_arch mips_elf_check_machine
#define vmcore_elf64_check_arch mips_elf_check_machine
/*
* Return non-zero if HDR identifies an o32 or n32 ELF binary.
*/
#define elf32_check_arch(hdr) \
({ \
int __res = 1; \
struct elfhdr *__h = (hdr); \
\
if (!mips_elf_check_machine(__h)) \
__res = 0; \
if (__h->e_ident[EI_CLASS] != ELFCLASS32) \
__res = 0; \
if ((__h->e_flags & EF_MIPS_ABI2) != 0) { \
if (!IS_ENABLED(CONFIG_MIPS32_N32) || \
(__h->e_flags & EF_MIPS_ABI)) \
__res = 0; \
} else { \
if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32)) \
__res = 0; \
if (((__h->e_flags & EF_MIPS_ABI) != 0) && \
((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \
__res = 0; \
if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \
__res = 0; \
} \
__res; \
})
/*
* Return non-zero if HDR identifies an n64 ELF binary.
*/
#define elf64_check_arch(hdr) \
({ \
int __res = 1; \
struct elfhdr *__h = (hdr); \
\
if (!mips_elf_check_machine(__h)) \
__res = 0; \
if (__h->e_ident[EI_CLASS] != ELFCLASS64) \
__res = 0; \
\
__res; \
})
struct mips_abi;
extern struct mips_abi mips_abi;
extern struct mips_abi mips_abi_32;
extern struct mips_abi mips_abi_n32;
#ifdef CONFIG_32BIT
#define SET_PERSONALITY2(ex, state) \
do { \
clear_thread_flag(TIF_HYBRID_FPREGS); \
set_thread_flag(TIF_32BIT_FPREGS); \
\
current->thread.abi = &mips_abi; \
\
mips_set_personality_fp(state); \
mips_set_personality_nan(state); \
\
if (personality(current->personality) != PER_LINUX) \
set_personality(PER_LINUX); \
} while (0)
#endif /* CONFIG_32BIT */
#ifdef CONFIG_64BIT
#ifdef CONFIG_MIPS32_N32
#define __SET_PERSONALITY32_N32() \
do { \
set_thread_flag(TIF_32BIT_ADDR); \
\
current->thread.abi = &mips_abi_n32; \
} while (0)
#else
#define __SET_PERSONALITY32_N32() \
do { } while (0)
#endif
#ifdef CONFIG_MIPS32_O32
#define __SET_PERSONALITY32_O32(ex, state) \
do { \
set_thread_flag(TIF_32BIT_REGS); \
set_thread_flag(TIF_32BIT_ADDR); \
clear_thread_flag(TIF_HYBRID_FPREGS); \
set_thread_flag(TIF_32BIT_FPREGS); \
\
current->thread.abi = &mips_abi_32; \
\
mips_set_personality_fp(state); \
} while (0)
#else
#define __SET_PERSONALITY32_O32(ex, state) \
do { } while (0)
#endif
#ifdef CONFIG_MIPS32_COMPAT
#define __SET_PERSONALITY32(ex, state) \
do { \
if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \
((ex).e_flags & EF_MIPS_ABI) == 0) \
__SET_PERSONALITY32_N32(); \
else \
__SET_PERSONALITY32_O32(ex, state); \
} while (0)
#else
#define __SET_PERSONALITY32(ex, state) do { } while (0)
#endif
#define SET_PERSONALITY2(ex, state) \
do { \
unsigned int p; \
\
clear_thread_flag(TIF_32BIT_REGS); \
clear_thread_flag(TIF_32BIT_FPREGS); \
clear_thread_flag(TIF_HYBRID_FPREGS); \
clear_thread_flag(TIF_32BIT_ADDR); \
current->personality &= ~READ_IMPLIES_EXEC; \
\
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
__SET_PERSONALITY32(ex, state); \
else \
current->thread.abi = &mips_abi; \
\
mips_set_personality_nan(state); \
\
p = personality(current->personality); \
if (p != PER_LINUX32 && p != PER_LINUX) \
set_personality(PER_LINUX); \
} while (0)
#endif /* CONFIG_64BIT */
#define CORE_DUMP_USE_REGSET
#define ELF_EXEC_PAGESIZE PAGE_SIZE
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. This could be done in userspace,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (elf_hwcap)
extern unsigned int elf_hwcap;
#include <asm/hwcap.h>
/*
* This yields a string that ld.so will use to load implementation
* specific libraries for optimization. This is more specific in
* intent than poking at uname or /proc/cpuinfo.
*/
#define ELF_PLATFORM __elf_platform
extern const char *__elf_platform;
#define ELF_BASE_PLATFORM __elf_base_platform
extern const char *__elf_base_platform;
/*
* See comments in asm-alpha/elf.h, this is the same thing
* on the MIPS.
*/
#define ELF_PLAT_INIT(_r, load_addr) do { \
_r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \
_r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \
_r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \
_r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \
_r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \
_r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \
_r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \
_r->regs[30] = _r->regs[31] = 0; \
} while (0)
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
#define ARCH_DLINFO \
do { \
NEW_AUX_ENT(AT_SYSINFO_EHDR, \
(unsigned long)current->mm->context.vdso); \
} while (0)
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
struct linux_binprm;
extern int arch_setup_additional_pages(struct linux_binprm *bprm,
int uses_interp);
#ifdef CONFIG_MIPS_FP_SUPPORT
struct arch_elf_state {
int nan_2008;
int fp_abi;
int interp_fp_abi;
int overall_fp_mode;
};
#define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (kernel internal) */
#define INIT_ARCH_ELF_STATE { \
.nan_2008 = -1, \
.fp_abi = MIPS_ABI_FP_UNKNOWN, \
.interp_fp_abi = MIPS_ABI_FP_UNKNOWN, \
.overall_fp_mode = -1, \
}
extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf,
bool is_interp, struct arch_elf_state *state);
extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr,
struct arch_elf_state *state);
/* Whether to accept legacy-NaN and 2008-NaN user binaries. */
extern bool mips_use_nan_legacy;
extern bool mips_use_nan_2008;
extern void mips_set_personality_nan(struct arch_elf_state *state);
extern void mips_set_personality_fp(struct arch_elf_state *state);
#else /* !CONFIG_MIPS_FP_SUPPORT */
struct arch_elf_state;
static inline void mips_set_personality_nan(struct arch_elf_state *state)
{
/* no-op */
}
static inline void mips_set_personality_fp(struct arch_elf_state *state)
{
/* no-op */
}
#endif /* !CONFIG_MIPS_FP_SUPPORT */
#define elf_read_implies_exec(ex, stk) mips_elf_read_implies_exec(&(ex), stk)
extern int mips_elf_read_implies_exec(void *elf_ex, int exstack);
#endif /* _ASM_ELF_H */
linux-7.2.3/arch/mips/include/asm/elfcore-compat.h
+29
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#ifndef _ASM_MIPS_ELFCORE_COMPAT_H
#define _ASM_MIPS_ELFCORE_COMPAT_H
/*
* On mips we have two 32bit ABIs - o32 and n32. The latter
* has bigger registers, so we use it for compat_elf_regset_t.
* The former uses o32_elf_prstatus and PRSTATUS_SIZE/SET_PR_FPVALID
* are used to choose the size and location of ->pr_fpvalid of
* the layout actually used.
*/
typedef elf_gregset_t compat_elf_gregset_t;
struct o32_elf_prstatus
{
struct compat_elf_prstatus_common common;
unsigned int pr_reg[ELF_NGREG];
compat_int_t pr_fpvalid;
};
#define PRSTATUS_SIZE \
(!test_thread_flag(TIF_32BIT_REGS) \
? sizeof(struct compat_elf_prstatus) \
: sizeof(struct o32_elf_prstatus))
#define SET_PR_FPVALID(S) \
(*(!test_thread_flag(TIF_32BIT_REGS) \
? &(S)->pr_fpvalid \
: &((struct o32_elf_prstatus *)(S))->pr_fpvalid) = 1)
#endif
linux-7.2.3/arch/mips/include/asm/errno.h
+17
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
*/
#ifndef _ASM_ERRNO_H
#define _ASM_ERRNO_H
#include <uapi/asm/errno.h>
/* The biggest error number defined here or in <linux/errno.h>. */
#define EMAXERRNO 1133
#endif /* _ASM_ERRNO_H */
linux-7.2.3/arch/mips/include/asm/eva.h
+43
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2014, Imagination Technologies Ltd.
*
* EVA functions for generic code
*/
#ifndef _ASM_EVA_H
#define _ASM_EVA_H
#include <kernel-entry-init.h>
#ifdef __ASSEMBLER__
#ifdef CONFIG_EVA
/*
* EVA early init code
*
* Platforms must define their own 'platform_eva_init' macro in
* their kernel-entry-init.h header. This macro usually does the
* platform specific configuration of the segmentation registers,
* and it is normally called from assembly code.
*
*/
.macro eva_init
platform_eva_init
.endm
#else
.macro eva_init
.endm
#endif /* CONFIG_EVA */
#endif /* __ASSEMBLER__ */
#endif
linux-7.2.3/arch/mips/include/asm/exec.h
+17
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
#ifndef _ASM_EXEC_H
#define _ASM_EXEC_H
extern unsigned long arch_align_stack(unsigned long sp);
#endif /* _ASM_EXEC_H */
linux-7.2.3/arch/mips/include/asm/extable.h
+14
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@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_EXTABLE_H
#define _ASM_EXTABLE_H
struct exception_table_entry
{
unsigned long insn;
unsigned long nextinsn;
};
struct pt_regs;
extern int fixup_exception(struct pt_regs *regs);
#endif
linux-7.2.3/arch/mips/include/asm/fixmap.h
+79
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/*
* fixmap.h: compile-time virtual memory allocation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Ingo Molnar
*
* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
*/
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
#include <asm/page.h>
#include <spaces.h>
#ifdef CONFIG_HIGHMEM
#include <linux/threads.h>
#include <asm/kmap_size.h>
#endif
/*
* Here we define all the compile-time 'special' virtual
* addresses. The point is to have a constant address at
* compile time, but to set the physical address only
* in the boot process. We allocate these special addresses
* from the end of virtual memory (0xfffff000) backwards.
* Also this lets us do fail-safe vmalloc(), we
* can guarantee that these special addresses and
* vmalloc()-ed addresses never overlap.
*
* these 'compile-time allocated' memory buffers are
* fixed-size 4k pages. (or larger if used with an increment
* highger than 1) use fixmap_set(idx,phys) to associate
* physical memory with fixmap indices.
*
* TLB entries of such buffers will not be flushed across
* task switches.
*/
/*
* on UP currently we will have no trace of the fixmap mechanizm,
* no page table allocations, etc. This might change in the
* future, say framebuffers for the console driver(s) could be
* fix-mapped?
*/
enum fixed_addresses {
#define FIX_N_COLOURS 8
FIX_CMAP_BEGIN,
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
#ifdef CONFIG_HIGHMEM
/* reserved pte's for temporary kernel mappings */
FIX_KMAP_BEGIN = FIX_CMAP_END + 1,
FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_MAX_IDX * NR_CPUS) - 1,
#endif
__end_of_fixed_addresses
};
/*
* used by vmalloc.c.
*
* Leave one empty page between vmalloc'ed areas and
* the start of the fixmap, and leave one page empty
* at the top of mem..
*/
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
#include <asm-generic/fixmap.h>
/*
* Called from pagetable_init()
*/
extern void fixrange_init(unsigned long start, unsigned long end,
pgd_t *pgd_base);
#endif
linux-7.2.3/arch/mips/include/asm/floppy.h
+41
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@@ -0,0 +1,41 @@
/*
* Architecture specific parts of the Floppy driver
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995 - 2000 Ralf Baechle
*/
#ifndef _ASM_FLOPPY_H
#define _ASM_FLOPPY_H
#include <asm/io.h>
static inline void fd_cacheflush(char * addr, long size)
{
dma_cache_wback_inv((unsigned long)addr, size);
}
#define MAX_BUFFER_SECTORS 24
/*
* And on Mips's the CMOS info fails also ...
*
* FIXME: This information should come from the ARC configuration tree
* or wherever a particular machine has stored this ...
*/
#define FLOPPY0_TYPE fd_drive_type(0)
#define FLOPPY1_TYPE fd_drive_type(1)
#define FDC1 fd_getfdaddr1()
#define N_FDC 1 /* do you *really* want a second controller? */
#define N_DRIVE 8
#define EXTRA_FLOPPY_PARAMS
#include <floppy.h>
#endif /* _ASM_FLOPPY_H */
linux-7.2.3/arch/mips/include/asm/fpregdef.h
+99
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@@ -0,0 +1,99 @@
/*
* Definitions for the FPU register names
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1999 Ralf Baechle
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_FPREGDEF_H
#define _ASM_FPREGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
* These definitions only cover the R3000-ish 16/32 register model.
* But we're trying to be R3000 friendly anyway ...
*/
#define fv0 $f0 /* return value */
#define fv0f $f1
#define fv1 $f2
#define fv1f $f3
#define fa0 $f12 /* argument registers */
#define fa0f $f13
#define fa1 $f14
#define fa1f $f15
#define ft0 $f4 /* caller saved */
#define ft0f $f5
#define ft1 $f6
#define ft1f $f7
#define ft2 $f8
#define ft2f $f9
#define ft3 $f10
#define ft3f $f11
#define ft4 $f16
#define ft4f $f17
#define ft5 $f18
#define ft5f $f19
#define fs0 $f20 /* callee saved */
#define fs0f $f21
#define fs1 $f22
#define fs1f $f23
#define fs2 $f24
#define fs2f $f25
#define fs3 $f26
#define fs3f $f27
#define fs4 $f28
#define fs4f $f29
#define fs5 $f30
#define fs5f $f31
#define fcr31 $31 /* FPU status register */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define fv0 $f0 /* return value */
#define fv1 $f2
#define fa0 $f12 /* argument registers */
#define fa1 $f13
#define fa2 $f14
#define fa3 $f15
#define fa4 $f16
#define fa5 $f17
#define fa6 $f18
#define fa7 $f19
#define ft0 $f4 /* caller saved */
#define ft1 $f5
#define ft2 $f6
#define ft3 $f7
#define ft4 $f8
#define ft5 $f9
#define ft6 $f10
#define ft7 $f11
#define ft8 $f20
#define ft9 $f21
#define ft10 $f22
#define ft11 $f23
#define ft12 $f1
#define ft13 $f3
#define fs0 $f24 /* callee saved */
#define fs1 $f25
#define fs2 $f26
#define fs3 $f27
#define fs4 $f28
#define fs5 $f29
#define fs6 $f30
#define fs7 $f31
#define fcr31 $31
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* _ASM_FPREGDEF_H */
linux-7.2.3/arch/mips/include/asm/fpu.h
+343
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2002 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*/
#ifndef _ASM_FPU_H
#define _ASM_FPU_H
#include <linux/sched.h>
#include <linux/sched/task_stack.h>
#include <linux/ptrace.h>
#include <linux/thread_info.h>
#include <linux/bitops.h>
#include <asm/mipsregs.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/fpu_emulator.h>
#include <asm/hazards.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/current.h>
#include <asm/msa.h>
#ifdef CONFIG_MIPS_MT_FPAFF
#include <asm/mips_mt.h>
#endif
/*
* This enum specifies a mode in which we want the FPU to operate, for cores
* which implement the Status.FR bit. Note that the bottom bit of the value
* purposefully matches the desired value of the Status.FR bit.
*/
enum fpu_mode {
FPU_32BIT = 0, /* FR = 0 */
FPU_64BIT, /* FR = 1, FRE = 0 */
FPU_AS_IS,
FPU_HYBRID, /* FR = 1, FRE = 1 */
#define FPU_FR_MASK 0x1
};
#ifdef CONFIG_MIPS_FP_SUPPORT
extern void _save_fp(struct task_struct *);
extern void _restore_fp(struct task_struct *);
#define __disable_fpu() \
do { \
clear_c0_status(ST0_CU1); \
disable_fpu_hazard(); \
} while (0)
static inline int __enable_fpu(enum fpu_mode mode)
{
int fr;
switch (mode) {
case FPU_AS_IS:
/* just enable the FPU in its current mode */
set_c0_status(ST0_CU1);
enable_fpu_hazard();
return 0;
case FPU_HYBRID:
if (!cpu_has_fre)
return SIGFPE;
/* set FRE */
set_c0_config5(MIPS_CONF5_FRE);
goto fr_common;
case FPU_64BIT:
#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT))
/* we only have a 32-bit FPU */
return SIGFPE;
#endif
/* fallthrough */
case FPU_32BIT:
if (cpu_has_fre) {
/* clear FRE */
clear_c0_config5(MIPS_CONF5_FRE);
}
fr_common:
/* set CU1 & change FR appropriately */
fr = (int)mode & FPU_FR_MASK;
change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
enable_fpu_hazard();
/* check FR has the desired value */
if (!!(read_c0_status() & ST0_FR) == !!fr)
return 0;
/* unsupported FR value */
__disable_fpu();
return SIGFPE;
default:
BUG();
}
return SIGFPE;
}
#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
static inline int __is_fpu_owner(void)
{
return test_thread_flag(TIF_USEDFPU);
}
static inline int is_fpu_owner(void)
{
return cpu_has_fpu && __is_fpu_owner();
}
static inline int __own_fpu(void)
{
enum fpu_mode mode;
int ret;
if (test_thread_flag(TIF_HYBRID_FPREGS))
mode = FPU_HYBRID;
else
mode = !test_thread_flag(TIF_32BIT_FPREGS);
ret = __enable_fpu(mode);
if (ret)
return ret;
if (current->thread.fpu.fcr31 & FPU_CSR_NAN2008) {
if (!cpu_has_nan_2008) {
ret = SIGFPE;
goto failed;
}
} else {
if (!cpu_has_nan_legacy) {
ret = SIGFPE;
goto failed;
}
}
KSTK_STATUS(current) |= ST0_CU1;
if (mode == FPU_64BIT || mode == FPU_HYBRID)
KSTK_STATUS(current) |= ST0_FR;
else /* mode == FPU_32BIT */
KSTK_STATUS(current) &= ~ST0_FR;
set_thread_flag(TIF_USEDFPU);
return 0;
failed:
__disable_fpu();
return ret;
}
static inline int own_fpu_inatomic(int restore)
{
int ret = 0;
if (cpu_has_fpu && !__is_fpu_owner()) {
ret = __own_fpu();
if (restore && !ret)
_restore_fp(current);
}
return ret;
}
static inline int own_fpu(int restore)
{
int ret;
preempt_disable();
ret = own_fpu_inatomic(restore);
preempt_enable();
return ret;
}
static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
{
if (is_msa_enabled()) {
if (save) {
save_msa(tsk);
tsk->thread.fpu.fcr31 =
read_32bit_cp1_register(CP1_STATUS);
}
disable_msa();
clear_tsk_thread_flag(tsk, TIF_USEDMSA);
__disable_fpu();
} else if (is_fpu_owner()) {
if (save)
_save_fp(tsk);
__disable_fpu();
} else {
/* FPU should not have been left enabled with no owner */
WARN(read_c0_status() & ST0_CU1,
"Orphaned FPU left enabled");
}
KSTK_STATUS(tsk) &= ~ST0_CU1;
clear_tsk_thread_flag(tsk, TIF_USEDFPU);
}
static inline void lose_fpu(int save)
{
preempt_disable();
lose_fpu_inatomic(save, current);
preempt_enable();
}
/**
* init_fp_ctx() - Initialize task FP context
* @target: The task whose FP context should be initialized.
*
* Initializes the FP context of the target task to sane default values if that
* target task does not already have valid FP context. Once the context has
* been initialized, the task will be marked as having used FP & thus having
* valid FP context.
*
* Returns: true if context is initialized, else false.
*/
static inline bool init_fp_ctx(struct task_struct *target)
{
/* If FP has been used then the target already has context */
if (tsk_used_math(target))
return false;
/* Begin with data registers set to all 1s... */
memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
/* FCSR has been preset by `mips_set_personality_nan'. */
/*
* Record that the target has "used" math, such that the context
* just initialised, and any modifications made by the caller,
* aren't discarded.
*/
set_stopped_child_used_math(target);
return true;
}
static inline void save_fp(struct task_struct *tsk)
{
if (cpu_has_fpu)
_save_fp(tsk);
}
static inline void restore_fp(struct task_struct *tsk)
{
if (cpu_has_fpu)
_restore_fp(tsk);
}
static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
{
if (tsk == current) {
preempt_disable();
if (is_fpu_owner())
_save_fp(current);
preempt_enable();
}
return tsk->thread.fpu.fpr;
}
#else /* !CONFIG_MIPS_FP_SUPPORT */
/*
* When FP support is disabled we provide only a minimal set of stub functions
* to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT.
*/
static inline int __enable_fpu(enum fpu_mode mode)
{
return SIGILL;
}
static inline void __disable_fpu(void)
{
/* no-op */
}
static inline int is_fpu_owner(void)
{
return 0;
}
static inline void clear_fpu_owner(void)
{
/* no-op */
}
static inline int own_fpu_inatomic(int restore)
{
return SIGILL;
}
static inline int own_fpu(int restore)
{
return SIGILL;
}
static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
{
/* no-op */
}
static inline void lose_fpu(int save)
{
/* no-op */
}
static inline bool init_fp_ctx(struct task_struct *target)
{
return false;
}
/*
* The following functions should only be called in paths where we know that FP
* support is enabled, typically a path where own_fpu() or __enable_fpu() have
* returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile
* time that this should never happen, so calls to these functions should be
* optimized away & never actually be emitted.
*/
extern void save_fp(struct task_struct *tsk)
__compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
extern void _save_fp(struct task_struct *)
__compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
extern void restore_fp(struct task_struct *tsk)
__compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
extern void _restore_fp(struct task_struct *)
__compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
extern union fpureg *get_fpu_regs(struct task_struct *tsk)
__compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
#endif /* !CONFIG_MIPS_FP_SUPPORT */
#endif /* _ASM_FPU_H */
linux-7.2.3/arch/mips/include/asm/fpu_emulator.h
+187
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Further private data for which no space exists in mips_fpu_struct.
* This should be subsumed into the mips_fpu_struct structure as
* defined in processor.h as soon as the absurd wired absolute assembler
* offsets become dynamic at compile time.
*
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*/
#ifndef _ASM_FPU_EMULATOR_H
#define _ASM_FPU_EMULATOR_H
#include <linux/sched.h>
#include <asm/dsemul.h>
#include <asm/thread_info.h>
#include <asm/inst.h>
#include <asm/local.h>
#include <asm/processor.h>
#ifdef CONFIG_DEBUG_FS
struct mips_fpu_emulator_stats {
unsigned long emulated;
unsigned long loads;
unsigned long stores;
unsigned long branches;
unsigned long cp1ops;
unsigned long cp1xops;
unsigned long errors;
unsigned long ieee754_inexact;
unsigned long ieee754_underflow;
unsigned long ieee754_overflow;
unsigned long ieee754_zerodiv;
unsigned long ieee754_invalidop;
unsigned long ds_emul;
unsigned long abs_s;
unsigned long abs_d;
unsigned long add_s;
unsigned long add_d;
unsigned long bc1eqz;
unsigned long bc1nez;
unsigned long ceil_w_s;
unsigned long ceil_w_d;
unsigned long ceil_l_s;
unsigned long ceil_l_d;
unsigned long class_s;
unsigned long class_d;
unsigned long cmp_af_s;
unsigned long cmp_af_d;
unsigned long cmp_eq_s;
unsigned long cmp_eq_d;
unsigned long cmp_le_s;
unsigned long cmp_le_d;
unsigned long cmp_lt_s;
unsigned long cmp_lt_d;
unsigned long cmp_ne_s;
unsigned long cmp_ne_d;
unsigned long cmp_or_s;
unsigned long cmp_or_d;
unsigned long cmp_ueq_s;
unsigned long cmp_ueq_d;
unsigned long cmp_ule_s;
unsigned long cmp_ule_d;
unsigned long cmp_ult_s;
unsigned long cmp_ult_d;
unsigned long cmp_un_s;
unsigned long cmp_un_d;
unsigned long cmp_une_s;
unsigned long cmp_une_d;
unsigned long cmp_saf_s;
unsigned long cmp_saf_d;
unsigned long cmp_seq_s;
unsigned long cmp_seq_d;
unsigned long cmp_sle_s;
unsigned long cmp_sle_d;
unsigned long cmp_slt_s;
unsigned long cmp_slt_d;
unsigned long cmp_sne_s;
unsigned long cmp_sne_d;
unsigned long cmp_sor_s;
unsigned long cmp_sor_d;
unsigned long cmp_sueq_s;
unsigned long cmp_sueq_d;
unsigned long cmp_sule_s;
unsigned long cmp_sule_d;
unsigned long cmp_sult_s;
unsigned long cmp_sult_d;
unsigned long cmp_sun_s;
unsigned long cmp_sun_d;
unsigned long cmp_sune_s;
unsigned long cmp_sune_d;
unsigned long cvt_d_l;
unsigned long cvt_d_s;
unsigned long cvt_d_w;
unsigned long cvt_l_s;
unsigned long cvt_l_d;
unsigned long cvt_s_d;
unsigned long cvt_s_l;
unsigned long cvt_s_w;
unsigned long cvt_w_s;
unsigned long cvt_w_d;
unsigned long div_s;
unsigned long div_d;
unsigned long floor_w_s;
unsigned long floor_w_d;
unsigned long floor_l_s;
unsigned long floor_l_d;
unsigned long maddf_s;
unsigned long maddf_d;
unsigned long max_s;
unsigned long max_d;
unsigned long maxa_s;
unsigned long maxa_d;
unsigned long min_s;
unsigned long min_d;
unsigned long mina_s;
unsigned long mina_d;
unsigned long mov_s;
unsigned long mov_d;
unsigned long msubf_s;
unsigned long msubf_d;
unsigned long mul_s;
unsigned long mul_d;
unsigned long neg_s;
unsigned long neg_d;
unsigned long recip_s;
unsigned long recip_d;
unsigned long rint_s;
unsigned long rint_d;
unsigned long round_w_s;
unsigned long round_w_d;
unsigned long round_l_s;
unsigned long round_l_d;
unsigned long rsqrt_s;
unsigned long rsqrt_d;
unsigned long sel_s;
unsigned long sel_d;
unsigned long seleqz_s;
unsigned long seleqz_d;
unsigned long selnez_s;
unsigned long selnez_d;
unsigned long sqrt_s;
unsigned long sqrt_d;
unsigned long sub_s;
unsigned long sub_d;
unsigned long trunc_w_s;
unsigned long trunc_w_d;
unsigned long trunc_l_s;
unsigned long trunc_l_d;
};
DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
#define MIPS_FPU_EMU_INC_STATS(M) \
do { \
preempt_disable(); \
__this_cpu_inc(fpuemustats.M); \
preempt_enable(); \
} while (0)
#else
#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
#endif /* CONFIG_DEBUG_FS */
extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
struct mips_fpu_struct *ctx, int has_fpu,
void __user **fault_addr);
void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
struct task_struct *tsk);
int process_fpemu_return(int sig, void __user *fault_addr,
unsigned long fcr31);
/*
* Mask the FCSR Cause bits according to the Enable bits, observing
* that Unimplemented is always enabled.
*/
static inline unsigned long mask_fcr31_x(unsigned long fcr31)
{
return fcr31 & (FPU_CSR_UNI_X |
((fcr31 & FPU_CSR_ALL_E) <<
(ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))));
}
#endif /* _ASM_FPU_EMULATOR_H */
linux-7.2.3/arch/mips/include/asm/ftrace.h
+110
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@@ -0,0 +1,110 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive for
* more details.
*
* Copyright (C) 2009 DSLab, Lanzhou University, China
* Author: Wu Zhangjin <wuzhangjin@gmail.com>
*/
#ifndef _ASM_MIPS_FTRACE_H
#define _ASM_MIPS_FTRACE_H
#ifdef CONFIG_FUNCTION_TRACER
#define MCOUNT_ADDR ((unsigned long)(_mcount))
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
#ifndef __ASSEMBLER__
extern void _mcount(void);
#define mcount _mcount
#define safe_load(load, src, dst, error) \
do { \
asm volatile ( \
"1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
" li %[tmp_err], 0\n" \
"2: .insn\n" \
\
".section .fixup, \"ax\"\n" \
"3: li %[tmp_err], 1\n" \
" j 2b\n" \
".previous\n" \
\
".section\t__ex_table,\"a\"\n\t" \
STR(PTR_WD) "\t1b, 3b\n\t" \
".previous\n" \
\
: [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
: [tmp_src] "r" (src) \
: "memory" \
); \
} while (0)
#define safe_store(store, src, dst, error) \
do { \
asm volatile ( \
"1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
" li %[tmp_err], 0\n" \
"2: .insn\n" \
\
".section .fixup, \"ax\"\n" \
"3: li %[tmp_err], 1\n" \
" j 2b\n" \
".previous\n" \
\
".section\t__ex_table,\"a\"\n\t"\
STR(PTR_WD) "\t1b, 3b\n\t" \
".previous\n" \
\
: [tmp_err] "=r" (error) \
: [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
: "memory" \
); \
} while (0)
#define safe_load_code(dst, src, error) \
safe_load(STR(lw), src, dst, error)
#define safe_store_code(src, dst, error) \
safe_store(STR(sw), src, dst, error)
#define safe_load_stack(dst, src, error) \
safe_load(STR(PTR_L), src, dst, error)
#define safe_store_stack(src, dst, error) \
safe_store(STR(PTR_S), src, dst, error)
#ifdef CONFIG_DYNAMIC_FTRACE
static inline unsigned long ftrace_call_adjust(unsigned long addr)
{
return addr;
}
struct dyn_arch_ftrace {
};
#endif /* CONFIG_DYNAMIC_FTRACE */
void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra,
unsigned long fp);
#endif /* __ASSEMBLER__ */
#endif /* CONFIG_FUNCTION_TRACER */
#ifdef CONFIG_FTRACE_SYSCALLS
#ifndef __ASSEMBLER__
/*
* Some syscall entry functions on mips start with "__sys_" (fork and clone,
* for instance). We should also match the sys_ variant with those.
*/
#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
static inline bool arch_syscall_match_sym_name(const char *sym,
const char *name)
{
return !strcmp(sym, name) ||
(!strncmp(sym, "__sys_", 6) && !strcmp(sym + 6, name + 4));
}
#endif /* __ASSEMBLER__ */
#endif /* CONFIG_FTRACE_SYSCALLS */
#endif /* _ASM_MIPS_FTRACE_H */
linux-7.2.3/arch/mips/include/asm/futex.h
+210
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@@ -0,0 +1,210 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H
#ifdef __KERNEL__
#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/asm-eva.h>
#include <asm/barrier.h>
#include <asm/compiler.h>
#include <asm/errno.h>
#include <asm/sync.h>
#define arch_futex_atomic_op_inuser arch_futex_atomic_op_inuser
#define futex_atomic_cmpxchg_inatomic futex_atomic_cmpxchg_inatomic
#include <asm-generic/futex.h>
#define __futex_atomic_op(op, insn, ret, oldval, uaddr, oparg) \
{ \
if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set push \n" \
" .set arch=r4000 \n" \
"1: ll %1, %4 # __futex_atomic_op \n" \
" .set pop \n" \
" " insn " \n" \
" .set arch=r4000 \n" \
"2: sc $1, %2 \n" \
" beqzl $1, 1b \n" \
__stringify(__WEAK_LLSC_MB) " \n" \
"3: \n" \
" .insn \n" \
" .set pop \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
" j 3b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=&r" (oldval), \
"=" GCC_OFF_SMALL_ASM() (*uaddr) \
: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
"i" (-EFAULT) \
: "memory"); \
} else if (cpu_has_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set push \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
" " __SYNC(full, loongson3_war) " \n" \
"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
" .set pop \n" \
" " insn " \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
"2: "user_sc("$1", "%2")" \n" \
" beqz $1, 1b \n" \
__stringify(__WEAK_LLSC_MB) " \n" \
"3: \n" \
" .insn \n" \
" .set pop \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
" j 3b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=&r" (oldval), \
"=" GCC_OFF_SMALL_ASM() (*uaddr) \
: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
"i" (-EFAULT) \
: "memory"); \
} else { \
/* fallback for non-SMP */ \
ret = futex_atomic_op_inuser_local(op, oparg, oval, uaddr); \
} \
}
static inline int
arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
{
int oldval = 0, ret;
if (!access_ok(uaddr, sizeof(u32)))
return -EFAULT;
switch (op) {
case FUTEX_OP_SET:
__futex_atomic_op(op, "move $1, %z5", ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ADD:
__futex_atomic_op(op, "addu $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_OR:
__futex_atomic_op(op, "or $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ANDN:
__futex_atomic_op(op, "and $1, %1, %z5",
ret, oldval, uaddr, ~oparg);
break;
case FUTEX_OP_XOR:
__futex_atomic_op(op, "xor $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
default:
ret = -ENOSYS;
}
if (!ret)
*oval = oldval;
return ret;
}
static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
u32 oldval, u32 newval)
{
int ret = 0;
u32 val;
if (!access_ok(uaddr, sizeof(u32)))
return -EFAULT;
if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
" .set push \n"
" .set arch=r4000 \n"
"1: ll %1, %3 \n"
" bne %1, %z4, 3f \n"
" .set pop \n"
" move $1, %z5 \n"
" .set arch=r4000 \n"
"2: sc $1, %2 \n"
" beqzl $1, 1b \n"
__stringify(__WEAK_LLSC_MB) " \n"
"3: \n"
" .insn \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
"4: li %0, %6 \n"
" j 3b \n"
" .previous \n"
" .section __ex_table,\"a\" \n"
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
"i" (-EFAULT)
: "memory");
} else if (cpu_has_llsc) {
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __SYNC(full, loongson3_war) " \n"
"1: "user_ll("%1", "%3")" \n"
" bne %1, %z4, 3f \n"
" .set pop \n"
" move $1, %z5 \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"2: "user_sc("$1", "%2")" \n"
" beqz $1, 1b \n"
"3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
" .insn \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
"4: li %0, %6 \n"
" j 3b \n"
" .previous \n"
" .section __ex_table,\"a\" \n"
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
"i" (-EFAULT)
: "memory");
} else {
return futex_atomic_cmpxchg_inatomic_local(uval, uaddr, oldval, newval);
}
*uval = val;
return ret;
}
#endif
#endif /* _ASM_FUTEX_H */
linux-7.2.3/arch/mips/include/asm/fw/arc/hinv.h
+176
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@@ -0,0 +1,176 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* ARCS hardware/memory inventory/configuration and system ID definitions.
*/
#ifndef _ASM_ARC_HINV_H
#define _ASM_ARC_HINV_H
#include <asm/sgidefs.h>
#include <asm/fw/arc/types.h>
/* configuration query defines */
typedef enum configclass {
SystemClass,
ProcessorClass,
CacheClass,
#ifndef _NT_PROM
MemoryClass,
AdapterClass,
ControllerClass,
PeripheralClass
#else /* _NT_PROM */
AdapterClass,
ControllerClass,
PeripheralClass,
MemoryClass
#endif /* _NT_PROM */
} CONFIGCLASS;
typedef enum configtype {
ARC,
CPU,
FPU,
PrimaryICache,
PrimaryDCache,
SecondaryICache,
SecondaryDCache,
SecondaryCache,
#ifndef _NT_PROM
Memory,
#endif
EISAAdapter,
TCAdapter,
SCSIAdapter,
DTIAdapter,
MultiFunctionAdapter,
DiskController,
TapeController,
CDROMController,
WORMController,
SerialController,
NetworkController,
DisplayController,
ParallelController,
PointerController,
KeyboardController,
AudioController,
OtherController,
DiskPeripheral,
FloppyDiskPeripheral,
TapePeripheral,
ModemPeripheral,
MonitorPeripheral,
PrinterPeripheral,
PointerPeripheral,
KeyboardPeripheral,
TerminalPeripheral,
LinePeripheral,
NetworkPeripheral,
#ifdef _NT_PROM
Memory,
#endif
OtherPeripheral,
/* new stuff for IP30 */
/* added without moving anything */
/* except ANONYMOUS. */
XTalkAdapter,
PCIAdapter,
GIOAdapter,
TPUAdapter,
Anonymous
} CONFIGTYPE;
typedef enum {
Failed = 1,
ReadOnly = 2,
Removable = 4,
ConsoleIn = 8,
ConsoleOut = 16,
Input = 32,
Output = 64
} IDENTIFIERFLAG;
#ifndef NULL /* for GetChild(NULL); */
#define NULL 0
#endif
union key_u {
struct {
#ifdef _MIPSEB
unsigned char c_bsize; /* block size in lines */
unsigned char c_lsize; /* line size in bytes/tag */
unsigned short c_size; /* cache size in 4K pages */
#else /* _MIPSEL */
unsigned short c_size; /* cache size in 4K pages */
unsigned char c_lsize; /* line size in bytes/tag */
unsigned char c_bsize; /* block size in lines */
#endif /* _MIPSEL */
} cache;
ULONG FullKey;
};
#if _MIPS_SIM == _MIPS_SIM_ABI64
#define SGI_ARCS_VERS 64 /* sgi 64-bit version */
#define SGI_ARCS_REV 0 /* rev .00 */
#else
#define SGI_ARCS_VERS 1 /* first version */
#define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */
#endif
typedef struct {
CONFIGCLASS Class;
CONFIGTYPE Type;
IDENTIFIERFLAG Flags;
USHORT Version;
USHORT Revision;
ULONG Key;
ULONG AffinityMask;
ULONG ConfigurationDataSize;
ULONG IdentifierLength;
char *Identifier;
} COMPONENT;
/* internal structure that holds pathname parsing data */
struct cfgdata {
char *name; /* full name */
int minlen; /* minimum length to match */
CONFIGTYPE type; /* type of token */
};
/* System ID */
typedef struct {
CHAR VendorId[8];
CHAR ProductId[8];
} SYSTEMID;
/* memory query functions */
typedef enum memorytype {
ExceptionBlock,
SPBPage, /* ARCS == SystemParameterBlock */
#ifndef _NT_PROM
FreeContiguous,
FreeMemory,
BadMemory,
LoadedProgram,
FirmwareTemporary,
FirmwarePermanent
#else /* _NT_PROM */
FreeMemory,
BadMemory,
LoadedProgram,
FirmwareTemporary,
FirmwarePermanent,
FreeContiguous
#endif /* _NT_PROM */
} MEMORYTYPE;
typedef struct {
MEMORYTYPE Type;
LONG BasePage;
LONG PageCount;
} MEMORYDESCRIPTOR;
#endif /* _ASM_ARC_HINV_H */
linux-7.2.3/arch/mips/include/asm/fw/arc/types.h
+86
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@@ -0,0 +1,86 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright 1999 Ralf Baechle (ralf@gnu.org)
* Copyright 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_ARC_TYPES_H
#define _ASM_ARC_TYPES_H
#ifdef CONFIG_FW_ARC32
typedef char CHAR;
typedef short SHORT;
typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
typedef long LONG __attribute__ ((__mode__ (__SI__)));
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__)));
typedef void VOID;
/* The pointer types. Note that we're using a 64-bit compiler but all
pointer in the ARC structures are only 32-bit, so we need some disgusting
workarounds. Keep your vomit bag handy. */
typedef LONG _PCHAR;
typedef LONG _PSHORT;
typedef LONG _PLARGE_INTEGER;
typedef LONG _PLONG;
typedef LONG _PUCHAR;
typedef LONG _PUSHORT;
typedef LONG _PULONG;
typedef LONG _PVOID;
#endif /* CONFIG_FW_ARC32 */
#ifdef CONFIG_FW_ARC64
typedef char CHAR;
typedef short SHORT;
typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
typedef long LONG __attribute__ ((__mode__ (__DI__)));
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__)));
typedef void VOID;
/* The pointer types. We're 64-bit and the firmware is also 64-bit, so
live is sane ... */
typedef CHAR *_PCHAR;
typedef SHORT *_PSHORT;
typedef LARGE_INTEGER *_PLARGE_INTEGER;
typedef LONG *_PLONG;
typedef UCHAR *_PUCHAR;
typedef USHORT *_PUSHORT;
typedef ULONG *_PULONG;
typedef VOID *_PVOID;
#endif /* CONFIG_FW_ARC64 */
typedef CHAR *PCHAR;
typedef SHORT *PSHORT;
typedef LARGE_INTEGER *PLARGE_INTEGER;
typedef LONG *PLONG;
typedef UCHAR *PUCHAR;
typedef USHORT *PUSHORT;
typedef ULONG *PULONG;
typedef VOID *PVOID;
/*
* Return type of ArcGetDisplayStatus()
*/
typedef struct {
USHORT CursorXPosition;
USHORT CursorYPosition;
USHORT CursorMaxXPosition;
USHORT CursorMaxYPosition;
USHORT ForegroundColor;
USHORT BackgroundColor;
UCHAR HighIntensity;
UCHAR Underscored;
UCHAR ReverseVideo;
} DISPLAY_STATUS;
#endif /* _ASM_ARC_TYPES_H */
linux-7.2.3/arch/mips/include/asm/fw/cfe/cfe_api.h
+108
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@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001, 2002 Broadcom Corporation
*/
/*
* Broadcom Common Firmware Environment (CFE)
*
* This file contains declarations for doing callbacks to
* cfe from an application. It should be the only header
* needed by the application to use this library
*
* Authors: Mitch Lichtenberg, Chris Demetriou
*/
#ifndef CFE_API_H
#define CFE_API_H
#include <linux/types.h>
#include <linux/string.h>
/*
* Constants
*/
/* Seal indicating CFE's presence, passed to user program. */
#define CFE_EPTSEAL 0x43464531
#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
#define CFE_MI_AVAILABLE 1 /* memory is available */
#define CFE_FLG_WARMSTART 0x00000001
#define CFE_FLG_FULL_ARENA 0x00000001
#define CFE_FLG_ENV_PERMANENT 0x00000001
#define CFE_CPU_CMD_START 1
#define CFE_CPU_CMD_STOP 0
#define CFE_STDHANDLE_CONSOLE 0
#define CFE_DEV_NETWORK 1
#define CFE_DEV_DISK 2
#define CFE_DEV_FLASH 3
#define CFE_DEV_SERIAL 4
#define CFE_DEV_CPU 5
#define CFE_DEV_NVRAM 6
#define CFE_DEV_CLOCK 7
#define CFE_DEV_OTHER 8
#define CFE_DEV_MASK 0x0F
#define CFE_CACHE_FLUSH_D 1
#define CFE_CACHE_INVAL_I 2
#define CFE_CACHE_INVAL_D 4
#define CFE_CACHE_INVAL_L2 8
#define CFE_FWI_64BIT 0x00000001
#define CFE_FWI_32BIT 0x00000002
#define CFE_FWI_RELOC 0x00000004
#define CFE_FWI_UNCACHED 0x00000008
#define CFE_FWI_MULTICPU 0x00000010
#define CFE_FWI_FUNCSIM 0x00000020
#define CFE_FWI_RTLSIM 0x00000040
typedef struct {
int64_t fwi_version; /* major, minor, eco version */
int64_t fwi_totalmem; /* total installed mem */
int64_t fwi_flags; /* various flags */
int64_t fwi_boardid; /* board ID */
int64_t fwi_bootarea_va; /* VA of boot area */
int64_t fwi_bootarea_pa; /* PA of boot area */
int64_t fwi_bootarea_size; /* size of boot area */
} cfe_fwinfo_t;
/*
* Defines and prototypes for functions which take no arguments.
*/
int64_t cfe_getticks(void);
/*
* Defines and prototypes for the rest of the functions.
*/
int cfe_close(int handle);
int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
int cfe_cpu_stop(int cpu);
int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
uint64_t * type);
int cfe_exit(int warm, int status);
int cfe_flushcache(int flg);
int cfe_getdevinfo(char *name);
int cfe_getenv(char *name, char *dest, int destlen);
int cfe_getfwinfo(cfe_fwinfo_t * info);
int cfe_getstdhandle(int flg);
int cfe_init(uint64_t handle, uint64_t ept);
int cfe_inpstat(int handle);
int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
int length, int *retlen, uint64_t offset);
int cfe_open(char *name);
int cfe_read(int handle, unsigned char *buffer, int length);
int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
int length);
int cfe_setenv(char *name, char *val);
int cfe_write(int handle, const char *buffer, int length);
int cfe_writeblk(int handle, int64_t offset, const char *buffer,
int length);
extern unsigned long cfe_seal;
__printf(1, 2) void cfe_die(char *fmt, ...);
#endif /* CFE_API_H */
linux-7.2.3/arch/mips/include/asm/fw/cfe/cfe_error.h
+67
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@@ -0,0 +1,67 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001, 2002 Broadcom Corporation
*/
/*
* Broadcom Common Firmware Environment (CFE)
*
* CFE's global error code list is here.
*
* Author: Mitch Lichtenberg
*/
#define CFE_OK 0
#define CFE_ERR -1 /* generic error */
#define CFE_ERR_INV_COMMAND -2
#define CFE_ERR_EOF -3
#define CFE_ERR_IOERR -4
#define CFE_ERR_NOMEM -5
#define CFE_ERR_DEVNOTFOUND -6
#define CFE_ERR_DEVOPEN -7
#define CFE_ERR_INV_PARAM -8
#define CFE_ERR_ENVNOTFOUND -9
#define CFE_ERR_ENVREADONLY -10
#define CFE_ERR_NOTELF -11
#define CFE_ERR_NOT32BIT -12
#define CFE_ERR_WRONGENDIAN -13
#define CFE_ERR_BADELFVERS -14
#define CFE_ERR_NOTMIPS -15
#define CFE_ERR_BADELFFMT -16
#define CFE_ERR_BADADDR -17
#define CFE_ERR_FILENOTFOUND -18
#define CFE_ERR_UNSUPPORTED -19
#define CFE_ERR_HOSTUNKNOWN -20
#define CFE_ERR_TIMEOUT -21
#define CFE_ERR_PROTOCOLERR -22
#define CFE_ERR_NETDOWN -23
#define CFE_ERR_NONAMESERVER -24
#define CFE_ERR_NOHANDLES -25
#define CFE_ERR_ALREADYBOUND -26
#define CFE_ERR_CANNOTSET -27
#define CFE_ERR_NOMORE -28
#define CFE_ERR_BADFILESYS -29
#define CFE_ERR_FSNOTAVAIL -30
#define CFE_ERR_INVBOOTBLOCK -31
#define CFE_ERR_WRONGDEVTYPE -32
#define CFE_ERR_BBCHECKSUM -33
#define CFE_ERR_BOOTPROGCHKSUM -34
#define CFE_ERR_LDRNOTAVAIL -35
#define CFE_ERR_NOTREADY -36
#define CFE_ERR_GETMEM -37
#define CFE_ERR_SETMEM -38
#define CFE_ERR_NOTCONN -39
#define CFE_ERR_ADDRINUSE -40
linux-7.2.3/arch/mips/include/asm/fw/fw.h
+31
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@@ -0,0 +1,31 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2012 MIPS Technologies, Inc.
*/
#ifndef __ASM_FW_H_
#define __ASM_FW_H_
#include <asm/bootinfo.h> /* For cleaner code... */
extern int fw_argc;
extern int *_fw_argv;
extern int *_fw_envp;
/*
* Most firmware like YAMON, PMON, etc. pass arguments and environment
* variables as 32-bit pointers. These take care of sign extension.
*/
#define fw_argv(index) ((char *)(long)_fw_argv[(index)])
#define fw_envp(index) ((char *)(long)_fw_envp[(index)])
extern void fw_init_cmdline(void);
extern char *fw_getcmdline(void);
extern void fw_meminit(void);
extern char *fw_getenv(char *name);
extern unsigned long fw_getenvl(char *name);
extern void fw_init_early_console(void);
#endif /* __ASM_FW_H_ */
linux-7.2.3/arch/mips/include/asm/ginvt.h
+59
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@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __MIPS_ASM_GINVT_H__
#define __MIPS_ASM_GINVT_H__
#include <asm/mipsregs.h>
enum ginvt_type {
GINVT_FULL,
GINVT_VA,
GINVT_MMID,
};
#ifdef TOOLCHAIN_SUPPORTS_GINV
# define _ASM_SET_GINV ".set ginv\n"
# define _ASM_UNSET_GINV
#else
# define _ASM_SET_GINV \
_ASM_MACRO_1R1I(ginvt, rs, type, \
_ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8)) \
_ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9)))
# define _ASM_UNSET_GINV ".purgem ginvt\n"
#endif
static __always_inline void ginvt(unsigned long addr, enum ginvt_type type)
{
asm volatile(
".set push\n"
_ASM_SET_GINV
" ginvt %0, %1\n"
_ASM_UNSET_GINV
".set pop"
: /* no outputs */
: "r"(addr), "i"(type)
: "memory");
}
static inline void ginvt_full(void)
{
ginvt(0, GINVT_FULL);
}
static inline void ginvt_va(unsigned long addr)
{
addr &= PAGE_MASK << 1;
ginvt(addr, GINVT_VA);
}
static inline void ginvt_mmid(void)
{
ginvt(0, GINVT_MMID);
}
static inline void ginvt_va_mmid(unsigned long addr)
{
addr &= PAGE_MASK << 1;
ginvt(addr, GINVT_VA | GINVT_MMID);
}
#endif /* __MIPS_ASM_GINVT_H__ */
linux-7.2.3/arch/mips/include/asm/gio_device.h
+47
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@@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/device.h>
#include <linux/mod_devicetable.h>
struct gio_device_id {
__u8 id;
};
struct gio_device {
struct device dev;
struct resource resource;
unsigned int irq;
unsigned int slotno;
const char *name;
struct gio_device_id id;
unsigned id32:1;
unsigned gio64:1;
};
#define to_gio_device(d) container_of(d, struct gio_device, dev)
struct gio_driver {
const char *name;
struct module *owner;
const struct gio_device_id *id_table;
int (*probe)(struct gio_device *, const struct gio_device_id *);
void (*remove)(struct gio_device *);
void (*shutdown)(struct gio_device *);
struct device_driver driver;
};
#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
extern struct gio_device *gio_dev_get(struct gio_device *);
extern void gio_dev_put(struct gio_device *);
extern int gio_device_register(struct gio_device *);
extern void gio_device_unregister(struct gio_device *);
extern int gio_register_driver(struct gio_driver *);
extern void gio_unregister_driver(struct gio_driver *);
#define gio_get_drvdata(_dev) dev_get_drvdata(&(_dev)->dev)
#define gio_set_drvdata(_dev, data) dev_set_drvdata(&(_dev)->dev, (data))
extern void gio_set_master(struct gio_device *);
linux-7.2.3/arch/mips/include/asm/gt64120.h
+566
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc.
* All rights reserved.
* Authors: Carsten Langgaard <carstenl@mips.com>
* Maciej W. Rozycki <macro@mips.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef _ASM_GT64120_H
#define _ASM_GT64120_H
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#define MSK(n) ((1 << (n)) - 1)
/*
* Register offset addresses
*/
/* CPU Configuration. */
#define GT_CPU_OFS 0x000
#define GT_MULTI_OFS 0x120
/* CPU Address Decode. */
#define GT_SCS10LD_OFS 0x008
#define GT_SCS10HD_OFS 0x010
#define GT_SCS32LD_OFS 0x018
#define GT_SCS32HD_OFS 0x020
#define GT_CS20LD_OFS 0x028
#define GT_CS20HD_OFS 0x030
#define GT_CS3BOOTLD_OFS 0x038
#define GT_CS3BOOTHD_OFS 0x040
#define GT_PCI0IOLD_OFS 0x048
#define GT_PCI0IOHD_OFS 0x050
#define GT_PCI0M0LD_OFS 0x058
#define GT_PCI0M0HD_OFS 0x060
#define GT_ISD_OFS 0x068
#define GT_PCI0M1LD_OFS 0x080
#define GT_PCI0M1HD_OFS 0x088
#define GT_PCI1IOLD_OFS 0x090
#define GT_PCI1IOHD_OFS 0x098
#define GT_PCI1M0LD_OFS 0x0a0
#define GT_PCI1M0HD_OFS 0x0a8
#define GT_PCI1M1LD_OFS 0x0b0
#define GT_PCI1M1HD_OFS 0x0b8
#define GT_PCI1M1LD_OFS 0x0b0
#define GT_PCI1M1HD_OFS 0x0b8
#define GT_SCS10AR_OFS 0x0d0
#define GT_SCS32AR_OFS 0x0d8
#define GT_CS20R_OFS 0x0e0
#define GT_CS3BOOTR_OFS 0x0e8
#define GT_PCI0IOREMAP_OFS 0x0f0
#define GT_PCI0M0REMAP_OFS 0x0f8
#define GT_PCI0M1REMAP_OFS 0x100
#define GT_PCI1IOREMAP_OFS 0x108
#define GT_PCI1M0REMAP_OFS 0x110
#define GT_PCI1M1REMAP_OFS 0x118
/* CPU Error Report. */
#define GT_CPUERR_ADDRLO_OFS 0x070
#define GT_CPUERR_ADDRHI_OFS 0x078
#define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */
#define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */
#define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */
/* CPU Sync Barrier. */
#define GT_PCI0SYNC_OFS 0x0c0
#define GT_PCI1SYNC_OFS 0x0c8
/* SDRAM and Device Address Decode. */
#define GT_SCS0LD_OFS 0x400
#define GT_SCS0HD_OFS 0x404
#define GT_SCS1LD_OFS 0x408
#define GT_SCS1HD_OFS 0x40c
#define GT_SCS2LD_OFS 0x410
#define GT_SCS2HD_OFS 0x414
#define GT_SCS3LD_OFS 0x418
#define GT_SCS3HD_OFS 0x41c
#define GT_CS0LD_OFS 0x420
#define GT_CS0HD_OFS 0x424
#define GT_CS1LD_OFS 0x428
#define GT_CS1HD_OFS 0x42c
#define GT_CS2LD_OFS 0x430
#define GT_CS2HD_OFS 0x434
#define GT_CS3LD_OFS 0x438
#define GT_CS3HD_OFS 0x43c
#define GT_BOOTLD_OFS 0x440
#define GT_BOOTHD_OFS 0x444
#define GT_ADERR_OFS 0x470
/* SDRAM Configuration. */
#define GT_SDRAM_CFG_OFS 0x448
#define GT_SDRAM_OPMODE_OFS 0x474
#define GT_SDRAM_BM_OFS 0x478
#define GT_SDRAM_ADDRDECODE_OFS 0x47c
/* SDRAM Parameters. */
#define GT_SDRAM_B0_OFS 0x44c
#define GT_SDRAM_B1_OFS 0x450
#define GT_SDRAM_B2_OFS 0x454
#define GT_SDRAM_B3_OFS 0x458
/* Device Parameters. */
#define GT_DEV_B0_OFS 0x45c
#define GT_DEV_B1_OFS 0x460
#define GT_DEV_B2_OFS 0x464
#define GT_DEV_B3_OFS 0x468
#define GT_DEV_BOOT_OFS 0x46c
/* ECC. */
#define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
#define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
#define GT_ECC_MEM 0x488 /* GT-64120A only */
#define GT_ECC_CALC 0x48c /* GT-64120A only */
#define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
/* DMA Record. */
#define GT_DMA0_CNT_OFS 0x800
#define GT_DMA1_CNT_OFS 0x804
#define GT_DMA2_CNT_OFS 0x808
#define GT_DMA3_CNT_OFS 0x80c
#define GT_DMA0_SA_OFS 0x810
#define GT_DMA1_SA_OFS 0x814
#define GT_DMA2_SA_OFS 0x818
#define GT_DMA3_SA_OFS 0x81c
#define GT_DMA0_DA_OFS 0x820
#define GT_DMA1_DA_OFS 0x824
#define GT_DMA2_DA_OFS 0x828
#define GT_DMA3_DA_OFS 0x82c
#define GT_DMA0_NEXT_OFS 0x830
#define GT_DMA1_NEXT_OFS 0x834
#define GT_DMA2_NEXT_OFS 0x838
#define GT_DMA3_NEXT_OFS 0x83c
#define GT_DMA0_CUR_OFS 0x870
#define GT_DMA1_CUR_OFS 0x874
#define GT_DMA2_CUR_OFS 0x878
#define GT_DMA3_CUR_OFS 0x87c
/* DMA Channel Control. */
#define GT_DMA0_CTRL_OFS 0x840
#define GT_DMA1_CTRL_OFS 0x844
#define GT_DMA2_CTRL_OFS 0x848
#define GT_DMA3_CTRL_OFS 0x84c
/* DMA Arbiter. */
#define GT_DMA_ARB_OFS 0x860
/* Timer/Counter. */
#define GT_TC0_OFS 0x850
#define GT_TC1_OFS 0x854
#define GT_TC2_OFS 0x858
#define GT_TC3_OFS 0x85c
#define GT_TC_CONTROL_OFS 0x864
/* PCI Internal. */
#define GT_PCI0_CMD_OFS 0xc00
#define GT_PCI0_TOR_OFS 0xc04
#define GT_PCI0_BS_SCS10_OFS 0xc08
#define GT_PCI0_BS_SCS32_OFS 0xc0c
#define GT_PCI0_BS_CS20_OFS 0xc10
#define GT_PCI0_BS_CS3BT_OFS 0xc14
#define GT_PCI1_IACK_OFS 0xc30
#define GT_PCI0_IACK_OFS 0xc34
#define GT_PCI0_BARE_OFS 0xc3c
#define GT_PCI0_PREFMBR_OFS 0xc40
#define GT_PCI0_SCS10_BAR_OFS 0xc48
#define GT_PCI0_SCS32_BAR_OFS 0xc4c
#define GT_PCI0_CS20_BAR_OFS 0xc50
#define GT_PCI0_CS3BT_BAR_OFS 0xc54
#define GT_PCI0_SSCS10_BAR_OFS 0xc58
#define GT_PCI0_SSCS32_BAR_OFS 0xc5c
#define GT_PCI0_SCS3BT_BAR_OFS 0xc64
#define GT_PCI1_CMD_OFS 0xc80
#define GT_PCI1_TOR_OFS 0xc84
#define GT_PCI1_BS_SCS10_OFS 0xc88
#define GT_PCI1_BS_SCS32_OFS 0xc8c
#define GT_PCI1_BS_CS20_OFS 0xc90
#define GT_PCI1_BS_CS3BT_OFS 0xc94
#define GT_PCI1_BARE_OFS 0xcbc
#define GT_PCI1_PREFMBR_OFS 0xcc0
#define GT_PCI1_SCS10_BAR_OFS 0xcc8
#define GT_PCI1_SCS32_BAR_OFS 0xccc
#define GT_PCI1_CS20_BAR_OFS 0xcd0
#define GT_PCI1_CS3BT_BAR_OFS 0xcd4
#define GT_PCI1_SSCS10_BAR_OFS 0xcd8
#define GT_PCI1_SSCS32_BAR_OFS 0xcdc
#define GT_PCI1_SCS3BT_BAR_OFS 0xce4
#define GT_PCI1_CFGADDR_OFS 0xcf0
#define GT_PCI1_CFGDATA_OFS 0xcf4
#define GT_PCI0_CFGADDR_OFS 0xcf8
#define GT_PCI0_CFGDATA_OFS 0xcfc
/* Interrupts. */
#define GT_INTRCAUSE_OFS 0xc18
#define GT_INTRMASK_OFS 0xc1c
#define GT_PCI0_ICMASK_OFS 0xc24
#define GT_PCI0_SERR0MASK_OFS 0xc28
#define GT_CPU_INTSEL_OFS 0xc70
#define GT_PCI0_INTSEL_OFS 0xc74
#define GT_HINTRCAUSE_OFS 0xc98
#define GT_HINTRMASK_OFS 0xc9c
#define GT_PCI0_HICMASK_OFS 0xca4
#define GT_PCI1_SERR1MASK_OFS 0xca8
/*
* I2O Support Registers
*/
#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
/*
* Register encodings
*/
#define GT_CPU_ENDIAN_SHF 12
#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
#define GT_CPU_WR_SHF 16
#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
#define GT_CPU_WR_BIT GT_CPU_WR_MSK
#define GT_CPU_WR_DXDXDXDX 0
#define GT_CPU_WR_DDDD 1
#define GT_PCI_DCRM_SHF 21
#define GT_PCI_LD_SHF 0
#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
#define GT_PCI_HD_SHF 0
#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
#define GT_PCI_REMAP_SHF 0
#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
#define GT_CFGADDR_CFGEN_SHF 31
#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
#define GT_CFGADDR_BUSNUM_SHF 16
#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
#define GT_CFGADDR_DEVNUM_SHF 11
#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
#define GT_CFGADDR_FUNCNUM_SHF 8
#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
#define GT_CFGADDR_REGNUM_SHF 2
#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
#define GT_SDRAM_BM_ORDER_SHF 2
#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
#define GT_SDRAM_BM_ORDER_SUB 1
#define GT_SDRAM_BM_ORDER_LIN 0
#define GT_SDRAM_BM_RSVD_ALL1 0xffb
#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
#define GT_SDRAM_ADDRDECODE_ADDR_0 0
#define GT_SDRAM_ADDRDECODE_ADDR_1 1
#define GT_SDRAM_ADDRDECODE_ADDR_2 2
#define GT_SDRAM_ADDRDECODE_ADDR_3 3
#define GT_SDRAM_ADDRDECODE_ADDR_4 4
#define GT_SDRAM_ADDRDECODE_ADDR_5 5
#define GT_SDRAM_ADDRDECODE_ADDR_6 6
#define GT_SDRAM_ADDRDECODE_ADDR_7 7
#define GT_SDRAM_B0_CASLAT_SHF 0
#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
#define GT_SDRAM_B0_CASLAT_2 1
#define GT_SDRAM_B0_CASLAT_3 2
#define GT_SDRAM_B0_FTDIS_SHF 2
#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
#define GT_SDRAM_B0_SRASPRCHG_SHF 3
#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
#define GT_SDRAM_B0_SRASPRCHG_2 0
#define GT_SDRAM_B0_SRASPRCHG_3 1
#define GT_SDRAM_B0_B0COMPAB_SHF 4
#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
#define GT_SDRAM_B0_64BITINT_SHF 5
#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2 0
#define GT_SDRAM_B0_64BITINT_4 1
#define GT_SDRAM_B0_BW_SHF 6
#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
#define GT_SDRAM_B0_BW_32 0
#define GT_SDRAM_B0_BW_64 1
#define GT_SDRAM_B0_BLODD_SHF 7
#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
#define GT_SDRAM_B0_PAR_SHF 8
#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
#define GT_SDRAM_B0_BYPASS_SHF 9
#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_2 0
#define GT_SDRAM_B0_SRAS2SCAS_3 1
#define GT_SDRAM_B0_SIZE_SHF 11
#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
#define GT_SDRAM_B0_SIZE_16M 0
#define GT_SDRAM_B0_SIZE_64M 1
#define GT_SDRAM_B0_EXTPAR_SHF 12
#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
#define GT_SDRAM_B0_BLEN_SHF 13
#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
#define GT_SDRAM_B0_BLEN_8 0
#define GT_SDRAM_B0_BLEN_4 1
#define GT_SDRAM_CFG_REFINT_SHF 0
#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
#define GT_SDRAM_CFG_RMW_SHF 15
#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
#define GT_SDRAM_CFG_DUPCNTL_SHF 19
#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
#define GT_SDRAM_CFG_DUPBA_SHF 20
#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
#define GT_SDRAM_CFG_DUPEOT0_SHF 21
#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT1_SHF 22
#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_OPMODE_OP_SHF 0
#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
#define GT_SDRAM_OPMODE_OP_NORMAL 0
#define GT_SDRAM_OPMODE_OP_NOP 1
#define GT_SDRAM_OPMODE_OP_PRCHG 2
#define GT_SDRAM_OPMODE_OP_MODE 3
#define GT_SDRAM_OPMODE_OP_CBR 4
#define GT_TC_CONTROL_ENTC0_SHF 0
#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
#define GT_TC_CONTROL_SELTC0_SHF 1
#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
#define GT_PCI0_BARE_INTIODIS_SHF 3
#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
#define GT_PCI0_BARE_INTMEMDIS_SHF 4
#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
#define GT_PCI0_BARE_CS20DIS_SHF 6
#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
#define GT_PCI0_BARE_SCS32DIS_SHF 7
#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
#define GT_PCI0_BARE_SCS10DIS_SHF 8
#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
#define GT_INTRCAUSE_MASABORT0_SHF 18
#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
#define GT_INTRCAUSE_TARABORT0_SHF 19
#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
#define GT_PCI0_CFGADDR_REGNUM_SHF 2
#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
#define GT_PCI0_CMD_MBYTESWAP_SHF 0
#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
#define GT_PCI0_CMD_MWORDSWAP_SHF 10
#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
#define GT_PCI0_CMD_SBYTESWAP_SHF 16
#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
#define GT_PCI0_CMD_SWORDSWAP_SHF 11
#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
#define GT_INTR_T0EXP_SHF 8
#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
#define GT_INTR_RETRYCTR0_SHF 20
#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
/*
* Misc
*/
#define GT_DEF_PCI0_IO_BASE 0x10000000UL
#define GT_DEF_PCI0_IO_SIZE 0x02000000UL
#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL
#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
#define GT_DEF_BASE 0x14000000UL
#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
#define GT_LATTIM_MIN 6 /* Minimum lat */
/*
* The gt64120_dep.h file must define the following macros
*
* GT_READ(ofs, data_pointer)
* GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit
*
* TIMER - gt64120 timer irq, temporary solution until
* full gt64120 cascade interrupt support is in place
*/
#include <mach-gt64120.h>
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian. We also provide non-swapping versions.
*/
#define __GT_READ(ofs) \
(*(volatile u32 *)(GT64120_BASE+(ofs)))
#define __GT_WRITE(ofs, data) \
do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
extern void gt641xx_set_base_clock(unsigned int clock);
extern int gt641xx_timer0_state(void);
#endif /* _ASM_GT64120_H */
linux-7.2.3/arch/mips/include/asm/hardirq.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997, 98, 99, 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#ifndef _ASM_HARDIRQ_H
#define _ASM_HARDIRQ_H
extern void ack_bad_irq(unsigned int irq);
#define ack_bad_irq ack_bad_irq
#include <asm-generic/hardirq.h>
#endif /* _ASM_HARDIRQ_H */
linux-7.2.3/arch/mips/include/asm/hazards.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) MIPS Technologies, Inc.
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H
#include <linux/stringify.h>
#include <asm/compiler.h>
#define ___ssnop \
sll $0, $0, 1
#define ___ehb \
sll $0, $0, 3
/*
* TLB hazards
*/
#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)) && \
!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
/*
* MIPSR2 defines ehb for hazard avoidance
*/
#define __mtc0_tlbw_hazard \
___ehb
#define __mtc0_tlbr_hazard \
___ehb
#define __tlbw_use_hazard \
___ehb
#define __tlb_read_hazard \
___ehb
#define __tlb_probe_hazard \
___ehb
#define __irq_enable_hazard \
___ehb
#define __irq_disable_hazard \
___ehb
#define __back_to_back_c0_hazard \
___ehb
/*
* gcc has a tradition of misscompiling the previous construct using the
* address of a label as argument to inline assembler. Gas otoh has the
* annoying difference between la and dla which are only usable for 32-bit
* rsp. 64-bit code, so can't be used without conditional compilation.
* The alternative is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code...
*/
#define instruction_hazard() \
do { \
unsigned long tmp; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
" dla %0, 1f \n" \
" jr.hb %0 \n" \
" .set pop \n" \
"1: \n" \
: "=r" (tmp)); \
} while (0)
#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
defined(CONFIG_CPU_BMIPS)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
* run fine on R2 processors.
*/
#define __mtc0_tlbw_hazard \
___ssnop; \
___ssnop; \
___ehb
#define __mtc0_tlbr_hazard \
___ssnop; \
___ssnop; \
___ehb
#define __tlbw_use_hazard \
___ssnop; \
___ssnop; \
___ssnop; \
___ehb
#define __tlb_read_hazard \
___ssnop; \
___ssnop; \
___ssnop; \
___ehb
#define __tlb_probe_hazard \
___ssnop; \
___ssnop; \
___ssnop; \
___ehb
#define __irq_enable_hazard \
___ssnop; \
___ssnop; \
___ssnop; \
___ehb
#define __irq_disable_hazard \
___ssnop; \
___ssnop; \
___ssnop; \
___ehb
#define __back_to_back_c0_hazard \
___ssnop; \
___ssnop; \
___ssnop; \
___ehb
/*
* gcc has a tradition of misscompiling the previous construct using the
* address of a label as argument to inline assembler. Gas otoh has the
* annoying difference between la and dla which are only usable for 32-bit
* rsp. 64-bit code, so can't be used without conditional compilation.
* The alternative is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code...
*/
#define __instruction_hazard() \
do { \
unsigned long tmp; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set mips64r2 \n" \
" dla %0, 1f \n" \
" jr.hb %0 \n" \
" .set pop \n" \
"1: \n" \
: "=r" (tmp)); \
} while (0)
#define instruction_hazard() \
do { \
if (cpu_has_mips_r2_r6) \
__instruction_hazard(); \
} while (0)
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
*/
#define __mtc0_tlbw_hazard
#define __mtc0_tlbr_hazard
#define __tlbw_use_hazard
#define __tlb_read_hazard
#define __tlb_probe_hazard
#define __irq_enable_hazard
#define __irq_disable_hazard
#define __back_to_back_c0_hazard
#define instruction_hazard() do { } while (0)
#elif defined(CONFIG_CPU_SB1)
/*
* Mostly like R4000 for historic reasons
*/
#define __mtc0_tlbw_hazard
#define __mtc0_tlbr_hazard
#define __tlbw_use_hazard
#define __tlb_read_hazard
#define __tlb_probe_hazard
#define __irq_enable_hazard
#define __irq_disable_hazard \
___ssnop; \
___ssnop; \
___ssnop
#define __back_to_back_c0_hazard
#define instruction_hazard() do { } while (0)
#else
/*
* Finally the catchall case for all other processors including R4000, R4400,
* R4600, R4700, R5000, RM7000, NEC VR41xx etc.
*
* The taken branch will result in a two cycle penalty for the two killed
* instructions on R4000 / R4400. Other processors only have a single cycle
* hazard so this is nice trick to have an optimal code for a range of
* processors.
*/
#define __mtc0_tlbw_hazard \
nop; \
nop
#define __mtc0_tlbr_hazard \
nop; \
nop
#define __tlbw_use_hazard \
nop; \
nop; \
nop
#define __tlb_read_hazard \
nop; \
nop; \
nop
#define __tlb_probe_hazard \
nop; \
nop; \
nop
#define __irq_enable_hazard \
___ssnop; \
___ssnop; \
___ssnop
#define __irq_disable_hazard \
nop; \
nop; \
nop
#define __back_to_back_c0_hazard \
___ssnop; \
___ssnop; \
___ssnop
#define instruction_hazard() do { } while (0)
#endif
/* FPU hazards */
#if defined(CONFIG_CPU_SB1)
#define __enable_fpu_hazard \
.set push; \
.set mips64; \
.set noreorder; \
___ssnop; \
bnezl $0, .+4; \
___ssnop; \
.set pop
#define __disable_fpu_hazard
#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
defined(CONFIG_CPU_MIPSR6)
#define __enable_fpu_hazard \
___ehb
#define __disable_fpu_hazard \
___ehb
#else
#define __enable_fpu_hazard \
nop; \
nop; \
nop; \
nop
#define __disable_fpu_hazard \
___ehb
#endif
#ifdef __ASSEMBLER__
#define _ssnop ___ssnop
#define _ehb ___ehb
#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
#define tlbw_use_hazard __tlbw_use_hazard
#define tlb_read_hazard __tlb_read_hazard
#define tlb_probe_hazard __tlb_probe_hazard
#define irq_enable_hazard __irq_enable_hazard
#define irq_disable_hazard __irq_disable_hazard
#define back_to_back_c0_hazard __back_to_back_c0_hazard
#define enable_fpu_hazard __enable_fpu_hazard
#define disable_fpu_hazard __disable_fpu_hazard
#else
#define _ssnop() \
do { \
__asm__ __volatile__( \
__stringify(___ssnop) \
); \
} while (0)
#define _ehb() \
do { \
__asm__ __volatile__( \
__stringify(___ehb) \
); \
} while (0)
#define mtc0_tlbw_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__mtc0_tlbw_hazard) \
); \
} while (0)
#define mtc0_tlbr_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__mtc0_tlbr_hazard) \
); \
} while (0)
#define tlbw_use_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__tlbw_use_hazard) \
); \
} while (0)
#define tlb_read_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__tlb_read_hazard) \
); \
} while (0)
#define tlb_probe_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__tlb_probe_hazard) \
); \
} while (0)
#define irq_enable_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__irq_enable_hazard) \
); \
} while (0)
#define irq_disable_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__irq_disable_hazard) \
); \
} while (0)
#define back_to_back_c0_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__back_to_back_c0_hazard) \
); \
} while (0)
#define enable_fpu_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__enable_fpu_hazard) \
); \
} while (0)
#define disable_fpu_hazard() \
do { \
__asm__ __volatile__( \
__stringify(__disable_fpu_hazard) \
); \
} while (0)
/*
* MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
*/
extern void mips_ihb(void);
#endif /* __ASSEMBLER__ */
#endif /* _ASM_HAZARDS_H */
linux-7.2.3/arch/mips/include/asm/highmem.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* highmem.h: virtual kernel memory mappings for high memory
*
* Used in CONFIG_HIGHMEM systems for memory pages which
* are not addressable by direct kernel virtual addresses.
*
* Copyright (C) 1999 Gerhard Wichert, Siemens AG
* Gerhard.Wichert@pdb.siemens.de
*
*
* Redesigned the x86 32-bit VM architecture to deal with
* up to 16 Terabyte physical memory. With current x86 CPUs
* we now support up to 64 Gigabytes physical RAM.
*
* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
*/
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
#ifdef __KERNEL__
#include <linux/bug.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <asm/cpu-features.h>
#include <asm/kmap_size.h>
/* declarations for highmem.c */
extern unsigned long highstart_pfn, highend_pfn;
extern pte_t *pkmap_page_table;
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM.
*/
#if defined(CONFIG_PHYS_ADDR_T_64BIT) || defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
#define LAST_PKMAP 512
#else
#define LAST_PKMAP 1024
#endif
#define LAST_PKMAP_MASK (LAST_PKMAP-1)
#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
#define ARCH_HAS_KMAP_FLUSH_TLB
extern void kmap_flush_tlb(unsigned long addr);
#define flush_cache_kmaps() BUG_ON(cpu_has_dc_aliases)
#define arch_kmap_local_set_pte(mm, vaddr, ptep, ptev) set_pte(ptep, ptev)
#define arch_kmap_local_post_map(vaddr, pteval) local_flush_tlb_one(vaddr)
#define arch_kmap_local_post_unmap(vaddr) local_flush_tlb_one(vaddr)
#endif /* __KERNEL__ */
#endif /* _ASM_HIGHMEM_H */
linux-7.2.3/arch/mips/include/asm/hpet.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_HPET_H
#define _ASM_HPET_H
#ifdef CONFIG_RS780_HPET
#define HPET_MMAP_SIZE 1024
#define HPET_ID 0x000
#define HPET_PERIOD 0x004
#define HPET_CFG 0x010
#define HPET_STATUS 0x020
#define HPET_COUNTER 0x0f0
#define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
#define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
#define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
#define HPET_T0_IRS 0x001
#define HPET_T1_IRS 0x002
#define HPET_T3_IRS 0x004
#define HPET_T0_CFG 0x100
#define HPET_T0_CMP 0x108
#define HPET_T0_ROUTE 0x110
#define HPET_T1_CFG 0x120
#define HPET_T1_CMP 0x128
#define HPET_T1_ROUTE 0x130
#define HPET_T2_CFG 0x140
#define HPET_T2_CMP 0x148
#define HPET_T2_ROUTE 0x150
#define HPET_ID_REV 0x000000ff
#define HPET_ID_NUMBER 0x00001f00
#define HPET_ID_64BIT 0x00002000
#define HPET_ID_LEGSUP 0x00008000
#define HPET_ID_VENDOR 0xffff0000
#define HPET_ID_NUMBER_SHIFT 8
#define HPET_ID_VENDOR_SHIFT 16
#define HPET_CFG_ENABLE 0x001
#define HPET_CFG_LEGACY 0x002
#define HPET_LEGACY_8254 2
#define HPET_LEGACY_RTC 8
#define HPET_TN_LEVEL 0x0002
#define HPET_TN_ENABLE 0x0004
#define HPET_TN_PERIODIC 0x0008
#define HPET_TN_PERIODIC_CAP 0x0010
#define HPET_TN_64BIT_CAP 0x0020
#define HPET_TN_SETVAL 0x0040
#define HPET_TN_32BIT 0x0100
#define HPET_TN_ROUTE 0x3e00
#define HPET_TN_FSB 0x4000
#define HPET_TN_FSB_CAP 0x8000
#define HPET_TN_ROUTE_SHIFT 9
/* Max HPET Period is 10^8 femto sec as in HPET spec */
#define HPET_MAX_PERIOD 100000000UL
/*
* Min HPET period is 10^5 femto sec just for safety. If it is less than this,
* then 32 bit HPET counter wrapsaround in less than 0.5 sec.
*/
#define HPET_MIN_PERIOD 100000UL
#define HPET_ADDR 0x20000
#define HPET_MMIO_ADDR 0x90000e0000020000
#define HPET_FREQ 14318780
#define HPET_COMPARE_VAL ((HPET_FREQ + HZ / 2) / HZ)
#define HPET_T0_IRQ 0
extern void __init setup_hpet_timer(void);
#endif /* CONFIG_RS780_HPET */
#endif /* _ASM_HPET_H */
linux-7.2.3/arch/mips/include/asm/hugetlb.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008, 2009 Cavium Networks, Inc.
*/
#ifndef __ASM_HUGETLB_H
#define __ASM_HUGETLB_H
#include <asm/page.h>
#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
unsigned long addr, pte_t *ptep,
unsigned long sz)
{
pte_t clear;
pte_t pte = *ptep;
pte_val(clear) = (unsigned long)invalid_pte_table;
set_pte_at(mm, addr, ptep, clear);
return pte;
}
#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
static inline pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t pte;
unsigned long sz = huge_page_size(hstate_vma(vma));
/*
* clear the huge pte entry firstly, so that the other smp threads will
* not get old pte entry after finishing flush_tlb_page and before
* setting new huge pte entry
*/
pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep, sz);
flush_tlb_page(vma, addr);
return pte;
}
#define __HAVE_ARCH_HUGE_PTE_NONE
static inline int huge_pte_none(pte_t pte)
{
unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
return !val || (val == (unsigned long)invalid_pte_table);
}
#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr,
pte_t *ptep, pte_t pte,
int dirty)
{
int changed = !pte_same(*ptep, pte);
if (changed) {
set_pte_at(vma->vm_mm, addr, ptep, pte);
/*
* There could be some standard sized pages in there,
* get them all.
*/
flush_tlb_range(vma, addr, addr + HPAGE_SIZE);
}
return changed;
}
#include <asm-generic/hugetlb.h>
#endif /* __ASM_HUGETLB_H */
linux-7.2.3/arch/mips/include/asm/hw_irq.h
+20
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000, 2001, 2002 by Ralf Baechle
*/
#ifndef __ASM_HW_IRQ_H
#define __ASM_HW_IRQ_H
#include <linux/atomic.h>
extern atomic_t irq_err_count;
/*
* interrupt-retrigger: NOP for now. This may not be appropriate for all
* machines, we'll see ...
*/
#endif /* __ASM_HW_IRQ_H */
linux-7.2.3/arch/mips/include/asm/i8259.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/i8259.h
*
* i8259A interrupt definitions.
*
* Copyright (C) 2003 Maciej W. Rozycki
* Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_I8259_H
#define _ASM_I8259_H
#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <irq.h>
/* i8259A PIC registers */
#define PIC_MASTER_CMD 0x20
#define PIC_MASTER_IMR 0x21
#define PIC_MASTER_ISR PIC_MASTER_CMD
#define PIC_MASTER_POLL PIC_MASTER_ISR
#define PIC_MASTER_OCW3 PIC_MASTER_ISR
#define PIC_SLAVE_CMD 0xa0
#define PIC_SLAVE_IMR 0xa1
/* i8259A PIC related value */
#define PIC_CASCADE_IR 2
#define MASTER_ICW4_DEFAULT 0x01
#define SLAVE_ICW4_DEFAULT 0x01
#define PIC_ICW4_AEOI 2
extern raw_spinlock_t i8259A_lock;
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
extern struct irq_domain *__init_i8259_irqs(struct device_node *node);
/**
* i8159_set_poll() - Override the i8259 polling function
* @poll: pointer to platform-specific polling function
*
* Call this to override the generic i8259 polling function, which directly
* accesses i8259 registers, with a platform specific one which may be faster
* in cases where hardware provides a more optimal means of polling for an
* interrupt.
*/
extern void i8259_set_poll(int (*poll)(void));
/*
* Do the traditional i8259 interrupt polling thing. This is for the few
* cases where no better interrupt acknowledge method is available and we
* absolutely must touch the i8259.
*/
static inline int i8259_irq(void)
{
int irq;
raw_spin_lock(&i8259A_lock);
/* Perform an interrupt acknowledge cycle on controller 1. */
outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
irq = inb(PIC_MASTER_CMD) & 7;
if (irq == PIC_CASCADE_IR) {
/*
* Interrupt is cascaded so perform interrupt
* acknowledge on controller 2.
*/
outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
}
if (unlikely(irq == 7)) {
/*
* This may be a spurious interrupt.
*
* Read the interrupt status register (ISR). If the most
* significant bit is not set then there is no valid
* interrupt.
*/
outb(0x0B, PIC_MASTER_ISR); /* ISR register */
if(~inb(PIC_MASTER_ISR) & 0x80)
irq = -1;
}
raw_spin_unlock(&i8259A_lock);
return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
}
#endif /* _ASM_I8259_H */
linux-7.2.3/arch/mips/include/asm/idle.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_IDLE_H
#define __ASM_IDLE_H
#include <linux/cpuidle.h>
#include <linux/linkage.h>
extern void (*cpu_wait)(void);
extern asmlinkage void r4k_wait(void);
extern void r4k_wait_irqoff(void);
static inline int using_skipover_handler(void)
{
return cpu_wait == r4k_wait;
}
extern void __init check_wait(void);
extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
#define MIPS_CPUIDLE_WAIT_STATE {\
.enter = mips_cpuidle_wait_enter,\
.exit_latency = 1,\
.target_residency = 1,\
.power_usage = UINT_MAX,\
.name = "wait",\
.desc = "MIPS wait",\
}
#endif /* __ASM_IDLE_H */

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