lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+77
View File
@@ -0,0 +1,77 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 Cavium Networks
*/
#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
#include <linux/types.h>
#include <asm/mipsregs.h>
/*
* Cavium Octeons are MIPS64v2 processors
*/
#define cpu_dcache_line_size() 128
#define cpu_icache_line_size() 128
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_llsc 1
/*
* We Disable LL/SC on non SMP systems as it is faster to disable
* interrupts for atomic access than a LL/SC.
*/
#ifdef CONFIG_SMP
# define kernel_uses_llsc 1
#else
# define kernel_uses_llsc 0
#endif
#define cpu_has_vtag_icache 1
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_64bits 1
#define cpu_has_octeon_cache 1
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 1
#define cpu_has_mips64r2 1
#define cpu_has_dsp 0
#define cpu_has_dsp2 0
#define cpu_has_mipsmt 0
#define cpu_has_vint 0
#define cpu_has_veic 0
#define cpu_hwrena_impl_bits (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
#define cpu_has_wsbh 1
#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
#define PREFETCH_STRIDE 128
#ifdef __OCTEON__
/*
* All gcc versions that have OCTEON support define __OCTEON__ and have the
* __builtin_popcount support.
*/
#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
#endif
/*
* The last 256MB are reserved for device to device mappings and the
* BAR1 hole.
*/
#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
#endif
linux-7.2.3/arch/mips/include/asm/mach-cavium-octeon/irq.h
+58
View File
@@ -0,0 +1,58 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004-2008 Cavium Networks
*/
#ifndef __OCTEON_IRQ_H__
#define __OCTEON_IRQ_H__
#define NR_IRQS OCTEON_IRQ_LAST
#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
enum octeon_irq {
/* 1 - 8 represent the 8 MIPS standard interrupt sources */
OCTEON_IRQ_SW0 = 1,
OCTEON_IRQ_SW1,
/* CIU0, CUI2, CIU4 are 3, 4, 5 */
OCTEON_IRQ_5 = 6,
OCTEON_IRQ_PERF,
OCTEON_IRQ_TIMER,
/* sources in CIU_INTX_EN0 */
OCTEON_IRQ_WORKQ0,
OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
OCTEON_IRQ_MBOX1,
OCTEON_IRQ_MBOX2,
OCTEON_IRQ_MBOX3,
OCTEON_IRQ_PCI_INT0,
OCTEON_IRQ_PCI_INT1,
OCTEON_IRQ_PCI_INT2,
OCTEON_IRQ_PCI_INT3,
OCTEON_IRQ_PCI_MSI0,
OCTEON_IRQ_PCI_MSI1,
OCTEON_IRQ_PCI_MSI2,
OCTEON_IRQ_PCI_MSI3,
OCTEON_IRQ_TWSI,
OCTEON_IRQ_TWSI2,
OCTEON_IRQ_RML,
OCTEON_IRQ_TIMER0,
OCTEON_IRQ_TIMER1,
OCTEON_IRQ_TIMER2,
OCTEON_IRQ_TIMER3,
#ifndef CONFIG_PCI_MSI
OCTEON_IRQ_LAST = 127
#endif
};
#ifdef CONFIG_PCI_MSI
/* 256 - 511 represent the MSI interrupts 0-255 */
#define OCTEON_IRQ_MSI_BIT0 (256)
#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
#endif
#endif
linux-7.2.3/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+168
View File
@@ -0,0 +1,168 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2008 Cavium Networks, Inc
*/
#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
#define CP0_CVMCTL_REG $9, 7
#define CP0_CVMMEMCTL_REG $11,7
#define CP0_PRID_REG $15, 0
#define CP0_DCACHE_ERR_REG $27, 1
#define CP0_PRID_OCTEON_PASS1 0x000d0000
#define CP0_PRID_OCTEON_CN30XX 0x000d0200
.macro kernel_entry_setup
# Registers set by bootloader:
# (only 32 bits set by bootloader, all addresses are physical
# addresses, and need to have the appropriate memory region set
# by the kernel
# a0 = argc
# a1 = argv (kseg0 compat addr)
# a2 = 1 if init core, zero otherwise
# a3 = address of boot descriptor block
.set push
.set arch=octeon
# Read the cavium mem control register
dmfc0 v0, CP0_CVMMEMCTL_REG
# Clear the lower 6 bits, the CVMSEG size
dins v0, $0, 0, 6
ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
# Disable unaligned load/store support but leave HW fixup enabled
# Needed for octeon specific memcpy
or v0, v0, 0x5001
xor v0, v0, 0x1001
# First clear off CvmCtl[IPPCI] bit and move the performance
# counters interrupt to IRQ 6
dli v1, ~(7 << 7)
and v0, v0, v1
ori v0, v0, (6 << 7)
mfc0 v1, CP0_PRID_REG
and t1, v1, 0xfff8
xor t1, t1, 0x9000 # 63-P1
beqz t1, 4f
and t1, v1, 0xfff8
xor t1, t1, 0x9008 # 63-P2
beqz t1, 4f
and t1, v1, 0xfff8
xor t1, t1, 0x9100 # 68-P1
beqz t1, 4f
and t1, v1, 0xff00
xor t1, t1, 0x9200 # 66-PX
bnez t1, 5f # Skip WAR for others.
and t1, v1, 0x00ff
slti t1, t1, 2 # 66-P1.2 and later good.
beqz t1, 5f
4: # core-16057 work around
or v0, v0, 0x2000 # Set IPREF bit.
5: # No core-16057 work around
# Write the cavium control register
dmtc0 v0, CP0_CVMCTL_REG
sync
# Flush dcache after config change
cache 9, 0($0)
# Zero all of CVMSEG to make sure parity is correct
dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
dsll v0, 7
beqz v0, 2f
1: dsubu v0, 8
sd $0, -32768(v0)
bnez v0, 1b
2:
mfc0 v0, CP0_PRID_REG
bbit0 v0, 15, 1f
# OCTEON II or better have bit 15 set. Clear the error bits.
and t1, v0, 0xff00
dli v0, 0x9500
bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0
dli v0, 0x27
dmtc0 v0, CP0_DCACHE_ERR_REG
1:
# Get my core id
rdhwr v0, $0
# Jump the master to kernel_entry
bne a2, zero, octeon_main_processor
nop
#ifdef CONFIG_SMP
#
# All cores other than the master need to wait here for SMP bootstrap
# to begin
#
octeon_spin_wait_boot:
#ifdef CONFIG_RELOCATABLE
PTR_LA t0, octeon_processor_relocated_kernel_entry
LONG_L t0, (t0)
beq zero, t0, 1f
nop
jr t0
nop
1:
#endif /* CONFIG_RELOCATABLE */
# This is the variable where the next core to boot is stored
PTR_LA t0, octeon_processor_boot
# Get the core id of the next to be booted
LONG_L t1, (t0)
# Keep looping if it isn't me
bne t1, v0, octeon_spin_wait_boot
nop
# Get my GP from the global variable
PTR_LA t0, octeon_processor_gp
LONG_L gp, (t0)
# Get my SP from the global variable
PTR_LA t0, octeon_processor_sp
LONG_L sp, (t0)
# Set the SP global variable to zero so the master knows we've started
LONG_S zero, (t0)
#ifdef __OCTEON__
syncw
syncw
#else
sync
#endif
# Jump to the normal Linux SMP entry point
j smp_bootstrap
nop
#else /* CONFIG_SMP */
#
# Someone tried to boot SMP with a non SMP kernel. All extra cores
# will halt here.
#
octeon_wait_forever:
wait
b octeon_wait_forever
nop
#endif /* CONFIG_SMP */
octeon_main_processor:
.set pop
.endm
/*
* Do SMP slave processor setup necessary before we can safely execute C code.
*/
.macro smp_slave_setup
.endm
#define USE_KEXEC_SMP_WAIT_FINAL
.macro kexec_smp_wait_final
.set push
.set noreorder
synci 0($0)
.set pop
.endm
#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
linux-7.2.3/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
+64
View File
@@ -0,0 +1,64 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
#define __ASM_MACH_GENERIC_MANGLE_PORT_H
#include <asm/byteorder.h>
#ifdef __BIG_ENDIAN
static inline bool __should_swizzle_bits(volatile void *a)
{
extern const bool octeon_should_swizzle_table[];
u64 did = ((u64)(uintptr_t)a >> 40) & 0xff;
return octeon_should_swizzle_table[did];
}
# define __swizzle_addr_b(port) (port)
# define __swizzle_addr_w(port) (port)
# define __swizzle_addr_l(port) (port)
# define __swizzle_addr_q(port) (port)
#else /* __LITTLE_ENDIAN */
#define __should_swizzle_bits(a) false
static inline bool __should_swizzle_addr(u64 p)
{
/* boot bus? */
return ((p >> 40) & 0xff) == 0;
}
# define __swizzle_addr_b(port) \
(__should_swizzle_addr(port) ? (port) ^ 7 : (port))
# define __swizzle_addr_w(port) \
(__should_swizzle_addr(port) ? (port) ^ 6 : (port))
# define __swizzle_addr_l(port) \
(__should_swizzle_addr(port) ? (port) ^ 4 : (port))
# define __swizzle_addr_q(port) (port)
#endif /* __BIG_ENDIAN */
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (__should_swizzle_bits(a) ? \
le16_to_cpu((__force __le16)(x)) : \
(x))
# define __mem_ioswabw(a, x) (x)
# define ioswabl(a, x) (__should_swizzle_bits(a) ? \
le32_to_cpu((__force __le32)(x)) : \
(x))
# define __mem_ioswabl(a, x) (x)
# define ioswabq(a, x) (__should_swizzle_bits(a) ? \
le64_to_cpu((__force __le64)(x)) : \
(x))
# define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
linux-7.2.3/arch/mips/include/asm/mach-cavium-octeon/spaces.h
+24
View File
@@ -0,0 +1,24 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2012 Cavium, Inc.
*/
#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
#include <linux/const.h>
#ifdef CONFIG_64BIT
/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
#define CAC_BASE _AC(0x8000000000000000, UL)
#define UNCAC_BASE _AC(0x8000000000000000, UL)
#define IO_BASE _AC(0x8000000000000000, UL)
#endif /* CONFIG_64BIT */
#include <asm/mach-generic/spaces.h>
#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */