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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Lantiq FALCON specific CPU feature overrides
*
* Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*/
#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_sb1_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_prefetch 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 1
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 1
#define cpu_has_mipsmt 1
#define cpu_has_vint 1
#define cpu_has_veic 1
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
linux-7.2.3/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
*/
#ifndef _FALCON_IRQ__
#define _FALCON_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define MAX_IM 5
#endif /* _FALCON_IRQ__ */
linux-7.2.3/arch/mips/include/asm/mach-lantiq/falcon/irq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
*/
#ifndef __FALCON_IRQ_H
#define __FALCON_IRQ_H
#include <falcon_irq.h>
#define NR_IRQS 328
#include <asm/mach-generic/irq.h>
#endif
linux-7.2.3/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
#ifndef _LTQ_FALCON_H__
#define _LTQ_FALCON_H__
#ifdef CONFIG_SOC_FALCON
#include <linux/pinctrl/pinctrl.h>
#include <lantiq.h>
/* Chip IDs */
#define SOC_ID_FALCON 0x01B8
/* SoC Types */
#define SOC_TYPE_FALCON 0x01
/*
* during early_printk no ioremap possible at this early stage
* let's use KSEG1 instead
*/
#define LTQ_ASC0_BASE_ADDR 0x1E100C00
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
/* WDT */
#define LTQ_RST_CAUSE_WDTRST 0x0002
/* CHIP ID */
#define LTQ_STATUS_BASE_ADDR 0x1E802000
#define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
#define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
#define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
#define SYSCTL_SYS1 0
#define SYSCTL_SYSETH 1
#define SYSCTL_SYSGPE 2
/* BOOT_SEL - find what boot media we have */
#define BS_FLASH 0x1
#define BS_SPI 0x4
/* global register ranges */
extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_sys1_membase;
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
/* allow the gpio and pinctrl drivers to talk to each other */
extern int pinctrl_falcon_get_range_size(int id);
extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
/*
* to keep the irq code generic we need to define this to 0 as falcon
* has no EIU/EBU
*/
#define LTQ_EBU_PCC_ISTAT 0
#endif /* CONFIG_SOC_FALCON */
#endif /* _LTQ_XWAY_H__ */
linux-7.2.3/arch/mips/include/asm/mach-lantiq/lantiq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
#ifndef _LANTIQ_H__
#define _LANTIQ_H__
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/clk.h>
/* generic reg access functions */
#define ltq_r32(reg) __raw_readl(reg)
#define ltq_w32(val, reg) __raw_writel(val, reg)
#define ltq_w32_mask(clear, set, reg) \
ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
#define ltq_r8(reg) __raw_readb(reg)
#define ltq_w8(val, reg) __raw_writeb(val, reg)
/* register access macros for EBU and CGU */
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
#define ltq_ebu_w32_mask(x, y, z) \
ltq_w32_mask(x, y, ltq_ebu_membase + (z))
extern __iomem void *ltq_ebu_membase;
/* spinlock all ebu i/o */
extern spinlock_t ebu_lock;
/* some irq helpers */
extern void ltq_disable_irq(struct irq_data *data);
extern void ltq_mask_and_ack_irq(struct irq_data *data);
extern void ltq_enable_irq(struct irq_data *data);
extern int ltq_eiu_get_irq(int exin);
/* clock handling */
extern int clk_activate(struct clk *clk);
extern void clk_deactivate(struct clk *clk);
extern struct clk *clk_get_cpu(void);
extern struct clk *clk_get_fpi(void);
extern struct clk *clk_get_io(void);
extern struct clk *clk_get_ppe(void);
/* find out what bootsource we have */
extern unsigned char ltq_boot_select(void);
/* find out the soc type */
extern int ltq_soc_type(void);
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
#endif
linux-7.2.3/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
#ifndef _LANTIQ_PLATFORM_H__
#define _LANTIQ_PLATFORM_H__
#include <linux/socket.h>
/* struct used to pass info to network drivers */
struct ltq_eth_data {
struct sockaddr mac;
int mii_mode;
};
#endif
linux-7.2.3/arch/mips/include/asm/mach-lantiq/xway/irq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
#ifndef __LANTIQ_IRQ_H
#define __LANTIQ_IRQ_H
#include <lantiq_irq.h>
#define NR_IRQS 256
#include <asm/mach-generic/irq.h>
#endif
linux-7.2.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
#ifndef _LANTIQ_XWAY_IRQ_H__
#define _LANTIQ_XWAY_IRQ_H__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define MAX_IM 5
#endif
linux-7.2.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
#ifndef _LTQ_XWAY_H__
#define _LTQ_XWAY_H__
#ifdef CONFIG_SOC_TYPE_XWAY
#include <lantiq.h>
/* Chip IDs */
#define SOC_ID_DANUBE1 0x129
#define SOC_ID_DANUBE2 0x12B
#define SOC_ID_TWINPASS 0x12D
#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
#define SOC_ID_ARX188 0x16C
#define SOC_ID_ARX168_1 0x16D
#define SOC_ID_ARX168_2 0x16E
#define SOC_ID_ARX182 0x16F
#define SOC_ID_GRX188 0x170
#define SOC_ID_GRX168 0x171
#define SOC_ID_VRX288 0x1C0 /* v1.1 */
#define SOC_ID_VRX282 0x1C1 /* v1.1 */
#define SOC_ID_VRX268 0x1C2 /* v1.1 */
#define SOC_ID_GRX268 0x1C8 /* v1.1 */
#define SOC_ID_GRX288 0x1C9 /* v1.1 */
#define SOC_ID_VRX288_2 0x00B /* v1.2 */
#define SOC_ID_VRX268_2 0x00C /* v1.2 */
#define SOC_ID_GRX288_2 0x00D /* v1.2 */
#define SOC_ID_GRX282_2 0x00E /* v1.2 */
#define SOC_ID_VRX220 0x000
#define SOC_ID_ARX362 0x004
#define SOC_ID_ARX368 0x005
#define SOC_ID_ARX382 0x007
#define SOC_ID_ARX388 0x008
#define SOC_ID_URX388 0x009
#define SOC_ID_GRX383 0x010
#define SOC_ID_GRX369 0x011
#define SOC_ID_GRX387 0x00F
#define SOC_ID_GRX389 0x012
/* SoC Types */
#define SOC_TYPE_DANUBE 0x01
#define SOC_TYPE_TWINPASS 0x02
#define SOC_TYPE_AR9 0x03
#define SOC_TYPE_VR9 0x04 /* v1.1 */
#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
#define SOC_TYPE_AMAZON_SE 0x06
#define SOC_TYPE_AR10 0x07
#define SOC_TYPE_GRX390 0x08
#define SOC_TYPE_VRX220 0x09
/* BOOT_SEL - find what boot media we have */
#define BS_EXT_ROM 0x0
#define BS_FLASH 0x1
#define BS_MII0 0x2
#define BS_PCI 0x3
#define BS_UART1 0x4
#define BS_SPI 0x5
#define BS_NAND 0x6
#define BS_RMII0 0x7
/* helpers used to access the cgu */
#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
extern __iomem void *ltq_cgu_membase;
/*
* during early_printk no ioremap is possible
* let's use KSEG1 instead
*/
#define LTQ_ASC1_BASE_ADDR 0x1E100C00
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
/* EBU - external bus unit */
#define LTQ_EBU_BUSCON0 0x0060
#define LTQ_EBU_PCC_CON 0x0090
#define LTQ_EBU_PCC_IEN 0x00A4
#define LTQ_EBU_PCC_ISTAT 0x00A0
#define LTQ_EBU_BUSCON1 0x0064
#define LTQ_EBU_ADDRSEL1 0x0024
#define EBU_WRDIS 0x80000000
/* WDT */
#define LTQ_RST_CAUSE_WDTRST 0x20
/* MPS - multi processor unit (voice) */
#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
/* request a non-gpio and set the PIO config */
#define PMU_PPE BIT(13)
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
/* VMMC */
extern unsigned int *ltq_get_cp1_base(void);
#endif /* CONFIG_SOC_TYPE_XWAY */
#endif /* _LTQ_XWAY_H__ */
linux-7.2.3/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright (C) 2011 John Crispin <john@phrozen.org>
*/
#ifndef LTQ_DMA_H__
#define LTQ_DMA_H__
#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */
#define LTQ_DESC_NUM 0xC0 /* 192 descriptors / channel */
#define LTQ_DMA_OWN BIT(31) /* owner bit */
#define LTQ_DMA_C BIT(30) /* complete bit */
#define LTQ_DMA_SOP BIT(29) /* start of packet */
#define LTQ_DMA_EOP BIT(28) /* end of packet */
#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */
#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */
#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */
struct ltq_dma_desc {
u32 ctl;
u32 addr;
};
struct ltq_dma_channel {
int nr; /* the channel number */
int irq; /* the mapped irq */
int desc; /* the current descriptor */
struct ltq_dma_desc *desc_base; /* the descriptor base */
int phys; /* physical addr */
struct device *dev;
};
enum {
DMA_PORT_ETOP = 0,
DMA_PORT_DEU,
};
extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
extern void ltq_dma_open(struct ltq_dma_channel *ch);
extern void ltq_dma_close(struct ltq_dma_channel *ch);
extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
extern void ltq_dma_free(struct ltq_dma_channel *ch);
extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
#endif