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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/arch/parisc/Kbuild
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# SPDX-License-Identifier: GPL-2.0-only
obj-y += mm/ kernel/ math-emu/ net/
# for cleaning
subdir- += boot
linux-7.2.3/arch/parisc/Kconfig
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# SPDX-License-Identifier: GPL-2.0
config PARISC
def_bool y
select ALTERNATE_USER_ADDRESS_SPACE
select ARCH_32BIT_OFF_T if !64BIT
select ARCH_MIGHT_HAVE_PC_PARPORT
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_SYSCALL_TRACEPOINTS
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANTS_MODULES_TEXT_SECTIONS if !64BIT
select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_DMA_ALLOC if PA11
select ARCH_HAS_DMA_OPS
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_HAS_STRICT_MODULE_RWX
select ARCH_HAS_UBSAN
select ARCH_HAS_PTE_SPECIAL
select ARCH_NO_SG_CHAIN
select ARCH_SPLIT_ARG64 if !64BIT
select ARCH_SUPPORTS_HUGETLBFS if PA20
select ARCH_SUPPORTS_MEMORY_FAILURE
select ARCH_STACKWALK
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select HAVE_RELIABLE_STACKTRACE
select RTC_CLASS
select RTC_DRV_GENERIC
select INIT_ALL_POSSIBLE
select BUG
select HAVE_KERNEL_UNCOMPRESSED
select HAVE_PCI
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
select PERF_USE_VMALLOC
select HAVE_KERNEL_BZIP2
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZ4
select HAVE_KERNEL_LZMA
select HAVE_KERNEL_LZO
select HAVE_KERNEL_XZ
select GENERIC_ATOMIC64 if !64BIT
select GENERIC_IRQ_PROBE
select GENERIC_PCI_IOMAP
select GENERIC_IOREMAP
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
select GENERIC_ARCH_TOPOLOGY if SMP
select ARCH_SUPPORTS_SCHED_MC if SMP && PA8X00
select GENERIC_CPU_DEVICES if !SMP
select GENERIC_LIB_DEVMEM_IS_ALLOWED
select SYSCTL_ARCH_UNALIGN_ALLOW
select SYSCTL_ARCH_UNALIGN_NO_WARN
select SYSCTL_EXCEPTION_TRACE
select HAVE_MOD_ARCH_SPECIFIC
select MODULES_USE_ELF_RELA
select CLONE_BACKWARDS
select TTY # Needed for pdc_cons.c
select HAS_IOPORT if PCI || EISA
select HAVE_DEBUG_STACKOVERFLOW
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
select HAVE_ARCH_MMAP_RND_BITS
select HAVE_ARCH_AUDITSYSCALL
select HAVE_ARCH_HASH
# select HAVE_ARCH_JUMP_LABEL
# select HAVE_ARCH_JUMP_LABEL_RELATIVE
select HAVE_ARCH_KFENCE
select HAVE_ARCH_SECCOMP_FILTER
select HAVE_ARCH_TRACEHOOK
select HAVE_EBPF_JIT
select ARCH_WANT_DEFAULT_BPF_JIT
select HAVE_REGS_AND_STACK_ACCESS_API
select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
select GENERIC_SCHED_CLOCK
select GENERIC_IRQ_MIGRATION if SMP
select HAVE_UNSTABLE_SCHED_CLOCK if SMP
select GENERIC_CLOCKEVENTS
select CPU_NO_EFFICIENT_FFS
select THREAD_INFO_IN_TASK
select MMU_GATHER_RCU_TABLE_FREE
select NEED_DMA_MAP_STATE
select NEED_SG_DMA_LENGTH
select HAVE_ARCH_KGDB
select HAVE_KPROBES
select HAVE_KRETPROBES
select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY if DYNAMIC_FTRACE
select HAVE_KPROBES_ON_FTRACE
select HAVE_DYNAMIC_FTRACE_WITH_REGS
select HAVE_SOFTIRQ_ON_OWN_STACK if IRQSTACKS
select TRACE_IRQFLAGS_SUPPORT
select HAVE_FUNCTION_DESCRIPTORS if 64BIT
select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
help
The PA-RISC microprocessor is designed by Hewlett-Packard and used
in many of their workstations & servers (HP9000 700 and 800 series,
and later HP3000 series). The PA-RISC Linux project home page is
at <https://parisc.wiki.kernel.org>.
config CPU_BIG_ENDIAN
def_bool y
config MMU
def_bool y
config STACK_GROWSUP
def_bool y
config GENERIC_LOCKBREAK
bool
default y
depends on SMP && PREEMPTION
config ARCH_HAS_ILOG2_U32
bool
default n
config ARCH_HAS_ILOG2_U64
bool
default n
config GENERIC_BUG
def_bool y
depends on BUG
select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
config GENERIC_BUG_RELATIVE_POINTERS
bool
config GENERIC_CSUM
def_bool y
config GENERIC_HWEIGHT
bool
default y
config GENERIC_CALIBRATE_DELAY
bool
default y
config TIME_LOW_RES
bool
depends on SMP
default y
config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT
default 8
config ARCH_MMAP_RND_COMPAT_BITS_MIN
default 8
config ARCH_MMAP_RND_BITS_MAX
default 18 if 64BIT
default 13
config ARCH_MMAP_RND_COMPAT_BITS_MAX
default 13
# unless you want to implement ACPI on PA-RISC ... ;-)
config PM
bool
config STACKTRACE_SUPPORT
def_bool y
config LOCKDEP_SUPPORT
bool
default y
config ISA_DMA_API
bool
config ARCH_MAY_HAVE_PC_FDC
bool
depends on BROKEN
default y
config PGTABLE_LEVELS
int
default 3 if 64BIT && PARISC_PAGE_SIZE_4KB
default 2
menu "Processor type and features"
choice
prompt "Processor type"
default PA7000 if "$(ARCH)" = "parisc"
config PA7000
bool "PA7000/PA7100" if "$(ARCH)" = "parisc"
help
This is the processor type of your CPU. This information is
used for optimizing purposes. In order to compile a kernel
that can run on all 32-bit PA CPUs (albeit not optimally fast),
you can specify "PA7000" here.
Specifying "PA8000" here will allow you to select a 64-bit kernel
which is required on some machines.
config PA7100LC
bool "PA7100LC" if "$(ARCH)" = "parisc"
help
Select this option for the PCX-L processor, as used in the
712, 715/64, 715/80, 715/100, 715/100XC, 725/100, 743, 748,
D200, D210, D300, D310 and E-class
config PA7200
bool "PA7200" if "$(ARCH)" = "parisc"
help
Select this option for the PCX-T' processor, as used in the
C100, C110, J100, J110, J210XC, D250, D260, D350, D360,
K100, K200, K210, K220, K400, K410 and K420
config PA7300LC
bool "PA7300LC" if "$(ARCH)" = "parisc"
help
Select this option for the PCX-L2 processor, as used in the
744, A180, B132L, B160L, B180L, C132L, C160L, C180L,
D220, D230, D320 and D330.
config PA8X00
bool "PA8000 and up"
help
Select this option for PCX-U to PCX-W2 processors.
endchoice
# Define implied options from the CPU selection here
config PA20
def_bool y
depends on PA8X00
config PA11
def_bool y
depends on PA7000 || PA7100LC || PA7200 || PA7300LC
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
config PREFETCH
def_bool y
depends on PA8X00 || PA7200
config PARISC_HUGE_KERNEL
def_bool y if !MODULES || UBSAN || FTRACE || COMPILE_TEST
config MLONGCALLS
bool "Enable the -mlong-calls compiler option for big kernels" if !PARISC_HUGE_KERNEL
depends on PA8X00
default PARISC_HUGE_KERNEL
help
If you configure the kernel to include many drivers built-in instead
as modules, the kernel executable may become too big, so that the
linker will not be able to resolve some long branches and fails to link
your vmlinux kernel. In that case enabling this option will help you
to overcome this limit by using the -mlong-calls compiler option.
Usually you want to say N here, unless you e.g. want to build
a kernel which includes all necessary drivers built-in and which can
be used for TFTP booting without the need to have an initrd ramdisk.
Enabling this option will probably slow down your kernel.
config 64BIT
bool "64-bit kernel" if "$(ARCH)" = "parisc"
depends on PA8X00
default "$(ARCH)" = "parisc64"
help
Enable this if you want to support 64bit kernel on PA-RISC platform.
At the moment, only people willing to use more than 2GB of RAM,
or having a 64bit-only capable PA-RISC machine should say Y here.
Since there is no 64bit userland on PA-RISC, there is no point to
enable this option otherwise. The 64bit kernel is significantly bigger
and slower than the 32bit one.
choice
prompt "Kernel page size"
default PARISC_PAGE_SIZE_4KB
config PARISC_PAGE_SIZE_4KB
bool "4KB"
select HAVE_PAGE_SIZE_4KB
help
This lets you select the page size of the kernel. For best
performance, a page size of 16KB is recommended. For best
compatibility with 32bit applications, a page size of 4KB should be
selected (the vast majority of 32bit binaries work perfectly fine
with a larger page size).
4KB For best 32bit compatibility
16KB For best performance
64KB For best performance, might give more overhead.
If you don't know what to do, choose 4KB.
config PARISC_PAGE_SIZE_16KB
bool "16KB"
select HAVE_PAGE_SIZE_16KB
depends on PA8X00 && BROKEN && !KFENCE
config PARISC_PAGE_SIZE_64KB
bool "64KB"
select HAVE_PAGE_SIZE_64KB
depends on PA8X00 && BROKEN && !KFENCE
endchoice
config SMP
bool "Symmetric multi-processing support"
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, say N. If you have a system with more
than one CPU, say Y.
If you say N here, the kernel will run on uni- and multiprocessor
machines, but will use only one CPU of a multiprocessor machine.
On a uniprocessor machine, the kernel will run faster if you say N.
See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO
available at <https://www.tldp.org/docs.html#howto>.
If you don't know what to do here, say N.
config IRQSTACKS
bool "Use separate kernel stacks when processing interrupts"
default y
help
If you say Y here the kernel will use separate kernel stacks
for handling hard and soft interrupts. This can help avoid
overflowing the process kernel stacks.
config HOTPLUG_CPU
bool
default y if SMP
config ARCH_SELECT_MEMORY_MODEL
def_bool y
depends on 64BIT
config ARCH_SPARSEMEM_ENABLE
def_bool y
depends on 64BIT
config ARCH_FLATMEM_ENABLE
def_bool y
config ARCH_SPARSEMEM_DEFAULT
def_bool y
depends on ARCH_SPARSEMEM_ENABLE
source "kernel/Kconfig.hz"
config COMPAT
bool "Kernel support for 32-bit binaries"
default 64BIT
depends on 64BIT
config AUDIT_ARCH
def_bool y
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
depends on SMP
default "8" if 64BIT
default "16"
endmenu
config ARCH_SUPPORTS_KEXEC
def_bool y
config ARCH_SUPPORTS_KEXEC_FILE
def_bool y
config ARCH_SELECTS_KEXEC_FILE
def_bool y
depends on KEXEC_FILE
select KEXEC_ELF
source "drivers/parisc/Kconfig"
linux-7.2.3/arch/parisc/Kconfig.debug
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# SPDX-License-Identifier: GPL-2.0
#
config LIGHTWEIGHT_SPINLOCK_CHECK
bool "Enable lightweight spinlock checks"
depends on DEBUG_KERNEL && SMP && !DEBUG_SPINLOCK
default y
help
Add checks with low performance impact to the spinlock functions
to catch memory overwrites at runtime. For more advanced
spinlock debugging you should choose the DEBUG_SPINLOCK option
which will detect unitialized spinlocks too.
If unsure say Y here.
config TLB_PTLOCK
bool "Use page table locks in TLB fault handler"
depends on DEBUG_KERNEL && SMP
default n
help
Select this option to enable page table locking in the TLB
fault handler. This ensures that page table entries are
updated consistently on SMP machines at the expense of some
loss in performance.
linux-7.2.3/arch/parisc/Makefile
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#
# parisc/Makefile
#
# This file is included by the global makefile so that you can add your own
# architecture-specific flags and dependencies.
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 1994 by Linus Torvalds
# Portions Copyright (C) 1999 The Puffin Group
#
# Modified for PA-RISC Linux by Paul Lahaie, Alex deVries,
# Mike Shaver, Helge Deller and Martin K. Petersen
#
boot := arch/parisc/boot
KBUILD_IMAGE := $(boot)/bzImage
CHECKFLAGS += -D__hppa__=1
ifdef CONFIG_64BIT
UTS_MACHINE := parisc64
CHECKFLAGS += -D__LP64__=1
LD_BFD := elf64-hppa-linux
else # 32-bit
LD_BFD := elf32-hppa-linux
endif
# select defconfig based on actual architecture
ifeq ($(ARCH),parisc64)
KBUILD_DEFCONFIG := generic-64bit_defconfig
CC_ARCHES := hppa64
else
KBUILD_DEFCONFIG := generic-32bit_defconfig
CC_ARCHES := hppa hppa2.0 hppa1.1
endif
export LD_BFD
# Set default 32 bits cross compilers for vdso.
# This means that for 64BIT, both the 64-bit tools and the 32-bit tools
# need to be in the path.
CC_ARCHES_32 = hppa hppa2.0 hppa1.1
CC_SUFFIXES = linux linux-gnu unknown-linux-gnu suse-linux
CROSS32_COMPILE := $(call cc-cross-prefix, \
$(foreach a,$(CC_ARCHES_32), \
$(foreach s,$(CC_SUFFIXES),$(a)-$(s)-)))
CROSS32CC := $(CROSS32_COMPILE)gcc
export CROSS32CC
# Set default cross compiler for kernel build
ifdef cross_compiling
ifeq ($(CROSS_COMPILE),)
CC_SUFFIXES = linux linux-gnu unknown-linux-gnu suse-linux
CROSS_COMPILE := $(call cc-cross-prefix, \
$(foreach a,$(CC_ARCHES), \
$(foreach s,$(CC_SUFFIXES),$(a)-$(s)-)))
endif
endif
ifdef CONFIG_DYNAMIC_FTRACE
ifdef CONFIG_64BIT
NOP_COUNT := 8
else
NOP_COUNT := 5
endif
export CC_USING_RECORD_MCOUNT:=1
export CC_USING_PATCHABLE_FUNCTION_ENTRY:=1
KBUILD_AFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY=1
KBUILD_CFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY=1 \
-DFTRACE_PATCHABLE_FUNCTION_SIZE=$(NOP_COUNT)
CC_FLAGS_FTRACE := -fpatchable-function-entry=$(NOP_COUNT),$(shell echo $$(($(NOP_COUNT)-1)))
endif
OBJCOPY_FLAGS =-O binary -R .note -R .comment -S
cflags-y := -pipe
# These flags should be implied by an hppa-linux configuration, but they
# are not in gcc 3.2.
cflags-y += -mno-space-regs
# -mfast-indirect-calls is only relevant for 32-bit kernels.
ifndef CONFIG_64BIT
cflags-y += -mfast-indirect-calls
endif
# Currently we save and restore fpregs on all kernel entry/interruption paths.
# If that gets optimized, we might need to disable the use of fpregs in the
# kernel.
cflags-y += -mdisable-fpregs
# Use long jumps instead of long branches (needed if your linker fails to
# link a too big vmlinux executable). Not enabled for building modules.
ifdef CONFIG_MLONGCALLS
KBUILD_CFLAGS_KERNEL += -mlong-calls
endif
# Without this, "ld -r" results in .text sections that are too big (> 0x40000)
# for branches to reach stubs. And multiple .text sections trigger a warning
# when creating the sysfs module information section.
ifndef CONFIG_64BIT
KBUILD_CFLAGS_MODULE += -ffunction-sections
endif
# select which processor to optimise for
cflags-$(CONFIG_PA7000) += -march=1.1 -mschedule=7100
cflags-$(CONFIG_PA7200) += -march=1.1 -mschedule=7200
cflags-$(CONFIG_PA7100LC) += -march=1.1 -mschedule=7100LC
cflags-$(CONFIG_PA7300LC) += -march=1.1 -mschedule=7300
cflags-$(CONFIG_PA8X00) += -march=2.0 -mschedule=8000
KBUILD_CFLAGS += $(cflags-y)
LIBGCC := $(shell $(CC) -print-libgcc-file-name)
export LIBGCC
libs-y += arch/parisc/lib/ $(LIBGCC)
drivers-$(CONFIG_VIDEO) += arch/parisc/video/
boot := arch/parisc/boot
PALO := $(shell if (which palo 2>&1); then : ; \
elif [ -x /sbin/palo ]; then echo /sbin/palo; \
fi)
PALOCONF := $(shell if [ -f $(srctree)/palo.conf ]; then echo $(srctree)/palo.conf; \
else echo $(objtree)/palo.conf; \
fi)
palo lifimage: vmlinuz
@if test ! -x "$(PALO)"; then \
echo 'ERROR: Please install palo first (apt-get install palo)';\
echo 'or build it from source and install it somewhere in your $$PATH';\
false; \
fi
@if test ! -f "$(PALOCONF)"; then \
cp $(srctree)/arch/parisc/defpalo.conf $(objtree)/palo.conf; \
echo 'A generic palo config file ($(objtree)/palo.conf) has been created for you.'; \
echo 'You should check it and re-run "make palo".'; \
echo 'WARNING: the "lifimage" file is now placed in this directory by default!'; \
false; \
fi
$(PALO) -f $(PALOCONF)
BOOT_TARGETS = zImage Image palo lifimage
INSTALL_TARGETS = zinstall install
PHONY += bzImage $(BOOT_TARGETS) $(INSTALL_TARGETS)
# Default kernel to build
all: bzImage
zImage: vmlinuz
Image: vmlinux
bzImage: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
vmlinuz: bzImage
$(OBJCOPY) $(boot)/bzImage $@
ifeq ($(KBUILD_EXTMOD),)
# We need to generate vdso-offsets.h before compiling certain files in kernel/.
# In order to do that, we should use the archprepare target, but we can't since
# asm-offsets.h is included in some files used to generate vdso-offsets.h, and
# asm-offsets.h is built in prepare0, for which archprepare is a dependency.
# Therefore we need to generate the header after prepare0 has been made, hence
# this hack.
prepare: vdso_prepare
vdso_prepare: prepare0
ifdef CONFIG_64BIT
$(Q)$(MAKE) $(build)=arch/parisc/kernel/vdso64 include/generated/vdso64-offsets.h
$(if $(CONFIG_COMPAT),$(Q)$(MAKE) \
$(build)=arch/parisc/kernel/vdso32 include/generated/vdso32-offsets.h)
else
$(Q)$(MAKE) $(build)=arch/parisc/kernel/vdso32 include/generated/vdso32-offsets.h
endif
endif
ifdef CONFIG_64BIT
vdso-install-y += arch/parisc/kernel/vdso64/vdso64.so
vdso-install-$(CONFIG_COMPAT) += arch/parisc/kernel/vdso32/vdso32.so
else
vdso-install-y += arch/parisc/kernel/vdso32/vdso32.so
endif
install: KBUILD_IMAGE := vmlinux
zinstall: KBUILD_IMAGE := vmlinuz
install zinstall:
$(call cmd,install)
CLEAN_FILES += lifimage
MRPROPER_FILES += palo.conf
define archhelp
@echo '* vmlinux - Uncompressed kernel image (./vmlinux)'
@echo ' vmlinuz - Compressed kernel image (./vmlinuz)'
@echo ' palo - Bootable image (./lifimage)'
@echo ' install - Install uncompressed vmlinux kernel using'
@echo ' (your) ~/bin/$(INSTALLKERNEL) or'
@echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
@echo ' copy to $$(INSTALL_PATH)'
@echo ' zinstall - Install compressed vmlinuz kernel'
endef
archheaders:
$(Q)$(MAKE) $(build)=arch/parisc/kernel/syscalls all
linux-7.2.3/arch/parisc/boot/.gitignore
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# SPDX-License-Identifier: GPL-2.0-only
image
bzImage
linux-7.2.3/arch/parisc/boot/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for the linux parisc-specific parts of the boot image creator.
#
targets := image
targets += bzImage
subdir- := compressed
$(obj)/image: vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/bzImage: $(if $(CONFIG_KERNEL_UNCOMPRESSED),$(objtree)/vmlinux,$(obj)/compressed/vmlinux) FORCE
$(call if_changed,objcopy)
$(obj)/compressed/vmlinux: FORCE
$(Q)$(MAKE) $(build)=$(obj)/compressed $@
linux-7.2.3/arch/parisc/boot/compressed/.gitignore
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# SPDX-License-Identifier: GPL-2.0-only
sizes.h
vmlinux
vmlinux.lds
linux-7.2.3/arch/parisc/boot/compressed/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
#
# linux/arch/parisc/boot/compressed/Makefile
#
# create a compressed self-extracting vmlinux image from the original vmlinux
#
OBJECTS := head.o real2.o firmware.o misc.o piggy.o
targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2
targets += vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.lz4
targets += $(OBJECTS) sizes.h
KBUILD_CFLAGS := -D__KERNEL__ -O2 -DBOOTLOADER
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
KBUILD_CFLAGS += -fno-strict-aliasing
KBUILD_CFLAGS += $(cflags-y) -fno-delete-null-pointer-checks -fno-builtin-printf
KBUILD_CFLAGS += -fno-PIE -mno-space-regs -mdisable-fpregs -Os
ifndef CONFIG_64BIT
KBUILD_CFLAGS += -mfast-indirect-calls
endif
KBUILD_CFLAGS += $(CC_FLAGS_DIALECT)
LDFLAGS_vmlinux := -X -e startup --as-needed -T
$(obj)/vmlinux: $(obj)/vmlinux.lds $(addprefix $(obj)/, $(OBJECTS)) $(LIBGCC) FORCE
$(call if_changed,ld)
sed-sizes := -e 's/^\([0-9a-fA-F]*\) . \(__bss_start\|_end\|parisc_kernel_start\)$$/\#define SZ\2 0x\1/p'
quiet_cmd_sizes = GEN $@
cmd_sizes = $(NM) $< | sed -n $(sed-sizes) > $@
$(obj)/sizes.h: vmlinux FORCE
$(call if_changed,sizes)
AFLAGS_head.o += -I$(objtree)/$(obj) -DBOOTLOADER
$(obj)/head.o: $(obj)/sizes.h
CFLAGS_misc.o += -I$(objtree)/$(obj)
$(obj)/misc.o: $(obj)/sizes.h
AFLAGS_real2.o += -DBOOTLOADER
CPPFLAGS_vmlinux.lds += -I$(objtree)/$(obj) -DBOOTLOADER
$(obj)/vmlinux.lds: $(obj)/sizes.h
OBJCOPYFLAGS_vmlinux.bin := -R .comment -R .note -S
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
suffix-$(CONFIG_KERNEL_GZIP) := gz
suffix-$(CONFIG_KERNEL_BZIP2) := bz2
suffix-$(CONFIG_KERNEL_LZ4) := lz4
suffix-$(CONFIG_KERNEL_LZMA) := lzma
suffix-$(CONFIG_KERNEL_LZO) := lzo
suffix-$(CONFIG_KERNEL_XZ) := xz
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
$(call if_changed,gzip)
$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
$(call if_changed,bzip2_with_size)
$(obj)/vmlinux.bin.lz4: $(obj)/vmlinux.bin FORCE
$(call if_changed,lz4_with_size)
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzma_with_size)
$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzo_with_size)
$(obj)/vmlinux.bin.xz: $(obj)/vmlinux.bin FORCE
$(call if_changed,xzkern_with_size)
LDFLAGS_piggy.o := -r --format binary --oformat $(LD_BFD) -T
$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE
$(call if_changed,ld)
linux-7.2.3/arch/parisc/boot/compressed/firmware.c
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// SPDX-License-Identifier: GPL-2.0-only
#include "../../kernel/firmware.c"
linux-7.2.3/arch/parisc/boot/compressed/head.S
+85
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@@ -0,0 +1,85 @@
/*
* Startup glue code to uncompress the kernel
*
* (C) 2017 Helge Deller <deller@gmx.de>
*/
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
#include <asm/psw.h>
#include <asm/pdc.h>
#include <asm/assembly.h>
#include "sizes.h"
#define BOOTADDR(x) (x)
#ifndef CONFIG_64BIT
.import $global$ /* forward declaration */
#endif /*!CONFIG_64BIT*/
__HEAD
ENTRY(startup)
.level PA_ASM_LEVEL
#define PSW_W_SM 0x200
#define PSW_W_BIT 36
;! nuke the W bit, saving original value
.level 2.0
rsm PSW_W_SM, %r1
.level 1.1
extrw,u %r1, PSW_W_BIT-32, 1, %r1
copy %r1, %arg0
/* Make sure sr4-sr7 are set to zero for the kernel address space */
mtsp %r0,%sr4
mtsp %r0,%sr5
mtsp %r0,%sr6
mtsp %r0,%sr7
/* Clear BSS */
.import _bss,data
.import _ebss,data
load32 BOOTADDR(_bss),%r3
load32 BOOTADDR(_ebss),%r4
ldo FRAME_SIZE(%r4),%sp /* stack at end of bss */
$bss_loop:
cmpb,<<,n %r3,%r4,$bss_loop
stw,ma %r0,4(%r3)
/* Initialize the global data pointer */
loadgp
/* arg0..arg4 were set by palo. */
copy %arg1, %r6 /* command line */
copy %arg2, %r7 /* rd-start */
copy %arg3, %r8 /* rd-end */
load32 BOOTADDR(decompress_kernel),%r3
#ifdef CONFIG_64BIT
.level PA_ASM_LEVEL
ssm PSW_W_SM, %r0 /* set W-bit */
depdi 0, 31, 32, %r3
#endif
load32 BOOTADDR(startup_continue), %r2
bv,n 0(%r3)
startup_continue:
#ifdef CONFIG_64BIT
.level PA_ASM_LEVEL
rsm PSW_W_SM, %r0 /* clear W-bit */
#endif
load32 KERNEL_BINARY_TEXT_START, %arg0 /* free mem */
copy %r6, %arg1 /* command line */
copy %r7, %arg2 /* rd-start */
copy %r8, %arg3 /* rd-end */
bv,n 0(%ret0)
END(startup)
linux-7.2.3/arch/parisc/boot/compressed/misc.c
+383
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@@ -0,0 +1,383 @@
/*
* Definitions and wrapper functions for kernel decompressor
*
* (C) 2017 Helge Deller <deller@gmx.de>
*/
#include <linux/uaccess.h>
#include <linux/elf.h>
#include <linux/unaligned.h>
#include <asm/page.h>
#include "sizes.h"
/*
* gzip declarations
*/
#define STATIC static
#undef memmove
#define memmove memmove
#define memzero(s, n) memset((s), 0, (n))
#define malloc malloc_gzip
#define free free_gzip
/* Symbols defined by linker scripts */
extern char input_data[];
extern int input_len;
/* output_len is inserted by the linker possibly at an unaligned address */
extern char output_len;
extern char _text, _end;
extern char _bss, _ebss;
extern char _startcode_end;
extern void startup_continue(void *entry, unsigned long cmdline,
unsigned long rd_start, unsigned long rd_end) __noreturn;
void error(char *m) __noreturn;
static unsigned long free_mem_ptr;
static unsigned long free_mem_end_ptr;
#ifdef CONFIG_KERNEL_GZIP
#include "../../../../lib/decompress_inflate.c"
#endif
#ifdef CONFIG_KERNEL_BZIP2
#include "../../../../lib/decompress_bunzip2.c"
#endif
#ifdef CONFIG_KERNEL_LZ4
#include "../../../../lib/decompress_unlz4.c"
#endif
#ifdef CONFIG_KERNEL_LZMA
#include "../../../../lib/decompress_unlzma.c"
#endif
#ifdef CONFIG_KERNEL_LZO
#include "../../../../lib/decompress_unlzo.c"
#endif
#ifdef CONFIG_KERNEL_XZ
#include "../../../../lib/decompress_unxz.c"
#endif
void *memmove(void *dest, const void *src, size_t n)
{
const char *s = src;
char *d = dest;
if (d <= s) {
while (n--)
*d++ = *s++;
} else {
d += n;
s += n;
while (n--)
*--d = *--s;
}
return dest;
}
void *memset(void *s, int c, size_t count)
{
char *xs = (char *)s;
while (count--)
*xs++ = c;
return s;
}
void *memcpy(void *d, const void *s, size_t len)
{
char *dest = (char *)d;
const char *source = (const char *)s;
while (len--)
*dest++ = *source++;
return d;
}
size_t strlen(const char *s)
{
const char *sc;
for (sc = s; *sc != '\0'; ++sc)
;
return sc - s;
}
char *strchr(const char *s, int c)
{
while (*s) {
if (*s == (char)c)
return (char *)s;
++s;
}
return NULL;
}
static int puts(const char *s)
{
const char *nuline = s;
while ((nuline = strchr(s, '\n')) != NULL) {
if (nuline != s)
pdc_iodc_print(s, nuline - s);
pdc_iodc_print("\r\n", 2);
s = nuline + 1;
}
if (*s != '\0')
pdc_iodc_print(s, strlen(s));
return 0;
}
static int putchar(int c)
{
char buf[2];
buf[0] = c;
buf[1] = '\0';
puts(buf);
return c;
}
void __noreturn error(char *x)
{
if (x) puts(x);
puts("\n -- System halted\n");
while (1) /* wait forever */
;
}
static int print_num(unsigned long num, int base)
{
const char hex[] = "0123456789abcdef";
char str[40];
int i = sizeof(str)-1;
str[i--] = '\0';
do {
str[i--] = hex[num % base];
num = num / base;
} while (num);
if (base == 16) {
str[i--] = 'x';
str[i] = '0';
} else i++;
puts(&str[i]);
return 0;
}
static int printf(const char *fmt, ...)
{
va_list args;
int i = 0;
va_start(args, fmt);
while (fmt[i]) {
if (fmt[i] != '%') {
put:
putchar(fmt[i++]);
continue;
}
if (fmt[++i] == '%')
goto put;
print_num(va_arg(args, unsigned long),
fmt[i] == 'x' ? 16:10);
++i;
}
va_end(args);
return 0;
}
/* helper functions for libgcc */
void abort(void)
{
error("aborted.");
}
#undef malloc
static void *malloc(size_t size)
{
return malloc_gzip(size);
}
#undef free
static void free(void *ptr)
{
return free_gzip(ptr);
}
static void flush_data_cache(char *start, unsigned long length)
{
char *end = start + length;
do {
asm volatile("fdc 0(%0)" : : "r" (start));
asm volatile("fic 0(%%sr0,%0)" : : "r" (start));
start += 16;
} while (start < end);
asm volatile("fdc 0(%0)" : : "r" (end));
asm ("sync");
}
static void parse_elf(void *output)
{
#ifdef CONFIG_64BIT
Elf64_Ehdr ehdr;
Elf64_Phdr *phdrs, *phdr;
#else
Elf32_Ehdr ehdr;
Elf32_Phdr *phdrs, *phdr;
#endif
void *dest;
int i;
memcpy(&ehdr, output, sizeof(ehdr));
if (ehdr.e_ident[EI_MAG0] != ELFMAG0 ||
ehdr.e_ident[EI_MAG1] != ELFMAG1 ||
ehdr.e_ident[EI_MAG2] != ELFMAG2 ||
ehdr.e_ident[EI_MAG3] != ELFMAG3) {
error("Kernel is not a valid ELF file");
return;
}
#ifdef DEBUG
printf("Parsing ELF... ");
#endif
phdrs = malloc(sizeof(*phdrs) * ehdr.e_phnum);
if (!phdrs)
error("Failed to allocate space for phdrs");
memcpy(phdrs, output + ehdr.e_phoff, sizeof(*phdrs) * ehdr.e_phnum);
for (i = 0; i < ehdr.e_phnum; i++) {
phdr = &phdrs[i];
switch (phdr->p_type) {
case PT_LOAD:
dest = (void *)((unsigned long) phdr->p_paddr &
(__PAGE_OFFSET_DEFAULT-1));
memmove(dest, output + phdr->p_offset, phdr->p_filesz);
break;
default:
break;
}
}
free(phdrs);
}
/*
* The regular get_unaligned_le32 uses __builtin_memcpy which can trigger
* warnings when reading a byte/char output_len as an integer, as the size of a
* char is less than that of an integer. Use type punning and the packed
* attribute, which requires -fno-strict-aliasing, to work around the problem.
*/
static u32 punned_get_unaligned_le32(const void *p)
{
const struct { __le32 x; } __packed * __get_pptr = p;
return le32_to_cpu(__get_pptr->x);
}
asmlinkage unsigned long __visible decompress_kernel(unsigned int started_wide,
unsigned int command_line,
const unsigned int rd_start,
const unsigned int rd_end)
{
char *output;
unsigned long vmlinux_addr, vmlinux_len;
unsigned long kernel_addr, kernel_len;
#ifdef CONFIG_64BIT
parisc_narrow_firmware = 0;
#endif
set_firmware_width_unlocked();
putchar('D'); /* if you get this D and no more, string storage */
/* in $GLOBAL$ is wrong or %dp is wrong */
puts("ecompressing Linux... ");
/* where the final bits are stored */
kernel_addr = KERNEL_BINARY_TEXT_START;
kernel_len = __pa(SZ_end) - __pa(SZparisc_kernel_start);
if ((unsigned long) &_startcode_end > kernel_addr)
error("Bootcode overlaps kernel code");
/*
* Calculate addr to where the vmlinux ELF file shall be decompressed.
* Assembly code in head.S positioned the stack directly behind bss, so
* leave 2 MB for the stack.
*/
vmlinux_addr = (unsigned long) &_ebss + 2*1024*1024;
vmlinux_len = punned_get_unaligned_le32(&output_len);
output = (char *) vmlinux_addr;
/*
* Initialize free_mem_ptr and free_mem_end_ptr.
*/
free_mem_ptr = vmlinux_addr + vmlinux_len;
/* Limit memory for bootoader to 1GB */
#define ARTIFICIAL_LIMIT (1*1024*1024*1024)
free_mem_end_ptr = PAGE0->imm_max_mem;
if (free_mem_end_ptr > ARTIFICIAL_LIMIT)
free_mem_end_ptr = ARTIFICIAL_LIMIT;
#ifdef CONFIG_BLK_DEV_INITRD
/* if we have ramdisk this is at end of memory */
if (rd_start && rd_start < free_mem_end_ptr)
free_mem_end_ptr = rd_start;
#endif
if (free_mem_ptr >= free_mem_end_ptr) {
int free_ram;
free_ram = (free_mem_ptr >> 20) + 1;
if (free_ram < 32)
free_ram = 32;
printf("\nKernel requires at least %d MB RAM.\n",
free_ram);
error(NULL);
}
#ifdef DEBUG
printf("\n");
printf("startcode_end = %x\n", &_startcode_end);
printf("commandline = %x\n", command_line);
printf("rd_start = %x\n", rd_start);
printf("rd_end = %x\n", rd_end);
printf("free_ptr = %x\n", free_mem_ptr);
printf("free_ptr_end = %x\n", free_mem_end_ptr);
printf("input_data = %x\n", input_data);
printf("input_len = %x\n", input_len);
printf("output = %x\n", output);
printf("output_len = %x\n", vmlinux_len);
printf("kernel_addr = %x\n", kernel_addr);
printf("kernel_len = %x\n", kernel_len);
#endif
__decompress(input_data, input_len, NULL, NULL,
output, 0, NULL, error);
parse_elf(output);
output = (char *) kernel_addr;
flush_data_cache(output, kernel_len);
printf("done.\nBooting the kernel.\n");
return (unsigned long) output;
}
linux-7.2.3/arch/parisc/boot/compressed/real2.S
+2
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@@ -0,0 +1,2 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "../../kernel/real2.S"
linux-7.2.3/arch/parisc/boot/compressed/vmlinux.lds.S
+107
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@@ -0,0 +1,107 @@
#include <asm-generic/vmlinux.lds.h>
#include <asm/page.h>
#include "sizes.h"
#ifndef CONFIG_64BIT
OUTPUT_FORMAT("elf32-hppa-linux")
OUTPUT_ARCH(hppa)
#else
OUTPUT_FORMAT("elf64-hppa-linux")
OUTPUT_ARCH(hppa:hppa2.0w)
#endif
ENTRY(startup)
SECTIONS
{
/* palo loads at 0x60000 */
/* loaded kernel will move to 0x10000 */
. = 0xe0000; /* should not overwrite palo code */
.head.text : {
_head = . ;
HEAD_TEXT
_ehead = . ;
}
/* keep __gp below 0x1000000 */
#ifdef CONFIG_64BIT
. = ALIGN(16);
/* Linkage tables */
.opd : {
__start_opd = .;
*(.opd)
__end_opd = .;
} PROVIDE (__gp = .);
.plt : {
*(.plt)
}
.dlt : {
*(.dlt)
}
#endif
_startcode_end = .;
/* vmlinux.bin.gz is here */
. = ALIGN(8);
.rodata.compressed : {
*(.rodata.compressed)
}
/* bootloader code and data starts at least behind area of extracted kernel */
. = MAX(ABSOLUTE(.), (SZ_end - SZparisc_kernel_start + KERNEL_BINARY_TEXT_START));
/* align on next page boundary */
. = ALIGN(4096);
.text : {
_text = .; /* Text */
*(.text)
*(.text.*)
_etext = . ;
}
. = ALIGN(8);
.data : {
_data = . ;
*(.data)
*(.data.*)
_edata = . ;
}
. = ALIGN(8);
.rodata : {
_rodata = . ;
*(.rodata) /* read-only data */
*(.rodata.*)
_erodata = . ;
}
. = ALIGN(8);
.bss : {
_bss = . ;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4096);
_ebss = .;
}
STABS_DEBUG
ELF_DETAILS
.note 0 : { *(.note) }
/* Sections to be discarded */
DISCARDS
/DISCARD/ : {
*(.modinfo)
#ifdef CONFIG_64BIT
/* temporary hack until binutils is fixed to not emit these
* for static binaries
*/
*(.PARISC.unwind) /* no unwind data */
*(.interp)
*(.dynsym)
*(.dynstr)
*(.dynamic)
*(.hash)
*(.gnu.hash)
#endif
}
}
linux-7.2.3/arch/parisc/boot/compressed/vmlinux.scr
+10
View File
@@ -0,0 +1,10 @@
SECTIONS
{
.rodata.compressed : {
input_len = .;
LONG(input_data_end - input_data) input_data = .;
*(.data)
output_len = . - 4; /* can be at unaligned address */
input_data_end = .;
}
}
linux-7.2.3/arch/parisc/configs/generic-32bit_defconfig
+276
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@@ -0,0 +1,276 @@
CONFIG_LOCALVERSION="-32bit"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
CONFIG_PA7100LC=y
CONFIG_SMP=y
CONFIG_HZ_100=y
CONFIG_IOMMU_CCIO=y
CONFIG_GSC_LASI=y
CONFIG_GSC_WAX=y
CONFIG_GSC_DINO=y
CONFIG_PCI_LBA=y
# CONFIG_PDC_CHASSIS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_MISC=m
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_DIAG=m
CONFIG_LLC2=m
# CONFIG_WIRELESS is not set
CONFIG_EISA=y
CONFIG_PCI=y
CONFIG_PCCARD=m
CONFIG_YENTA=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=m
CONFIG_PARPORT_1284=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=6144
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_SCSI_LASI700=y
CONFIG_SCSI_SYM53C8XX_2=y
CONFIG_SCSI_ZALON=y
CONFIG_SCSI_DH=y
CONFIG_ATA=y
CONFIG_PATA_NS87415=y
CONFIG_ATA_GENERIC=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_BLK_DEV_DM=y
CONFIG_DM_UEVENT=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_TUN=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
CONFIG_NET_TULIP=y
CONFIG_TULIP=y
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_LASI_82596=y
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPPOE=m
# CONFIG_WLAN is not set
CONFIG_KEYBOARD_HIL_OLD=m
CONFIG_KEYBOARD_HIL=m
CONFIG_MOUSE_SERIAL=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=m
CONFIG_LEGACY_PTY_COUNT=64
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=8
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_PRINTER=m
CONFIG_PPDEV=m
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_HWMON=m
CONFIG_DRM=m
CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
CONFIG_DRM_RADEON=m
CONFIG_DRM_NOUVEAU=m
# CONFIG_DRM_NOUVEAU_BACKLIGHT is not set
# CONFIG_DRM_NOUVEAU_CH7006 is not set
# CONFIG_DRM_NOUVEAU_SIL164 is not set
CONFIG_DRM_VGEM=m
CONFIG_DRM_UDL=m
CONFIG_DRM_MGAG200=m
CONFIG_FB=y
CONFIG_FB_FOREIGN_ENDIAN=y
CONFIG_FB_PM2=m
CONFIG_FB_PM2_FIFO_DISCONNECT=y
CONFIG_FB_NVIDIA=m
CONFIG_FB_NVIDIA_I2C=y
# CONFIG_FB_NVIDIA_BACKLIGHT is not set
CONFIG_FB_RIVA=m
CONFIG_FB_RIVA_I2C=y
# CONFIG_FB_RIVA_BACKLIGHT is not set
CONFIG_FB_MATROX=m
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
CONFIG_FB_MATROX_G=y
CONFIG_FB_MATROX_I2C=m
CONFIG_FB_MATROX_MAVEN=m
CONFIG_FB_ATY128=m
# CONFIG_FB_ATY128_BACKLIGHT is not set
CONFIG_FB_ATY=m
CONFIG_FB_ATY_CT=y
CONFIG_FB_ATY_GX=y
# CONFIG_FB_ATY_BACKLIGHT is not set
CONFIG_FB_S3=m
CONFIG_FB_SAVAGE=m
CONFIG_FB_SAVAGE_I2C=y
CONFIG_FB_SAVAGE_ACCEL=y
CONFIG_FB_SIS=m
CONFIG_FB_SIS_300=y
CONFIG_FB_SIS_315=y
CONFIG_FB_VOODOO1=m
CONFIG_FB_TRIDENT=m
CONFIG_FB_SMSCUFX=m
CONFIG_FB_UDL=m
CONFIG_DUMMY_CONSOLE_COLUMNS=128
CONFIG_DUMMY_CONSOLE_ROWS=48
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_AD1889=m
CONFIG_SND_HARMONY=m
CONFIG_HIDRAW=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_HID_EZKEY=y
CONFIG_HID_KYE=y
CONFIG_HID_GYRATION=y
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_GREENASIA=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THRUSTMASTER=y
CONFIG_HID_ZEROPLUS=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_UHCI_HCD=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_DMADEVICES=y
CONFIG_AUXDISPLAY=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_QFMT_V2=y
CONFIG_AUTOFS_FS=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_XATTR=y
CONFIG_NFS_FS=m
# CONFIG_NFS_V2 is not set
CONFIG_NFSD=m
CONFIG_CIFS=m
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
# CONFIG_CIFS_DEBUG is not set
CONFIG_CRYPTO_BENCHMARK=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_DEFLATE=y
CONFIG_FONTS=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_LATENCYTOP=y
CONFIG_LKDTM=m
linux-7.2.3/arch/parisc/configs/generic-64bit_defconfig
+295
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@@ -0,0 +1,295 @@
CONFIG_LOCALVERSION="-64bit"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZ4=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_CGROUP_PIDS=y
CONFIG_CPUSETS=y
CONFIG_USER_NS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SMP=y
CONFIG_HPPB=y
CONFIG_IOMMU_CCIO=y
CONFIG_GSC_LASI=y
CONFIG_GSC_WAX=y
CONFIG_GSC_DINO=y
CONFIG_PCI_LBA=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BINFMT_MISC=m
# CONFIG_COMPAT_BRK is not set
# CONFIG_COMPACTION is not set
CONFIG_MEMORY_FAILURE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_DIAG=m
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_DCB=y
# CONFIG_WIRELESS is not set
CONFIG_PCI=y
CONFIG_PCI_STUB=m
CONFIG_PCI_IOV=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_SCSI_SRP_ATTRS=y
CONFIG_ISCSI_BOOT_SYSFS=y
CONFIG_SCSI_MPT2SAS=y
CONFIG_SCSI_LASI700=y
CONFIG_SCSI_SYM53C8XX_2=y
CONFIG_SCSI_ZALON=y
CONFIG_SCSI_QLA_ISCSI=m
CONFIG_SCSI_DH=y
CONFIG_ATA=y
CONFIG_SATA_SIL=y
CONFIG_SATA_SIS=y
CONFIG_SATA_VIA=y
CONFIG_PATA_NS87415=y
CONFIG_PATA_SIL680=y
CONFIG_ATA_GENERIC=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
CONFIG_DM_RAID=m
CONFIG_DM_UEVENT=y
CONFIG_DM_AUDIT=y
CONFIG_FUSION=y
CONFIG_FUSION_SPI=y
CONFIG_FUSION_SAS=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_TUN=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
CONFIG_NET_TULIP=y
CONFIG_TULIP=y
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_LASI_82596=y
CONFIG_E1000=y
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
CONFIG_QLA3XXX=m
CONFIG_QLCNIC=m
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y
CONFIG_BROADCOM_PHY=m
CONFIG_CICADA_PHY=m
CONFIG_DAVICOM_PHY=m
CONFIG_ICPLUS_PHY=m
CONFIG_LXT_PHY=m
CONFIG_LSI_ET1011C_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_NATIONAL_PHY=m
CONFIG_QSEMI_PHY=m
CONFIG_REALTEK_PHY=m
CONFIG_SMSC_PHY=m
CONFIG_STE10XP=m
CONFIG_VITESSE_PHY=m
CONFIG_MDIO_BITBANG=m
CONFIG_SLIP=m
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_HIL_OLD is not set
# CONFIG_KEYBOARD_HIL is not set
# CONFIG_MOUSE_PS2 is not set
CONFIG_INPUT_MISC=y
CONFIG_SERIO_SERPORT=m
# CONFIG_HP_SDC is not set
CONFIG_SERIO_RAW=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=8
CONFIG_SERIAL_8250_RUNTIME_UARTS=8
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_JSM=m
CONFIG_NOZOMI=m
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_DEVICE_INTERFACE=y
CONFIG_IPMI_SI=y
# CONFIG_HW_RANDOM is not set
CONFIG_TCG_TPM=m
CONFIG_TCG_ATMEL=m
CONFIG_PTP_1588_CLOCK=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_VT1211=m
CONFIG_SENSORS_VT8231=m
CONFIG_SENSORS_W83627EHF=m
CONFIG_WATCHDOG=y
CONFIG_SOFT_WATCHDOG=m
CONFIG_SSB=m
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_LPC_SCH=m
CONFIG_MFD_SM501=m
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_AGP=y
CONFIG_AGP_PARISC=y
CONFIG_DRM=y
CONFIG_DRM_RADEON=y
CONFIG_DRM_NOUVEAU=m
# CONFIG_DRM_NOUVEAU_BACKLIGHT is not set
# CONFIG_DRM_NOUVEAU_CH7006 is not set
# CONFIG_DRM_NOUVEAU_SIL164 is not set
CONFIG_DRM_MGAG200=m
CONFIG_FB=y
CONFIG_FB_PM2=m
CONFIG_FB_PM2_FIFO_DISCONNECT=y
CONFIG_FB_NVIDIA=m
CONFIG_FB_NVIDIA_I2C=y
# CONFIG_FB_NVIDIA_BACKLIGHT is not set
CONFIG_FB_RIVA=m
CONFIG_FB_RIVA_I2C=y
# CONFIG_FB_RIVA_BACKLIGHT is not set
CONFIG_FB_MATROX=m
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
CONFIG_FB_MATROX_G=y
CONFIG_FB_MATROX_I2C=m
CONFIG_FB_MATROX_MAVEN=m
CONFIG_FB_RADEON=y
# CONFIG_FB_RADEON_BACKLIGHT is not set
CONFIG_FB_ATY128=m
# CONFIG_FB_ATY128_BACKLIGHT is not set
CONFIG_FB_ATY=m
CONFIG_FB_ATY_CT=y
CONFIG_FB_ATY_GX=y
# CONFIG_FB_ATY_BACKLIGHT is not set
CONFIG_FB_S3=m
CONFIG_FB_SAVAGE=m
CONFIG_FB_SAVAGE_I2C=y
CONFIG_FB_SAVAGE_ACCEL=y
CONFIG_FB_SIS=m
CONFIG_FB_SIS_300=y
CONFIG_FB_SIS_315=y
CONFIG_FB_VOODOO1=m
CONFIG_FB_TRIDENT=m
CONFIG_FB_SMSCUFX=m
CONFIG_FB_UDL=m
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_HIDRAW=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
CONFIG_STAGING=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_XFS_FS=m
CONFIG_BTRFS_FS=m
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_QFMT_V2=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_ISO9660_FS=y
CONFIG_UDF_FS=y
CONFIG_VFAT_FS=m
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_XATTR=y
CONFIG_CONFIGFS_FS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V4=m
CONFIG_NFS_V4_1=y
CONFIG_NFSD=m
CONFIG_NFSD_V4=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_UTF8=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DEFLATE=m
# CONFIG_CRYPTO_HW is not set
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_KERNEL=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_STACKOVERFLOW=y
# CONFIG_SCHED_DEBUG is not set
linux-7.2.3/arch/parisc/defpalo.conf
+21
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@@ -0,0 +1,21 @@
# This a generic Palo configuration file. For more information about how
# it works try 'palo -?'.
#
# Most people using 'make palo' want a bootable file, usable for
# network or tape booting for example.
--init-tape=lifimage
--recoverykernel=vmlinuz
########## Pick your ROOT here! ##########
# You need at least one 'root='!
#
# If you want a root ramdisk, use the next 2 lines
# (Edit the ramdisk image name!!!!)
--ramdisk=ram-disk-image-file
--commandline=0/vmlinuz HOME=/ root=/dev/ram initrd=0/ramdisk panic_timeout=60 panic=-1
# If you want NFS root, use the following command line (Edit the HOSTNAME!!!)
#--commandline=0/vmlinuz HOME=/ root=/dev/nfs nfsroot=HOSTNAME ip=bootp
# If you have root on a disk partition, use this (Edit the partition name!!!)
#--commandline=0/vmlinuz HOME=/ root=/dev/sda1
linux-7.2.3/arch/parisc/include/asm/Kbuild
+8
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@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
generated-y += syscall_table_32.h
generated-y += syscall_table_64.h
generic-y += agp.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
generic-y += ring_buffer.h
generic-y += user.h
linux-7.2.3/arch/parisc/include/asm/alternative.h
+66
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@@ -0,0 +1,66 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_ALTERNATIVE_H
#define __ASM_PARISC_ALTERNATIVE_H
#define ALT_COND_ALWAYS 0x80 /* always replace instruction */
#define ALT_COND_NO_SMP 0x01 /* when running UP instead of SMP */
#define ALT_COND_NO_DCACHE 0x02 /* if system has no d-cache */
#define ALT_COND_NO_ICACHE 0x04 /* if system has no i-cache */
#define ALT_COND_NO_SPLIT_TLB 0x08 /* if split_tlb == 0 */
#define ALT_COND_NO_IOC_FDC 0x10 /* if I/O cache does not need flushes */
#define ALT_COND_RUN_ON_QEMU 0x20 /* if running on QEMU */
#define INSN_PxTLB 0x02 /* modify pdtlb, pitlb */
#define INSN_NOP 0x08000240 /* nop */
#ifndef __ASSEMBLER__
#include <linux/init.h>
#include <linux/types.h>
#include <linux/stddef.h>
#include <linux/stringify.h>
struct alt_instr {
s32 orig_offset; /* offset to original instructions */
s16 len; /* end of original instructions */
u16 cond; /* see ALT_COND_XXX */
u32 replacement; /* replacement instruction or code */
} __packed;
void set_kernel_text_rw(int enable_read_write);
void apply_alternatives_all(void);
void apply_alternatives(struct alt_instr *start, struct alt_instr *end,
const char *module_name);
/* Alternative SMP implementation. */
#define ALTERNATIVE(cond, replacement) "!0:" \
".section .altinstructions, \"a\" !" \
".align 4 !" \
".word (0b-4-.) !" \
".hword 1, " __stringify(cond) " !" \
".word " __stringify(replacement) " !" \
".previous"
#else
/* to replace one single instructions by a new instruction */
#define ALTERNATIVE(from, to, cond, replacement)\
.section .altinstructions, "a" ! \
.align 4 ! \
.word (from - .) ! \
.hword (to - from)/4, cond ! \
.word replacement ! \
.previous
/* to replace multiple instructions by new code */
#define ALTERNATIVE_CODE(from, num_instructions, cond, new_instr_ptr)\
.section .altinstructions, "a" ! \
.align 4 ! \
.word (from - .) ! \
.hword -num_instructions, cond ! \
.word (new_instr_ptr - .) ! \
.previous
#endif /* __ASSEMBLER__ */
#endif /* __ASM_PARISC_ALTERNATIVE_H */
linux-7.2.3/arch/parisc/include/asm/asm-offsets.h
+1
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@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
linux-7.2.3/arch/parisc/include/asm/asmregs.h
+170
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@@ -0,0 +1,170 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
*/
#ifndef _PARISC_ASMREGS_H
#define _PARISC_ASMREGS_H
;! General Registers
rp: .reg %r2
arg3: .reg %r23
arg2: .reg %r24
arg1: .reg %r25
arg0: .reg %r26
dp: .reg %r27
ret0: .reg %r28
ret1: .reg %r29
sl: .reg %r29
sp: .reg %r30
#if 0
/* PA20_REVISIT */
arg7: .reg r19
arg6: .reg r20
arg5: .reg r21
arg4: .reg r22
gp: .reg r27
ap: .reg r29
#endif
r0: .reg %r0
r1: .reg %r1
r2: .reg %r2
r3: .reg %r3
r4: .reg %r4
r5: .reg %r5
r6: .reg %r6
r7: .reg %r7
r8: .reg %r8
r9: .reg %r9
r10: .reg %r10
r11: .reg %r11
r12: .reg %r12
r13: .reg %r13
r14: .reg %r14
r15: .reg %r15
r16: .reg %r16
r17: .reg %r17
r18: .reg %r18
r19: .reg %r19
r20: .reg %r20
r21: .reg %r21
r22: .reg %r22
r23: .reg %r23
r24: .reg %r24
r25: .reg %r25
r26: .reg %r26
r27: .reg %r27
r28: .reg %r28
r29: .reg %r29
r30: .reg %r30
r31: .reg %r31
;! Space Registers
sr0: .reg %sr0
sr1: .reg %sr1
sr2: .reg %sr2
sr3: .reg %sr3
sr4: .reg %sr4
sr5: .reg %sr5
sr6: .reg %sr6
sr7: .reg %sr7
;! Floating Point Registers
fr0: .reg %fr0
fr1: .reg %fr1
fr2: .reg %fr2
fr3: .reg %fr3
fr4: .reg %fr4
fr5: .reg %fr5
fr6: .reg %fr6
fr7: .reg %fr7
fr8: .reg %fr8
fr9: .reg %fr9
fr10: .reg %fr10
fr11: .reg %fr11
fr12: .reg %fr12
fr13: .reg %fr13
fr14: .reg %fr14
fr15: .reg %fr15
fr16: .reg %fr16
fr17: .reg %fr17
fr18: .reg %fr18
fr19: .reg %fr19
fr20: .reg %fr20
fr21: .reg %fr21
fr22: .reg %fr22
fr23: .reg %fr23
fr24: .reg %fr24
fr25: .reg %fr25
fr26: .reg %fr26
fr27: .reg %fr27
fr28: .reg %fr28
fr29: .reg %fr29
fr30: .reg %fr30
fr31: .reg %fr31
;! Control Registers
rctr: .reg %cr0
pidr1: .reg %cr8
pidr2: .reg %cr9
ccr: .reg %cr10
sar: .reg %cr11
pidr3: .reg %cr12
pidr4: .reg %cr13
iva: .reg %cr14
eiem: .reg %cr15
itmr: .reg %cr16
pcsq: .reg %cr17
pcoq: .reg %cr18
iir: .reg %cr19
isr: .reg %cr20
ior: .reg %cr21
ipsw: .reg %cr22
eirr: .reg %cr23
tr0: .reg %cr24
tr1: .reg %cr25
tr2: .reg %cr26
tr3: .reg %cr27
tr4: .reg %cr28
tr5: .reg %cr29
tr6: .reg %cr30
tr7: .reg %cr31
cr0: .reg %cr0
cr8: .reg %cr8
cr9: .reg %cr9
cr10: .reg %cr10
cr11: .reg %cr11
cr12: .reg %cr12
cr13: .reg %cr13
cr14: .reg %cr14
cr15: .reg %cr15
cr16: .reg %cr16
cr17: .reg %cr17
cr18: .reg %cr18
cr19: .reg %cr19
cr20: .reg %cr20
cr21: .reg %cr21
cr22: .reg %cr22
cr23: .reg %cr23
cr24: .reg %cr24
cr25: .reg %cr25
cr26: .reg %cr26
cr27: .reg %cr27
cr28: .reg %cr28
cr29: .reg %cr29
cr30: .reg %cr30
cr31: .reg %cr31
#endif
linux-7.2.3/arch/parisc/include/asm/assembly.h
+586
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@@ -0,0 +1,586 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
* Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
* Copyright (C) 1999 SuSE GmbH
* Copyright (C) 2021 Helge Deller <deller@gmx.de>
*/
#ifndef _PARISC_ASSEMBLY_H
#define _PARISC_ASSEMBLY_H
#ifdef CONFIG_64BIT
#define RP_OFFSET 16
#define FRAME_SIZE 128
#define CALLEE_REG_FRAME_SIZE 144
#define REG_SZ 8
#define ASM_ULONG_INSN .dword
#else /* CONFIG_64BIT */
#define RP_OFFSET 20
#define FRAME_SIZE 64
#define CALLEE_REG_FRAME_SIZE 128
#define REG_SZ 4
#define ASM_ULONG_INSN .word
#endif
/* Frame alignment for 32- and 64-bit */
#define FRAME_ALIGN 64
#define CALLEE_FLOAT_FRAME_SIZE 80
#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
#ifdef CONFIG_PA20
#define LDCW ldcw,co
#define BL b,l
# ifdef CONFIG_64BIT
# define PA_ASM_LEVEL 2.0w
# else
# define PA_ASM_LEVEL 2.0
# endif
#else
#define LDCW ldcw
#define BL bl
#define PA_ASM_LEVEL 1.1
#endif
/* Privilege level field in the rightmost two bits of the IA queues */
#define PRIV_USER 3
#define PRIV_KERNEL 0
/* Space register used inside kernel */
#define SR_KERNEL 0
#define SR_TEMP1 1
#define SR_TEMP2 2
#define SR_USER 3
#ifdef __ASSEMBLER__
#ifdef CONFIG_64BIT
#define LDREG ldd
#define STREG std
#define LDREGX ldd,s
#define LDREGM ldd,mb
#define STREGM std,ma
#define SHRREG shrd
#define SHLREG shld
#define ANDCM andcm,*
#define COND(x) * ## x
#else /* CONFIG_64BIT */
#define LDREG ldw
#define STREG stw
#define LDREGX ldwx,s
#define LDREGM ldwm
#define STREGM stwm
#define SHRREG shr
#define SHLREG shlw
#define ANDCM andcm
#define COND(x) x
#endif
#ifdef CONFIG_64BIT
/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
* work around that for now... */
.level 2.0w
#endif
#include <asm/asm-offsets.h>
#include <asm/page.h>
#include <asm/types.h>
#include <asm/asmregs.h>
#include <asm/psw.h>
/*
* We provide two versions of each macro to convert from physical
* to virtual and vice versa. The "_r1" versions take one argument
* register, but trashes r1 to do the conversion. The other
* version takes two arguments: a src and destination register.
* However, the source and destination registers can not be
* the same register.
*
* We use add,l to avoid clobbering the C/B bits in the PSW.
*/
.macro tophys grvirt, grphys
ldil L%(-__PAGE_OFFSET), \grphys
addl \grvirt, \grphys, \grphys
.endm
.macro tovirt grphys, grvirt
ldil L%(__PAGE_OFFSET), \grvirt
addl \grphys, \grvirt, \grvirt
.endm
.macro tophys_r1 gr
ldil L%(-__PAGE_OFFSET), %r1
addl \gr, %r1, \gr
.endm
.macro tovirt_r1 gr
ldil L%(__PAGE_OFFSET), %r1
addl \gr, %r1, \gr
.endm
.macro delay value
ldil L%\value, 1
ldo R%\value(1), 1
addib,UV,n -1,1,.
addib,NUV,n -1,1,.+8
nop
.endm
.macro debug value
.endm
.macro shlw r, sa, t
zdep \r, 31-(\sa), 32-(\sa), \t
.endm
/* And the PA 2.0W shift left */
.macro shld r, sa, t
depd,z \r, 63-(\sa), 64-(\sa), \t
.endm
/* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
.macro shr r, sa, t
extru \r, 31-(\sa), 32-(\sa), \t
.endm
/* pa20w version of shift right */
.macro shrd r, sa, t
extrd,u \r, 63-(\sa), 64-(\sa), \t
.endm
/* Extract unsigned for 32- and 64-bit
* The extru instruction leaves the most significant 32 bits of the
* target register in an undefined state on PA 2.0 systems. */
.macro extru_safe r, p, len, t
#ifdef CONFIG_64BIT
extrd,u \r, 32+(\p), \len, \t
#else
extru \r, \p, \len, \t
#endif
.endm
/* The depi instruction leaves the most significant 32 bits of the
* target register in an undefined state on PA 2.0 systems. */
.macro depi_safe i, p, len, t
#ifdef CONFIG_64BIT
depdi \i, 32+(\p), \len, \t
#else
depi \i, \p, \len, \t
#endif
.endm
/* The depw instruction leaves the most significant 32 bits of the
* target register in an undefined state on PA 2.0 systems. */
.macro dep_safe i, p, len, t
#ifdef CONFIG_64BIT
depd \i, 32+(\p), \len, \t
#else
depw \i, \p, \len, \t
#endif
.endm
/* load 32-bit 'value' into 'reg' compensating for the ldil
* sign-extension when running in wide mode.
* WARNING!! neither 'value' nor 'reg' can be expressions
* containing '.'!!!! */
.macro load32 value, reg
ldil L%\value, \reg
ldo R%\value(\reg), \reg
.endm
.macro loadgp
#ifdef CONFIG_64BIT
ldil L%__gp, %r27
ldo R%__gp(%r27), %r27
#else
ldil L%$global$, %r27
ldo R%$global$(%r27), %r27
#endif
.endm
#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
.macro save_general regs
STREG %r1, PT_GR1 (\regs)
STREG %r2, PT_GR2 (\regs)
STREG %r3, PT_GR3 (\regs)
STREG %r4, PT_GR4 (\regs)
STREG %r5, PT_GR5 (\regs)
STREG %r6, PT_GR6 (\regs)
STREG %r7, PT_GR7 (\regs)
STREG %r8, PT_GR8 (\regs)
STREG %r9, PT_GR9 (\regs)
STREG %r10, PT_GR10(\regs)
STREG %r11, PT_GR11(\regs)
STREG %r12, PT_GR12(\regs)
STREG %r13, PT_GR13(\regs)
STREG %r14, PT_GR14(\regs)
STREG %r15, PT_GR15(\regs)
STREG %r16, PT_GR16(\regs)
STREG %r17, PT_GR17(\regs)
STREG %r18, PT_GR18(\regs)
STREG %r19, PT_GR19(\regs)
STREG %r20, PT_GR20(\regs)
STREG %r21, PT_GR21(\regs)
STREG %r22, PT_GR22(\regs)
STREG %r23, PT_GR23(\regs)
STREG %r24, PT_GR24(\regs)
STREG %r25, PT_GR25(\regs)
/* r26 is saved in get_stack and used to preserve a value across virt_map */
STREG %r27, PT_GR27(\regs)
STREG %r28, PT_GR28(\regs)
/* r29 is saved in get_stack and used to point to saved registers */
/* r30 stack pointer saved in get_stack */
STREG %r31, PT_GR31(\regs)
.endm
.macro rest_general regs
/* r1 used as a temp in rest_stack and is restored there */
LDREG PT_GR2 (\regs), %r2
LDREG PT_GR3 (\regs), %r3
LDREG PT_GR4 (\regs), %r4
LDREG PT_GR5 (\regs), %r5
LDREG PT_GR6 (\regs), %r6
LDREG PT_GR7 (\regs), %r7
LDREG PT_GR8 (\regs), %r8
LDREG PT_GR9 (\regs), %r9
LDREG PT_GR10(\regs), %r10
LDREG PT_GR11(\regs), %r11
LDREG PT_GR12(\regs), %r12
LDREG PT_GR13(\regs), %r13
LDREG PT_GR14(\regs), %r14
LDREG PT_GR15(\regs), %r15
LDREG PT_GR16(\regs), %r16
LDREG PT_GR17(\regs), %r17
LDREG PT_GR18(\regs), %r18
LDREG PT_GR19(\regs), %r19
LDREG PT_GR20(\regs), %r20
LDREG PT_GR21(\regs), %r21
LDREG PT_GR22(\regs), %r22
LDREG PT_GR23(\regs), %r23
LDREG PT_GR24(\regs), %r24
LDREG PT_GR25(\regs), %r25
LDREG PT_GR26(\regs), %r26
LDREG PT_GR27(\regs), %r27
LDREG PT_GR28(\regs), %r28
/* r29 points to register save area, and is restored in rest_stack */
/* r30 stack pointer restored in rest_stack */
LDREG PT_GR31(\regs), %r31
.endm
.macro save_fp regs
fstd,ma %fr0, 8(\regs)
fstd,ma %fr1, 8(\regs)
fstd,ma %fr2, 8(\regs)
fstd,ma %fr3, 8(\regs)
fstd,ma %fr4, 8(\regs)
fstd,ma %fr5, 8(\regs)
fstd,ma %fr6, 8(\regs)
fstd,ma %fr7, 8(\regs)
fstd,ma %fr8, 8(\regs)
fstd,ma %fr9, 8(\regs)
fstd,ma %fr10, 8(\regs)
fstd,ma %fr11, 8(\regs)
fstd,ma %fr12, 8(\regs)
fstd,ma %fr13, 8(\regs)
fstd,ma %fr14, 8(\regs)
fstd,ma %fr15, 8(\regs)
fstd,ma %fr16, 8(\regs)
fstd,ma %fr17, 8(\regs)
fstd,ma %fr18, 8(\regs)
fstd,ma %fr19, 8(\regs)
fstd,ma %fr20, 8(\regs)
fstd,ma %fr21, 8(\regs)
fstd,ma %fr22, 8(\regs)
fstd,ma %fr23, 8(\regs)
fstd,ma %fr24, 8(\regs)
fstd,ma %fr25, 8(\regs)
fstd,ma %fr26, 8(\regs)
fstd,ma %fr27, 8(\regs)
fstd,ma %fr28, 8(\regs)
fstd,ma %fr29, 8(\regs)
fstd,ma %fr30, 8(\regs)
fstd %fr31, 0(\regs)
.endm
.macro rest_fp regs
fldd 0(\regs), %fr31
fldd,mb -8(\regs), %fr30
fldd,mb -8(\regs), %fr29
fldd,mb -8(\regs), %fr28
fldd,mb -8(\regs), %fr27
fldd,mb -8(\regs), %fr26
fldd,mb -8(\regs), %fr25
fldd,mb -8(\regs), %fr24
fldd,mb -8(\regs), %fr23
fldd,mb -8(\regs), %fr22
fldd,mb -8(\regs), %fr21
fldd,mb -8(\regs), %fr20
fldd,mb -8(\regs), %fr19
fldd,mb -8(\regs), %fr18
fldd,mb -8(\regs), %fr17
fldd,mb -8(\regs), %fr16
fldd,mb -8(\regs), %fr15
fldd,mb -8(\regs), %fr14
fldd,mb -8(\regs), %fr13
fldd,mb -8(\regs), %fr12
fldd,mb -8(\regs), %fr11
fldd,mb -8(\regs), %fr10
fldd,mb -8(\regs), %fr9
fldd,mb -8(\regs), %fr8
fldd,mb -8(\regs), %fr7
fldd,mb -8(\regs), %fr6
fldd,mb -8(\regs), %fr5
fldd,mb -8(\regs), %fr4
fldd,mb -8(\regs), %fr3
fldd,mb -8(\regs), %fr2
fldd,mb -8(\regs), %fr1
fldd,mb -8(\regs), %fr0
.endm
.macro callee_save_float
fstd,ma %fr12, 8(%r30)
fstd,ma %fr13, 8(%r30)
fstd,ma %fr14, 8(%r30)
fstd,ma %fr15, 8(%r30)
fstd,ma %fr16, 8(%r30)
fstd,ma %fr17, 8(%r30)
fstd,ma %fr18, 8(%r30)
fstd,ma %fr19, 8(%r30)
fstd,ma %fr20, 8(%r30)
fstd,ma %fr21, 8(%r30)
.endm
.macro callee_rest_float
fldd,mb -8(%r30), %fr21
fldd,mb -8(%r30), %fr20
fldd,mb -8(%r30), %fr19
fldd,mb -8(%r30), %fr18
fldd,mb -8(%r30), %fr17
fldd,mb -8(%r30), %fr16
fldd,mb -8(%r30), %fr15
fldd,mb -8(%r30), %fr14
fldd,mb -8(%r30), %fr13
fldd,mb -8(%r30), %fr12
.endm
#ifdef CONFIG_64BIT
.macro callee_save
std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
mfctl %cr27, %r3
std %r4, -136(%r30)
std %r5, -128(%r30)
std %r6, -120(%r30)
std %r7, -112(%r30)
std %r8, -104(%r30)
std %r9, -96(%r30)
std %r10, -88(%r30)
std %r11, -80(%r30)
std %r12, -72(%r30)
std %r13, -64(%r30)
std %r14, -56(%r30)
std %r15, -48(%r30)
std %r16, -40(%r30)
std %r17, -32(%r30)
std %r18, -24(%r30)
std %r3, -16(%r30)
.endm
.macro callee_rest
ldd -16(%r30), %r3
ldd -24(%r30), %r18
ldd -32(%r30), %r17
ldd -40(%r30), %r16
ldd -48(%r30), %r15
ldd -56(%r30), %r14
ldd -64(%r30), %r13
ldd -72(%r30), %r12
ldd -80(%r30), %r11
ldd -88(%r30), %r10
ldd -96(%r30), %r9
ldd -104(%r30), %r8
ldd -112(%r30), %r7
ldd -120(%r30), %r6
ldd -128(%r30), %r5
ldd -136(%r30), %r4
mtctl %r3, %cr27
ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
.endm
#else /* ! CONFIG_64BIT */
.macro callee_save
stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
mfctl %cr27, %r3
stw %r4, -124(%r30)
stw %r5, -120(%r30)
stw %r6, -116(%r30)
stw %r7, -112(%r30)
stw %r8, -108(%r30)
stw %r9, -104(%r30)
stw %r10, -100(%r30)
stw %r11, -96(%r30)
stw %r12, -92(%r30)
stw %r13, -88(%r30)
stw %r14, -84(%r30)
stw %r15, -80(%r30)
stw %r16, -76(%r30)
stw %r17, -72(%r30)
stw %r18, -68(%r30)
stw %r3, -64(%r30)
.endm
.macro callee_rest
ldw -64(%r30), %r3
ldw -68(%r30), %r18
ldw -72(%r30), %r17
ldw -76(%r30), %r16
ldw -80(%r30), %r15
ldw -84(%r30), %r14
ldw -88(%r30), %r13
ldw -92(%r30), %r12
ldw -96(%r30), %r11
ldw -100(%r30), %r10
ldw -104(%r30), %r9
ldw -108(%r30), %r8
ldw -112(%r30), %r7
ldw -116(%r30), %r6
ldw -120(%r30), %r5
ldw -124(%r30), %r4
mtctl %r3, %cr27
ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
.endm
#endif /* ! CONFIG_64BIT */
.macro save_specials regs
SAVE_SP (%sr0, PT_SR0 (\regs))
SAVE_SP (%sr1, PT_SR1 (\regs))
SAVE_SP (%sr2, PT_SR2 (\regs))
SAVE_SP (%sr3, PT_SR3 (\regs))
SAVE_SP (%sr4, PT_SR4 (\regs))
SAVE_SP (%sr5, PT_SR5 (\regs))
SAVE_SP (%sr6, PT_SR6 (\regs))
SAVE_CR (%cr17, PT_IASQ0(\regs))
mtctl %r0, %cr17
SAVE_CR (%cr17, PT_IASQ1(\regs))
SAVE_CR (%cr18, PT_IAOQ0(\regs))
mtctl %r0, %cr18
SAVE_CR (%cr18, PT_IAOQ1(\regs))
#ifdef CONFIG_64BIT
/* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0
* For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
* reads 5 bits. Use mfctl,w to read all six bits. Otherwise
* we lose the 6th bit on a save/restore over interrupt.
*/
mfctl,w %cr11, %r1
STREG %r1, PT_SAR (\regs)
#else
SAVE_CR (%cr11, PT_SAR (\regs))
#endif
SAVE_CR (%cr19, PT_IIR (\regs))
/*
* Code immediately following this macro (in intr_save) relies
* on r8 containing ipsw.
*/
mfctl %cr22, %r8
STREG %r8, PT_PSW(\regs)
.endm
.macro rest_specials regs
REST_SP (%sr0, PT_SR0 (\regs))
REST_SP (%sr1, PT_SR1 (\regs))
REST_SP (%sr2, PT_SR2 (\regs))
REST_SP (%sr3, PT_SR3 (\regs))
REST_SP (%sr4, PT_SR4 (\regs))
REST_SP (%sr5, PT_SR5 (\regs))
REST_SP (%sr6, PT_SR6 (\regs))
REST_SP (%sr7, PT_SR7 (\regs))
REST_CR (%cr17, PT_IASQ0(\regs))
REST_CR (%cr17, PT_IASQ1(\regs))
REST_CR (%cr18, PT_IAOQ0(\regs))
REST_CR (%cr18, PT_IAOQ1(\regs))
REST_CR (%cr11, PT_SAR (\regs))
REST_CR (%cr22, PT_PSW (\regs))
.endm
/* First step to create a "relied upon translation"
* See PA 2.0 Arch. page F-4 and F-5.
*
* The ssm was originally necessary due to a "PCxT bug".
* But someone decided it needed to be added to the architecture
* and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
* It's been carried forward into PA 2.0 Arch as well. :^(
*
* "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
* rsm/ssm prevents the ifetch unit from speculatively fetching
* instructions past this line in the code stream.
* PA 2.0 processor will single step all insn in the same QUAD (4 insn).
*/
.macro pcxt_ssm_bug
rsm PSW_SM_I,%r0
nop /* 1 */
nop /* 2 */
nop /* 3 */
nop /* 4 */
nop /* 5 */
nop /* 6 */
nop /* 7 */
.endm
/* Switch to virtual mapping, trashing only %r1 */
.macro virt_map
/* pcxt_ssm_bug */
rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
mtsp %r0, %sr4
mtsp %r0, %sr5
mtsp %r0, %sr6
tovirt_r1 %r29
load32 KERNEL_PSW, %r1
rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
mtctl %r0, %cr17 /* Clear IIASQ tail */
mtctl %r0, %cr17 /* Clear IIASQ head */
mtctl %r1, %ipsw
load32 4f, %r1
mtctl %r1, %cr18 /* Set IIAOQ tail */
ldo 4(%r1), %r1
mtctl %r1, %cr18 /* Set IIAOQ head */
rfir
nop
4:
.endm
/*
* ASM_EXCEPTIONTABLE_ENTRY
*
* Creates an exception table entry.
* Do not convert to a assembler macro. This won't work.
*/
#define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \
.section __ex_table,"aw" ! \
.align 4 ! \
.word (fault_addr - .), (except_addr - .) ! \
or %r0,%r0,%r0 ! \
.previous
#endif /* __ASSEMBLER__ */
#endif
linux-7.2.3/arch/parisc/include/asm/atomic.h
+238
View File
@@ -0,0 +1,238 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
* Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
*/
#ifndef _ASM_PARISC_ATOMIC_H_
#define _ASM_PARISC_ATOMIC_H_
#include <linux/types.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*
* And probably incredibly slow on parisc. OTOH, we don't
* have to write any serious assembly. prumpf
*/
#ifdef CONFIG_SMP
#include <asm/spinlock.h>
#include <asm/cache.h> /* we use L1_CACHE_BYTES */
/* Use an array of spinlocks for our atomic_ts.
* Hash function to index into a different SPINLOCK.
* Since "a" is usually an address, use one spinlock per cacheline.
*/
# define ATOMIC_HASH_SIZE 4
# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
/* Can't use raw_spin_lock_irq because of #include problems, so
* this is the substitute */
#define _atomic_spin_lock_irqsave(l,f) do { \
arch_spinlock_t *s = ATOMIC_HASH(l); \
local_irq_save(f); \
arch_spin_lock(s); \
} while(0)
#define _atomic_spin_unlock_irqrestore(l,f) do { \
arch_spinlock_t *s = ATOMIC_HASH(l); \
arch_spin_unlock(s); \
local_irq_restore(f); \
} while(0)
#else
# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
#endif
/*
* Note that we need not lock read accesses - aligned word writes/reads
* are atomic, so a reader never sees inconsistent values.
*/
static __inline__ void arch_atomic_set(atomic_t *v, int i)
{
unsigned long flags;
_atomic_spin_lock_irqsave(v, flags);
v->counter = i;
_atomic_spin_unlock_irqrestore(v, flags);
}
#define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
static __inline__ int arch_atomic_read(const atomic_t *v)
{
return READ_ONCE((v)->counter);
}
#define ATOMIC_OP(op, c_op) \
static __inline__ void arch_atomic_##op(int i, atomic_t *v) \
{ \
unsigned long flags; \
\
_atomic_spin_lock_irqsave(v, flags); \
v->counter c_op i; \
_atomic_spin_unlock_irqrestore(v, flags); \
}
#define ATOMIC_OP_RETURN(op, c_op) \
static __inline__ int arch_atomic_##op##_return(int i, atomic_t *v) \
{ \
unsigned long flags; \
int ret; \
\
_atomic_spin_lock_irqsave(v, flags); \
ret = (v->counter c_op i); \
_atomic_spin_unlock_irqrestore(v, flags); \
\
return ret; \
}
#define ATOMIC_FETCH_OP(op, c_op) \
static __inline__ int arch_atomic_fetch_##op(int i, atomic_t *v) \
{ \
unsigned long flags; \
int ret; \
\
_atomic_spin_lock_irqsave(v, flags); \
ret = v->counter; \
v->counter c_op i; \
_atomic_spin_unlock_irqrestore(v, flags); \
\
return ret; \
}
#define ATOMIC_OPS(op, c_op) \
ATOMIC_OP(op, c_op) \
ATOMIC_OP_RETURN(op, c_op) \
ATOMIC_FETCH_OP(op, c_op)
ATOMIC_OPS(add, +=)
ATOMIC_OPS(sub, -=)
#define arch_atomic_add_return arch_atomic_add_return
#define arch_atomic_sub_return arch_atomic_sub_return
#define arch_atomic_fetch_add arch_atomic_fetch_add
#define arch_atomic_fetch_sub arch_atomic_fetch_sub
#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op) \
ATOMIC_OP(op, c_op) \
ATOMIC_FETCH_OP(op, c_op)
ATOMIC_OPS(and, &=)
ATOMIC_OPS(or, |=)
ATOMIC_OPS(xor, ^=)
#define arch_atomic_fetch_and arch_atomic_fetch_and
#define arch_atomic_fetch_or arch_atomic_fetch_or
#define arch_atomic_fetch_xor arch_atomic_fetch_xor
#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP
#ifdef CONFIG_64BIT
#define ATOMIC64_INIT(i) { (i) }
#define ATOMIC64_OP(op, c_op) \
static __inline__ void arch_atomic64_##op(s64 i, atomic64_t *v) \
{ \
unsigned long flags; \
\
_atomic_spin_lock_irqsave(v, flags); \
v->counter c_op i; \
_atomic_spin_unlock_irqrestore(v, flags); \
}
#define ATOMIC64_OP_RETURN(op, c_op) \
static __inline__ s64 arch_atomic64_##op##_return(s64 i, atomic64_t *v) \
{ \
unsigned long flags; \
s64 ret; \
\
_atomic_spin_lock_irqsave(v, flags); \
ret = (v->counter c_op i); \
_atomic_spin_unlock_irqrestore(v, flags); \
\
return ret; \
}
#define ATOMIC64_FETCH_OP(op, c_op) \
static __inline__ s64 arch_atomic64_fetch_##op(s64 i, atomic64_t *v) \
{ \
unsigned long flags; \
s64 ret; \
\
_atomic_spin_lock_irqsave(v, flags); \
ret = v->counter; \
v->counter c_op i; \
_atomic_spin_unlock_irqrestore(v, flags); \
\
return ret; \
}
#define ATOMIC64_OPS(op, c_op) \
ATOMIC64_OP(op, c_op) \
ATOMIC64_OP_RETURN(op, c_op) \
ATOMIC64_FETCH_OP(op, c_op)
ATOMIC64_OPS(add, +=)
ATOMIC64_OPS(sub, -=)
#define arch_atomic64_add_return arch_atomic64_add_return
#define arch_atomic64_sub_return arch_atomic64_sub_return
#define arch_atomic64_fetch_add arch_atomic64_fetch_add
#define arch_atomic64_fetch_sub arch_atomic64_fetch_sub
#undef ATOMIC64_OPS
#define ATOMIC64_OPS(op, c_op) \
ATOMIC64_OP(op, c_op) \
ATOMIC64_FETCH_OP(op, c_op)
ATOMIC64_OPS(and, &=)
ATOMIC64_OPS(or, |=)
ATOMIC64_OPS(xor, ^=)
#define arch_atomic64_fetch_and arch_atomic64_fetch_and
#define arch_atomic64_fetch_or arch_atomic64_fetch_or
#define arch_atomic64_fetch_xor arch_atomic64_fetch_xor
#undef ATOMIC64_OPS
#undef ATOMIC64_FETCH_OP
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP
static __inline__ void
arch_atomic64_set(atomic64_t *v, s64 i)
{
unsigned long flags;
_atomic_spin_lock_irqsave(v, flags);
v->counter = i;
_atomic_spin_unlock_irqrestore(v, flags);
}
#define arch_atomic64_set_release(v, i) arch_atomic64_set((v), (i))
static __inline__ s64
arch_atomic64_read(const atomic64_t *v)
{
return READ_ONCE((v)->counter);
}
#endif /* !CONFIG_64BIT */
#endif /* _ASM_PARISC_ATOMIC_H_ */
linux-7.2.3/arch/parisc/include/asm/barrier.h
+97
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@@ -0,0 +1,97 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H
#include <asm/alternative.h>
#ifndef __ASSEMBLER__
/* The synchronize caches instruction executes as a nop on systems in
which all memory references are performed in order. */
#define synchronize_caches() asm volatile("sync" \
ALTERNATIVE(ALT_COND_NO_SMP, INSN_NOP) \
: : : "memory")
#if defined(CONFIG_SMP)
#define mb() do { synchronize_caches(); } while (0)
#define rmb() mb()
#define wmb() mb()
#define dma_rmb() mb()
#define dma_wmb() mb()
#else
#define mb() barrier()
#define rmb() barrier()
#define wmb() barrier()
#define dma_rmb() barrier()
#define dma_wmb() barrier()
#endif
#define __smp_mb() mb()
#define __smp_rmb() mb()
#define __smp_wmb() mb()
#define __smp_store_release(p, v) \
do { \
typeof(p) __p = (p); \
union { typeof(*p) __val; char __c[1]; } __u = \
{ .__val = (__force typeof(*p)) (v) }; \
compiletime_assert_atomic_type(*p); \
switch (sizeof(*p)) { \
case 1: \
asm volatile("stb,ma %0,0(%1)" \
: : "r"(*(__u8 *)__u.__c), "r"(__p) \
: "memory"); \
break; \
case 2: \
asm volatile("sth,ma %0,0(%1)" \
: : "r"(*(__u16 *)__u.__c), "r"(__p) \
: "memory"); \
break; \
case 4: \
asm volatile("stw,ma %0,0(%1)" \
: : "r"(*(__u32 *)__u.__c), "r"(__p) \
: "memory"); \
break; \
case 8: \
if (IS_ENABLED(CONFIG_64BIT)) \
asm volatile("std,ma %0,0(%1)" \
: : "r"(*(__u64 *)__u.__c), "r"(__p) \
: "memory"); \
break; \
} \
} while (0)
#define __smp_load_acquire(p) \
({ \
union { typeof(*p) __val; char __c[1]; } __u; \
typeof(p) __p = (p); \
compiletime_assert_atomic_type(*p); \
switch (sizeof(*p)) { \
case 1: \
asm volatile("ldb,ma 0(%1),%0" \
: "=r"(*(__u8 *)__u.__c) : "r"(__p) \
: "memory"); \
break; \
case 2: \
asm volatile("ldh,ma 0(%1),%0" \
: "=r"(*(__u16 *)__u.__c) : "r"(__p) \
: "memory"); \
break; \
case 4: \
asm volatile("ldw,ma 0(%1),%0" \
: "=r"(*(__u32 *)__u.__c) : "r"(__p) \
: "memory"); \
break; \
case 8: \
if (IS_ENABLED(CONFIG_64BIT)) \
asm volatile("ldd,ma 0(%1),%0" \
: "=r"(*(__u64 *)__u.__c) : "r"(__p) \
: "memory"); \
break; \
} \
__u.__val; \
})
#include <asm-generic/barrier.h>
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_BARRIER_H */
linux-7.2.3/arch/parisc/include/asm/bitops.h
+209
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_BITOPS_H
#define _PARISC_BITOPS_H
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <linux/compiler.h>
#include <asm/types.h>
#include <asm/byteorder.h>
#include <asm/barrier.h>
#include <linux/atomic.h>
/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
* on use of volatile and __*_bit() (set/clear/change):
* *_bit() want use of volatile.
* __*_bit() are "relaxed" and don't use spinlock or volatile.
*/
static __inline__ void set_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long flags;
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr |= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}
static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long flags;
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr &= ~mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}
static __inline__ void change_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long flags;
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr ^= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}
static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long old;
unsigned long flags;
int set;
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
old = *addr;
set = (old & mask) ? 1 : 0;
if (!set)
*addr = old | mask;
_atomic_spin_unlock_irqrestore(addr, flags);
return set;
}
static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long old;
unsigned long flags;
int set;
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
old = *addr;
set = (old & mask) ? 1 : 0;
if (set)
*addr = old & ~mask;
_atomic_spin_unlock_irqrestore(addr, flags);
return set;
}
static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = BIT_MASK(nr);
unsigned long oldbit;
unsigned long flags;
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
oldbit = *addr;
*addr = oldbit ^ mask;
_atomic_spin_unlock_irqrestore(addr, flags);
return (oldbit & mask) ? 1 : 0;
}
#include <asm-generic/bitops/non-atomic.h>
/**
* __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
* @word: The word to search
*
* __ffs() return is undefined if no bit is set.
*
* 32-bit fast __ffs by LaMont Jones "lamont At hp com".
* 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
* (with help from willy/jejb to get the semantics right)
*
* This algorithm avoids branches by making use of nullification.
* One side effect of "extr" instructions is it sets PSW[N] bit.
* How PSW[N] (nullify next insn) gets set is determined by the
* "condition" field (eg "<>" or "TR" below) in the extr* insn.
* Only the 1st and one of either the 2cd or 3rd insn will get executed.
* Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
* cycles for each mispredicted branch.
*/
static __inline__ __attribute_const__ unsigned long __ffs(unsigned long x)
{
unsigned long ret;
__asm__(
#ifdef CONFIG_64BIT
" ldi 63,%1\n"
" extrd,u,*<> %0,63,32,%%r0\n"
" extrd,u,*TR %0,31,32,%0\n" /* move top 32-bits down */
" addi -32,%1,%1\n"
#else
" ldi 31,%1\n"
#endif
" extru,<> %0,31,16,%%r0\n"
" extru,TR %0,15,16,%0\n" /* xxxx0000 -> 0000xxxx */
" addi -16,%1,%1\n"
" extru,<> %0,31,8,%%r0\n"
" extru,TR %0,23,8,%0\n" /* 0000xx00 -> 000000xx */
" addi -8,%1,%1\n"
" extru,<> %0,31,4,%%r0\n"
" extru,TR %0,27,4,%0\n" /* 000000x0 -> 0000000x */
" addi -4,%1,%1\n"
" extru,<> %0,31,2,%%r0\n"
" extru,TR %0,29,2,%0\n" /* 0000000y, 1100b -> 0011b */
" addi -2,%1,%1\n"
" extru,= %0,31,1,%%r0\n" /* check last bit */
" addi -1,%1,%1\n"
: "+r" (x), "=r" (ret) );
return ret;
}
#include <asm-generic/bitops/ffz.h>
/*
* ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
* This is defined the same way as the libc and compiler builtin
* ffs routines, therefore differs in spirit from the above ffz (man ffs).
*/
static __inline__ __attribute_const__ int ffs(int x)
{
return x ? (__ffs((unsigned long)x) + 1) : 0;
}
/*
* fls: find last (most significant) bit set.
* fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static __inline__ __attribute_const__ int fls(unsigned int x)
{
int ret;
if (!x)
return 0;
__asm__(
" ldi 1,%1\n"
" extru,<> %0,15,16,%%r0\n"
" zdep,TR %0,15,16,%0\n" /* xxxx0000 */
" addi 16,%1,%1\n"
" extru,<> %0,7,8,%%r0\n"
" zdep,TR %0,23,24,%0\n" /* xx000000 */
" addi 8,%1,%1\n"
" extru,<> %0,3,4,%%r0\n"
" zdep,TR %0,27,28,%0\n" /* x0000000 */
" addi 4,%1,%1\n"
" extru,<> %0,1,2,%%r0\n"
" zdep,TR %0,29,30,%0\n" /* y0000000 (y&3 = 0) */
" addi 2,%1,%1\n"
" extru,= %0,0,1,%%r0\n"
" addi 1,%1,%1\n" /* if y & 8, add 1 */
: "+r" (x), "=r" (ret) );
return ret;
}
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic-setbit.h>
#endif /* _PARISC_BITOPS_H */
linux-7.2.3/arch/parisc/include/asm/bug.h
+99
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_BUG_H
#define _PARISC_BUG_H
/*
* Tell the user there is some problem.
* The offending file and line are encoded in the __bug_table section.
*/
#ifdef CONFIG_BUG
#define HAVE_ARCH_BUG
#define HAVE_ARCH_WARN_ON
/* the break instruction is used as BUG() marker. */
#define PARISC_BUG_BREAK_ASM "break 0x1f, 0x1fff"
#define PARISC_BUG_BREAK_INSN 0x03ffe01f /* PARISC_BUG_BREAK_ASM */
#ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
# define __BUG_REL(val) ".word " __stringify(val) " - ."
#else
# define __BUG_REL(val) ".word " __stringify(val)
#endif
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define BUG() \
do { \
asm volatile("\n" \
"1:\t" PARISC_BUG_BREAK_ASM "\n" \
"\t.pushsection __bug_table,\"a\"\n" \
"\t.align 4\n" \
"2:\t" __BUG_REL(1b) "\n" \
"\t" __BUG_REL(%c0) "\n" \
"\t.short %1, %2\n" \
"\t.blockz %3-2*4-2*2\n" \
"\t.popsection" \
: : "i" (__FILE__), "i" (__LINE__), \
"i" (0), "i" (sizeof(struct bug_entry)) ); \
unreachable(); \
} while(0)
#else
#define BUG() \
do { \
asm volatile(PARISC_BUG_BREAK_ASM : : ); \
unreachable(); \
} while(0)
#endif
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define __WARN_FLAGS(cond_str, flags) \
do { \
asm volatile("\n" \
"1:\t" PARISC_BUG_BREAK_ASM "\n" \
"\t.pushsection __bug_table,\"a\"\n" \
"\t.align 4\n" \
"2:\t" __BUG_REL(1b) "\n" \
"\t" __BUG_REL(%c0) "\n" \
"\t.short %1, %2\n" \
"\t.blockz %3-2*4-2*2\n" \
"\t.popsection" \
: : "i" (WARN_CONDITION_STR(cond_str) __FILE__), "i" (__LINE__), \
"i" (BUGFLAG_WARNING|(flags)), \
"i" (sizeof(struct bug_entry)) ); \
} while(0)
#else
#define __WARN_FLAGS(cond_str, flags) \
do { \
asm volatile("\n" \
"1:\t" PARISC_BUG_BREAK_ASM "\n" \
"\t.pushsection __bug_table,\"a\"\n" \
"\t.align 4\n" \
"2:\t" __BUG_REL(1b) "\n" \
"\t.short %0\n" \
"\t.blockz %1-4-2\n" \
"\t.popsection" \
: : "i" (BUGFLAG_WARNING|(flags)), \
"i" (sizeof(struct bug_entry)) ); \
} while(0)
#endif
#define WARN_ON(x) ({ \
int __ret_warn_on = !!(x); \
if (__builtin_constant_p(__ret_warn_on)) { \
if (__ret_warn_on) \
__WARN(); \
} else { \
if (unlikely(__ret_warn_on)) \
__WARN(); \
} \
unlikely(__ret_warn_on); \
})
#endif
#include <asm-generic/bug.h>
#endif
linux-7.2.3/arch/parisc/include/asm/cache.h
+77
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* include/asm-parisc/cache.h
*/
#ifndef __ARCH_PARISC_CACHE_H
#define __ARCH_PARISC_CACHE_H
#include <asm/alternative.h>
/*
* PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
* have 32-byte cachelines. The L1 length appears to be 16 bytes but this
* is not clearly documented.
*/
#define L1_CACHE_BYTES 16
#define L1_CACHE_SHIFT 4
#ifndef __ASSEMBLER__
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#ifdef CONFIG_PA20
#define ARCH_DMA_MINALIGN 128
#else
#define ARCH_DMA_MINALIGN 32
#endif
#define ARCH_KMALLOC_MINALIGN 16 /* ldcw requires 16-byte alignment */
#define arch_slab_minalign() ((unsigned)dcache_stride)
#define cache_line_size() dcache_stride
#define dma_get_cache_alignment cache_line_size
#define __read_mostly __section(".data..read_mostly")
void parisc_cache_init(void); /* initializes cache-flushing */
void disable_sr_hashing_asm(int); /* low level support for above */
void disable_sr_hashing(void); /* turns off space register hashing */
void free_sid(unsigned long);
unsigned long alloc_sid(void);
struct seq_file;
extern void show_cache_info(struct seq_file *m);
extern int split_tlb;
extern int dcache_stride;
extern int icache_stride;
extern struct pdc_cache_info cache_info;
extern struct pdc_btlb_info btlb_info;
void parisc_setup_cache_timing(void);
#define pdtlb(sr, addr) asm volatile("pdtlb 0(%%sr%0,%1)" \
ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
: : "i"(sr), "r" (addr) : "memory")
#define pitlb(sr, addr) asm volatile("pitlb 0(%%sr%0,%1)" \
ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
: : "i"(sr), "r" (addr) : "memory")
#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
: : "r" (addr) : "memory")
#define asm_io_sync() asm volatile("sync" \
ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
#define asm_syncdma() asm volatile("syncdma" :::"memory")
#endif /* ! __ASSEMBLER__ */
/* Classes of processor wrt: disabling space register hashing */
#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
#define SRHASH_PCXL 1 /* pcxl */
#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
#endif
linux-7.2.3/arch/parisc/include/asm/cacheflush.h
+86
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_CACHEFLUSH_H
#define _PARISC_CACHEFLUSH_H
#include <linux/mm.h>
#include <linux/uaccess.h>
#include <asm/tlbflush.h>
/* The usual comment is "Caches aren't brain-dead on the <architecture>".
* Unfortunately, that doesn't apply to PA-RISC. */
#include <linux/jump_label.h>
DECLARE_STATIC_KEY_TRUE(parisc_has_cache);
DECLARE_STATIC_KEY_TRUE(parisc_has_dcache);
DECLARE_STATIC_KEY_TRUE(parisc_has_icache);
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
void flush_user_icache_range_asm(unsigned long, unsigned long);
void flush_kernel_icache_range_asm(unsigned long, unsigned long);
void flush_user_dcache_range_asm(unsigned long, unsigned long);
void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
void purge_kernel_dcache_range_asm(unsigned long, unsigned long);
void flush_kernel_dcache_page_asm(const void *addr);
void flush_kernel_icache_page(void *);
/* Cache flush operations */
void flush_cache_all_local(void);
void flush_cache_all(void);
void flush_cache_mm(struct mm_struct *mm);
#define flush_kernel_dcache_range(start,size) \
flush_kernel_dcache_range_asm((start), (start)+(size));
/* The only way to flush a vmap range is to flush whole cache */
#define ARCH_IMPLEMENTS_FLUSH_KERNEL_VMAP_RANGE 1
void flush_kernel_vmap_range(void *vaddr, int size);
void invalidate_kernel_vmap_range(void *vaddr, int size);
void flush_cache_vmap(unsigned long start, unsigned long end);
#define flush_cache_vmap_early(start, end) do { } while (0)
void flush_cache_vunmap(unsigned long start, unsigned long end);
void flush_dcache_folio(struct folio *folio);
#define flush_dcache_folio flush_dcache_folio
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
static inline void flush_dcache_page(struct page *page)
{
flush_dcache_folio(page_folio(page));
}
#define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages)
#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages)
#define flush_dcache_mmap_lock_irqsave(mapping, flags) \
xa_lock_irqsave(&mapping->i_pages, flags)
#define flush_dcache_mmap_unlock_irqrestore(mapping, flags) \
xa_unlock_irqrestore(&mapping->i_pages, flags)
void flush_icache_pages(struct vm_area_struct *vma, struct page *page,
unsigned int nr);
#define flush_icache_pages flush_icache_pages
#define flush_icache_range(s,e) do { \
flush_kernel_dcache_range_asm(s,e); \
flush_kernel_icache_range_asm(s,e); \
} while (0)
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long user_vaddr, void *dst, void *src, int len);
void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long user_vaddr, void *dst, void *src, int len);
void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
unsigned long pfn);
void flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
#define ARCH_HAS_FLUSH_ANON_PAGE
void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr);
#define ARCH_HAS_FLUSH_ON_KUNMAP
void kunmap_flush_on_unmap(const void *addr);
#endif /* _PARISC_CACHEFLUSH_H */
linux-7.2.3/arch/parisc/include/asm/cachetype.h
+9
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@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_CACHETYPE_H
#define __ASM_PARISC_CACHETYPE_H
#include <linux/types.h>
#define cpu_dcache_is_aliasing() true
#endif
linux-7.2.3/arch/parisc/include/asm/checksum.h
+94
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@@ -0,0 +1,94 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_CHECKSUM_H
#define _PARISC_CHECKSUM_H
#include <linux/in6.h>
#define csum_tcpudp_nofold csum_tcpudp_nofold
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
__u32 len, __u8 proto,
__wsum sum)
{
__asm__(
" add %1, %0, %0\n"
" addc %2, %0, %0\n"
" addc %3, %0, %0\n"
" addc %%r0, %0, %0\n"
: "=r" (sum)
: "r" (daddr), "r"(saddr), "r"(proto+len), "0"(sum));
return sum;
}
#include <asm-generic/checksum.h>
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
const struct in6_addr *daddr,
__u32 len, __u8 proto,
__wsum sum)
{
unsigned long t0, t1, t2, t3;
len += proto; /* add 16-bit proto + len */
__asm__ __volatile__ (
#if BITS_PER_LONG > 32
/*
** We can execute two loads and two adds per cycle on PA 8000.
** But add insn's get serialized waiting for the carry bit.
** Try to keep 4 registers with "live" values ahead of the ALU.
*/
" depdi 0, 31, 32, %0\n"/* clear upper half of incoming checksum */
" ldd,ma 8(%1), %4\n" /* get 1st saddr word */
" ldd,ma 8(%2), %5\n" /* get 1st daddr word */
" add %4, %0, %0\n"
" ldd,ma 8(%1), %6\n" /* 2nd saddr */
" ldd,ma 8(%2), %7\n" /* 2nd daddr */
" add,dc %5, %0, %0\n"
" add,dc %6, %0, %0\n"
" add,dc %7, %0, %0\n"
" add,dc %3, %0, %0\n" /* fold in proto+len | carry bit */
" extrd,u %0, 31, 32, %4\n"/* copy upper half down */
" depdi 0, 31, 32, %0\n"/* clear upper half */
" add,dc %4, %0, %0\n" /* fold into 32-bits, plus carry */
" addc 0, %0, %0\n" /* add final carry */
#else
/*
** For PA 1.x, the insn order doesn't matter as much.
** Insn stream is serialized on the carry bit here too.
** result from the previous operation (eg r0 + x)
*/
" ldw,ma 4(%1), %4\n" /* get 1st saddr word */
" ldw,ma 4(%2), %5\n" /* get 1st daddr word */
" add %4, %0, %0\n"
" ldw,ma 4(%1), %6\n" /* 2nd saddr */
" addc %5, %0, %0\n"
" ldw,ma 4(%2), %7\n" /* 2nd daddr */
" addc %6, %0, %0\n"
" ldw,ma 4(%1), %4\n" /* 3rd saddr */
" addc %7, %0, %0\n"
" ldw,ma 4(%2), %5\n" /* 3rd daddr */
" addc %4, %0, %0\n"
" ldw,ma 4(%1), %6\n" /* 4th saddr */
" addc %5, %0, %0\n"
" ldw,ma 4(%2), %7\n" /* 4th daddr */
" addc %6, %0, %0\n"
" addc %7, %0, %0\n"
" addc %3, %0, %0\n" /* fold in proto+len */
" addc 0, %0, %0\n" /* add carry */
#endif
: "=r" (sum), "=r" (saddr), "=r" (daddr), "=r" (len),
"=r" (t0), "=r" (t1), "=r" (t2), "=r" (t3)
: "0" (sum), "1" (saddr), "2" (daddr), "3" (len)
: "memory");
return csum_fold(sum);
}
#endif
linux-7.2.3/arch/parisc/include/asm/cmpxchg.h
+122
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* forked from parisc asm/atomic.h which was:
* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
* Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
*/
#ifndef _ASM_PARISC_CMPXCHG_H_
#define _ASM_PARISC_CMPXCHG_H_
/* This should get optimized out since it's never called.
** Or get a link error if xchg is used "wrong".
*/
extern void __xchg_called_with_bad_pointer(void);
/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
extern unsigned long __xchg8(char, volatile char *);
extern unsigned long __xchg32(int, volatile int *);
#ifdef CONFIG_64BIT
extern unsigned long __xchg64(unsigned long, volatile unsigned long *);
#endif
/* optimizer better get rid of switch since size is a constant */
static inline unsigned long
__arch_xchg(unsigned long x, volatile void *ptr, int size)
{
switch (size) {
#ifdef CONFIG_64BIT
case 8: return __xchg64(x, (volatile unsigned long *) ptr);
#endif
case 4: return __xchg32((int) x, (volatile int *) ptr);
case 1: return __xchg8((char) x, (volatile char *) ptr);
}
__xchg_called_with_bad_pointer();
return x;
}
/*
** REVISIT - Abandoned use of LDCW in xchg() for now:
** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
** o and while we are at it, could CONFIG_64BIT code use LDCD too?
**
** if (__builtin_constant_p(x) && (x == NULL))
** if (((unsigned long)p & 0xf) == 0)
** return __ldcw(p);
*/
#define arch_xchg(ptr, x) \
({ \
__typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) _x_ = (x); \
__ret = (__typeof__(*(ptr))) \
__arch_xchg((unsigned long)_x_, (ptr), sizeof(*(ptr))); \
__ret; \
})
/* bug catcher for when unsupported size is used - won't link */
extern void __cmpxchg_called_with_bad_pointer(void);
/* __cmpxchg_u... defined in arch/parisc/lib/bitops.c */
extern u8 __cmpxchg_u8(volatile u8 *ptr, u8 old, u8 new_);
extern u16 __cmpxchg_u16(volatile u16 *ptr, u16 old, u16 new_);
extern u32 __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
extern u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new_);
/* don't worry...optimizer will get rid of most of this */
static inline unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
{
return
#ifdef CONFIG_64BIT
size == 8 ? __cmpxchg_u64(ptr, old, new_) :
#endif
size == 4 ? __cmpxchg_u32(ptr, old, new_) :
size == 2 ? __cmpxchg_u16(ptr, old, new_) :
size == 1 ? __cmpxchg_u8(ptr, old, new_) :
(__cmpxchg_called_with_bad_pointer(), old);
}
#define arch_cmpxchg(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr))); \
})
#include <asm-generic/cmpxchg-local.h>
static inline unsigned long __cmpxchg_local(volatile void *ptr,
unsigned long old,
unsigned long new_, int size)
{
switch (size) {
#ifdef CONFIG_64BIT
case 8: return __cmpxchg_u64((u64 *)ptr, old, new_);
#endif
case 4: return __cmpxchg_u32(ptr, old, new_);
default:
return __generic_cmpxchg_local(ptr, old, new_, size);
}
}
/*
* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
* them available.
*/
#define arch_cmpxchg_local(ptr, o, n) \
((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
(unsigned long)(n), sizeof(*(ptr))))
#ifdef CONFIG_64BIT
#define arch_cmpxchg64_local(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg_local((ptr), (o), (n)); \
})
#else
#define arch_cmpxchg64_local(ptr, o, n) __generic_cmpxchg64_local((ptr), (o), (n))
#endif
#define arch_cmpxchg64(ptr, o, n) __cmpxchg_u64(ptr, o, n)
#endif /* _ASM_PARISC_CMPXCHG_H_ */
linux-7.2.3/arch/parisc/include/asm/compat.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_COMPAT_H
#define _ASM_PARISC_COMPAT_H
/*
* Architecture specific compatibility types
*/
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/thread_info.h>
#define compat_mode_t compat_mode_t
typedef u16 compat_mode_t;
#define compat_ipc_pid_t compat_ipc_pid_t
typedef u16 compat_ipc_pid_t;
#define compat_ipc64_perm compat_ipc64_perm
#include <asm-generic/compat.h>
#define COMPAT_UTS_MACHINE "parisc\0\0"
typedef u16 compat_nlink_t;
struct compat_stat {
compat_dev_t st_dev; /* dev_t is 32 bits on parisc */
compat_ino_t st_ino; /* 32 bits */
compat_mode_t st_mode; /* 16 bits */
compat_nlink_t st_nlink; /* 16 bits */
u16 st_reserved1; /* old st_uid */
u16 st_reserved2; /* old st_gid */
compat_dev_t st_rdev;
compat_off_t st_size;
old_time32_t st_atime;
u32 st_atime_nsec;
old_time32_t st_mtime;
u32 st_mtime_nsec;
old_time32_t st_ctime;
u32 st_ctime_nsec;
s32 st_blksize;
s32 st_blocks;
u32 __unused1; /* ACL stuff */
compat_dev_t __unused2; /* network */
compat_ino_t __unused3; /* network */
u32 __unused4; /* cnodes */
u16 __unused5; /* netsite */
short st_fstype;
compat_dev_t st_realdev;
u16 st_basemode;
u16 st_spareshort;
__compat_uid32_t st_uid;
__compat_gid32_t st_gid;
u32 st_spare4[3];
};
struct compat_sigcontext {
compat_int_t sc_flags;
compat_int_t sc_gr[32]; /* PSW in sc_gr[0] */
u64 sc_fr[32];
compat_int_t sc_iasq[2];
compat_int_t sc_iaoq[2];
compat_int_t sc_sar; /* cr11 */
};
struct compat_ipc64_perm {
compat_key_t key;
__compat_uid_t uid;
__compat_gid_t gid;
__compat_uid_t cuid;
__compat_gid_t cgid;
unsigned short int __pad1;
compat_mode_t mode;
unsigned short int __pad2;
unsigned short int seq;
unsigned int __pad3;
unsigned long __unused1; /* yes they really are 64bit pads */
unsigned long __unused2;
};
struct compat_semid64_ds {
struct compat_ipc64_perm sem_perm;
unsigned int sem_otime_high;
unsigned int sem_otime;
unsigned int sem_ctime_high;
unsigned int sem_ctime;
compat_ulong_t sem_nsems;
compat_ulong_t __unused3;
compat_ulong_t __unused4;
};
struct compat_msqid64_ds {
struct compat_ipc64_perm msg_perm;
unsigned int msg_stime_high;
unsigned int msg_stime;
unsigned int msg_rtime_high;
unsigned int msg_rtime;
unsigned int msg_ctime_high;
unsigned int msg_ctime;
compat_ulong_t msg_cbytes;
compat_ulong_t msg_qnum;
compat_ulong_t msg_qbytes;
compat_pid_t msg_lspid;
compat_pid_t msg_lrpid;
compat_ulong_t __unused4;
compat_ulong_t __unused5;
};
struct compat_shmid64_ds {
struct compat_ipc64_perm shm_perm;
unsigned int shm_atime_high;
unsigned int shm_atime;
unsigned int shm_dtime_high;
unsigned int shm_dtime;
unsigned int shm_ctime_high;
unsigned int shm_ctime;
unsigned int __unused4;
compat_size_t shm_segsz;
compat_pid_t shm_cpid;
compat_pid_t shm_lpid;
compat_ulong_t shm_nattch;
compat_ulong_t __unused5;
compat_ulong_t __unused6;
};
/*
* The type of struct elf_prstatus.pr_reg in compatible core dumps.
*/
#define COMPAT_ELF_NGREG 80
typedef compat_ulong_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
static inline int __is_compat_task(struct task_struct *t)
{
return IS_ENABLED(CONFIG_COMPAT) && test_tsk_thread_flag(t, TIF_32BIT);
}
static inline int is_compat_task(void)
{
return __is_compat_task(current);
}
#endif /* _ASM_PARISC_COMPAT_H */
linux-7.2.3/arch/parisc/include/asm/compat_ucontext.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_COMPAT_UCONTEXT_H
#define _ASM_PARISC_COMPAT_UCONTEXT_H
#include <linux/compat.h>
/* 32-bit ucontext as seen from an 64-bit kernel */
struct compat_ucontext {
compat_uint_t uc_flags;
compat_uptr_t uc_link;
compat_stack_t uc_stack; /* struct compat_sigaltstack (12 bytes)*/
/* FIXME: Pad out to get uc_mcontext to start at an 8-byte aligned boundary */
compat_uint_t pad[1];
struct compat_sigcontext uc_mcontext;
compat_sigset_t uc_sigmask; /* mask last for extensibility */
};
#endif /* !_ASM_PARISC_COMPAT_UCONTEXT_H */
linux-7.2.3/arch/parisc/include/asm/current.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_CURRENT_H
#define _ASM_PARISC_CURRENT_H
#ifndef __ASSEMBLER__
struct task_struct;
static __always_inline struct task_struct *get_current(void)
{
struct task_struct *ts;
/* do not use mfctl() macro as it is marked volatile */
asm( "mfctl %%cr30,%0" : "=r" (ts) );
return ts;
}
#define current get_current()
#endif /* __ASSEMBLER__ */
#endif /* _ASM_PARISC_CURRENT_H */
linux-7.2.3/arch/parisc/include/asm/delay.h
+23
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_DELAY_H
#define _ASM_PARISC_DELAY_H
static __inline__ void __delay(unsigned long loops) {
asm volatile(
" .balignl 64,0x34000034\n"
" addib,UV -1,%0,.\n"
" nop\n"
: "=r" (loops) : "0" (loops));
}
extern void __udelay(unsigned long usecs);
extern void __udelay_bad(unsigned long usecs);
static inline void udelay(unsigned long usecs)
{
if (__builtin_constant_p(usecs) && (usecs) > 20000)
__udelay_bad(usecs);
__udelay(usecs);
}
#endif /* _ASM_PARISC_DELAY_H */
linux-7.2.3/arch/parisc/include/asm/dma-mapping.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_DMA_MAPPING_H
#define _PARISC_DMA_MAPPING_H
/*
** We need to support 4 different coherent dma models with one binary:
**
** I/O MMU consistent method dma_sync behavior
** ============= ====================== =======================
** a) PA-7x00LC uncachable host memory flush/purge
** b) U2/Uturn cachable host memory NOP
** c) Ike/Astro cachable host memory NOP
** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel
**
** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
**
** Systems (eg PCX-T workstations) that don't fall into the above
** categories will need to modify the needed drivers to perform
** flush/purge and allocate "regular" cacheable pages for everything.
*/
extern const struct dma_map_ops *hppa_dma_ops;
static inline const struct dma_map_ops *get_arch_dma_ops(void)
{
return hppa_dma_ops;
}
#endif
linux-7.2.3/arch/parisc/include/asm/dma.h
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/* SPDX-License-Identifier: GPL-2.0 */
/* asm/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
* (c) Copyright 2000, Grant Grundler
*/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <asm/io.h> /* need byte IO */
#define dma_outb outb
#define dma_inb inb
extern unsigned long pcxl_dma_start;
/*
** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
** (or rather not merge) DMAs into manageable chunks.
** On parisc, this is more of the software/tuning constraint
** rather than the HW. I/O MMU allocation algorithms can be
** faster with smaller sizes (to some degree).
*/
#define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE)
/* The maximum address that we can perform a DMA transfer to on this platform
** New dynamic DMA interfaces should obsolete this....
*/
#define MAX_DMA_ADDRESS (~0UL)
/*
** We don't have DMA channels... well V-class does but the
** Dynamic DMA Mapping interface will support them... right? :^)
** Note: this is not relevant right now for PA-RISC, but we cannot
** leave this as undefined because some things (e.g. sound)
** won't compile :-(
*/
#define MAX_DMA_CHANNELS 8
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG 0x08 /* command register (w) */
#define DMA1_STAT_REG 0x08 /* status register (r) */
#define DMA1_REQ_REG 0x09 /* request register (w) */
#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
#define DMA1_MODE_REG 0x0B /* mode register (w) */
#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
#define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
#define DMA2_CMD_REG 0xD0 /* command register (w) */
#define DMA2_STAT_REG 0xD0 /* status register (r) */
#define DMA2_REQ_REG 0xD2 /* request register (w) */
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
#define DMA2_MODE_REG 0xD6 /* mode register (w) */
#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
static __inline__ unsigned long claim_dma_lock(void)
{
return 0;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr<=3)? count : (count<<1);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
#ifdef CONFIG_SUPERIO
if (dmanr<=3)
dma_outb(dmanr, DMA1_MASK_REG);
else
dma_outb(dmanr & 3, DMA2_MASK_REG);
#endif
}
static __inline__ void disable_dma(unsigned int dmanr)
{
#ifdef CONFIG_SUPERIO
if (dmanr<=3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
#endif
}
/* reserve a DMA channel */
#define request_dma(dmanr, device_id) (0)
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
}
/* Set only the page register bits of the transfer address.
* This is used for successive transfers when we know the contents of
* the lower 16 bits of the DMA current address register, but a 64k boundary
* may have been crossed.
*/
static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
{
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
}
#define free_dma(dmanr)
#endif /* _ASM_DMA_H */
linux-7.2.3/arch/parisc/include/asm/dwarf.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2016 Helge Deller <deller@gmx.de>
*/
#ifndef _ASM_PARISC_DWARF_H
#define _ASM_PARISC_DWARF_H
#ifdef __ASSEMBLER__
#define CFI_STARTPROC .cfi_startproc
#define CFI_ENDPROC .cfi_endproc
#define CFI_DEF_CFA .cfi_def_cfa
#define CFI_REGISTER .cfi_register
#define CFI_REL_OFFSET .cfi_rel_offset
#define CFI_UNDEFINED .cfi_undefined
#endif /* __ASSEMBLER__ */
#endif /* _ASM_PARISC_DWARF_H */
linux-7.2.3/arch/parisc/include/asm/eisa_bus.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* eisa_bus.h interface between the eisa BA driver and the bus enumerator
*
* Copyright (c) 2002 Daniel Engstrom <5116@telia.com>
*/
#ifndef ASM_EISA_H
#define ASM_EISA_H
extern void eisa_make_irq_level(int num);
extern void eisa_make_irq_edge(int num);
extern int eisa_enumerator(unsigned long eeprom_addr,
struct resource *io_parent,
struct resource *mem_parent);
extern int eisa_eeprom_init(unsigned long addr);
#endif
linux-7.2.3/arch/parisc/include/asm/eisa_eeprom.h
+148
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* eisa_eeprom.h - provide support for EISA adapters in PA-RISC machines
*
* Copyright (c) 2001, 2002 Daniel Engstrom <5116@telia.com>
*/
#ifndef ASM_EISA_EEPROM_H
#define ASM_EISA_EEPROM_H
extern void __iomem *eisa_eeprom_addr;
#define HPEE_MAX_LENGTH 0x2000 /* maximum eeprom length */
#define HPEE_SLOT_INFO(slot) (20+(48*slot))
struct eeprom_header
{
u_int32_t num_writes; /* number of writes */
u_int8_t flags; /* flags, usage? */
u_int8_t ver_maj;
u_int8_t ver_min;
u_int8_t num_slots; /* number of EISA slots in system */
u_int16_t csum; /* checksum, I don't know how to calculate this */
u_int8_t pad[10];
} __attribute__ ((packed));
struct eeprom_eisa_slot_info
{
u_int32_t eisa_slot_id;
u_int32_t config_data_offset;
u_int32_t num_writes;
u_int16_t csum;
u_int16_t num_functions;
u_int16_t config_data_length;
/* bits 0..3 are the duplicate slot id */
#define HPEE_SLOT_INFO_EMBEDDED 0x10
#define HPEE_SLOT_INFO_VIRTUAL 0x20
#define HPEE_SLOT_INFO_NO_READID 0x40
#define HPEE_SLOT_INFO_DUPLICATE 0x80
u_int8_t slot_info;
#define HPEE_SLOT_FEATURES_ENABLE 0x01
#define HPEE_SLOT_FEATURES_IOCHK 0x02
#define HPEE_SLOT_FEATURES_CFG_INCOMPLETE 0x80
u_int8_t slot_features;
u_int8_t ver_min;
u_int8_t ver_maj;
#define HPEE_FUNCTION_INFO_HAVE_TYPE 0x01
#define HPEE_FUNCTION_INFO_HAVE_MEMORY 0x02
#define HPEE_FUNCTION_INFO_HAVE_IRQ 0x04
#define HPEE_FUNCTION_INFO_HAVE_DMA 0x08
#define HPEE_FUNCTION_INFO_HAVE_PORT 0x10
#define HPEE_FUNCTION_INFO_HAVE_PORT_INIT 0x20
/* I think there are two slighty different
* versions of the function_info field
* one int the fixed header and one optional
* in the parsed slot data area */
#define HPEE_FUNCTION_INFO_HAVE_FUNCTION 0x01
#define HPEE_FUNCTION_INFO_F_DISABLED 0x80
#define HPEE_FUNCTION_INFO_CFG_FREE_FORM 0x40
u_int8_t function_info;
#define HPEE_FLAG_BOARD_IS_ISA 0x01 /* flag and minor version for isa board */
u_int8_t flags;
u_int8_t pad[24];
} __attribute__ ((packed));
#define HPEE_MEMORY_MAX_ENT 9
/* memory descriptor: byte 0 */
#define HPEE_MEMORY_WRITABLE 0x01
#define HPEE_MEMORY_CACHABLE 0x02
#define HPEE_MEMORY_TYPE_MASK 0x18
#define HPEE_MEMORY_TYPE_SYS 0x00
#define HPEE_MEMORY_TYPE_EXP 0x08
#define HPEE_MEMORY_TYPE_VIR 0x10
#define HPEE_MEMORY_TYPE_OTH 0x18
#define HPEE_MEMORY_SHARED 0x20
#define HPEE_MEMORY_MORE 0x80
/* memory descriptor: byte 1 */
#define HPEE_MEMORY_WIDTH_MASK 0x03
#define HPEE_MEMORY_WIDTH_BYTE 0x00
#define HPEE_MEMORY_WIDTH_WORD 0x01
#define HPEE_MEMORY_WIDTH_DWORD 0x02
#define HPEE_MEMORY_DECODE_MASK 0x0c
#define HPEE_MEMORY_DECODE_20BITS 0x00
#define HPEE_MEMORY_DECODE_24BITS 0x04
#define HPEE_MEMORY_DECODE_32BITS 0x08
/* byte 2 and 3 are a 16bit LE value
* containing the memory size in kilobytes */
/* byte 4,5,6 are a 24bit LE value
* containing the memory base address */
#define HPEE_IRQ_MAX_ENT 7
/* Interrupt entry: byte 0 */
#define HPEE_IRQ_CHANNEL_MASK 0xf
#define HPEE_IRQ_TRIG_LEVEL 0x20
#define HPEE_IRQ_MORE 0x80
/* byte 1 seems to be unused */
#define HPEE_DMA_MAX_ENT 4
/* dma entry: byte 0 */
#define HPEE_DMA_CHANNEL_MASK 7
#define HPEE_DMA_SIZE_MASK 0xc
#define HPEE_DMA_SIZE_BYTE 0x0
#define HPEE_DMA_SIZE_WORD 0x4
#define HPEE_DMA_SIZE_DWORD 0x8
#define HPEE_DMA_SHARED 0x40
#define HPEE_DMA_MORE 0x80
/* dma entry: byte 1 */
#define HPEE_DMA_TIMING_MASK 0x30
#define HPEE_DMA_TIMING_ISA 0x0
#define HPEE_DMA_TIMING_TYPEA 0x10
#define HPEE_DMA_TIMING_TYPEB 0x20
#define HPEE_DMA_TIMING_TYPEC 0x30
#define HPEE_PORT_MAX_ENT 20
/* port entry byte 0 */
#define HPEE_PORT_SIZE_MASK 0x1f
#define HPEE_PORT_SHARED 0x40
#define HPEE_PORT_MORE 0x80
/* byte 1 and 2 is a 16bit LE value
* containing the start port number */
#define HPEE_PORT_INIT_MAX_LEN 60 /* in bytes here */
/* port init entry byte 0 */
#define HPEE_PORT_INIT_WIDTH_MASK 0x3
#define HPEE_PORT_INIT_WIDTH_BYTE 0x0
#define HPEE_PORT_INIT_WIDTH_WORD 0x1
#define HPEE_PORT_INIT_WIDTH_DWORD 0x2
#define HPEE_PORT_INIT_MASK 0x4
#define HPEE_PORT_INIT_MORE 0x80
#define HPEE_SELECTION_MAX_ENT 26
#define HPEE_TYPE_MAX_LEN 80
#endif
linux-7.2.3/arch/parisc/include/asm/elf.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASMPARISC_ELF_H
#define __ASMPARISC_ELF_H
/*
* ELF register definitions..
*/
#include <linux/types.h>
#define EM_PARISC 15
/* HPPA specific definitions. */
/* Legal values for e_flags field of Elf32_Ehdr. */
#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */
#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */
#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */
#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */
#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch
prediction. */
#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */
#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */
/* Defined values for `e_flags & EF_PARISC_ARCH' are: */
#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */
#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
/* Additional section indices. */
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared
symbols in ANSI C. */
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */
/* Legal values for sh_type field of Elf32_Shdr. */
#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */
#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */
#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */
/* Legal values for sh_flags field of Elf32_Shdr. */
#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */
#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */
#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */
/* Legal values for ST_TYPE subfield of st_info (symbol type). */
#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */
#define STT_HP_OPAQUE (STT_LOOS + 0x1)
#define STT_HP_STUB (STT_LOOS + 0x2)
/* HPPA relocs. */
#define R_PARISC_NONE 0 /* No reloc. */
#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */
#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */
#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */
#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */
#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */
#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */
#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */
#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */
#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */
#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */
#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */
#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */
#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */
#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */
#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */
#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */
#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */
#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */
#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */
#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */
#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */
#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */
#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */
#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */
#define R_PARISC_FPTR64 64 /* 64 bits function address. */
#define R_PARISC_PLABEL32 65 /* 32 bits function address. */
#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */
#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */
#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */
#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */
#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */
#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */
#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */
#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */
#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */
#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */
#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */
#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */
#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */
#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */
#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */
#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */
#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */
#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */
#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */
#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */
#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */
#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */
#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */
#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */
#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */
#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */
#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */
#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */
#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */
#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */
#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */
#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */
#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */
#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */
#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */
#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */
#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */
#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */
#define R_PARISC_LORESERVE 128
#define R_PARISC_COPY 128 /* Copy relocation. */
#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */
#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */
#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */
#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */
#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */
#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */
#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/
#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */
#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */
#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */
#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */
#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */
#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */
#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */
#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */
#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/
#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/
#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */
#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */
#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */
#define R_PARISC_HIRESERVE 255
#define PA_PLABEL_FDESC 0x02 /* bit set if PLABEL points to
* a function descriptor, not
* an address */
/* The following are PA function descriptors
*
* addr: the absolute address of the function
* gp: either the data pointer (r27) for non-PIC code or
* the PLT pointer (r19) for PIC code */
/* Format for the Elf32 Function descriptor */
typedef struct elf32_fdesc {
__u32 addr;
__u32 gp;
} Elf32_Fdesc;
/* Format for the Elf64 Function descriptor */
typedef struct elf64_fdesc {
__u64 dummy[2]; /* used by 64-bit eBPF and tracing functions */
__u64 addr;
__u64 gp;
} Elf64_Fdesc;
#ifdef CONFIG_64BIT
#define Elf_Fdesc Elf64_Fdesc
#else
#define Elf_Fdesc Elf32_Fdesc
#endif /*CONFIG_64BIT*/
/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */
#define PT_HP_TLS (PT_LOOS + 0x0)
#define PT_HP_CORE_NONE (PT_LOOS + 0x1)
#define PT_HP_CORE_VERSION (PT_LOOS + 0x2)
#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3)
#define PT_HP_CORE_COMM (PT_LOOS + 0x4)
#define PT_HP_CORE_PROC (PT_LOOS + 0x5)
#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6)
#define PT_HP_CORE_STACK (PT_LOOS + 0x7)
#define PT_HP_CORE_SHM (PT_LOOS + 0x8)
#define PT_HP_CORE_MMF (PT_LOOS + 0x9)
#define PT_HP_PARALLEL (PT_LOOS + 0x10)
#define PT_HP_FASTBIND (PT_LOOS + 0x11)
#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12)
#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13)
#define PT_HP_STACK (PT_LOOS + 0x14)
#define PT_PARISC_ARCHEXT 0x70000000
#define PT_PARISC_UNWIND 0x70000001
/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */
#define PF_PARISC_SBP 0x08000000
#define PF_HP_PAGE_SIZE 0x00100000
#define PF_HP_FAR_SHARED 0x00200000
#define PF_HP_NEAR_SHARED 0x00400000
#define PF_HP_CODE 0x01000000
#define PF_HP_MODIFY 0x02000000
#define PF_HP_LAZYSWAP 0x04000000
#define PF_HP_SBP 0x08000000
/*
* This yields a string that ld.so will use to load implementation
* specific libraries for optimization. This is more specific in
* intent than poking at uname or /proc/cpuinfo.
*/
#define ELF_PLATFORM ("PARISC")
/*
* The following definitions are those for 32-bit ELF binaries on a 32-bit
* kernel and for 64-bit binaries on a 64-bit kernel. To run 32-bit binaries
* on a 64-bit kernel, fs/compat_binfmt_elf.c defines ELF_CLASS and then
* #includes binfmt_elf.c, which then includes this file.
*/
#ifndef ELF_CLASS
#ifdef CONFIG_64BIT
#define ELF_CLASS ELFCLASS64
#else
#define ELF_CLASS ELFCLASS32
#endif
typedef unsigned long elf_greg_t;
#define SET_PERSONALITY(ex) \
({ \
set_personality((current->personality & ~PER_MASK) | PER_LINUX); \
clear_thread_flag(TIF_32BIT); \
current->thread.map_base = DEFAULT_MAP_BASE; \
current->thread.task_size = DEFAULT_TASK_SIZE; \
})
#endif /* ! ELF_CLASS */
#define COMPAT_SET_PERSONALITY(ex) \
({ \
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \
set_thread_flag(TIF_32BIT); \
current->thread.map_base = DEFAULT_MAP_BASE32; \
current->thread.task_size = DEFAULT_TASK_SIZE32; \
} else clear_thread_flag(TIF_32BIT); \
})
/*
* Fill in general registers in a core dump. This saves pretty
* much the same registers as hp-ux, although in a different order.
* Registers marked # below are not currently saved in pt_regs, so
* we use their current values here.
*
* gr0..gr31
* sr0..sr7
* iaoq0..iaoq1
* iasq0..iasq1
* cr11 (sar)
* cr19 (iir)
* cr20 (isr)
* cr21 (ior)
* # cr22 (ipsw)
* # cr0 (recovery counter)
* # cr24..cr31 (temporary registers)
* # cr8,9,12,13 (protection IDs)
* # cr10 (scr/ccr)
* # cr15 (ext int enable mask)
*
*/
#define ELF_CORE_COPY_REGS(dst, pt) \
memset(dst, 0, sizeof(dst)); /* don't leak any "random" bits */ \
{ int i; \
for (i = 0; i < 32; i++) dst[i] = pt->gr[i]; \
for (i = 0; i < 8; i++) dst[32 + i] = pt->sr[i]; \
} \
dst[40] = pt->iaoq[0]; dst[41] = pt->iaoq[1]; \
dst[42] = pt->iasq[0]; dst[43] = pt->iasq[1]; \
dst[44] = pt->sar; dst[45] = pt->iir; \
dst[46] = pt->isr; dst[47] = pt->ior; \
dst[48] = mfctl(22); dst[49] = mfctl(0); \
dst[50] = mfctl(24); dst[51] = mfctl(25); \
dst[52] = mfctl(26); dst[53] = mfctl(27); \
dst[54] = mfctl(28); dst[55] = mfctl(29); \
dst[56] = mfctl(30); dst[57] = mfctl(31); \
dst[58] = mfctl( 8); dst[59] = mfctl( 9); \
dst[60] = mfctl(12); dst[61] = mfctl(13); \
dst[62] = mfctl(10); dst[63] = mfctl(15);
#define CORE_DUMP_USE_REGSET
#define ELF_NGREG 80 /* We only need 64 at present, but leave space
for expansion. */
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
#define ELF_NFPREG 32
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
struct task_struct;
struct pt_regs; /* forward declaration... */
#define elf_check_arch(x) \
((x)->e_machine == EM_PARISC && (x)->e_ident[EI_CLASS] == ELF_CLASS)
#define compat_elf_check_arch(x) \
((x)->e_machine == EM_PARISC && (x)->e_ident[EI_CLASS] == ELFCLASS32)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_DATA ELFDATA2MSB
#define ELF_ARCH EM_PARISC
#define ELF_OSABI ELFOSABI_LINUX
/* %r23 is set by ld.so to a pointer to a function which might be
registered using atexit. This provides a means for the dynamic
linker to call DT_FINI functions for shared libraries that have
been loaded before the code runs.
So that we can use the same startup file with static executables,
we start programs with a value of 0 to indicate that there is no
such function. */
#define ELF_PLAT_INIT(_r, load_addr) _r->gr[23] = 0
#define ELF_EXEC_PAGESIZE 4096
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk.
(2 * TASK_SIZE / 3) turns into something undefined when run through a
32 bit preprocessor and in some cases results in the kernel trying to map
ld.so to the kernel virtual base. Use a sane value instead. /Jes
*/
#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x01000000)
/* This yields a mask that user programs can use to figure out what
instruction set this CPU supports. This could be done in user space,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP 0
#define STACK_RND_MASK 0x7ff /* 8MB of VA */
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
struct linux_binprm;
extern int arch_setup_additional_pages(struct linux_binprm *bprm,
int executable_stack);
#define VDSO_AUX_ENT(a, b) NEW_AUX_ENT(a, b)
#define VDSO_CURRENT_BASE current->mm->context.vdso_base
#define ARCH_DLINFO \
do { \
if (VDSO_CURRENT_BASE) { \
NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_CURRENT_BASE);\
} \
} while (0)
#endif
linux-7.2.3/arch/parisc/include/asm/extable.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PARISC_EXTABLE_H
#define __PARISC_EXTABLE_H
#include <asm/ptrace.h>
#include <linux/compiler.h>
/*
* The exception table consists of three addresses:
*
* - A relative address to the instruction that is allowed to fault.
* - A relative address at which the program should continue (fixup routine)
* - An asm statement which specifies which CPU register will
* receive -EFAULT when an exception happens if the lowest bit in
* the fixup address is set.
*
* Note: The register specified in the err_opcode instruction will be
* modified at runtime if a fault happens. Register %r0 will be ignored.
*
* Since relative addresses are used, 32bit values are sufficient even on
* 64bit kernel.
*/
struct pt_regs;
int fixup_exception(struct pt_regs *regs);
#define ARCH_HAS_RELATIVE_EXTABLE
struct exception_table_entry {
int insn; /* relative address of insn that is allowed to fault. */
int fixup; /* relative address of fixup routine */
int err_opcode; /* sample opcode with register which holds error code */
};
#define ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr, opcode )\
".section __ex_table,\"aw\"\n" \
".align 4\n" \
".word (" #fault_addr " - .), (" #except_addr " - .)\n" \
opcode "\n" \
".previous\n"
/*
* ASM_EXCEPTIONTABLE_ENTRY_EFAULT() creates a special exception table entry
* (with lowest bit set) for which the fault handler in fixup_exception() will
* load -EFAULT on fault into the register specified by the err_opcode instruction,
* and zeroes the target register in case of a read fault in get_user().
*/
#define ASM_EXCEPTIONTABLE_VAR(__err_var) \
int __err_var = 0
#define ASM_EXCEPTIONTABLE_ENTRY_EFAULT( fault_addr, except_addr, register )\
ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr + 1, "or %%r0,%%r0," register)
static inline void swap_ex_entry_fixup(struct exception_table_entry *a,
struct exception_table_entry *b,
struct exception_table_entry tmp,
int delta)
{
a->fixup = b->fixup + delta;
b->fixup = tmp.fixup - delta;
a->err_opcode = b->err_opcode;
b->err_opcode = tmp.err_opcode;
}
#define swap_ex_entry_fixup swap_ex_entry_fixup
#endif
linux-7.2.3/arch/parisc/include/asm/fixmap.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
/*
* This file defines the locations of the fixed mappings on parisc.
*
* All of the values in this file are machine virtual addresses.
*
* All of the values in this file must be <4GB (because of assembly
* loading restrictions). If you place this region anywhere above
* __PAGE_OFFSET, you must adjust the memory map accordingly
*/
/*
* The tmpalias region is used in kernel space to copy/clear/flush data
* from pages congruently mapped with user space. It is comprised of
* a pair regions. The size of these regions is determined by the largest
* cache aliasing boundary for machines that support equivalent aliasing.
*
* The c3750 with PA8700 processor returns an alias value of 11. This
* indicates that it has an alias boundary of 4 MB. It also supports
* non-equivalent aliasing without a performance penalty.
*
* Machines with PA8800/PA8900 processors return an alias value of 0.
* This indicates the alias boundary is unknown and may be larger than
* 16 MB. Non-equivalent aliasing is not supported.
*
* Here we assume the maximum alias boundary is 4 MB.
*/
#define TMPALIAS_SIZE_BITS 22 /* 4 MB */
#define TMPALIAS_MAP_START ((__PAGE_OFFSET) - (2 << TMPALIAS_SIZE_BITS))
#define FIXMAP_SIZE (FIX_BITMAP_COUNT << PAGE_SHIFT)
#define FIXMAP_START (TMPALIAS_MAP_START - FIXMAP_SIZE)
/* This is the kernel area for all maps (vmalloc, dma etc.) most
* usually, it extends up to TMPALIAS_MAP_START. Virtual addresses
* 0..GATEWAY_PAGE_SIZE are reserved for the gateway page */
#define KERNEL_MAP_START (GATEWAY_PAGE_SIZE)
#define KERNEL_MAP_END (FIXMAP_START)
#ifndef __ASSEMBLER__
enum fixed_addresses {
/* Support writing RO kernel text via kprobes, jump labels, etc. */
FIX_TEXT_POKE0,
FIX_TEXT_KEXEC,
FIX_BITMAP_COUNT
};
extern void *parisc_vmalloc_start;
#define PCXL_DMA_MAP_SIZE (8*1024*1024)
#define VMALLOC_START ((unsigned long)parisc_vmalloc_start)
#define VMALLOC_END (KERNEL_MAP_END)
#define __fix_to_virt(_x) (FIXMAP_START + ((_x) << PAGE_SHIFT))
void set_fixmap(enum fixed_addresses idx, phys_addr_t phys);
void clear_fixmap(enum fixed_addresses idx);
#endif /*__ASSEMBLER__*/
#endif /*_ASM_FIXMAP_H*/
linux-7.2.3/arch/parisc/include/asm/floppy.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Architecture specific parts of the Floppy driver
*
* Linux/PA-RISC Project (http://www.parisc-linux.org/)
* Copyright (C) 2000 Matthew Wilcox (willy a debian . org)
* Copyright (C) 2000 Dave Kennedy
*/
#ifndef __ASM_PARISC_FLOPPY_H
#define __ASM_PARISC_FLOPPY_H
#include <linux/sizes.h>
#include <linux/vmalloc.h>
/*
* The DMA channel used by the floppy controller cannot access data at
* addresses >= 16MB
*
* Went back to the 1MB limit, as some people had problems with the floppy
* driver otherwise. It doesn't matter much for performance anyway, as most
* floppy accesses go through the track buffer.
*/
#define _CROSS_64KB(a,s,vdma) \
(!(vdma) && \
((unsigned long)(a) / SZ_64K != ((unsigned long)(a) + (s) - 1) / SZ_64K))
#define SW fd_routine[use_virtual_dma&1]
#define CSW fd_routine[can_use_virtual_dma & 1]
#define fd_inb(base, reg) readb((base) + (reg))
#define fd_outb(value, base, reg) writeb(value, (base) + (reg))
#define fd_request_dma() CSW._request_dma(FLOPPY_DMA,"floppy")
#define fd_free_dma() CSW._free_dma(FLOPPY_DMA)
#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL)
#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
#define FLOPPY_CAN_FALLBACK_ON_NODMA
static int virtual_dma_count=0;
static int virtual_dma_residue=0;
static char *virtual_dma_addr=0;
static int virtual_dma_mode=0;
static int doing_pdma=0;
static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs)
{
register unsigned char st;
#undef TRACE_FLPY_INT
#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
#endif
if (!doing_pdma) {
floppy_interrupt(irq, dev_id, regs);
return;
}
#ifdef TRACE_FLPY_INT
if(!calls)
bytes = virtual_dma_count;
#endif
{
register int lcount;
register char *lptr = virtual_dma_addr;
for (lcount = virtual_dma_count; lcount; lcount--) {
st = fd_inb(virtual_dma_port, FD_STATUS);
st &= STATUS_DMA | STATUS_READY;
if (st != (STATUS_DMA | STATUS_READY))
break;
if (virtual_dma_mode) {
fd_outb(*lptr, virtual_dma_port, FD_DATA);
} else {
*lptr = fd_inb(virtual_dma_port, FD_DATA);
}
lptr++;
}
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
st = fd_inb(virtual_dma_port, FD_STATUS);
}
#ifdef TRACE_FLPY_INT
calls++;
#endif
if (st == STATUS_DMA)
return;
if (!(st & STATUS_DMA)) {
virtual_dma_residue += virtual_dma_count;
virtual_dma_count = 0;
#ifdef TRACE_FLPY_INT
printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
dma_wait=0;
#endif
doing_pdma = 0;
floppy_interrupt(irq, dev_id, regs);
return;
}
#ifdef TRACE_FLPY_INT
if (!virtual_dma_count)
dma_wait++;
#endif
}
static void fd_disable_dma(void)
{
if(! (can_use_virtual_dma & 1))
disable_dma(FLOPPY_DMA);
doing_pdma = 0;
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
}
static int vdma_request_dma(unsigned int dmanr, const char * device_id)
{
return 0;
}
static void vdma_nop(unsigned int dummy)
{
}
static int vdma_get_dma_residue(unsigned int dummy)
{
return virtual_dma_count + virtual_dma_residue;
}
static int fd_request_irq(void)
{
if(can_use_virtual_dma)
return request_irq(FLOPPY_IRQ, floppy_hardint,
0, "floppy", NULL);
else
return request_irq(FLOPPY_IRQ, floppy_interrupt,
0, "floppy", NULL);
}
static unsigned long dma_mem_alloc(unsigned long size)
{
return __get_dma_pages(GFP_KERNEL, get_order(size));
}
static unsigned long vdma_mem_alloc(unsigned long size)
{
return (unsigned long) vmalloc(size);
}
#define nodma_mem_alloc(size) vdma_mem_alloc(size)
static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
{
if((unsigned int) addr >= (unsigned int) high_memory)
return vfree((void *)addr);
else
free_pages(addr, get_order(size));
}
#define fd_dma_mem_free(addr, size) _fd_dma_mem_free(addr, size)
static void _fd_chose_dma_mode(char *addr, unsigned long size)
{
if(can_use_virtual_dma == 2) {
if((unsigned int) addr >= (unsigned int) high_memory ||
virt_to_phys(addr) >= 0x1000000 ||
_CROSS_64KB(addr, size, 0))
use_virtual_dma = 1;
else
use_virtual_dma = 0;
} else {
use_virtual_dma = can_use_virtual_dma & 1;
}
}
#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size)
static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
{
doing_pdma = 1;
virtual_dma_port = io;
virtual_dma_mode = (mode == DMA_MODE_WRITE);
virtual_dma_addr = addr;
virtual_dma_count = size;
virtual_dma_residue = 0;
return 0;
}
static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
{
#ifdef FLOPPY_SANITY_CHECK
if (_CROSS_64KB(addr, size, use_virtual_dma & 1)) {
printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size);
return -1;
}
#endif
/* actual, physical DMA */
doing_pdma = 0;
clear_dma_ff(FLOPPY_DMA);
set_dma_mode(FLOPPY_DMA,mode);
set_dma_addr(FLOPPY_DMA,virt_to_phys(addr));
set_dma_count(FLOPPY_DMA,size);
enable_dma(FLOPPY_DMA);
return 0;
}
static struct fd_routine_l {
int (*_request_dma)(unsigned int dmanr, const char * device_id);
void (*_free_dma)(unsigned int dmanr);
int (*_get_dma_residue)(unsigned int dummy);
unsigned long (*_dma_mem_alloc) (unsigned long size);
int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
} fd_routine[] = {
{
request_dma,
free_dma,
get_dma_residue,
dma_mem_alloc,
hard_dma_setup
},
{
vdma_request_dma,
vdma_nop,
vdma_get_dma_residue,
vdma_mem_alloc,
vdma_dma_setup
}
};
static int FDC1 = 0x3f0; /* Lies. Floppy controller is memory mapped, not io mapped */
static int FDC2 = -1;
#define FLOPPY0_TYPE 0
#define FLOPPY1_TYPE 0
#define N_FDC 1
#define N_DRIVE 8
#define EXTRA_FLOPPY_PARAMS
#endif /* __ASM_PARISC_FLOPPY_H */
linux-7.2.3/arch/parisc/include/asm/ftrace.h
+34
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_FTRACE_H
#define _ASM_PARISC_FTRACE_H
#ifndef __ASSEMBLER__
extern void mcount(void);
#define MCOUNT_ADDR ((unsigned long)mcount)
#define MCOUNT_INSN_SIZE 4
#define CC_USING_NOP_MCOUNT
#define ARCH_SUPPORTS_FTRACE_OPS 1
extern unsigned long sys_call_table[];
extern unsigned long return_address(unsigned int);
struct ftrace_regs;
extern void ftrace_function_trampoline(unsigned long parent,
unsigned long self_addr, unsigned long org_sp_gr3,
struct ftrace_regs *fregs);
#ifdef CONFIG_DYNAMIC_FTRACE
extern void ftrace_caller(void);
struct dyn_arch_ftrace {
};
unsigned long ftrace_call_adjust(unsigned long addr);
#endif
#define ftrace_return_address(n) return_address(n)
#endif /* __ASSEMBLER__ */
#endif /* _ASM_PARISC_FTRACE_H */
linux-7.2.3/arch/parisc/include/asm/futex.h
+127
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_FUTEX_H
#define _ASM_PARISC_FUTEX_H
#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/atomic.h>
#include <asm/errno.h>
/* The following has to match the LWS code in syscall.S. We have
* 256 four-word locks. We use bits 20-27 of the futex virtual
* address for the hash index.
*/
static inline unsigned long _futex_hash_index(unsigned long ua)
{
return (ua >> 2) & 0x3fc;
}
static inline void
_futex_spin_lock_irqsave(arch_spinlock_t *s, unsigned long *flags)
{
local_irq_save(*flags);
arch_spin_lock(s);
}
static inline void
_futex_spin_unlock_irqrestore(arch_spinlock_t *s, unsigned long *flags)
{
arch_spin_unlock(s);
local_irq_restore(*flags);
}
static inline int
arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
{
extern u32 lws_lock_start[];
unsigned long ua = (unsigned long)uaddr;
arch_spinlock_t *s;
unsigned long flags;
int oldval, ret;
u32 tmp;
s = (arch_spinlock_t *)&lws_lock_start[_futex_hash_index(ua)];
_futex_spin_lock_irqsave(s, &flags);
/* Return -EFAULT if we encounter a page fault or COW break */
if (unlikely(get_user(oldval, uaddr) != 0)) {
ret = -EFAULT;
goto out_pagefault_enable;
}
ret = 0;
tmp = oldval;
switch (op) {
case FUTEX_OP_SET:
tmp = oparg;
break;
case FUTEX_OP_ADD:
tmp += oparg;
break;
case FUTEX_OP_OR:
tmp |= oparg;
break;
case FUTEX_OP_ANDN:
tmp &= ~oparg;
break;
case FUTEX_OP_XOR:
tmp ^= oparg;
break;
default:
ret = -ENOSYS;
goto out_pagefault_enable;
}
if (unlikely(put_user(tmp, uaddr) != 0))
ret = -EFAULT;
out_pagefault_enable:
_futex_spin_unlock_irqrestore(s, &flags);
if (!ret)
*oval = oldval;
return ret;
}
static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
u32 oldval, u32 newval)
{
extern u32 lws_lock_start[];
unsigned long ua = (unsigned long)uaddr;
arch_spinlock_t *s;
u32 val;
unsigned long flags;
if (!access_ok(uaddr, sizeof(u32)))
return -EFAULT;
/* HPPA has no cmpxchg in hardware and therefore the
* best we can do here is use an array of locks. The
* lock selected is based on a hash of the virtual
* address of the futex. This should scale to a couple
* of CPUs.
*/
s = (arch_spinlock_t *)&lws_lock_start[_futex_hash_index(ua)];
_futex_spin_lock_irqsave(s, &flags);
if (unlikely(get_user(val, uaddr) != 0)) {
_futex_spin_unlock_irqrestore(s, &flags);
return -EFAULT;
}
if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) {
_futex_spin_unlock_irqrestore(s, &flags);
return -EFAULT;
}
*uval = val;
_futex_spin_unlock_irqrestore(s, &flags);
return 0;
}
#endif /*_ASM_PARISC_FUTEX_H*/
linux-7.2.3/arch/parisc/include/asm/grfioctl.h
+62
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Architecture specific parts of HP's STI (framebuffer) driver.
* Structures are HP-UX compatible for XFree86 usage.
*
* Linux/PA-RISC Project (http://www.parisc-linux.org/)
* Copyright (C) 2001 Helge Deller (deller a parisc-linux org)
*/
#ifndef __ASM_PARISC_GRFIOCTL_H
#define __ASM_PARISC_GRFIOCTL_H
/* upper 32 bits of graphics id (HP/UX identifier) */
#define GRFGATOR 8
#define S9000_ID_S300 9
#define GRFBOBCAT 9
#define GRFCATSEYE 9
#define S9000_ID_98720 10
#define GRFRBOX 10
#define S9000_ID_98550 11
#define GRFFIREEYE 11
#define S9000_ID_A1096A 12
#define GRFHYPERION 12
#define S9000_ID_FRI 13
#define S9000_ID_98730 14
#define GRFDAVINCI 14
#define S9000_ID_98705 0x26C08070 /* Tigershark */
#define S9000_ID_98736 0x26D148AB
#define S9000_ID_A1659A 0x26D1482A /* CRX 8 plane color (=ELK) */
#define S9000_ID_ELK S9000_ID_A1659A
#define S9000_ID_A1439A 0x26D148EE /* CRX24 = CRX+ (24-plane color) */
#define S9000_ID_A1924A 0x26D1488C /* GRX gray-scale */
#define S9000_ID_ELM S9000_ID_A1924A
#define S9000_ID_98765 0x27480DEF
#define S9000_ID_ELK_768 0x27482101
#define S9000_ID_STINGER 0x27A4A402
#define S9000_ID_TIMBER 0x27F12392 /* Bushmaster (710) Graphics */
#define S9000_ID_TOMCAT 0x27FCCB6D /* dual-headed ELK (Dual CRX) */
#define S9000_ID_ARTIST 0x2B4DED6D /* Artist (Gecko/712 & 715) onboard Graphics */
#define S9000_ID_HCRX 0x2BCB015A /* Hyperdrive/Hyperbowl (A4071A) Graphics */
#define CRX24_OVERLAY_PLANES 0x920825AA /* Overlay planes on CRX24 */
#define CRT_ID_ELK_1024 S9000_ID_ELK_768 /* Elk 1024x768 CRX */
#define CRT_ID_ELK_1280 S9000_ID_A1659A /* Elk 1280x1024 CRX */
#define CRT_ID_ELK_1024DB 0x27849CA5 /* Elk 1024x768 double buffer */
#define CRT_ID_ELK_GS S9000_ID_A1924A /* Elk 1280x1024 GreyScale */
#define CRT_ID_CRX24 S9000_ID_A1439A /* Piranha */
#define CRT_ID_VISUALIZE_EG 0x2D08C0A7 /* Graffiti, A4450A (built-in B132+/B160L) */
#define CRT_ID_THUNDER 0x2F23E5FC /* Thunder 1 VISUALIZE 48*/
#define CRT_ID_THUNDER2 0x2F8D570E /* Thunder 2 VISUALIZE 48 XP*/
#define CRT_ID_HCRX S9000_ID_HCRX /* Hyperdrive HCRX */
#define CRT_ID_CRX48Z S9000_ID_STINGER /* Stinger */
#define CRT_ID_DUAL_CRX S9000_ID_TOMCAT /* Tomcat */
#define CRT_ID_PVRX S9000_ID_98705 /* Tigershark */
#define CRT_ID_TIMBER S9000_ID_TIMBER /* Timber (710 builtin) */
#define CRT_ID_TVRX S9000_ID_98765 /* TVRX (gto/falcon) */
#define CRT_ID_ARTIST S9000_ID_ARTIST /* Artist */
#define CRT_ID_SUMMIT 0x2FC1066B /* Summit FX2, FX4, FX6 ... */
#define CRT_ID_LEGO 0x35ACDA30 /* Lego FX5, FX10 ... */
#define CRT_ID_PINNACLE 0x35ACDA16 /* Pinnacle FXe */
#endif /* __ASM_PARISC_GRFIOCTL_H */
linux-7.2.3/arch/parisc/include/asm/hardirq.h
+35
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/* SPDX-License-Identifier: GPL-2.0 */
/* hardirq.h: PA-RISC hard IRQ support.
*
* Copyright (C) 2001 Matthew Wilcox <matthew@wil.cx>
* Copyright (C) 2013 Helge Deller <deller@gmx.de>
*/
#ifndef _PARISC_HARDIRQ_H
#define _PARISC_HARDIRQ_H
#include <linux/cache.h>
#include <linux/threads.h>
#include <linux/irq.h>
typedef struct {
unsigned int __softirq_pending;
unsigned int kernel_stack_usage;
unsigned int irq_stack_usage;
#ifdef CONFIG_SMP
unsigned int irq_resched_count;
unsigned int irq_call_count;
#endif
unsigned int irq_unaligned_count;
unsigned int irq_fpassist_count;
unsigned int irq_tlb_count;
} ____cacheline_aligned irq_cpustat_t;
DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
#define __ARCH_IRQ_STAT
#define inc_irq_stat(member) this_cpu_inc(irq_stat.member)
#define __inc_irq_stat(member) __this_cpu_inc(irq_stat.member)
#define ack_bad_irq(irq) WARN(1, "unexpected IRQ trap at vector %02x\n", irq)
#endif /* _PARISC_HARDIRQ_H */
linux-7.2.3/arch/parisc/include/asm/hardware.h
+127
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_HARDWARE_H
#define _PARISC_HARDWARE_H
#include <linux/device-id/parisc.h>
#define HWTYPE_ANY_ID PA_HWTYPE_ANY_ID
#define HVERSION_ANY_ID PA_HVERSION_ANY_ID
#define HVERSION_REV_ANY_ID PA_HVERSION_REV_ANY_ID
#define SVERSION_ANY_ID PA_SVERSION_ANY_ID
struct hp_hardware {
unsigned int hw_type:8; /* HPHW_xxx */
unsigned int hversion:12;
unsigned int sversion:12;
unsigned char opt;
unsigned char name[59]; /* The hardware description */
} __packed;
struct parisc_device;
enum cpu_type {
pcx = 0, /* pa7000 pa 1.0 */
pcxs = 1, /* pa7000 pa 1.1a */
pcxt = 2, /* pa7100 pa 1.1b */
pcxt_ = 3, /* pa7200 (t') pa 1.1c */
pcxl = 4, /* pa7100lc pa 1.1d */
pcxl2 = 5, /* pa7300lc pa 1.1e */
pcxu = 6, /* pa8000 pa 2.0 */
pcxu_ = 7, /* pa8200 (u+) pa 2.0 */
pcxw = 8, /* pa8500 pa 2.0 */
pcxw_ = 9, /* pa8600 (w+) pa 2.0 */
pcxw2 = 10, /* pa8700 pa 2.0 */
mako = 11, /* pa8800 pa 2.0 */
mako2 = 12 /* pa8900 pa 2.0 */
};
extern const char * const cpu_name_version[][2]; /* mapping from enum cpu_type to strings */
struct parisc_driver;
struct io_module {
volatile uint32_t nothing; /* reg 0 */
volatile uint32_t io_eim;
volatile uint32_t io_dc_adata;
volatile uint32_t io_ii_cdata;
volatile uint32_t io_dma_link; /* reg 4 */
volatile uint32_t io_dma_command;
volatile uint32_t io_dma_address;
volatile uint32_t io_dma_count;
volatile uint32_t io_flex; /* reg 8 */
volatile uint32_t io_spa_address;
volatile uint32_t reserved1[2];
volatile uint32_t io_command; /* reg 12 */
volatile uint32_t io_status;
volatile uint32_t io_control;
volatile uint32_t io_data;
volatile uint32_t reserved2; /* reg 16 */
volatile uint32_t chain_addr;
volatile uint32_t sub_mask_clr;
volatile uint32_t reserved3[13];
volatile uint32_t undefined[480];
volatile uint32_t unpriv[512];
};
struct bc_module {
volatile uint32_t unused1[12];
volatile uint32_t io_command;
volatile uint32_t io_status;
volatile uint32_t io_control;
volatile uint32_t unused2[1];
volatile uint32_t io_err_resp;
volatile uint32_t io_err_info;
volatile uint32_t io_err_req;
volatile uint32_t unused3[11];
volatile uint32_t io_io_low;
volatile uint32_t io_io_high;
};
#define HPHW_NPROC 0
#define HPHW_MEMORY 1
#define HPHW_B_DMA 2
#define HPHW_OBSOLETE 3
#define HPHW_A_DMA 4
#define HPHW_A_DIRECT 5
#define HPHW_OTHER 6
#define HPHW_BCPORT 7
#define HPHW_CIO 8
#define HPHW_CONSOLE 9
#define HPHW_FIO 10
#define HPHW_BA 11
#define HPHW_IOA 12
#define HPHW_BRIDGE 13
#define HPHW_FABRIC 14
#define HPHW_MC 15
#define HPHW_FAULTY 31
/* hardware.c: */
extern const char *parisc_hardware_description(struct parisc_device_id *id);
extern enum cpu_type parisc_get_cpu_type(unsigned long hversion);
struct pci_dev;
struct hardware_path;
/* drivers.c: */
extern struct parisc_device *alloc_pa_dev(unsigned long hpa,
struct hardware_path *path);
extern int register_parisc_device(struct parisc_device *dev);
extern int register_parisc_driver(struct parisc_driver *driver);
extern int count_parisc_driver(struct parisc_driver *driver);
extern int unregister_parisc_driver(struct parisc_driver *driver);
extern void walk_central_bus(void);
extern const struct parisc_device *find_pa_parent_type(const struct parisc_device *, int);
extern void print_parisc_devices(void);
extern char *print_pa_hwpath(struct parisc_device *dev, char *path);
extern char *print_pci_hwpath(struct pci_dev *dev, char *path);
extern void get_pci_node_path(struct pci_dev *dev, struct hardware_path *path);
extern void init_parisc_bus(void);
extern struct device *hwpath_to_device(struct hardware_path *modpath);
extern void device_to_hwpath(struct device *dev, struct hardware_path *path);
extern int machine_has_merced_bus(void);
/* inventory.c: */
extern void do_memory_inventory(void);
extern void do_device_inventory(void);
#endif /* _PARISC_HARDWARE_H */
linux-7.2.3/arch/parisc/include/asm/hash.h
+147
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_HASH_H
#define _ASM_HASH_H
/*
* HP-PA only implements integer multiply in the FPU. However, for
* integer multiplies by constant, it has a number of shift-and-add
* (but no shift-and-subtract, sigh!) instructions that a compiler
* can synthesize a code sequence with.
*
* Unfortunately, GCC isn't very efficient at using them. For example
* it uses three instructions for "x *= 21" when only two are needed.
* But we can find a sequence manually.
*/
#define HAVE_ARCH__HASH_32 1
/*
* This is a multiply by GOLDEN_RATIO_32 = 0x61C88647 optimized for the
* PA7100 pairing rules. This is an in-order 2-way superscalar processor.
* Only one instruction in a pair may be a shift (by more than 3 bits),
* but other than that, simple ALU ops (including shift-and-add by up
* to 3 bits) may be paired arbitrarily.
*
* PA8xxx processors also dual-issue ALU instructions, although with
* fewer constraints, so this schedule is good for them, too.
*
* This 6-step sequence was found by Yevgen Voronenko's implementation
* of the Hcub algorithm at http://spiral.ece.cmu.edu/mcm/gen.html.
*/
static inline u32 __attribute_const__ __hash_32(u32 x)
{
u32 a, b, c;
/*
* Phase 1: Compute a = (x << 19) + x,
* b = (x << 9) + a, c = (x << 23) + b.
*/
a = x << 19; /* Two shifts can't be paired */
b = x << 9; a += x;
c = x << 23; b += a;
c += b;
/* Phase 2: Return (b<<11) + (c<<6) + (a<<3) - c */
b <<= 11;
a += c << 3; b -= c;
return (a << 3) + b;
}
#if BITS_PER_LONG == 64
#define HAVE_ARCH_HASH_64 1
/*
* Finding a good shift-and-add chain for GOLDEN_RATIO_64 is tricky,
* because available software for the purpose chokes on constants this
* large. (It's mostly designed for compiling FIR filter coefficients
* into FPGAs.)
*
* However, Jason Thong pointed out a work-around. The Hcub software
* (http://spiral.ece.cmu.edu/mcm/gen.html) is designed for *multiple*
* constant multiplication, and is good at finding shift-and-add chains
* which share common terms.
*
* Looking at 0x0x61C8864680B583EB in binary:
* 0110000111001000100001100100011010000000101101011000001111101011
* \______________/ \__________/ \_______/ \________/
* \____________________________/ \____________________/
* you can see the non-zero bits are divided into several well-separated
* blocks. Hcub can find algorithms for those terms separately, which
* can then be shifted and added together.
*
* Dividing the input into 2, 3 or 4 blocks, Hcub can find solutions
* with 10, 9 or 8 adds, respectively, making a total of 11 for the
* whole number.
*
* Using just two large blocks, 0xC3910C8D << 31 in the high bits,
* and 0xB583EB in the low bits, produces as good an algorithm as any,
* and with one more small shift than alternatives.
*
* The high bits are a larger number and more work to compute, as well
* as needing one extra cycle to shift left 31 bits before the final
* addition, so they are the critical path for scheduling. The low bits
* can fit into the scheduling slots left over.
*/
/*
* This _ASSIGN(dst, src) macro performs "dst = src", but prevents GCC
* from inferring anything about the value assigned to "dest".
*
* This prevents it from mis-optimizing certain sequences.
* In particular, gcc is annoyingly eager to combine consecutive shifts.
* Given "x <<= 19; y += x; z += x << 1;", GCC will turn this into
* "y += x << 19; z += x << 20;" even though the latter sequence needs
* an additional instruction and temporary register.
*
* Because no actual assembly code is generated, this construct is
* usefully portable across all GCC platforms, and so can be test-compiled
* on non-PA systems.
*
* In two places, additional unused input dependencies are added. This
* forces GCC's scheduling so it does not rearrange instructions too much.
* Because the PA-8xxx is out of order, I'm not sure how much this matters,
* but why make it more difficult for the processor than necessary?
*/
#define _ASSIGN(dst, src, ...) asm("" : "=r" (dst) : "0" (src), ##__VA_ARGS__)
/*
* Multiply by GOLDEN_RATIO_64 = 0x0x61C8864680B583EB using a heavily
* optimized shift-and-add sequence.
*
* Without the final shift, the multiply proper is 19 instructions,
* 10 cycles and uses only 4 temporaries. Whew!
*
* You are not expected to understand this.
*/
static __always_inline u32 __attribute_const__
hash_64(u64 a, unsigned int bits)
{
u64 b, c, d;
/*
* Encourage GCC to move a dynamic shift to %sar early,
* thereby freeing up an additional temporary register.
*/
if (!__builtin_constant_p(bits))
asm("" : "=q" (bits) : "0" (64 - bits));
else
bits = 64 - bits;
_ASSIGN(b, a*5); c = a << 13;
b = (b << 2) + a; _ASSIGN(d, a << 17);
a = b + (a << 1); c += d;
d = a << 10; _ASSIGN(a, a << 19);
d = a - d; _ASSIGN(a, a << 4, "X" (d));
c += b; a += b;
d -= c; c += a << 1;
a += c << 3; _ASSIGN(b, b << (7+31), "X" (c), "X" (d));
a <<= 31; b += d;
a += b;
return a >> bits;
}
#undef _ASSIGN /* We're a widely-used header file, so don't litter! */
#endif /* BITS_PER_LONG == 64 */
#endif /* _ASM_HASH_H */
linux-7.2.3/arch/parisc/include/asm/hugetlb.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC64_HUGETLB_H
#define _ASM_PARISC64_HUGETLB_H
#include <asm/page.h>
#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT
void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte, unsigned long sz);
#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long sz);
#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
static inline pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
return *ptep;
}
#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
void huge_ptep_set_wrprotect(struct mm_struct *mm,
unsigned long addr, pte_t *ptep);
#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep,
pte_t pte, int dirty);
#include <asm-generic/hugetlb.h>
#endif /* _ASM_PARISC64_HUGETLB_H */
linux-7.2.3/arch/parisc/include/asm/io.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_IO_H
#define _ASM_IO_H
#include <linux/types.h>
#include <linux/pgtable.h>
#define virt_to_phys(a) ((unsigned long)__pa(a))
#define phys_to_virt(a) __va(a)
static inline unsigned long isa_bus_to_virt(unsigned long addr) {
BUG();
return 0;
}
static inline unsigned long isa_virt_to_bus(void *addr) {
BUG();
return 0;
}
/*
* Memory mapped I/O
*
* readX()/writeX() do byteswapping and take an ioremapped address
* __raw_readX()/__raw_writeX() don't byteswap and take an ioremapped address.
* gsc_*() don't byteswap and operate on physical addresses;
* eg dev->hpa or 0xfee00000.
*/
static inline unsigned char gsc_readb(unsigned long addr)
{
long flags;
unsigned char ret;
__asm__ __volatile__(
" rsm %3,%0\n"
" ldbx 0(%2),%1\n"
" mtsm %0\n"
: "=&r" (flags), "=r" (ret) : "r" (addr), "i" (PSW_SM_D) );
return ret;
}
static inline unsigned short gsc_readw(unsigned long addr)
{
long flags;
unsigned short ret;
__asm__ __volatile__(
" rsm %3,%0\n"
" ldhx 0(%2),%1\n"
" mtsm %0\n"
: "=&r" (flags), "=r" (ret) : "r" (addr), "i" (PSW_SM_D) );
return ret;
}
static inline unsigned int gsc_readl(unsigned long addr)
{
u32 ret;
__asm__ __volatile__(
" ldwax 0(%1),%0\n"
: "=r" (ret) : "r" (addr) );
return ret;
}
static inline unsigned long long gsc_readq(unsigned long addr)
{
unsigned long long ret;
#ifdef CONFIG_64BIT
__asm__ __volatile__(
" ldda 0(%1),%0\n"
: "=r" (ret) : "r" (addr) );
#else
/* two reads may have side effects.. */
ret = ((u64) gsc_readl(addr)) << 32;
ret |= gsc_readl(addr+4);
#endif
return ret;
}
static inline void gsc_writeb(unsigned char val, unsigned long addr)
{
long flags;
__asm__ __volatile__(
" rsm %3,%0\n"
" stbs %1,0(%2)\n"
" mtsm %0\n"
: "=&r" (flags) : "r" (val), "r" (addr), "i" (PSW_SM_D) );
}
static inline void gsc_writew(unsigned short val, unsigned long addr)
{
long flags;
__asm__ __volatile__(
" rsm %3,%0\n"
" sths %1,0(%2)\n"
" mtsm %0\n"
: "=&r" (flags) : "r" (val), "r" (addr), "i" (PSW_SM_D) );
}
static inline void gsc_writel(unsigned int val, unsigned long addr)
{
__asm__ __volatile__(
" stwas %0,0(%1)\n"
: : "r" (val), "r" (addr) );
}
static inline void gsc_writeq(unsigned long long val, unsigned long addr)
{
#ifdef CONFIG_64BIT
__asm__ __volatile__(
" stda %0,0(%1)\n"
: : "r" (val), "r" (addr) );
#else
/* two writes may have side effects.. */
gsc_writel(val >> 32, addr);
gsc_writel(val, addr+4);
#endif
}
/*
* The standard PCI ioremap interfaces
*/
#define ioremap_prot ioremap_prot
#define _PAGE_IOREMAP (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
_PAGE_ACCESSED | _PAGE_NO_CACHE)
#define ioremap_wc(addr, size) \
ioremap_prot((addr), (size), __pgprot(_PAGE_IOREMAP))
#define pci_iounmap pci_iounmap
/* Port-space IO */
#define inb_p inb
#define inw_p inw
#define inl_p inl
#define outb_p outb
#define outw_p outw
#define outl_p outl
extern unsigned char eisa_in8(unsigned short port);
extern unsigned short eisa_in16(unsigned short port);
extern unsigned int eisa_in32(unsigned short port);
extern void eisa_out8(unsigned char data, unsigned short port);
extern void eisa_out16(unsigned short data, unsigned short port);
extern void eisa_out32(unsigned int data, unsigned short port);
#if defined(CONFIG_PCI)
extern unsigned char inb(int addr);
extern unsigned short inw(int addr);
extern unsigned int inl(int addr);
extern void outb(unsigned char b, int addr);
extern void outw(unsigned short b, int addr);
extern void outl(unsigned int b, int addr);
#define inb inb
#define inw inw
#define inl inl
#define outb outb
#define outw outw
#define outl outl
#elif defined(CONFIG_EISA)
#define inb eisa_in8
#define inw eisa_in16
#define inl eisa_in32
#define outb eisa_out8
#define outw eisa_out16
#define outl eisa_out32
#else
static inline char inb(unsigned long addr)
{
BUG();
return -1;
}
static inline short inw(unsigned long addr)
{
BUG();
return -1;
}
static inline int inl(unsigned long addr)
{
BUG();
return -1;
}
#define inb inb
#define inw inw
#define inl inl
#define outb(x, y) ({(void)(x); (void)(y); BUG(); 0;})
#define outw(x, y) ({(void)(x); (void)(y); BUG(); 0;})
#define outl(x, y) ({(void)(x); (void)(y); BUG(); 0;})
#endif
/*
* String versions of in/out ops:
*/
extern void insb (unsigned long port, void *dst, unsigned long count);
extern void insw (unsigned long port, void *dst, unsigned long count);
extern void insl (unsigned long port, void *dst, unsigned long count);
extern void outsb (unsigned long port, const void *src, unsigned long count);
extern void outsw (unsigned long port, const void *src, unsigned long count);
extern void outsl (unsigned long port, const void *src, unsigned long count);
#define insb insb
#define insw insw
#define insl insl
#define outsb outsb
#define outsw outsw
#define outsl outsl
/* IO Port space is : BBiiii where BB is HBA number. */
#define IO_SPACE_LIMIT 0x00ffffff
/* PA machines have an MM I/O space from 0xf0000000-0xffffffff in 32
* bit mode and from 0xfffffffff0000000-0xfffffffffffffff in 64 bit
* mode (essentially just sign extending. This macro takes in a 32
* bit I/O address (still with the leading f) and outputs the correct
* value for either 32 or 64 bit mode */
#define F_EXTEND(x) ((unsigned long)((x) | (0xffffffff00000000ULL)))
#ifdef CONFIG_64BIT
extern u64 ioread64(const void __iomem *addr);
extern u64 ioread64be(const void __iomem *addr);
#define ioread64 ioread64
#define ioread64be ioread64be
extern void iowrite64(u64 val, void __iomem *addr);
extern void iowrite64be(u64 val, void __iomem *addr);
#define iowrite64 iowrite64
#define iowrite64be iowrite64be
#endif
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *);
#define ioport_map ioport_map
#define ioport_unmap ioport_unmap
extern unsigned int ioread8(const void __iomem *);
extern unsigned int ioread16(const void __iomem *);
extern unsigned int ioread16be(const void __iomem *);
extern unsigned int ioread32(const void __iomem *);
extern unsigned int ioread32be(const void __iomem *);
#define ioread8 ioread8
#define ioread16 ioread16
#define ioread32 ioread32
#define ioread16be ioread16be
#define ioread32be ioread32be
extern void iowrite8(u8, void __iomem *);
extern void iowrite16(u16, void __iomem *);
extern void iowrite16be(u16, void __iomem *);
extern void iowrite32(u32, void __iomem *);
extern void iowrite32be(u32, void __iomem *);
#define iowrite8 iowrite8
#define iowrite16 iowrite16
#define iowrite32 iowrite32
#define iowrite16be iowrite16be
#define iowrite32be iowrite32be
extern void ioread8_rep(const void __iomem *port, void *buf, unsigned long count);
extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long count);
extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count);
#define ioread8_rep ioread8_rep
#define ioread16_rep ioread16_rep
#define ioread32_rep ioread32_rep
extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
#define iowrite8_rep iowrite8_rep
#define iowrite16_rep iowrite16_rep
#define iowrite32_rep iowrite32_rep
extern int devmem_is_allowed(unsigned long pfn);
#include <asm-generic/io.h>
#endif
linux-7.2.3/arch/parisc/include/asm/irq.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* include/asm-parisc/irq.h
*
* Copyright 2005 Matthew Wilcox <matthew@wil.cx>
*/
#ifndef _ASM_PARISC_IRQ_H
#define _ASM_PARISC_IRQ_H
#include <linux/cpumask.h>
#include <asm/types.h>
#define NO_IRQ (-1)
#ifdef CONFIG_GSC
#define GSC_IRQ_BASE 16
#define GSC_IRQ_MAX 63
#define CPU_IRQ_BASE 64
#else
#define CPU_IRQ_BASE 16
#endif
#define TIMER_IRQ (CPU_IRQ_BASE + 0)
#define IPI_IRQ (CPU_IRQ_BASE + 1)
#define CPU_IRQ_MAX (CPU_IRQ_BASE + (BITS_PER_LONG - 1))
#define NR_IRQS (CPU_IRQ_MAX + 1)
static __inline__ int irq_canonicalize(int irq)
{
return (irq == 2) ? 9 : irq;
}
struct irq_chip;
struct irq_data;
void cpu_ack_irq(struct irq_data *d);
void cpu_eoi_irq(struct irq_data *d);
extern int txn_alloc_irq(unsigned int nbits);
extern int txn_claim_irq(int);
extern unsigned int txn_alloc_data(unsigned int);
extern unsigned long txn_alloc_addr(unsigned int);
extern unsigned long txn_affinity_addr(unsigned int irq, int cpu);
extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *);
extern int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest);
#endif /* _ASM_PARISC_IRQ_H */
linux-7.2.3/arch/parisc/include/asm/irqflags.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PARISC_IRQFLAGS_H
#define __PARISC_IRQFLAGS_H
#include <linux/types.h>
#include <asm/psw.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("ssm 0, %0" : "=r" (flags) : : "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
asm volatile("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory");
}
static inline void arch_local_irq_enable(void)
{
asm volatile("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory");
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
asm volatile("rsm %1,%0" : "=r" (flags) : "i" (PSW_I) : "memory");
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
/* warn if IRQs are on although they should be off */
if (IS_ENABLED(CONFIG_LIGHTWEIGHT_SPINLOCK_CHECK))
if (arch_local_save_flags() & PSW_I)
asm volatile("break 6,6\n"); /* SPINLOCK_BREAK_INSN */
asm volatile("mtsm %0" : : "r" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & PSW_I) == 0;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* __PARISC_IRQFLAGS_H */
linux-7.2.3/arch/parisc/include/asm/jump_label.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_JUMP_LABEL_H
#define _ASM_PARISC_JUMP_LABEL_H
#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <linux/stringify.h>
#include <asm/assembly.h>
#define JUMP_LABEL_NOP_SIZE 4
static __always_inline bool arch_static_branch(struct static_key *key, bool branch)
{
asm goto("1:\n\t"
"nop\n\t"
".pushsection __jump_table, \"aw\"\n\t"
".align %1\n\t"
".word 1b - ., %l[l_yes] - .\n\t"
__stringify(ASM_ULONG_INSN) " %c0 - .\n\t"
".popsection\n\t"
: : "i" (&((char *)key)[branch]), "i" (sizeof(long))
: : l_yes);
return false;
l_yes:
return true;
}
static __always_inline bool arch_static_branch_jump(struct static_key *key, bool branch)
{
asm goto("1:\n\t"
"b,n %l[l_yes]\n\t"
".pushsection __jump_table, \"aw\"\n\t"
".align %1\n\t"
".word 1b - ., %l[l_yes] - .\n\t"
__stringify(ASM_ULONG_INSN) " %c0 - .\n\t"
".popsection\n\t"
: : "i" (&((char *)key)[branch]), "i" (sizeof(long))
: : l_yes);
return false;
l_yes:
return true;
}
#endif /* __ASSEMBLER__ */
#endif
linux-7.2.3/arch/parisc/include/asm/kbdleds.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_KBDLEDS_H
#define _ASM_PARISC_KBDLEDS_H
/*
* On HIL keyboards of PARISC machines there is no NumLock key and
* everyone expects the keypad to be used for numbers. That's why
* we can safely turn on the NUMLOCK bit.
*/
static inline int kbd_defleds(void)
{
#if defined(CONFIG_KEYBOARD_HIL) || defined(CONFIG_KEYBOARD_HIL_OLD)
return 1 << VC_NUMLOCK;
#else
return 0;
#endif
}
#endif /* _ASM_PARISC_KBDLEDS_H */
linux-7.2.3/arch/parisc/include/asm/kexec.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_KEXEC_H
#define _ASM_PARISC_KEXEC_H
/* Maximum physical address we can use pages from */
#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
/* Maximum address we can reach in physical address mode */
#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
/* Maximum address we can use for the control code buffer */
#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
#define KEXEC_CONTROL_PAGE_SIZE 4096
#define KEXEC_ARCH KEXEC_ARCH_PARISC
#define ARCH_HAS_KIMAGE_ARCH
#ifndef __ASSEMBLER__
struct kimage_arch {
unsigned long initrd_start;
unsigned long initrd_end;
unsigned long cmdline;
};
static inline void crash_setup_regs(struct pt_regs *newregs,
struct pt_regs *oldregs)
{
/* Dummy implementation for now */
}
#endif /* __ASSEMBLER__ */
#endif /* _ASM_PARISC_KEXEC_H */
linux-7.2.3/arch/parisc/include/asm/kfence.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* PA-RISC KFENCE support.
*
* Copyright (C) 2021, Helge Deller <deller@gmx.de>
*/
#ifndef _ASM_PARISC_KFENCE_H
#define _ASM_PARISC_KFENCE_H
#include <linux/kfence.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
static inline bool arch_kfence_init_pool(void)
{
return true;
}
/* Protect the given page and flush TLB. */
static inline bool kfence_protect_page(unsigned long addr, bool protect)
{
pte_t *pte = virt_to_kpte(addr);
if (WARN_ON(!pte))
return false;
/*
* We need to avoid IPIs, as we may get KFENCE allocations or faults
* with interrupts disabled.
*/
if (protect)
set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT));
else
set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT));
flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
return true;
}
#endif /* _ASM_PARISC_KFENCE_H */
linux-7.2.3/arch/parisc/include/asm/kgdb.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* PA-RISC KGDB support
*
* Copyright (c) 2019 Sven Schnelle <svens@stackframe.org>
*
*/
#ifndef __PARISC_KGDB_H__
#define __PARISC_KGDB_H__
#define BREAK_INSTR_SIZE 4
#define PARISC_KGDB_COMPILED_BREAK_INSN 0x3ffc01f
#define PARISC_KGDB_BREAK_INSN 0x3ffa01f
#define NUMREGBYTES sizeof(struct parisc_gdb_regs)
#define BUFMAX 4096
#define KGDB_MAX_BREAKPOINTS 40
#define CACHE_FLUSH_IS_SAFE 1
#ifndef __ASSEMBLER__
static inline void arch_kgdb_breakpoint(void)
{
asm(".word %0" : : "i"(PARISC_KGDB_COMPILED_BREAK_INSN) : "memory");
}
struct parisc_gdb_regs {
unsigned long gpr[32];
unsigned long sar;
unsigned long iaoq_f;
unsigned long iasq_f;
unsigned long iaoq_b;
unsigned long iasq_b;
unsigned long eiem;
unsigned long iir;
unsigned long isr;
unsigned long ior;
unsigned long ipsw;
unsigned long __unused0;
unsigned long sr4;
unsigned long sr0;
unsigned long sr1;
unsigned long sr2;
unsigned long sr3;
unsigned long sr5;
unsigned long sr6;
unsigned long sr7;
unsigned long cr0;
unsigned long pid1;
unsigned long pid2;
unsigned long scrccr;
unsigned long pid3;
unsigned long pid4;
unsigned long cr24;
unsigned long cr25;
unsigned long cr26;
unsigned long cr27;
unsigned long cr28;
unsigned long cr29;
unsigned long cr30;
u64 fr[32];
};
#endif
#endif
linux-7.2.3/arch/parisc/include/asm/kprobes.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/parisc/include/asm/kprobes.h
*
* PA-RISC kprobes implementation
*
* Copyright (c) 2019 Sven Schnelle <svens@stackframe.org>
*/
#ifndef _PARISC_KPROBES_H
#define _PARISC_KPROBES_H
#include <asm-generic/kprobes.h>
#ifdef CONFIG_KPROBES
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/notifier.h>
#define PARISC_KPROBES_BREAK_INSN 0x3ff801f
#define PARISC_KPROBES_BREAK_INSN2 0x3ff801e
#define __ARCH_WANT_KPROBES_INSN_SLOT
#define MAX_INSN_SIZE 2
typedef u32 kprobe_opcode_t;
struct kprobe;
void arch_remove_kprobe(struct kprobe *p);
#define flush_insn_slot(p) \
flush_icache_range((unsigned long)&(p)->ainsn.insn[0], \
(unsigned long)&(p)->ainsn.insn[0] + \
MAX_INSN_SIZE*sizeof(kprobe_opcode_t))
#define kretprobe_blacklist_size 0
struct arch_specific_insn {
kprobe_opcode_t *insn;
};
struct prev_kprobe {
struct kprobe *kp;
unsigned long status;
};
struct kprobe_ctlblk {
unsigned int kprobe_status;
struct prev_kprobe prev_kprobe;
unsigned long iaoq[2];
};
int __kprobes parisc_kprobe_break_handler(struct pt_regs *regs);
int __kprobes parisc_kprobe_ss_handler(struct pt_regs *regs);
static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
{
return 0;
}
#endif /* CONFIG_KPROBES */
#endif /* _PARISC_KPROBES_H */
linux-7.2.3/arch/parisc/include/asm/ldcw.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PARISC_LDCW_H
#define __PARISC_LDCW_H
/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
and GCC only guarantees 8-byte alignment for stack locals, we can't
be assured of 16-byte alignment for atomic lock data even if we
specify "__attribute ((aligned(16)))" in the type declaration. So,
we use a struct containing an array of four ints for the atomic lock
type and dynamically select the 16-byte aligned int from the array
for the semaphore. */
/* From: "Jim Hull" <jim.hull of hp.com>
I've attached a summary of the change, but basically, for PA 2.0, as
long as the ",CO" (coherent operation) completer is implemented, then the
16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
they only require "natural" alignment (4-byte for ldcw, 8-byte for
ldcd).
Although the cache control hint is accepted by all PA 2.0 processors,
it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still
require 16-byte alignment. If the address is unaligned, the operation
of the instruction is undefined. The ldcw instruction does not generate
unaligned data reference traps so misaligned accesses are not detected.
This hid the problem for years. So, restore the 16-byte alignment dropped
by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */
#define __PA_LDCW_ALIGNMENT 16
#define __ldcw_align(a) ({ \
unsigned long __ret = (unsigned long) &(a)->lock[0]; \
__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
& ~(__PA_LDCW_ALIGNMENT - 1); \
(volatile unsigned int *) __ret; \
})
#ifdef CONFIG_PA20
#define __LDCW "ldcw,co"
#else
#define __LDCW "ldcw"
#endif
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
We don't explicitly expose that "*a" may be written as reload
fails to find a register in class R1_REGS when "a" needs to be
reloaded when generating 64-bit PIC code. Instead, we clobber
memory to indicate to the compiler that the assembly code reads
or writes to items other than those listed in the input and output
operands. This may pessimize the code somewhat but __ldcw is
usually used within code blocks surrounded by memory barriers. */
#define __ldcw(a) ({ \
unsigned __ret; \
__asm__ __volatile__(__LDCW " 0(%1),%0" \
: "=r" (__ret) : "r" (a) : "memory"); \
__ret; \
})
#ifdef CONFIG_SMP
# define __lock_aligned __section(".data..lock_aligned") __aligned(16)
#endif
#endif /* __PARISC_LDCW_H */
linux-7.2.3/arch/parisc/include/asm/led.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef LED_H
#define LED_H
#define LED7 0x80 /* top (or furthest right) LED */
#define LED6 0x40
#define LED5 0x20
#define LED4 0x10
#define LED3 0x08
#define LED2 0x04
#define LED1 0x02
#define LED0 0x01 /* bottom (or furthest left) LED */
#define LED_LAN_RCV LED0 /* for LAN receive activity */
#define LED_LAN_TX LED1 /* for LAN transmit activity */
#define LED_DISK_IO LED2 /* for disk activity */
#define LED_HEARTBEAT LED3 /* heartbeat */
/* values for pdc_chassis_lcd_info_ret_block.model: */
#define DISPLAY_MODEL_LCD 0 /* KittyHawk LED or LCD */
#define DISPLAY_MODEL_NONE 1 /* no LED or LCD */
#define DISPLAY_MODEL_LASI 2 /* LASI style 8 bit LED */
#define DISPLAY_MODEL_OLD_ASP 0x7F /* faked: ASP style 8 x 1 bit LED (only very old ASP versions) */
#define LED_CMD_REG_NONE 0 /* NULL == no addr for the cmd register */
/* register_led_driver() */
int register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg);
#ifdef CONFIG_CHASSIS_LCD_LED
/* writes a string to the LCD display (if possible on this h/w) */
void lcd_print(const char *str);
#else
#define lcd_print(str) do { } while (0)
#endif
#endif /* LED_H */
linux-7.2.3/arch/parisc/include/asm/linkage.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_LINKAGE_H
#define __ASM_PARISC_LINKAGE_H
#include <asm/dwarf.h>
#ifndef __ALIGN
#define __ALIGN .align 4
#define __ALIGN_STR ".align 4"
#endif
/*
* In parisc assembly a semicolon marks a comment while a
* exclamation mark is used to separate independent lines.
*/
#define ASM_NL !
#ifdef __ASSEMBLER__
#define ENTRY(name) \
ALIGN !\
name: ASM_NL\
.export name
#define ENTRY_CFI(name, ...) \
ENTRY(name) ASM_NL\
.proc ASM_NL\
.callinfo __VA_ARGS__ ASM_NL\
.entry ASM_NL\
CFI_STARTPROC
#define ENDPROC_CFI(name) \
CFI_ENDPROC ASM_NL\
.exit ASM_NL\
.procend ASM_NL\
ENDPROC(name)
#endif /* __ASSEMBLER__ */
#endif /* __ASM_PARISC_LINKAGE_H */
linux-7.2.3/arch/parisc/include/asm/mman.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MMAN_H__
#define __ASM_MMAN_H__
#include <linux/fs.h>
#include <uapi/asm/mman.h>
/* PARISC cannot allow mdwe as it needs writable stacks */
static inline bool arch_memory_deny_write_exec_supported(void)
{
return false;
}
#define arch_memory_deny_write_exec_supported arch_memory_deny_write_exec_supported
static inline unsigned long arch_calc_vm_flag_bits(struct file *file, unsigned long flags)
{
/*
* The stack on parisc grows upwards, so if userspace requests memory
* for a stack, mark it with VM_GROWSUP so that the stack expansion in
* the fault handler will work.
*/
if (flags & MAP_STACK)
return VM_GROWSUP;
return 0;
}
#define arch_calc_vm_flag_bits(file, flags) arch_calc_vm_flag_bits(file, flags)
#endif /* __ASM_MMAN_H__ */
linux-7.2.3/arch/parisc/include/asm/mmu.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_MMU_H_
#define _PARISC_MMU_H_
typedef struct {
unsigned long space_id;
unsigned long vdso_base;
} mm_context_t;
#endif /* _PARISC_MMU_H_ */
linux-7.2.3/arch/parisc/include/asm/mmu_context.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PARISC_MMU_CONTEXT_H
#define __PARISC_MMU_CONTEXT_H
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/atomic.h>
#include <linux/spinlock.h>
#include <asm-generic/mm_hooks.h>
/* on PA-RISC, we actually have enough contexts to justify an allocator
* for them. prumpf */
extern unsigned long alloc_sid(void);
extern void free_sid(unsigned long);
#define init_new_context init_new_context
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
BUG_ON(atomic_read(&mm->mm_users) != 1);
mm->context.space_id = alloc_sid();
return 0;
}
#define destroy_context destroy_context
static inline void
destroy_context(struct mm_struct *mm)
{
free_sid(mm->context.space_id);
mm->context.space_id = 0;
}
static inline unsigned long __space_to_prot(mm_context_t context)
{
#if SPACEID_SHIFT == 0
return context.space_id << 1;
#else
return context.space_id >> (SPACEID_SHIFT - 1);
#endif
}
static inline void load_context(mm_context_t context)
{
mtsp(context.space_id, SR_USER);
mtctl(__space_to_prot(context), 8);
}
static inline void switch_mm_irqs_off(struct mm_struct *prev,
struct mm_struct *next, struct task_struct *tsk)
{
if (prev != next) {
#ifdef CONFIG_TLB_PTLOCK
/* put physical address of page_table_lock in cr28 (tr4)
for TLB faults */
spinlock_t *pgd_lock = &next->page_table_lock;
mtctl(__pa(__ldcw_align(&pgd_lock->rlock.raw_lock)), 28);
#endif
mtctl(__pa(next->pgd), 25);
load_context(next->context);
}
}
static inline void switch_mm(struct mm_struct *prev,
struct mm_struct *next, struct task_struct *tsk)
{
unsigned long flags;
if (prev == next)
return;
local_irq_save(flags);
switch_mm_irqs_off(prev, next, tsk);
local_irq_restore(flags);
}
#define switch_mm_irqs_off switch_mm_irqs_off
#define activate_mm activate_mm
static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
/*
* Activate_mm is our one chance to allocate a space id
* for a new mm created in the exec path. There's also
* some lazy tlb stuff, which is currently dead code, but
* we only allocate a space id if one hasn't been allocated
* already, so we should be OK.
*/
BUG_ON(next == &init_mm); /* Should never happen */
if (next->context.space_id == 0)
next->context.space_id = alloc_sid();
switch_mm(prev,next,current);
}
#include <asm-generic/mmu_context.h>
#endif
linux-7.2.3/arch/parisc/include/asm/mmzone.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_MMZONE_H
#define _PARISC_MMZONE_H
#define MAX_PHYSMEM_RANGES 4 /* Fix the size for now (current known max is 3) */
#endif /* _PARISC_MMZONE_H */
linux-7.2.3/arch/parisc/include/asm/module.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_MODULE_H
#define _ASM_PARISC_MODULE_H
#include <asm-generic/module.h>
/*
* This file contains the parisc architecture specific module code.
*/
struct unwind_table;
struct mod_arch_specific
{
unsigned long got_offset, got_count, got_max;
unsigned long fdesc_offset, fdesc_count, fdesc_max;
struct {
unsigned long stub_offset;
unsigned int stub_entries;
} *section;
int unwind_section;
struct unwind_table *unwind;
};
#endif /* _ASM_PARISC_MODULE_H */
linux-7.2.3/arch/parisc/include/asm/page.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_PAGE_H
#define _PARISC_PAGE_H
#include <linux/const.h>
#include <vdso/page.h>
#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
#ifndef __ASSEMBLER__
#include <asm/types.h>
#include <asm/cache.h>
#define clear_page(page) clear_page_asm((void *)(page))
#define copy_page(to, from) copy_page_asm((void *)(to), (void *)(from))
struct page;
struct vm_area_struct;
void clear_page_asm(void *page);
void copy_page_asm(void *to, void *from);
void copy_user_highpage(struct page *to, struct page *from, unsigned long vaddr,
struct vm_area_struct *vma);
#define __HAVE_ARCH_COPY_USER_HIGHPAGE
/*
* These are used to make use of C type-checking..
*/
#define STRICT_MM_TYPECHECKS
#ifdef STRICT_MM_TYPECHECKS
typedef struct { unsigned long pte; } pte_t; /* either 32 or 64bit */
/* NOTE: even on 64 bits, these entries are __u32 because we allocate
* the pmd and pgd in ZONE_DMA (i.e. under 4GB) */
typedef struct { __u32 pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
#if CONFIG_PGTABLE_LEVELS == 3
typedef struct { __u32 pmd; } pmd_t;
#define __pmd(x) ((pmd_t) { (x) } )
/* pXd_val() do not work as lvalues, so make sure we don't use them as such. */
#define pmd_val(x) ((x).pmd + 0)
#endif
#define pte_val(x) ((x).pte)
#define pgd_val(x) ((x).pgd + 0)
#define pgprot_val(x) ((x).pgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
#else
/*
* .. while these make it easier on the compiler
*/
typedef unsigned long pte_t;
#if CONFIG_PGTABLE_LEVELS == 3
typedef __u32 pmd_t;
#define pmd_val(x) (x)
#define __pmd(x) (x)
#endif
typedef __u32 pgd_t;
typedef unsigned long pgprot_t;
#define pte_val(x) (x)
#define pgd_val(x) (x)
#define pgprot_val(x) (x)
#define __pte(x) (x)
#define __pgd(x) (x)
#define __pgprot(x) (x)
#endif /* STRICT_MM_TYPECHECKS */
#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
#if CONFIG_PGTABLE_LEVELS == 3
#define set_pud(pudptr, pudval) (*(pudptr) = (pudval))
#endif
typedef struct page *pgtable_t;
typedef struct __physmem_range {
unsigned long start_pfn;
unsigned long pages; /* PAGE_SIZE pages */
} physmem_range_t;
extern physmem_range_t pmem_ranges[];
extern int npmem_ranges;
#endif /* !__ASSEMBLER__ */
/* WARNING: The definitions below must match exactly to sizeof(pte_t)
* etc
*/
#ifdef CONFIG_64BIT
#define BITS_PER_PTE_ENTRY 3
#define BITS_PER_PMD_ENTRY 2
#define BITS_PER_PGD_ENTRY 2
#else
#define BITS_PER_PTE_ENTRY 2
#define BITS_PER_PMD_ENTRY 2
#define BITS_PER_PGD_ENTRY 2
#endif
#define PGD_ENTRY_SIZE (1UL << BITS_PER_PGD_ENTRY)
#define PMD_ENTRY_SIZE (1UL << BITS_PER_PMD_ENTRY)
#define PTE_ENTRY_SIZE (1UL << BITS_PER_PTE_ENTRY)
#define LINUX_GATEWAY_SPACE 0
/* This governs the relationship between virtual and physical addresses.
* If you alter it, make sure to take care of our various fixed mapping
* segments in fixmap.h */
#ifdef CONFIG_64BIT
#define __PAGE_OFFSET_DEFAULT (0x40000000) /* 1GB */
#else
#define __PAGE_OFFSET_DEFAULT (0x10000000) /* 256MB */
#endif
#if defined(BOOTLOADER)
#define __PAGE_OFFSET (0) /* bootloader uses physical addresses */
#else
#define __PAGE_OFFSET __PAGE_OFFSET_DEFAULT
#endif /* BOOTLOADER */
#define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET)
/* The size of the gateway page (we leave lots of room for expansion) */
#define GATEWAY_PAGE_SIZE 0x4000
/* The start of the actual kernel binary---used in vmlinux.lds.S
* Leave some space after __PAGE_OFFSET for detecting kernel null
* ptr derefs */
#define KERNEL_BINARY_TEXT_START (__PAGE_OFFSET + 0x100000)
/* These macros don't work for 64-bit C code -- don't allow in C at all */
#ifdef __ASSEMBLER__
# define PA(x) ((x)-__PAGE_OFFSET)
# define VA(x) ((x)+__PAGE_OFFSET)
#endif
#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
#ifdef CONFIG_HUGETLB_PAGE
#define HPAGE_SHIFT PMD_SHIFT /* fixed for transparent huge pages */
#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
# define REAL_HPAGE_SHIFT 20 /* 20 = 1MB */
# define _HUGE_PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_1M
#elif !defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
# define REAL_HPAGE_SHIFT 22 /* 22 = 4MB */
# define _HUGE_PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4M
#else
# define REAL_HPAGE_SHIFT 24 /* 24 = 16MB */
# define _HUGE_PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16M
#endif
#endif /* CONFIG_HUGETLB_PAGE */
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>
#include <asm/pdc.h>
#define PAGE0 ((struct zeropage *)absolute_pointer(__PAGE_OFFSET))
/* DEFINITION OF THE ZERO-PAGE (PAG0) */
/* based on work by Jason Eckhardt (jason@equator.com) */
#endif /* _PARISC_PAGE_H */
linux-7.2.3/arch/parisc/include/asm/parisc-device.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_PARISC_DEVICE_H_
#define _ASM_PARISC_PARISC_DEVICE_H_
#include <linux/device.h>
#include <linux/device-id/parisc.h>
struct parisc_device {
struct resource hpa; /* Hard Physical Address */
struct parisc_device_id id;
struct parisc_driver *driver; /* Driver for this device */
char name[80]; /* The hardware description */
int irq;
int aux_irq; /* Some devices have a second IRQ */
char hw_path; /* The module number on this bus */
unsigned int num_addrs; /* some devices have additional address ranges. */
unsigned long *addr; /* which will be stored here */
#ifdef CONFIG_64BIT
/* parms for pdc_pat_cell_module() call */
unsigned long pcell_loc; /* Physical Cell location */
unsigned long mod_index; /* PAT specific - Misc Module info */
/* generic info returned from pdc_pat_cell_module() */
unsigned long mod_info; /* PAT specific - Misc Module info */
unsigned long pmod_loc; /* physical Module location */
unsigned long mod0;
#endif
u64 dma_mask; /* DMA mask for I/O */
struct device dev;
};
struct parisc_driver {
struct parisc_driver *next;
char *name;
const struct parisc_device_id *id_table;
int (*probe)(struct parisc_device *dev); /* New device discovered */
void (*remove)(struct parisc_device *dev);
struct device_driver drv;
};
#define to_parisc_device(d) container_of(d, struct parisc_device, dev)
#define to_parisc_driver(d) container_of_const(d, struct parisc_driver, drv)
#define parisc_parent(d) to_parisc_device(d->dev.parent)
static inline const char *parisc_pathname(struct parisc_device *d)
{
return dev_name(&d->dev);
}
static inline void
parisc_set_drvdata(struct parisc_device *d, void *p)
{
dev_set_drvdata(&d->dev, p);
}
static inline void *
parisc_get_drvdata(struct parisc_device *d)
{
return dev_get_drvdata(&d->dev);
}
extern const struct bus_type parisc_bus_type;
int iosapic_serial_irq(struct parisc_device *dev);
#endif /*_ASM_PARISC_PARISC_DEVICE_H_*/
linux-7.2.3/arch/parisc/include/asm/parport.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
*
* parport.h: ia32-compatible parport initialisation
*
* This file should only be included by drivers/parport/parport_pc.c.
*/
#ifndef _ASM_PARPORT_H
#define _ASM_PARPORT_H 1
static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
{
/* nothing ! */
return 0;
}
#endif /* !(_ASM_PARPORT_H) */
linux-7.2.3/arch/parisc/include/asm/pci.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_PCI_H
#define __ASM_PARISC_PCI_H
#include <linux/scatterlist.h>
/*
** HP PCI platforms generally support multiple bus adapters.
** (workstations 1-~4, servers 2-~32)
**
** Newer platforms number the busses across PCI bus adapters *sparsely*.
** E.g. 0, 8, 16, ...
**
** Under a PCI bus, most HP platforms support PPBs up to two or three
** levels deep. See "Bit3" product line.
*/
#define PCI_MAX_BUSSES 256
/* To be used as: mdelay(pci_post_reset_delay);
*
* post_reset is the time the kernel should stall to prevent anyone from
* accessing the PCI bus once #RESET is de-asserted.
* PCI spec somewhere says 1 second but with multi-PCI bus systems,
* this makes the boot time much longer than necessary.
* 20ms seems to work for all the HP PCI implementations to date.
*/
#define pci_post_reset_delay 50
/*
** pci_hba_data (aka H2P_OBJECT in HP/UX)
**
** This is the "common" or "base" data structure which HBA drivers
** (eg Dino or LBA) are required to place at the top of their own
** platform_data structure. I've heard this called "C inheritance" too.
**
** Data needed by pcibios layer belongs here.
*/
struct pci_hba_data {
void __iomem *base_addr; /* aka Host Physical Address */
const struct parisc_device *dev; /* device from PA bus walk */
struct pci_bus *hba_bus; /* primary PCI bus below HBA */
int hba_num; /* I/O port space access "key" */
struct resource bus_num; /* PCI bus numbers */
struct resource io_space; /* PIOP */
struct resource lmmio_space; /* bus addresses < 4Gb */
struct resource elmmio_space; /* additional bus addresses < 4Gb */
struct resource gmmio_space; /* bus addresses > 4Gb */
/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
* elmmio_space and gmmio_space as a contiguous array of
* resources. This #define represents the array size */
#define DINO_MAX_LMMIO_RESOURCES 3
unsigned long lmmio_space_offset; /* CPU view - PCI view */
struct ioc *iommu; /* IOMMU this device is under */
/* REVISIT - spinlock to protect resources? */
#define HBA_NAME_SIZE 16
char io_name[HBA_NAME_SIZE];
char lmmio_name[HBA_NAME_SIZE];
char elmmio_name[HBA_NAME_SIZE];
char gmmio_name[HBA_NAME_SIZE];
};
/*
** We support 2^16 I/O ports per HBA. These are set up in the form
** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
** space address.
*/
#define HBA_PORT_SPACE_BITS 16
#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
#ifdef CONFIG_64BIT
#define PCI_F_EXTEND 0xffffffff00000000UL
#else /* !CONFIG_64BIT */
#define PCI_F_EXTEND 0UL
#endif /* !CONFIG_64BIT */
/*
** Most PCI devices (eg Tulip, NCR720) also export the same registers
** to both MMIO and I/O port space. Due to poor performance of I/O Port
** access under HP PCI bus adapters, strongly recommend the use of MMIO
** address space.
**
** While I'm at it more PA programming notes:
**
** 1) MMIO stores (writes) are posted operations. This means the processor
** gets an "ACK" before the write actually gets to the device. A read
** to the same device (or typically the bus adapter above it) will
** force in-flight write transaction(s) out to the targeted device
** before the read can complete.
**
** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
** respect to DMA on all platforms. Ie PIO data can reach the processor
** before in-flight DMA reaches memory. Since most SMP PA platforms
** are I/O coherent, it generally doesn't matter...but sometimes
** it does.
**
** I've helped device driver writers debug both types of problems.
*/
struct pci_port_ops {
u8 (*inb) (struct pci_hba_data *hba, u16 port);
u16 (*inw) (struct pci_hba_data *hba, u16 port);
u32 (*inl) (struct pci_hba_data *hba, u16 port);
void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
};
struct pci_bios_ops {
void (*init)(void);
void (*fixup_bus)(struct pci_bus *bus);
};
/*
** Stuff declared in arch/parisc/kernel/pci.c
*/
extern struct pci_port_ops *pci_port;
extern struct pci_bios_ops *pci_bios;
#ifdef CONFIG_PCI
extern void pcibios_register_hba(struct pci_hba_data *);
#else
static inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif
extern void pcibios_init_bridge(struct pci_dev *);
/*
* pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
* 0 == check if bridge is numbered before re-numbering.
* 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
*
* We *should* set this to zero for "legacy" platforms and one
* for PAT platforms.
*
* But legacy platforms also need to renumber the busses below a Host
* Bus controller. Adding a 4-port Tulip card on the first PCI root
* bus of a C200 resulted in the secondary bus being numbered as 1.
* The second PCI host bus controller's root bus had already been
* assigned bus number 1 by firmware and sysfs complained.
*
* Firmware isn't doing anything wrong here since each controller
* is its own PCI domain. It's simpler and easier for us to renumber
* the busses rather than treat each Dino as a separate PCI domain.
* Eventually, we may want to introduce PCI domains for Superdome or
* rp7420/8420 boxes and then revisit this issue.
*/
#define pcibios_assign_all_busses() (1)
#define PCIBIOS_MIN_IO 0x10
#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE
#endif /* __ASM_PARISC_PCI_H */
linux-7.2.3/arch/parisc/include/asm/pdc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_PDC_H
#define _PARISC_PDC_H
#include <uapi/asm/pdc.h>
#if !defined(__ASSEMBLER__)
extern int parisc_narrow_firmware;
extern int pdc_type;
extern unsigned long parisc_cell_num; /* cell number the CPU runs on (PAT) */
extern unsigned long parisc_cell_loc; /* cell location of CPU (PAT) */
extern unsigned long parisc_pat_pdc_cap; /* PDC capabilities (PAT) */
/* Values for pdc_type */
#define PDC_TYPE_ILLEGAL -1
#define PDC_TYPE_PAT 0 /* 64-bit PAT-PDC */
#define PDC_TYPE_SYSTEM_MAP 1 /* 32-bit, but supports PDC_SYSTEM_MAP */
#define PDC_TYPE_SNAKE 2 /* Doesn't support SYSTEM_MAP */
void setup_pdc(void); /* in inventory.c */
/* wrapper-functions from pdc.c */
int pdc_add_valid(unsigned long address);
int pdc_instr(unsigned int *instr);
int pdc_chassis_info(struct pdc_chassis_info *chassis_info, void *led_info, unsigned long len);
int pdc_chassis_disp(unsigned long disp);
int pdc_chassis_warn(unsigned long *warn);
int pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info);
int pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info);
int pdc_iodc_read(unsigned long *actcnt, unsigned long hpa, unsigned int index,
void *iodc_data, unsigned int iodc_data_size);
int pdc_system_map_find_mods(struct pdc_system_map_mod_info *pdc_mod_info,
struct pdc_module_path *mod_path, long mod_index);
int pdc_system_map_find_addrs(struct pdc_system_map_addr_info *pdc_addr_info,
long mod_index, long addr_index);
int pdc_model_info(struct pdc_model *model);
int pdc_model_sysmodel(unsigned int os_id, char *name);
int pdc_model_cpuid(unsigned long *cpu_id);
int pdc_model_versions(unsigned long *versions, int id);
int pdc_model_capabilities(unsigned long *capabilities);
int pdc_model_platform_info(char *orig_prod_num, char *current_prod_num, char *serial_no);
int pdc_cache_info(struct pdc_cache_info *cache);
int pdc_spaceid_bits(unsigned long *space_bits);
int pdc_btlb_info(struct pdc_btlb_info *btlb);
int pdc_btlb_insert(unsigned long long vpage, unsigned long physpage, unsigned long len,
unsigned long entry_info, unsigned long slot);
int pdc_btlb_purge_all(void);
int pdc_mem_map_hpa(struct pdc_memory_map *r_addr, struct pdc_module_path *mod_path);
int pdc_pim_toc11(struct pdc_toc_pim_11 *ret);
int pdc_pim_toc20(struct pdc_toc_pim_20 *ret);
int pdc_lan_station_id(char *lan_addr, unsigned long net_hpa);
int pdc_stable_read(unsigned long staddr, void *memaddr, unsigned long count);
int pdc_stable_write(unsigned long staddr, void *memaddr, unsigned long count);
int pdc_stable_get_size(unsigned long *size);
int pdc_stable_verify_contents(void);
int pdc_stable_initialize(void);
int pdc_pci_irt_size(unsigned long *num_entries, unsigned long hpa);
int pdc_pci_irt(unsigned long num_entries, unsigned long hpa, void *tbl);
int pdc_get_initiator(struct hardware_path *, struct pdc_initiator *);
int pdc_tod_read(struct pdc_tod *tod);
int pdc_tod_set(unsigned long sec, unsigned long usec);
void pdc_pdt_init(void); /* in pdt.c */
int pdc_mem_pdt_info(struct pdc_mem_retinfo *rinfo);
int pdc_mem_pdt_read_entries(struct pdc_mem_read_pdt *rpdt_read,
unsigned long *pdt_entries_ptr);
#ifdef CONFIG_64BIT
int pdc_mem_mem_table(struct pdc_memory_table_raddr *r_addr,
struct pdc_memory_table *tbl, unsigned long entries);
#endif
void set_firmware_width(void);
void set_firmware_width_unlocked(void);
int pdc_do_firm_test_reset(unsigned long ftc_bitmap);
int pdc_do_reset(void);
int pdc_soft_power_info(unsigned long *power_reg);
int pdc_soft_power_button(int sw_control);
int pdc_soft_power_button_panic(int sw_control);
void pdc_io_reset(void);
void pdc_io_reset_devices(void);
int pdc_iodc_getc(void);
int pdc_iodc_print(const unsigned char *str, unsigned count);
void pdc_emergency_unlock(void);
int pdc_sti_call(unsigned long func, unsigned long flags,
unsigned long inptr, unsigned long outputr,
unsigned long glob_cfg, int do_call64);
int __pdc_cpu_rendezvous(void);
void pdc_cpu_rendezvous_lock(void);
void pdc_cpu_rendezvous_unlock(void);
static inline char * os_id_to_string(u16 os_id) {
switch(os_id) {
case OS_ID_NONE: return "No OS";
case OS_ID_HPUX: return "HP-UX";
case OS_ID_MPEXL: return "MPE-iX";
case OS_ID_OSF: return "OSF";
case OS_ID_HPRT: return "HP-RT";
case OS_ID_NOVEL: return "Novell Netware";
case OS_ID_LINUX: return "Linux";
default: return "Unknown";
}
}
#endif /* !defined(__ASSEMBLER__) */
#endif /* _PARISC_PDC_H */
linux-7.2.3/arch/parisc/include/asm/pdc_chassis.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* include/asm-parisc/pdc_chassis.h
*
* Copyright (C) 2002 Laurent Canet <canetl@esiee.fr>
* Copyright (C) 2002 Thibaut Varene <varenet@parisc-linux.org>
*
* TODO: - handle processor number on SMP systems (Reporting Entity ID)
* - handle message ID
* - handle timestamps
*/
#ifndef _PARISC_PDC_CHASSIS_H
#define _PARISC_PDC_CHASSIS_H
/*
* ----------
* Prototypes
* ----------
*/
int pdc_chassis_send_status(int message);
void parisc_pdc_chassis_init(void);
/*
* -----------------
* Direct call names
* -----------------
* They setup everything for you, the Log message and the corresponding LED state
*/
#define PDC_CHASSIS_DIRECT_BSTART 0
#define PDC_CHASSIS_DIRECT_BCOMPLETE 1
#define PDC_CHASSIS_DIRECT_SHUTDOWN 2
#define PDC_CHASSIS_DIRECT_PANIC 3
#define PDC_CHASSIS_DIRECT_HPMC 4
#define PDC_CHASSIS_DIRECT_LPMC 5
#define PDC_CHASSIS_DIRECT_DUMP 6 /* not yet implemented */
#define PDC_CHASSIS_DIRECT_OOPS 7 /* not yet implemented */
/*
* ------------
* LEDs control
* ------------
* Set the three LEDs -- Run, Attn, and Fault.
*/
/* Old PDC LED control */
#define PDC_CHASSIS_DISP_DATA(v) ((unsigned long)(v) << 17)
/*
* Available PDC PAT LED states
*/
#define PDC_CHASSIS_LED_RUN_OFF (0ULL << 4)
#define PDC_CHASSIS_LED_RUN_FLASH (1ULL << 4)
#define PDC_CHASSIS_LED_RUN_ON (2ULL << 4)
#define PDC_CHASSIS_LED_RUN_NC (3ULL << 4)
#define PDC_CHASSIS_LED_ATTN_OFF (0ULL << 6)
#define PDC_CHASSIS_LED_ATTN_FLASH (1ULL << 6)
#define PDC_CHASSIS_LED_ATTN_NC (3ULL << 6) /* ATTN ON is invalid */
#define PDC_CHASSIS_LED_FAULT_OFF (0ULL << 8)
#define PDC_CHASSIS_LED_FAULT_FLASH (1ULL << 8)
#define PDC_CHASSIS_LED_FAULT_ON (2ULL << 8)
#define PDC_CHASSIS_LED_FAULT_NC (3ULL << 8)
#define PDC_CHASSIS_LED_VALID (1ULL << 10)
/*
* Valid PDC PAT LED states combinations
*/
/* System running normally */
#define PDC_CHASSIS_LSTATE_RUN_NORMAL (PDC_CHASSIS_LED_RUN_ON | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_OFF | \
PDC_CHASSIS_LED_VALID )
/* System crashed and rebooted itself successfully */
#define PDC_CHASSIS_LSTATE_RUN_CRASHREC (PDC_CHASSIS_LED_RUN_ON | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_FLASH | \
PDC_CHASSIS_LED_VALID )
/* There was a system interruption that did not take the system down */
#define PDC_CHASSIS_LSTATE_RUN_SYSINT (PDC_CHASSIS_LED_RUN_ON | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_OFF | \
PDC_CHASSIS_LED_VALID )
/* System running and unexpected reboot or non-critical error detected */
#define PDC_CHASSIS_LSTATE_RUN_NCRIT (PDC_CHASSIS_LED_RUN_ON | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_FLASH | \
PDC_CHASSIS_LED_VALID )
/* Executing non-OS code */
#define PDC_CHASSIS_LSTATE_NONOS (PDC_CHASSIS_LED_RUN_FLASH | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_OFF | \
PDC_CHASSIS_LED_VALID )
/* Boot failed - Executing non-OS code */
#define PDC_CHASSIS_LSTATE_NONOS_BFAIL (PDC_CHASSIS_LED_RUN_FLASH | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_ON | \
PDC_CHASSIS_LED_VALID )
/* Unexpected reboot occurred - Executing non-OS code */
#define PDC_CHASSIS_LSTATE_NONOS_UNEXP (PDC_CHASSIS_LED_RUN_FLASH | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_FLASH | \
PDC_CHASSIS_LED_VALID )
/* Executing non-OS code - Non-critical error detected */
#define PDC_CHASSIS_LSTATE_NONOS_NCRIT (PDC_CHASSIS_LED_RUN_FLASH | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_OFF | \
PDC_CHASSIS_LED_VALID )
/* Boot failed - Executing non-OS code - Non-critical error detected */
#define PDC_CHASSIS_LSTATE_BFAIL_NCRIT (PDC_CHASSIS_LED_RUN_FLASH | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_ON | \
PDC_CHASSIS_LED_VALID )
/* Unexpected reboot/recovering - Executing non-OS code - Non-critical error detected */
#define PDC_CHASSIS_LSTATE_UNEXP_NCRIT (PDC_CHASSIS_LED_RUN_FLASH | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_FLASH | \
PDC_CHASSIS_LED_VALID )
/* Cannot execute PDC */
#define PDC_CHASSIS_LSTATE_CANNOT_PDC (PDC_CHASSIS_LED_RUN_OFF | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_OFF | \
PDC_CHASSIS_LED_VALID )
/* Boot failed - OS not up - PDC has detected a failure that prevents boot */
#define PDC_CHASSIS_LSTATE_FATAL_BFAIL (PDC_CHASSIS_LED_RUN_OFF | \
PDC_CHASSIS_LED_ATTN_OFF | \
PDC_CHASSIS_LED_FAULT_ON | \
PDC_CHASSIS_LED_VALID )
/* No code running - Non-critical error detected (double fault situation) */
#define PDC_CHASSIS_LSTATE_NOCODE_NCRIT (PDC_CHASSIS_LED_RUN_OFF | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_OFF | \
PDC_CHASSIS_LED_VALID )
/* Boot failed - OS not up - Fatal failure detected - Non-critical error detected */
#define PDC_CHASSIS_LSTATE_FATAL_NCRIT (PDC_CHASSIS_LED_RUN_OFF | \
PDC_CHASSIS_LED_ATTN_FLASH | \
PDC_CHASSIS_LED_FAULT_ON | \
PDC_CHASSIS_LED_VALID )
/* All other states are invalid */
/*
* --------------
* PDC Log events
* --------------
* Here follows bits needed to fill up the log event sent to PDC_CHASSIS
* The log message contains: Alert level, Source, Source detail,
* Source ID, Problem detail, Caller activity, Activity status,
* Caller subactivity, Reporting entity type, Reporting entity ID,
* Data type, Unique message ID and EOM.
*/
/* Alert level */
#define PDC_CHASSIS_ALERT_FORWARD (0ULL << 36) /* no failure detected */
#define PDC_CHASSIS_ALERT_SERPROC (1ULL << 36) /* service proc - no failure */
#define PDC_CHASSIS_ALERT_NURGENT (2ULL << 36) /* non-urgent operator attn */
#define PDC_CHASSIS_ALERT_BLOCKED (3ULL << 36) /* system blocked */
#define PDC_CHASSIS_ALERT_CONF_CHG (4ULL << 36) /* unexpected configuration change */
#define PDC_CHASSIS_ALERT_ENV_PB (5ULL << 36) /* boot possible, environmental pb */
#define PDC_CHASSIS_ALERT_PENDING (6ULL << 36) /* boot possible, pending failure */
#define PDC_CHASSIS_ALERT_PERF_IMP (8ULL << 36) /* boot possible, performance impaired */
#define PDC_CHASSIS_ALERT_FUNC_IMP (10ULL << 36) /* boot possible, functionality impaired */
#define PDC_CHASSIS_ALERT_SOFT_FAIL (12ULL << 36) /* software failure */
#define PDC_CHASSIS_ALERT_HANG (13ULL << 36) /* system hang */
#define PDC_CHASSIS_ALERT_ENV_FATAL (14ULL << 36) /* fatal power or environmental pb */
#define PDC_CHASSIS_ALERT_HW_FATAL (15ULL << 36) /* fatal hardware problem */
/* Source */
#define PDC_CHASSIS_SRC_NONE (0ULL << 28) /* unknown, no source stated */
#define PDC_CHASSIS_SRC_PROC (1ULL << 28) /* processor */
/* For later use ? */
#define PDC_CHASSIS_SRC_PROC_CACHE (2ULL << 28) /* processor cache*/
#define PDC_CHASSIS_SRC_PDH (3ULL << 28) /* processor dependent hardware */
#define PDC_CHASSIS_SRC_PWR (4ULL << 28) /* power */
#define PDC_CHASSIS_SRC_FAB (5ULL << 28) /* fabric connector */
#define PDC_CHASSIS_SRC_PLATi (6ULL << 28) /* platform */
#define PDC_CHASSIS_SRC_MEM (7ULL << 28) /* memory */
#define PDC_CHASSIS_SRC_IO (8ULL << 28) /* I/O */
#define PDC_CHASSIS_SRC_CELL (9ULL << 28) /* cell */
#define PDC_CHASSIS_SRC_PD (10ULL << 28) /* protected domain */
/* Source detail field */
#define PDC_CHASSIS_SRC_D_PROC (1ULL << 24) /* processor general */
/* Source ID - platform dependent */
#define PDC_CHASSIS_SRC_ID_UNSPEC (0ULL << 16)
/* Problem detail - problem source dependent */
#define PDC_CHASSIS_PB_D_PROC_NONE (0ULL << 32) /* no problem detail */
#define PDC_CHASSIS_PB_D_PROC_TIMEOUT (4ULL << 32) /* timeout */
/* Caller activity */
#define PDC_CHASSIS_CALL_ACT_HPUX_BL (7ULL << 12) /* Boot Loader */
#define PDC_CHASSIS_CALL_ACT_HPUX_PD (8ULL << 12) /* SAL_PD activities */
#define PDC_CHASSIS_CALL_ACT_HPUX_EVENT (9ULL << 12) /* SAL_EVENTS activities */
#define PDC_CHASSIS_CALL_ACT_HPUX_IO (10ULL << 12) /* SAL_IO activities */
#define PDC_CHASSIS_CALL_ACT_HPUX_PANIC (11ULL << 12) /* System panic */
#define PDC_CHASSIS_CALL_ACT_HPUX_INIT (12ULL << 12) /* System initialization */
#define PDC_CHASSIS_CALL_ACT_HPUX_SHUT (13ULL << 12) /* System shutdown */
#define PDC_CHASSIS_CALL_ACT_HPUX_WARN (14ULL << 12) /* System warning */
#define PDC_CHASSIS_CALL_ACT_HPUX_DU (15ULL << 12) /* Display_Activity() update */
/* Activity status - implementation dependent */
#define PDC_CHASSIS_ACT_STATUS_UNSPEC (0ULL << 0)
/* Caller subactivity - implementation dependent */
/* FIXME: other subactivities ? */
#define PDC_CHASSIS_CALL_SACT_UNSPEC (0ULL << 4) /* implementation dependent */
/* Reporting entity type */
#define PDC_CHASSIS_RET_GENERICOS (12ULL << 52) /* generic OSes */
#define PDC_CHASSIS_RET_IA64_NT (13ULL << 52) /* IA-64 NT */
#define PDC_CHASSIS_RET_HPUX (14ULL << 52) /* HP-UX */
#define PDC_CHASSIS_RET_DIAG (15ULL << 52) /* offline diagnostics & utilities */
/* Reporting entity ID */
#define PDC_CHASSIS_REID_UNSPEC (0ULL << 44)
/* Data type */
#define PDC_CHASSIS_DT_NONE (0ULL << 59) /* data field unused */
/* For later use ? Do we need these ? */
#define PDC_CHASSIS_DT_PHYS_ADDR (1ULL << 59) /* physical address */
#define PDC_CHASSIS_DT_DATA_EXPECT (2ULL << 59) /* expected data */
#define PDC_CHASSIS_DT_ACTUAL (3ULL << 59) /* actual data */
#define PDC_CHASSIS_DT_PHYS_LOC (4ULL << 59) /* physical location */
#define PDC_CHASSIS_DT_PHYS_LOC_EXT (5ULL << 59) /* physical location extension */
#define PDC_CHASSIS_DT_TAG (6ULL << 59) /* tag */
#define PDC_CHASSIS_DT_SYNDROME (7ULL << 59) /* syndrome */
#define PDC_CHASSIS_DT_CODE_ADDR (8ULL << 59) /* code address */
#define PDC_CHASSIS_DT_ASCII_MSG (9ULL << 59) /* ascii message */
#define PDC_CHASSIS_DT_POST (10ULL << 59) /* POST code */
#define PDC_CHASSIS_DT_TIMESTAMP (11ULL << 59) /* timestamp */
#define PDC_CHASSIS_DT_DEV_STAT (12ULL << 59) /* device status */
#define PDC_CHASSIS_DT_DEV_TYPE (13ULL << 59) /* device type */
#define PDC_CHASSIS_DT_PB_DET (14ULL << 59) /* problem detail */
#define PDC_CHASSIS_DT_ACT_LEV (15ULL << 59) /* activity level/timeout */
#define PDC_CHASSIS_DT_SER_NUM (16ULL << 59) /* serial number */
#define PDC_CHASSIS_DT_REV_NUM (17ULL << 59) /* revision number */
#define PDC_CHASSIS_DT_INTERRUPT (18ULL << 59) /* interruption information */
#define PDC_CHASSIS_DT_TEST_NUM (19ULL << 59) /* test number */
#define PDC_CHASSIS_DT_STATE_CHG (20ULL << 59) /* major changes in system state */
#define PDC_CHASSIS_DT_PROC_DEALLOC (21ULL << 59) /* processor deallocate */
#define PDC_CHASSIS_DT_RESET (30ULL << 59) /* reset type and cause */
#define PDC_CHASSIS_DT_PA_LEGACY (31ULL << 59) /* legacy PA hex chassis code */
/* System states - part of major changes in system state data field */
#define PDC_CHASSIS_SYSTATE_BSTART (0ULL << 0) /* boot start */
#define PDC_CHASSIS_SYSTATE_BCOMP (1ULL << 0) /* boot complete */
#define PDC_CHASSIS_SYSTATE_CHANGE (2ULL << 0) /* major change */
#define PDC_CHASSIS_SYSTATE_LED (3ULL << 0) /* LED change */
#define PDC_CHASSIS_SYSTATE_PANIC (9ULL << 0) /* OS Panic */
#define PDC_CHASSIS_SYSTATE_DUMP (10ULL << 0) /* memory dump */
#define PDC_CHASSIS_SYSTATE_HPMC (11ULL << 0) /* processing HPMC */
#define PDC_CHASSIS_SYSTATE_HALT (15ULL << 0) /* system halted */
/* Message ID */
#define PDC_CHASSIS_MSG_ID (0ULL << 40) /* we do not handle msg IDs atm */
/* EOM - separates log entries */
#define PDC_CHASSIS_EOM_CLEAR (0ULL << 43)
#define PDC_CHASSIS_EOM_SET (1ULL << 43)
/*
* Preformated well known messages
*/
/* Boot started */
#define PDC_CHASSIS_PMSG_BSTART (PDC_CHASSIS_ALERT_SERPROC | \
PDC_CHASSIS_SRC_PROC | \
PDC_CHASSIS_SRC_D_PROC | \
PDC_CHASSIS_SRC_ID_UNSPEC | \
PDC_CHASSIS_PB_D_PROC_NONE | \
PDC_CHASSIS_CALL_ACT_HPUX_INIT | \
PDC_CHASSIS_ACT_STATUS_UNSPEC | \
PDC_CHASSIS_CALL_SACT_UNSPEC | \
PDC_CHASSIS_RET_HPUX | \
PDC_CHASSIS_REID_UNSPEC | \
PDC_CHASSIS_DT_STATE_CHG | \
PDC_CHASSIS_SYSTATE_BSTART | \
PDC_CHASSIS_MSG_ID | \
PDC_CHASSIS_EOM_SET )
/* Boot complete */
#define PDC_CHASSIS_PMSG_BCOMPLETE (PDC_CHASSIS_ALERT_SERPROC | \
PDC_CHASSIS_SRC_PROC | \
PDC_CHASSIS_SRC_D_PROC | \
PDC_CHASSIS_SRC_ID_UNSPEC | \
PDC_CHASSIS_PB_D_PROC_NONE | \
PDC_CHASSIS_CALL_ACT_HPUX_INIT | \
PDC_CHASSIS_ACT_STATUS_UNSPEC | \
PDC_CHASSIS_CALL_SACT_UNSPEC | \
PDC_CHASSIS_RET_HPUX | \
PDC_CHASSIS_REID_UNSPEC | \
PDC_CHASSIS_DT_STATE_CHG | \
PDC_CHASSIS_SYSTATE_BCOMP | \
PDC_CHASSIS_MSG_ID | \
PDC_CHASSIS_EOM_SET )
/* Shutdown */
#define PDC_CHASSIS_PMSG_SHUTDOWN (PDC_CHASSIS_ALERT_SERPROC | \
PDC_CHASSIS_SRC_PROC | \
PDC_CHASSIS_SRC_D_PROC | \
PDC_CHASSIS_SRC_ID_UNSPEC | \
PDC_CHASSIS_PB_D_PROC_NONE | \
PDC_CHASSIS_CALL_ACT_HPUX_SHUT | \
PDC_CHASSIS_ACT_STATUS_UNSPEC | \
PDC_CHASSIS_CALL_SACT_UNSPEC | \
PDC_CHASSIS_RET_HPUX | \
PDC_CHASSIS_REID_UNSPEC | \
PDC_CHASSIS_DT_STATE_CHG | \
PDC_CHASSIS_SYSTATE_HALT | \
PDC_CHASSIS_MSG_ID | \
PDC_CHASSIS_EOM_SET )
/* Panic */
#define PDC_CHASSIS_PMSG_PANIC (PDC_CHASSIS_ALERT_SOFT_FAIL | \
PDC_CHASSIS_SRC_PROC | \
PDC_CHASSIS_SRC_D_PROC | \
PDC_CHASSIS_SRC_ID_UNSPEC | \
PDC_CHASSIS_PB_D_PROC_NONE | \
PDC_CHASSIS_CALL_ACT_HPUX_PANIC| \
PDC_CHASSIS_ACT_STATUS_UNSPEC | \
PDC_CHASSIS_CALL_SACT_UNSPEC | \
PDC_CHASSIS_RET_HPUX | \
PDC_CHASSIS_REID_UNSPEC | \
PDC_CHASSIS_DT_STATE_CHG | \
PDC_CHASSIS_SYSTATE_PANIC | \
PDC_CHASSIS_MSG_ID | \
PDC_CHASSIS_EOM_SET )
// FIXME: extrapolated data
/* HPMC */
#define PDC_CHASSIS_PMSG_HPMC (PDC_CHASSIS_ALERT_CONF_CHG /*?*/ | \
PDC_CHASSIS_SRC_PROC | \
PDC_CHASSIS_SRC_D_PROC | \
PDC_CHASSIS_SRC_ID_UNSPEC | \
PDC_CHASSIS_PB_D_PROC_NONE | \
PDC_CHASSIS_CALL_ACT_HPUX_WARN | \
PDC_CHASSIS_RET_HPUX | \
PDC_CHASSIS_DT_STATE_CHG | \
PDC_CHASSIS_SYSTATE_HPMC | \
PDC_CHASSIS_MSG_ID | \
PDC_CHASSIS_EOM_SET )
/* LPMC */
#define PDC_CHASSIS_PMSG_LPMC (PDC_CHASSIS_ALERT_BLOCKED /*?*/| \
PDC_CHASSIS_SRC_PROC | \
PDC_CHASSIS_SRC_D_PROC | \
PDC_CHASSIS_SRC_ID_UNSPEC | \
PDC_CHASSIS_PB_D_PROC_NONE | \
PDC_CHASSIS_CALL_ACT_HPUX_WARN | \
PDC_CHASSIS_ACT_STATUS_UNSPEC | \
PDC_CHASSIS_CALL_SACT_UNSPEC | \
PDC_CHASSIS_RET_HPUX | \
PDC_CHASSIS_REID_UNSPEC | \
PDC_CHASSIS_DT_STATE_CHG | \
PDC_CHASSIS_SYSTATE_CHANGE | \
PDC_CHASSIS_MSG_ID | \
PDC_CHASSIS_EOM_SET )
#endif /* _PARISC_PDC_CHASSIS_H */
linux-7.2.3/arch/parisc/include/asm/pdcpat.h
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#ifndef __PARISC_PATPDC_H
#define __PARISC_PATPDC_H
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright 2000 (c) Hewlett Packard (Paul Bame <bame()spam.parisc-linux.org>)
* Copyright 2000,2004 (c) Grant Grundler <grundler()nahspam.parisc-linux.org>
*/
#define PDC_PAT_CELL 64L /* Interface for gaining and
* manipulatin g cell state within PD */
#define PDC_PAT_CELL_GET_NUMBER 0L /* Return Cell number */
#define PDC_PAT_CELL_GET_INFO 1L /* Returns info about Cell */
#define PDC_PAT_CELL_MODULE 2L /* Returns info about Module */
#define PDC_PAT_CELL_SET_ATTENTION 9L /* Set Cell Attention indicator */
#define PDC_PAT_CELL_NUMBER_TO_LOC 10L /* Cell Number -> Location */
#define PDC_PAT_CELL_WALK_FABRIC 11L /* Walk the Fabric */
#define PDC_PAT_CELL_GET_RDT_SIZE 12L /* Return Route Distance Table Sizes */
#define PDC_PAT_CELL_GET_RDT 13L /* Return Route Distance Tables */
#define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
#define PDC_PAT_CELL_SET_LOCAL_PDH 15L /* Write Local PDH Buffer */
#define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
#define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
#define PDC_PAT_CELL_GET_DBG_INFO 128L /* Return DBG Buffer Info */
#define PDC_PAT_CELL_CHANGE_ALIAS 129L /* Change Non-Equivalent Alias Chacking */
/*
** Arg to PDC_PAT_CELL_MODULE memaddr[4]
**
** Addresses on the Merced Bus != all Runway Bus addresses.
** This is intended for programming SBA/LBA chips range registers.
*/
#define IO_VIEW 0UL
#define PA_VIEW 1UL
/* PDC_PAT_CELL_MODULE entity type values */
#define PAT_ENTITY_CA 0 /* central agent */
#define PAT_ENTITY_PROC 1 /* processor */
#define PAT_ENTITY_MEM 2 /* memory controller */
#define PAT_ENTITY_SBA 3 /* system bus adapter */
#define PAT_ENTITY_LBA 4 /* local bus adapter */
#define PAT_ENTITY_PBC 5 /* processor bus converter */
#define PAT_ENTITY_XBC 6 /* crossbar fabric connect */
#define PAT_ENTITY_RC 7 /* fabric interconnect */
/* PDC_PAT_CELL_MODULE address range type values */
#define PAT_PBNUM 0 /* PCI Bus Number */
#define PAT_LMMIO 1 /* < 4G MMIO Space */
#define PAT_GMMIO 2 /* > 4G MMIO Space */
#define PAT_NPIOP 3 /* Non Postable I/O Port Space */
#define PAT_PIOP 4 /* Postable I/O Port Space */
#define PAT_AHPA 5 /* Addional HPA Space */
#define PAT_UFO 6 /* HPA Space (UFO for Mariposa) */
#define PAT_GNIP 7 /* GNI Reserved Space */
/* PDC PAT CHASSIS LOG -- Platform logging & forward progress functions */
#define PDC_PAT_CHASSIS_LOG 65L
#define PDC_PAT_CHASSIS_WRITE_LOG 0L /* Write Log Entry */
#define PDC_PAT_CHASSIS_READ_LOG 1L /* Read Log Entry */
/* PDC PAT COMPLEX */
#define PDC_PAT_COMPLEX 66L
/* PDC PAT CPU -- CPU configuration within the protection domain */
#define PDC_PAT_CPU 67L
#define PDC_PAT_CPU_INFO 0L /* Return CPU config info */
#define PDC_PAT_CPU_DELETE 1L /* Delete CPU */
#define PDC_PAT_CPU_ADD 2L /* Add CPU */
#define PDC_PAT_CPU_GET_NUMBER 3L /* Return CPU Number */
#define PDC_PAT_CPU_GET_HPA 4L /* Return CPU HPA */
#define PDC_PAT_CPU_STOP 5L /* Stop CPU */
#define PDC_PAT_CPU_RENDEZVOUS 6L /* Rendezvous CPU */
#define PDC_PAT_CPU_GET_CLOCK_INFO 7L /* Return CPU Clock info */
#define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
#define PDC_PAT_CPU_GET_PDC_ENTRYPOINT 11L /* Return PDC Entry point */
#define PDC_PAT_CPU_PLUNGE_FABRIC 128L /* Plunge Fabric */
#define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache
* Cleansing Mode */
/* PDC PAT EVENT -- Platform Events */
#define PDC_PAT_EVENT 68L
#define PDC_PAT_EVENT_GET_CAPS 0L /* Get Capabilities */
#define PDC_PAT_EVENT_SET_MODE 1L /* Set Notification Mode */
#define PDC_PAT_EVENT_SCAN 2L /* Scan Event */
#define PDC_PAT_EVENT_HANDLE 3L /* Handle Event */
#define PDC_PAT_EVENT_GET_NB_CALL 4L /* Get Non-Blocking call Args */
/* PDC PAT HPMC -- Cause processor to go into spin loop, and wait
* for wake up from Monarch Processor.
*/
#define PDC_PAT_HPMC 70L
#define PDC_PAT_HPMC_RENDEZ_CPU 0L /* go into spin loop */
#define PDC_PAT_HPMC_SET_PARAMS 1L /* Allows OS to specify intr which PDC
* will use to interrupt OS during
* machine check rendezvous */
/* parameters for PDC_PAT_HPMC_SET_PARAMS: */
#define HPMC_SET_PARAMS_INTR 1L /* Rendezvous Interrupt */
#define HPMC_SET_PARAMS_WAKE 2L /* Wake up processor */
/* PDC PAT IO -- On-line services for I/O modules */
#define PDC_PAT_IO 71L
#define PDC_PAT_IO_GET_SLOT_STATUS 5L /* Get Slot Status Info*/
#define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
/* Hardware Path */
#define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from
* Physical Location */
#define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
* Address from Hardware Path */
#define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path
* from PCI Configuration Address */
#define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L /* Read Host Bridge State Info */
#define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table
* Size */
#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE 16L /* Get PCI INT Routing Table */
#define PDC_PAT_IO_GET_HINT_TABLE_SIZE 17L /* Get Hint Table Size */
#define PDC_PAT_IO_GET_HINT_TABLE 18L /* Get Hint Table */
#define PDC_PAT_IO_PCI_CONFIG_READ 19L /* PCI Config Read */
#define PDC_PAT_IO_PCI_CONFIG_WRITE 20L /* PCI Config Write */
#define PDC_PAT_IO_GET_NUM_IO_SLOTS 21L /* Get Number of I/O Bay Slots in
* Cabinet */
#define PDC_PAT_IO_GET_LOC_IO_SLOTS 22L /* Get Physical Location of I/O */
/* Bay Slots in Cabinet */
#define PDC_PAT_IO_BAY_STATUS_INFO 28L /* Get I/O Bay Slot Status Info */
#define PDC_PAT_IO_GET_PROC_VIEW 29L /* Get Processor view of IO address */
#define PDC_PAT_IO_PROG_SBA_DIR_RANGE 30L /* Program directed range */
/* PDC PAT MEM -- Manage memory page deallocation */
#define PDC_PAT_MEM 72L
#define PDC_PAT_MEM_PD_INFO 0L /* Return PDT info for PD */
#define PDC_PAT_MEM_PD_CLEAR 1L /* Clear PDT for PD */
#define PDC_PAT_MEM_PD_READ 2L /* Read PDT entries for PD */
#define PDC_PAT_MEM_PD_RESET 3L /* Reset clear bit for PD */
#define PDC_PAT_MEM_CELL_INFO 5L /* Return PDT info For Cell */
#define PDC_PAT_MEM_CELL_CLEAR 6L /* Clear PDT For Cell */
#define PDC_PAT_MEM_CELL_READ 7L /* Read PDT entries For Cell */
#define PDC_PAT_MEM_CELL_RESET 8L /* Reset clear bit For Cell */
#define PDC_PAT_MEM_SETGM 9L /* Set Good Memory value */
#define PDC_PAT_MEM_ADD_PAGE 10L /* ADDs a page to the cell */
#define PDC_PAT_MEM_ADDRESS 11L /* Get Physical Location From */
/* Memory Address */
#define PDC_PAT_MEM_GET_TXT_SIZE 12L /* Get Formatted Text Size */
#define PDC_PAT_MEM_GET_PD_TXT 13L /* Get PD Formatted Text */
#define PDC_PAT_MEM_GET_CELL_TXT 14L /* Get Cell Formatted Text */
#define PDC_PAT_MEM_RD_STATE_INFO 15L /* Read Mem Module State Info*/
#define PDC_PAT_MEM_CLR_STATE_INFO 16L /*Clear Mem Module State Info*/
#define PDC_PAT_MEM_CLEAN_RANGE 128L /*Clean Mem in specific range*/
#define PDC_PAT_MEM_GET_TBL_SIZE 131L /* Get Memory Table Size */
#define PDC_PAT_MEM_GET_TBL 132L /* Get Memory Table */
/* PDC PAT NVOLATILE -- Access Non-Volatile Memory */
#define PDC_PAT_NVOLATILE 73L
#define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */
#define PDC_PAT_NVOLATILE_WRITE 1L /* Write Non-Volatile Memory */
#define PDC_PAT_NVOLATILE_GET_SIZE 2L /* Return size of NVM */
#define PDC_PAT_NVOLATILE_VERIFY 3L /* Verify contents of NVM */
#define PDC_PAT_NVOLATILE_INIT 4L /* Initialize NVM */
/* PDC PAT PD */
#define PDC_PAT_PD 74L /* Protection Domain Info */
#define PDC_PAT_PD_GET_ADDR_MAP 0L /* Get Address Map */
#define PDC_PAT_PD_GET_PDC_INTERF_REV 1L /* Get PDC Interface Revisions */
#define PDC_PAT_PD_GET_PLATFORM_COUNTER 10L /* Get 64-bit free running counter */
#define PDC_PAT_CAPABILITY_BIT_PDC_SERIALIZE (1UL << 0)
#define PDC_PAT_CAPABILITY_BIT_PDC_POLLING (1UL << 1)
#define PDC_PAT_CAPABILITY_BIT_PDC_NBC (1UL << 2) /* non-blocking calls */
#define PDC_PAT_CAPABILITY_BIT_PDC_UFO (1UL << 3)
#define PDC_PAT_CAPABILITY_BIT_PDC_IODC_32 (1UL << 4)
#define PDC_PAT_CAPABILITY_BIT_PDC_IODC_64 (1UL << 5)
#define PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ (1UL << 6)
#define PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB (1UL << 7)
/* PDC_PAT_PD_GET_ADDR_MAP entry types */
#define PAT_MEMORY_DESCRIPTOR 1
/* PDC_PAT_PD_GET_ADDR_MAP memory types */
#define PAT_MEMTYPE_MEMORY 0
#define PAT_MEMTYPE_FIRMWARE 4
/* PDC_PAT_PD_GET_ADDR_MAP memory usage */
#define PAT_MEMUSE_GENERAL 0
#define PAT_MEMUSE_GI 128
#define PAT_MEMUSE_GNI 129
/* PDC PAT REGISTER TOC */
#define PDC_PAT_REGISTER_TOC 75L
#define PDC_PAT_TOC_REGISTER_VECTOR 0L /* Register TOC Vector */
#define PDC_PAT_TOC_READ_VECTOR 1L /* Read TOC Vector */
/* PDC PAT SYSTEM_INFO */
#define PDC_PAT_SYSTEM_INFO 76L
/* PDC_PAT_SYSTEM_INFO uses the same options as PDC_SYSTEM_INFO function. */
#ifndef __ASSEMBLER__
#include <linux/types.h>
#ifdef CONFIG_64BIT
#define is_pdc_pat() (PDC_TYPE_PAT == pdc_type)
extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
#else /* ! CONFIG_64BIT */
/* No PAT support for 32-bit kernels...sorry */
#define is_pdc_pat() (0)
#define pdc_pat_get_irt_size(num_entries, cell_numn) PDC_BAD_PROC
#define pdc_pat_get_irt(r_addr, cell_num) PDC_BAD_PROC
#endif /* ! CONFIG_64BIT */
struct pdc_pat_cell_num {
unsigned long cell_num;
unsigned long cell_loc;
};
struct pdc_pat_cpu_num {
unsigned long cpu_num;
unsigned long cpu_loc;
};
struct pdc_pat_mem_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_INFO (return info) */
unsigned int ke; /* bit 0: memory inside good memory? */
unsigned int current_pdt_entries:16;
unsigned int max_pdt_entries:16;
unsigned long Cs_bitmap;
unsigned long Ic_bitmap;
unsigned long good_mem;
unsigned long first_dbe_loc; /* first location of double bit error */
unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
};
struct pdc_pat_mem_cell_pdt_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_CELL_INFO */
u64 reserved:32;
u64 cs:1; /* clear status: cleared since the last call? */
u64 current_pdt_entries:15;
u64 ic:1; /* interleaving had to be changed ? */
u64 max_pdt_entries:15;
unsigned long good_mem;
unsigned long first_dbe_loc; /* first location of double bit error */
unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
};
struct pdc_pat_mem_read_pd_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_READ */
unsigned long actual_count_bytes;
unsigned long pdt_entries;
};
struct pdc_pat_mem_phys_mem_location { /* PDC_PAT_MEM/PDC_PAT_MEM_ADDRESS */
u64 cabinet:8;
u64 ign1:8;
u64 ign2:8;
u64 cell_slot:8;
u64 ign3:8;
u64 dimm_slot:8; /* DIMM slot, e.g. 0x1A, 0x2B, show user hex value! */
u64 ign4:8;
u64 source:4; /* for mem: always 0x07 */
u64 source_detail:4; /* for mem: always 0x04 (SIMM or DIMM) */
};
struct pdc_pat_pd_addr_map_entry {
unsigned char entry_type; /* 1 = Memory Descriptor Entry Type */
unsigned char reserve1[5];
unsigned char memory_type;
unsigned char memory_usage;
unsigned long paddr;
unsigned int pages; /* Length in 4K pages */
unsigned int reserve2;
unsigned long cell_map;
};
/********************************************************************
* PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr
* ----------------------------------------------------------
* Bit 0 to 51 - conf_base_addr
* Bit 52 to 62 - reserved
* Bit 63 - endianess bit
********************************************************************/
#define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
/********************************************************************
* PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info
* ----------------------------------------------------
* Bit 0 to 7 - entity type
* 0 = central agent, 1 = processor,
* 2 = memory controller, 3 = system bus adapter,
* 4 = local bus adapter, 5 = processor bus converter,
* 6 = crossbar fabric connect, 7 = fabric interconnect,
* 8 to 254 reserved, 255 = unknown.
* Bit 8 to 15 - DVI
* Bit 16 to 23 - IOC functions
* Bit 24 to 39 - reserved
* Bit 40 to 63 - mod_pages
* number of 4K pages a module occupies starting at conf_base_addr
********************************************************************/
#define PAT_GET_ENTITY(value) (((value) >> 56) & 0xffUL)
#define PAT_GET_DVI(value) (((value) >> 48) & 0xffUL)
#define PAT_GET_IOC(value) (((value) >> 40) & 0xffUL)
#define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
/*
** PDC_PAT_CELL_GET_INFO return block
*/
typedef struct pdc_pat_cell_info_rtn_block {
unsigned long pdc_rev;
unsigned long capabilities; /* see PDC_PAT_CAPABILITY_BIT_* */
unsigned long reserved0[2];
unsigned long cell_info; /* 0x20 */
unsigned long cell_phys_location;
unsigned long cpu_info;
unsigned long cpu_speed;
unsigned long io_chassis_phys_location;
unsigned long cell_io_information;
unsigned long reserved1[2];
unsigned long io_slot_info_size; /* 0x60 */
struct {
unsigned long header, info0, info1;
unsigned long phys_loc, hw_path;
} io_slot[16];
unsigned long cell_mem_size; /* 0x2e8 */
unsigned long cell_dimm_info_size;
unsigned long dimm_info[16];
unsigned long fabric_info_size; /* 0x3f8 */
struct { /* 0x380 */
unsigned long fabric_info_xbc_port;
unsigned long rc_attached_to_xbc;
} xbc[8*4];
} pdc_pat_cell_info_rtn_block_t;
/* FIXME: mod[508] should really be a union of the various mod components */
struct pdc_pat_cell_mod_maddr_block { /* PDC_PAT_CELL_MODULE */
unsigned long cba; /* func 0 cfg space address */
unsigned long mod_info; /* module information */
unsigned long mod_location; /* physical location of the module */
struct hardware_path mod_path; /* module path (device path - layers) */
unsigned long mod[508]; /* PAT cell module components */
} __attribute__((aligned(8))) ;
typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
extern int pdc_pat_get_PDC_entrypoint(unsigned long *pdc_entry);
extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
extern int pdc_pat_cell_info(struct pdc_pat_cell_info_rtn_block *info,
unsigned long *actcnt, unsigned long offset,
unsigned long cell_number);
extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc,
unsigned long mod, unsigned long view_type, void *mem_addr);
extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, unsigned long hpa);
extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr,
unsigned long count, unsigned long offset);
extern int pdc_pat_pd_get_pdc_revisions(unsigned long *legacy_rev,
unsigned long *pat_rev, unsigned long *pdc_cap);
extern int pdc_pat_pd_get_platform_counter(uint64_t **addr,
unsigned long *freq, unsigned long *uniq);
extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val);
extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val);
extern int pdc_pat_mem_pdt_info(struct pdc_pat_mem_retinfo *rinfo);
extern int pdc_pat_mem_pdt_cell_info(struct pdc_pat_mem_cell_pdt_retinfo *rinfo,
unsigned long cell);
extern int pdc_pat_mem_read_cell_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
unsigned long *pdt_entries_ptr, unsigned long max_entries);
extern int pdc_pat_mem_read_pd_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
unsigned long *pdt_entries_ptr, unsigned long count,
unsigned long offset);
extern int pdc_pat_mem_get_dimm_phys_location(
struct pdc_pat_mem_phys_mem_location *pret,
unsigned long phys_addr);
#endif /* __ASSEMBLER__ */
#endif /* ! __PARISC_PATPDC_H */
linux-7.2.3/arch/parisc/include/asm/perf.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PERF_H_
#define _ASM_PERF_H_
/* ioctls */
#define PA_PERF_ON _IO('p', 1)
#define PA_PERF_OFF _IOR('p', 2, unsigned int)
#define PA_PERF_VERSION _IOR('p', 3, int)
#define PA_PERF_DEV "perf"
#define PA_PERF_MINOR 146
/* Interface types */
#define UNKNOWN_INTF 255
#define ONYX_INTF 0
#define CUDA_INTF 1
/* Common Onyx and Cuda images */
#define CPI 0
#define BUSUTIL 1
#define TLBMISS 2
#define TLBHANDMISS 3
#define PTKN 4
#define PNTKN 5
#define IMISS 6
#define DMISS 7
#define DMISS_ACCESS 8
#define BIG_CPI 9
#define BIG_LS 10
#define BR_ABORT 11
#define ISNT 12
#define QUADRANT 13
#define RW_PDFET 14
#define RW_WDFET 15
#define SHLIB_CPI 16
/* Cuda only Images */
#define FLOPS 17
#define CACHEMISS 18
#define BRANCHES 19
#define CRSTACK 20
#define I_CACHE_SPEC 21
#define MAX_CUDA_IMAGES 22
/* Onyx only Images */
#define ADDR_INV_ABORT_ALU 17
#define BRAD_STALL 18
#define CNTL_IN_PIPEL 19
#define DSNT_XFH 20
#define FET_SIG1 21
#define FET_SIG2 22
#define G7_1 23
#define G7_2 24
#define G7_3 25
#define G7_4 26
#define MPB_LABORT 27
#define PANIC 28
#define RARE_INST 29
#define RW_DFET 30
#define RW_IFET 31
#define RW_SDFET 32
#define SPEC_IFET 33
#define ST_COND0 34
#define ST_COND1 35
#define ST_COND2 36
#define ST_COND3 37
#define ST_COND4 38
#define ST_UNPRED0 39
#define ST_UNPRED1 40
#define UNPRED 41
#define GO_STORE 42
#define SHLIB_CALL 43
#define MAX_ONYX_IMAGES 44
#endif
linux-7.2.3/arch/parisc/include/asm/perf_event.h
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#ifndef __ASM_PARISC_PERF_EVENT_H
#define __ASM_PARISC_PERF_EVENT_H
#include <asm/psw.h>
#define perf_arch_fetch_caller_regs(regs, __ip) { \
(regs)->gr[0] = KERNEL_PSW; \
(regs)->iaoq[0] = (__ip); \
asm volatile("copy %%sp, %0\n":"=r"((regs)->gr[30])); \
}
#endif /* __ASM_PARISC_PERF_EVENT_H */
linux-7.2.3/arch/parisc/include/asm/pgalloc.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PGALLOC_H
#define _ASM_PGALLOC_H
#include <linux/gfp.h>
#include <linux/mm.h>
#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/fixmap.h>
#include <asm/cache.h>
#define __HAVE_ARCH_PMD_ALLOC_ONE
#include <asm-generic/pgalloc.h>
/* Allocate the top level pgd (page directory) */
static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
return __pgd_alloc(mm, PGD_TABLE_ORDER);
}
#if CONFIG_PGTABLE_LEVELS == 3
/* Three Level Page Table Support for pmd's */
static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
{
set_pud(pud, __pud((PxD_FLAG_PRESENT | PxD_FLAG_VALID) +
(__u32)(__pa((unsigned long)pmd) >> PxD_VALUE_SHIFT)));
}
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct ptdesc *ptdesc;
gfp_t gfp = GFP_PGTABLE_USER;
if (mm == &init_mm)
gfp = GFP_PGTABLE_KERNEL;
ptdesc = pagetable_alloc(gfp, PMD_TABLE_ORDER);
if (!ptdesc)
return NULL;
if (!pagetable_pmd_ctor(mm, ptdesc)) {
pagetable_free(ptdesc);
return NULL;
}
return ptdesc_address(ptdesc);
}
#endif
static inline void
pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
{
set_pmd(pmd, __pmd((PxD_FLAG_PRESENT | PxD_FLAG_VALID)
+ (__u32)(__pa((unsigned long)pte) >> PxD_VALUE_SHIFT)));
}
#define pmd_populate(mm, pmd, pte_page) \
pmd_populate_kernel(mm, pmd, page_address(pte_page))
#endif
linux-7.2.3/arch/parisc/include/asm/pgtable.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_PGTABLE_H
#define _PARISC_PGTABLE_H
#include <asm/page.h>
#if CONFIG_PGTABLE_LEVELS == 3
#include <asm-generic/pgtable-nopud.h>
#elif CONFIG_PGTABLE_LEVELS == 2
#include <asm-generic/pgtable-nopmd.h>
#endif
#include <asm/fixmap.h>
#ifndef __ASSEMBLER__
/*
* we simulate an x86-style page table for the linux mm code
*/
#include <linux/bitops.h>
#include <linux/spinlock.h>
#include <linux/mm_types.h>
#include <asm/processor.h>
#include <asm/cache.h>
/* This is for the serialization of PxTLB broadcasts. At least on the N class
* systems, only one PxTLB inter processor broadcast can be active at any one
* time on the Merced bus. */
extern spinlock_t pa_tlb_flush_lock;
#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
extern int pa_serialize_tlb_flushes;
#else
#define pa_serialize_tlb_flushes (0)
#endif
#define purge_tlb_start(flags) do { \
if (pa_serialize_tlb_flushes) \
spin_lock_irqsave(&pa_tlb_flush_lock, flags); \
else \
local_irq_save(flags); \
} while (0)
#define purge_tlb_end(flags) do { \
if (pa_serialize_tlb_flushes) \
spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \
else \
local_irq_restore(flags); \
} while (0)
/* Purge data and instruction TLB entries. The TLB purge instructions
* are slow on SMP machines since the purge must be broadcast to all CPUs.
*/
static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
{
unsigned long flags;
purge_tlb_start(flags);
mtsp(mm->context.space_id, SR_TEMP1);
pdtlb(SR_TEMP1, addr);
pitlb(SR_TEMP1, addr);
purge_tlb_end(flags);
}
extern void __update_cache(pte_t pte);
/* Certain architectures need to do special things when PTEs
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
#define set_pte(pteptr, pteval) \
do { \
*(pteptr) = (pteval); \
mb(); \
} while(0)
#endif /* !__ASSEMBLER__ */
#define pte_ERROR(e) \
printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#if CONFIG_PGTABLE_LEVELS == 3
#define pmd_ERROR(e) \
printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
#endif
#define pgd_ERROR(e) \
printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
/* This is the size of the initially mapped kernel memory */
#if defined(CONFIG_64BIT) || defined(CONFIG_KALLSYMS)
#define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */
#else
#define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */
#endif
#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
#if CONFIG_PGTABLE_LEVELS == 3
#define PMD_TABLE_ORDER 1
#define PGD_TABLE_ORDER 0
#else
#define PGD_TABLE_ORDER 1
#endif
/* Definitions for 3rd level (we use PLD here for Page Lower directory
* because PTE_SHIFT is used lower down to mean shift that has to be
* done to get usable bits out of the PTE) */
#define PLD_SHIFT PAGE_SHIFT
#define PLD_SIZE PAGE_SIZE
#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
#define PTRS_PER_PTE (1UL << BITS_PER_PTE)
/* Definitions for 2nd level */
#if CONFIG_PGTABLE_LEVELS == 3
#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
#define BITS_PER_PMD (PAGE_SHIFT + PMD_TABLE_ORDER - BITS_PER_PMD_ENTRY)
#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
#else
#define BITS_PER_PMD 0
#endif
/* Definitions for 1st level */
#define PGDIR_SHIFT (PLD_SHIFT + BITS_PER_PTE + BITS_PER_PMD)
#if (PGDIR_SHIFT + PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
#define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
#else
#define BITS_PER_PGD (PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY)
#endif
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
#define PTRS_PER_PGD (1UL << BITS_PER_PGD)
#define USER_PTRS_PER_PGD PTRS_PER_PGD
#ifdef CONFIG_64BIT
#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
#else
#define MAX_ADDRBITS (BITS_PER_LONG)
#define MAX_ADDRESS (1ULL << MAX_ADDRBITS)
#define SPACEID_SHIFT 0
#endif
/* This calculates the number of initial pages we need for the initial
* page tables */
#if (KERNEL_INITIAL_ORDER) >= (PLD_SHIFT + BITS_PER_PTE)
# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PLD_SHIFT - BITS_PER_PTE))
#else
# define PT_INITIAL (1) /* all initial PTEs fit into one page */
#endif
/*
* pgd entries used up by user/kernel:
*/
/* NB: The tlb miss handlers make certain assumptions about the order */
/* of the following bits, so be careful (One example, bits 25-31 */
/* are moved together in one instruction). */
#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
#define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
#ifdef CONFIG_HUGETLB_PAGE
#define _PAGE_SPECIAL_BIT _PAGE_DMB_BIT /* DMB feature is currently unused */
#else
#define _PAGE_SPECIAL_BIT _PAGE_HPAGE_BIT /* use unused HUGE PAGE bit */
#endif
/* N.B. The bits are defined in terms of a 32 bit word above, so the */
/* following macro is ok for both 32 and 64 bit. */
#define xlate_pabit(x) (31 - x)
/* this defines the shift to the usable bits in the PTE it is set so
* that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
* to zero */
#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
#define PFN_PTE_SHIFT 12
#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
#define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
#define _PAGE_SPECIAL (1 << xlate_pabit(_PAGE_SPECIAL_BIT))
#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SPECIAL)
#define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
#define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
#define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
/* We borrow bit 23 to store the exclusive marker in swap PTEs. */
#define _PAGE_SWP_EXCLUSIVE _PAGE_ACCESSED
/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
* are page-aligned, we don't care about the PAGE_OFFSET bits, except
* for a few meta-information bits, so we shift the address to be
* able to effectively address 40/42/44-bits of physical address space
* depending on 4k/16k/64k PAGE_SIZE */
#define _PxD_PRESENT_BIT 31
#define _PxD_VALID_BIT 30
#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
#define PxD_FLAG_MASK (0xf)
#define PxD_FLAG_SHIFT (4)
#define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
#ifndef __ASSEMBLER__
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE)
/* Others seem to make this executable, I don't know if that's correct
or not. The stack is mapped this way though so this is necessary
in the short term - dhd@linuxcare.com, 2000-08-08 */
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ)
#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE)
#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC)
#define PAGE_COPY PAGE_EXECREAD
#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
#define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ)
/*
* We could have an execute only page using "gateway - promote to priv
* level 3", but that is kind of silly. So, the way things are defined
* now, we must always have read permission for pages with execute
* permission. For the fun of it we'll go ahead and support write only
* pages.
*/
/*xwr*/
extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
/* initial page tables for 0-8MB for kernel */
extern pte_t pg0[];
#define pte_none(x) (pte_val(x) == 0)
#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
#define pte_user(x) (pte_val(x) & _PAGE_USER)
#define pte_clear(mm, addr, xp) set_pte_at((mm), (addr), (xp), __pte(0))
#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
#define pud_flag(x) (pud_val(x) & PxD_FLAG_MASK)
#define pud_address(x) ((unsigned long)(pud_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
#define pmd_none(x) (!pmd_val(x))
#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
static inline void pmd_clear(pmd_t *pmd) {
set_pmd(pmd, __pmd(0));
}
#if CONFIG_PGTABLE_LEVELS == 3
#define pud_pgtable(pud) ((pmd_t *) __va(pud_address(pud)))
#define pud_page(pud) virt_to_page((void *)pud_pgtable(pud))
/* For 64 bit we have three level tables */
#define pud_none(x) (!pud_val(x))
#define pud_bad(x) (!(pud_flag(x) & PxD_FLAG_VALID))
#define pud_present(x) (pud_flag(x) & PxD_FLAG_PRESENT)
static inline void pud_clear(pud_t *pud) {
set_pud(pud, __pud(0));
}
#endif
/*
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkwrite_novma(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) { pte_val(pte) |= _PAGE_SPECIAL; return pte; }
/*
* Huge pte definitions.
*/
#ifdef CONFIG_HUGETLB_PAGE
#define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE)
#define pte_mkhuge(pte) (__pte(pte_val(pte) | \
(parisc_requires_coherency() ? 0 : _PAGE_HUGE)))
#else
#define pte_huge(pte) (0)
#define pte_mkhuge(pte) (pte)
#endif
#define __mk_pte(addr,pgprot) \
({ \
pte_t __pte; \
\
pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
\
__pte; \
})
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
{
pte_t pte;
pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
return pte;
}
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
/* Permanent address of a page. On parisc we don't have highmem. */
#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
static inline unsigned long pmd_page_vaddr(pmd_t pmd)
{
return ((unsigned long) __va(pmd_address(pmd)));
}
#define pmd_pfn(pmd) (pmd_address(pmd) >> PAGE_SHIFT)
#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
/* Find an entry in the second-level page table.. */
extern void paging_init (void);
static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte, unsigned int nr)
{
if (pte_present(pte) && pte_user(pte))
__update_cache(pte);
for (;;) {
*ptep = pte;
purge_tlb_entries(mm, addr);
if (--nr == 0)
break;
ptep++;
pte_val(pte) += 1 << PFN_PTE_SHIFT;
addr += PAGE_SIZE;
}
}
#define set_ptes set_ptes
#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1)
/* Used for deferring calls to flush_dcache_page() */
#define PG_dcache_dirty PG_arch_1
#define update_mmu_cache_range(vmf, vma, addr, ptep, nr) __update_cache(*ptep)
#define update_mmu_cache(vma, addr, ptep) __update_cache(*ptep)
/*
* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
* are !pte_none() && !pte_present().
*
* Format of swap PTEs (32bit):
*
* 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
* <---------------- offset -----------------> P E <ofs> < type ->
*
* E is the exclusive marker that is not stored in swap entries.
* _PAGE_PRESENT (P) must be 0.
*
* For the 64bit version, the offset is extended by 32bit.
*/
#define __swp_type(x) ((x).val & 0x1f)
#define __swp_offset(x) ( (((x).val >> 5) & 0x7) | \
(((x).val >> 10) << 3) )
#define __swp_entry(type, offset) ((swp_entry_t) { \
((type) & 0x1f) | \
((offset & 0x7) << 5) | \
((offset >> 3) << 10) })
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
static inline bool pte_swp_exclusive(pte_t pte)
{
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
}
static inline pte_t pte_swp_mkexclusive(pte_t pte)
{
pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
return pte;
}
static inline pte_t pte_swp_clear_exclusive(pte_t pte)
{
pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
return pte;
}
static inline pte_t ptep_get(pte_t *ptep)
{
return READ_ONCE(*ptep);
}
#define ptep_get ptep_get
static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
pte_t pte;
pte = ptep_get(ptep);
if (!pte_young(pte)) {
return false;
}
set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
return true;
}
bool ptep_clear_flush_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep);
pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep);
struct mm_struct;
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
set_pte_at(mm, addr, ptep, pte_wrprotect(*ptep));
}
#define pte_same(A,B) (pte_val(A) == pte_val(B))
#endif /* !__ASSEMBLER__ */
/* TLB page size encoding - see table 3-1 in parisc20.pdf */
#define _PAGE_SIZE_ENCODING_4K 0
#define _PAGE_SIZE_ENCODING_16K 1
#define _PAGE_SIZE_ENCODING_64K 2
#define _PAGE_SIZE_ENCODING_256K 3
#define _PAGE_SIZE_ENCODING_1M 4
#define _PAGE_SIZE_ENCODING_4M 5
#define _PAGE_SIZE_ENCODING_16M 6
#define _PAGE_SIZE_ENCODING_64M 7
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
#endif
#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
/* We provide our own get_unmapped_area to provide cache coherency */
#define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
#define __HAVE_ARCH_PTE_SAME
#endif /* _PARISC_PGTABLE_H */
linux-7.2.3/arch/parisc/include/asm/prefetch.h
+45
View File
@@ -0,0 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* include/asm-parisc/prefetch.h
*
* PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
* In addition, many implementations do hardware prefetching of both
* instructions and data.
*
* PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
* to gr0 but not in a way that Linux can use. If the load would cause an
* interruption (eg due to prefetching 0), it is suppressed on PA2.0
* processors, but not on 7300LC.
*
*/
#ifndef __ASM_PARISC_PREFETCH_H
#define __ASM_PARISC_PREFETCH_H
#ifndef __ASSEMBLER__
#ifdef CONFIG_PREFETCH
#define ARCH_HAS_PREFETCH
static inline void prefetch(const void *addr)
{
__asm__(
#ifndef CONFIG_PA20
/* Need to avoid prefetch of NULL on PA7300LC */
" extrw,u,= %0,31,32,%%r0\n"
#endif
" ldw 0(%0), %%r0" : : "r" (addr));
}
/* LDD is a PA2.0 addition. */
#ifdef CONFIG_PA20
#define ARCH_HAS_PREFETCHW
static inline void prefetchw(const void *addr)
{
__asm__("ldd 0(%0), %%r0" : : "r" (addr));
}
#endif /* CONFIG_PA20 */
#endif /* CONFIG_PREFETCH */
#endif /* __ASSEMBLER__ */
#endif /* __ASM_PARISC_PROCESSOR_H */
linux-7.2.3/arch/parisc/include/asm/processor.h
+330
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@@ -0,0 +1,330 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* include/asm-parisc/processor.h
*
* Copyright (C) 1994 Linus Torvalds
* Copyright (C) 2001 Grant Grundler
*/
#ifndef __ASM_PARISC_PROCESSOR_H
#define __ASM_PARISC_PROCESSOR_H
#ifndef __ASSEMBLER__
#include <linux/threads.h>
#include <linux/irqreturn.h>
#include <asm/assembly.h>
#include <asm/prefetch.h>
#include <asm/hardware.h>
#include <asm/pdc.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/percpu.h>
#endif /* __ASSEMBLER__ */
#define HAVE_ARCH_PICK_MMAP_LAYOUT
#define TASK_SIZE_OF(tsk) ((tsk)->thread.task_size)
#define TASK_SIZE TASK_SIZE_OF(current)
#define TASK_UNMAPPED_BASE (current->thread.map_base)
#define DEFAULT_TASK_SIZE32 (0xFFF00000UL)
#define DEFAULT_MAP_BASE32 (0x40000000UL)
#ifdef CONFIG_64BIT
#define DEFAULT_TASK_SIZE (MAX_ADDRESS-0xf000000)
#define DEFAULT_MAP_BASE (0x200000000UL)
#else
#define DEFAULT_TASK_SIZE DEFAULT_TASK_SIZE32
#define DEFAULT_MAP_BASE DEFAULT_MAP_BASE32
#endif
/* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc.
* prumpf */
#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX DEFAULT_TASK_SIZE
#ifndef __ASSEMBLER__
struct rlimit;
unsigned long mmap_upper_limit(const struct rlimit *rlim_stack);
unsigned long calc_max_stack_size(unsigned long stack_max);
/*
* Data detected about CPUs at boot time which is the same for all CPU's.
* HP boxes are SMP - ie identical processors.
*
* FIXME: some CPU rev info may be processor specific...
*/
struct system_cpuinfo_parisc {
unsigned int cpu_count;
unsigned int cpu_hz;
unsigned int hversion;
unsigned int sversion;
enum cpu_type cpu_type;
struct {
struct pdc_model model;
unsigned long versions;
unsigned long cpuid;
unsigned long capabilities;
char sys_model_name[81]; /* PDC-ROM returnes this model name */
} pdc;
const char *cpu_name; /* e.g. "PA7300LC (PCX-L2)" */
const char *family_name; /* e.g. "1.1e" */
};
/* Per CPU data structure - ie varies per CPU. */
struct cpuinfo_parisc {
unsigned long it_value; /* Interval Timer at last timer Intr */
unsigned long irq_count; /* number of IRQ's since boot */
unsigned long cpuid; /* aka slot_number or set to NO_PROC_ID */
unsigned long hpa; /* Host Physical address */
unsigned long txn_addr; /* MMIO addr of EIR or id_eid */
#ifdef CONFIG_SMP
unsigned long pending_ipi; /* bitmap of type ipi_message_type */
#endif
unsigned long bh_count; /* number of times bh was invoked */
unsigned long fp_rev;
unsigned long fp_model;
unsigned long cpu_num; /* CPU number from PAT firmware */
unsigned long cpu_loc; /* CPU location from PAT firmware */
unsigned int state;
struct parisc_device *dev;
};
extern struct system_cpuinfo_parisc boot_cpu_data;
DECLARE_PER_CPU(struct cpuinfo_parisc, cpu_data);
extern int time_keeper_id; /* CPU used for timekeeping */
#define CPU_HVERSION ((boot_cpu_data.hversion >> 4) & 0x0FFF)
struct thread_struct {
struct pt_regs regs;
unsigned long task_size;
unsigned long map_base;
unsigned long flags;
};
#define task_pt_regs(tsk) ((struct pt_regs *)&((tsk)->thread.regs))
/* Thread struct flags. */
#define PARISC_UAC_NOPRINT (1UL << 0) /* see prctl and unaligned.c */
#define PARISC_UAC_SIGBUS (1UL << 1)
#define PARISC_KERNEL_DEATH (1UL << 31) /* see die_if_kernel()... */
#define PARISC_UAC_SHIFT 0
#define PARISC_UAC_MASK (PARISC_UAC_NOPRINT|PARISC_UAC_SIGBUS)
#define SET_UNALIGN_CTL(task,value) \
({ \
(task)->thread.flags = (((task)->thread.flags & ~PARISC_UAC_MASK) \
| (((value) << PARISC_UAC_SHIFT) & \
PARISC_UAC_MASK)); \
0; \
})
#define GET_UNALIGN_CTL(task,addr) \
({ \
put_user(((task)->thread.flags & PARISC_UAC_MASK) \
>> PARISC_UAC_SHIFT, (int __user *) (addr)); \
})
#define INIT_THREAD { \
.regs = { .gr = { 0, }, \
.fr = { 0, }, \
.sr = { 0, }, \
.iasq = { 0, }, \
.iaoq = { 0, }, \
.cr27 = 0, \
}, \
.task_size = DEFAULT_TASK_SIZE, \
.map_base = DEFAULT_MAP_BASE, \
.flags = 0 \
}
struct task_struct;
void show_trace(struct task_struct *task, unsigned long *stack);
/*
* Start user thread in another space.
*
* Note that we set both the iaoq and r31 to the new pc. When
* the kernel initially calls execve it will return through an
* rfi path that will use the values in the iaoq. The execve
* syscall path will return through the gateway page, and
* that uses r31 to branch to.
*
* For ELF we clear r23, because the dynamic linker uses it to pass
* the address of the finalizer function.
*
* We also initialize sr3 to an illegal value (illegal for our
* implementation, not for the architecture).
*/
typedef unsigned int elf_caddr_t;
/* The ELF abi wants things done a "wee bit" differently than
* som does. Supporting this behavior here avoids
* having our own version of create_elf_tables.
*
* Oh, and yes, that is not a typo, we are really passing argc in r25
* and argv in r24 (rather than r26 and r25). This is because that's
* where __libc_start_main wants them.
*
* Duplicated from dl-machine.h for the benefit of readers:
*
* Our initial stack layout is rather different from everyone else's
* due to the unique PA-RISC ABI. As far as I know it looks like
* this:
----------------------------------- (user startup code creates this frame)
| 32 bytes of magic |
|---------------------------------|
| 32 bytes argument/sp save area |
|---------------------------------| (bprm->p)
| ELF auxiliary info |
| (up to 28 words) |
|---------------------------------|
| NULL |
|---------------------------------|
| Environment pointers |
|---------------------------------|
| NULL |
|---------------------------------|
| Argument pointers |
|---------------------------------| <- argv
| argc (1 word) |
|---------------------------------| <- bprm->exec (HACK!)
| N bytes of slack |
|---------------------------------|
| filename passed to execve |
|---------------------------------| (mm->env_end)
| env strings |
|---------------------------------| (mm->env_start, mm->arg_end)
| arg strings |
|---------------------------------|
| additional faked arg strings if |
| we're invoked via binfmt_script |
|---------------------------------| (mm->arg_start)
stack base is at TASK_SIZE - rlim_max.
on downward growing arches, it looks like this:
stack base at TASK_SIZE
| filename passed to execve
| env strings
| arg strings
| faked arg strings
| slack
| ELF
| envps
| argvs
| argc
* The pleasant part of this is that if we need to skip arguments we
* can just decrement argc and move argv, because the stack pointer
* is utterly unrelated to the location of the environment and
* argument vectors.
*
* Note that the S/390 people took the easy way out and hacked their
* GCC to make the stack grow downwards.
*
* Final Note: For entry from syscall, the W (wide) bit of the PSW
* is stuffed into the lowest bit of the user sp (%r30), so we fill
* it in here from the current->personality
*/
#define USER_WIDE_MODE (!is_32bit_task())
#define start_thread(regs, new_pc, new_sp) do { \
elf_addr_t *sp = (elf_addr_t *)new_sp; \
__u32 spaceid = (__u32)current->mm->context.space_id; \
elf_addr_t pc = (elf_addr_t)new_pc | 3; \
elf_caddr_t *argv = (elf_caddr_t *)bprm->exec + 1; \
\
regs->iasq[0] = spaceid; \
regs->iasq[1] = spaceid; \
regs->iaoq[0] = pc; \
regs->iaoq[1] = pc + 4; \
regs->sr[2] = LINUX_GATEWAY_SPACE; \
regs->sr[3] = 0xffff; \
regs->sr[4] = spaceid; \
regs->sr[5] = spaceid; \
regs->sr[6] = spaceid; \
regs->sr[7] = spaceid; \
regs->gr[ 0] = USER_PSW | (USER_WIDE_MODE ? PSW_W : 0); \
regs->fr[ 0] = 0LL; \
regs->fr[ 1] = 0LL; \
regs->fr[ 2] = 0LL; \
regs->fr[ 3] = 0LL; \
regs->gr[30] = (((unsigned long)sp + 63) &~ 63) | (USER_WIDE_MODE ? 1 : 0); \
regs->gr[31] = pc; \
\
get_user(regs->gr[25], (argv - 1)); \
regs->gr[24] = (long) argv; \
regs->gr[23] = 0; \
} while(0)
struct mm_struct;
extern unsigned long __get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) ((tsk)->thread.regs.iaoq[0])
#define KSTK_ESP(tsk) ((tsk)->thread.regs.gr[30])
#define cpu_relax() barrier()
/*
* parisc_requires_coherency() is used to identify the combined VIPT/PIPT
* cached CPUs which require a guarantee of coherency (no inequivalent aliases
* with different data, whether clean or not) to operate
*/
#ifdef CONFIG_PA8X00
extern int _parisc_requires_coherency;
#define parisc_requires_coherency() _parisc_requires_coherency
#else
#define parisc_requires_coherency() (0)
#endif
extern int running_on_qemu;
extern int parisc_narrow_firmware;
extern void __noreturn toc_intr(struct pt_regs *regs);
extern void toc_handler(void);
extern unsigned int toc_handler_size;
extern unsigned int toc_handler_csum;
extern void do_cpu_irq_mask(struct pt_regs *);
extern irqreturn_t timer_interrupt(int, void *);
extern irqreturn_t ipi_interrupt(int, void *);
extern void parisc_clockevent_init(void);
extern void handle_interruption(int, struct pt_regs *);
/* called from assembly code: */
extern void start_parisc(void);
extern void smp_callin(unsigned long);
extern void sys_rt_sigreturn(struct pt_regs *, int);
extern void do_notify_resume(struct pt_regs *, long);
extern long do_syscall_trace_enter(struct pt_regs *);
extern void do_syscall_trace_exit(struct pt_regs *);
/* CPU startup and info */
struct seq_file;
extern void early_trap_init(void);
extern void collect_boot_cpu_data(void);
extern void btlb_init_per_cpu(void);
extern int show_cpuinfo (struct seq_file *m, void *v);
/* driver code in driver/parisc */
extern void processor_init(void);
struct parisc_device;
struct resource;
extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
extern void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask);
extern void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
#endif /* __ASSEMBLER__ */
#endif /* __ASM_PARISC_PROCESSOR_H */
linux-7.2.3/arch/parisc/include/asm/psw.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_PSW_H
#define _PARISC_PSW_H
#define PSW_I 0x00000001
#define PSW_D 0x00000002
#define PSW_P 0x00000004
#define PSW_Q 0x00000008
#define PSW_R 0x00000010
#define PSW_F 0x00000020
#define PSW_G 0x00000040 /* PA1.x only */
#define PSW_O 0x00000080 /* PA2.0 only */
/* ssm/rsm instructions number PSW_W and PSW_E differently */
#define PSW_SM_I PSW_I /* Enable External Interrupts */
#define PSW_SM_D PSW_D
#define PSW_SM_P PSW_P
#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
#define PSW_SM_QUIET PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I
#define PSW_CB 0x0000ff00
#define PSW_M 0x00010000
#define PSW_V 0x00020000
#define PSW_C 0x00040000
#define PSW_B 0x00080000
#define PSW_X 0x00100000
#define PSW_N 0x00200000
#define PSW_L 0x00400000
#define PSW_H 0x00800000
#define PSW_T 0x01000000
#define PSW_S 0x02000000
#define PSW_E 0x04000000
#define PSW_W 0x08000000 /* PA2.0 only */
#define PSW_W_BIT 36 /* PA2.0 only */
#define PSW_Z 0x40000000 /* PA1.x only */
#define PSW_Y 0x80000000 /* PA1.x only */
#ifdef CONFIG_64BIT
# define PSW_HI_CB 0x000000ff /* PA2.0 only */
#endif
#ifdef CONFIG_64BIT
# define USER_PSW_HI_MASK PSW_HI_CB
# define WIDE_PSW PSW_W
#else
# define WIDE_PSW 0
#endif
/* Used when setting up for rfi */
#define KERNEL_PSW (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D)
#define REAL_MODE_PSW (WIDE_PSW | PSW_Q)
#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
#ifndef __ASSEMBLER__
/* The program status word as bitfields. */
struct pa_psw {
unsigned int y:1;
unsigned int z:1;
unsigned int rv:2;
unsigned int w:1;
unsigned int e:1;
unsigned int s:1;
unsigned int t:1;
unsigned int h:1;
unsigned int l:1;
unsigned int n:1;
unsigned int x:1;
unsigned int b:1;
unsigned int c:1;
unsigned int v:1;
unsigned int m:1;
unsigned int cb:8;
unsigned int o:1;
unsigned int g:1;
unsigned int f:1;
unsigned int r:1;
unsigned int q:1;
unsigned int p:1;
unsigned int d:1;
unsigned int i:1;
};
#ifdef CONFIG_64BIT
#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
#else
#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
#endif
#endif /* !__ASSEMBLER__ */
#endif
linux-7.2.3/arch/parisc/include/asm/ptrace.h
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/* SPDX-License-Identifier: GPL-2.0 */
/* written by Philipp Rumpf, Copyright (C) 1999 SuSE GmbH Nuernberg
** Copyright (C) 2000 Grant Grundler, Hewlett-Packard
*/
#ifndef _PARISC_PTRACE_H
#define _PARISC_PTRACE_H
#include <asm/assembly.h>
#include <uapi/asm/ptrace.h>
#include <linux/compiler.h>
#define task_regs(task) ((struct pt_regs *) ((char *)(task) + TASK_REGS))
#define arch_has_single_step() 1
#define arch_has_block_step() 1
/* XXX should we use iaoq[1] or iaoq[0] ? */
#define user_mode(regs) (((regs)->iaoq[0] & 3) != PRIV_KERNEL)
#define user_space(regs) ((regs)->iasq[1] != PRIV_KERNEL)
#define instruction_pointer(regs) ((regs)->iaoq[0] & ~3)
#define user_stack_pointer(regs) ((regs)->gr[30])
unsigned long profile_pc(struct pt_regs *);
static inline unsigned long regs_return_value(struct pt_regs *regs)
{
return regs->gr[28];
}
static inline void instruction_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->iaoq[0] = val;
regs->iaoq[1] = val + 4;
}
/* Query offset/name of register from its name/offset */
extern int regs_query_register_offset(const char *name);
extern const char *regs_query_register_name(unsigned int offset);
#define MAX_REG_OFFSET (offsetof(struct pt_regs, ipsw))
#define kernel_stack_pointer(regs) ((regs)->gr[30])
static inline unsigned long regs_get_register(struct pt_regs *regs,
unsigned int offset)
{
if (unlikely(offset > MAX_REG_OFFSET))
return 0;
return *(unsigned long *)((unsigned long)regs + offset);
}
unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n);
int regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
#endif
linux-7.2.3/arch/parisc/include/asm/ropes.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_ROPES_H_
#define _ASM_PARISC_ROPES_H_
#include <asm/parisc-device.h>
#ifdef CONFIG_64BIT
/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
#define ZX1_SUPPORT
#endif
#ifdef CONFIG_PROC_FS
/* depends on proc fs support. But costs CPU performance */
#undef SBA_COLLECT_STATS
#endif
/*
** The number of pdir entries to "free" before issuing
** a read to PCOM register to flush out PCOM writes.
** Interacts with allocation granularity (ie 4 or 8 entries
** allocated and free'd/purged at a time might make this
** less interesting).
*/
#define DELAYED_RESOURCE_CNT 16
#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
struct ioc {
void __iomem *ioc_hpa; /* I/O MMU base address */
char *res_map; /* resource map, bit == pdir entry */
__le64 *pdir_base; /* physical base address */
unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
#ifdef ZX1_SUPPORT
unsigned long iovp_mask; /* help convert IOVA to IOVP */
#endif
unsigned long *res_hint; /* next avail IOVP - circular search */
spinlock_t res_lock;
unsigned int res_bitshift; /* from the LEFT! */
unsigned int res_size; /* size of resource map in bytes */
#ifdef SBA_HINT_SUPPORT
/* FIXME : DMA HINTs not used */
unsigned long hint_mask_pdir; /* bits used for DMA hints */
unsigned int hint_shift_pdir;
#endif
#if DELAYED_RESOURCE_CNT > 0
int saved_cnt;
struct sba_dma_pair {
dma_addr_t iova;
size_t size;
} saved[DELAYED_RESOURCE_CNT];
#endif
#ifdef SBA_COLLECT_STATS
#define SBA_SEARCH_SAMPLE 0x100
unsigned long avg_search[SBA_SEARCH_SAMPLE];
unsigned long avg_idx; /* current index into avg_search */
unsigned long used_pages;
unsigned long msingle_calls;
unsigned long msingle_pages;
unsigned long msg_calls;
unsigned long msg_pages;
unsigned long usingle_calls;
unsigned long usingle_pages;
unsigned long usg_calls;
unsigned long usg_pages;
#endif
/* STUFF We don't need in performance path */
unsigned int pdir_size; /* in bytes, determined by IOV Space size */
};
struct sba_device {
struct sba_device *next; /* list of SBA's in system */
struct parisc_device *dev; /* dev found in bus walk */
const char *name;
void __iomem *sba_hpa; /* base address */
spinlock_t sba_lock;
unsigned int flags; /* state/functionality enabled */
unsigned int hw_rev; /* HW revision of chip */
struct resource chip_resv; /* MMIO reserved for chip */
struct resource iommu_resv; /* MMIO reserved for iommu */
unsigned int num_ioc; /* number of on-board IOC's */
struct ioc ioc[MAX_IOC];
};
/* list of SBA's in system, see drivers/parisc/sba_iommu.c */
extern struct sba_device *sba_list;
#define ASTRO_RUNWAY_PORT 0x582
#define IKE_MERCED_PORT 0x803
#define REO_MERCED_PORT 0x804
#define REOG_MERCED_PORT 0x805
#define PLUTO_MCKINLEY_PORT 0x880
static inline int IS_ASTRO(struct parisc_device *d) {
return d->id.hversion == ASTRO_RUNWAY_PORT;
}
static inline int IS_IKE(struct parisc_device *d) {
return d->id.hversion == IKE_MERCED_PORT;
}
static inline int IS_PLUTO(struct parisc_device *d) {
return d->id.hversion == PLUTO_MCKINLEY_PORT;
}
#define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */
#define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */
#define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2)
#define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
#define SBA_AGPGART_COOKIE (__force __le64) 0x0000badbadc0ffeeULL
#define SBA_FUNC_ID 0x0000 /* function id */
#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
/* Ike's IOC's occupy functions 2 and 3 */
#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
#define IOC_CTRL 0x8 /* IOC_CTRL offset */
#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
#define IOC_CTRL_RM (1 << 8) /* Real Mode */
#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
/*
** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
** Firmware programs this stuff. Don't touch it.
*/
#define LMMIO_DIRECT0_BASE 0x300
#define LMMIO_DIRECT0_MASK 0x308
#define LMMIO_DIRECT0_ROUTE 0x310
#define LMMIO_DIST_BASE 0x360
#define LMMIO_DIST_MASK 0x368
#define LMMIO_DIST_ROUTE 0x370
#define IOS_DIST_BASE 0x390
#define IOS_DIST_MASK 0x398
#define IOS_DIST_ROUTE 0x3A0
#define IOS_DIRECT_BASE 0x3C0
#define IOS_DIRECT_MASK 0x3C8
#define IOS_DIRECT_ROUTE 0x3D0
/*
** Offsets into I/O TLB (Function 2 and 3 on Ike)
*/
#define ROPE0_CTL 0x200 /* "regbus pci0" */
#define ROPE1_CTL 0x208
#define ROPE2_CTL 0x210
#define ROPE3_CTL 0x218
#define ROPE4_CTL 0x220
#define ROPE5_CTL 0x228
#define ROPE6_CTL 0x230
#define ROPE7_CTL 0x238
#define IOC_ROPE0_CFG 0x500 /* pluto only */
#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
#define HF_ENABLE 0x40
#define IOC_IBASE 0x300 /* IO TLB */
#define IOC_IMASK 0x308
#define IOC_PCOM 0x310
#define IOC_TCNFG 0x318
#define IOC_PDIR_BASE 0x320
/*
** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
** It's safer (avoid memory corruption) to keep DMA page mappings
** equivalently sized to VM PAGE_SIZE.
**
** We really can't avoid generating a new mapping for each
** page since the Virtual Coherence Index has to be generated
** and updated for each page.
**
** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
*/
#define IOVP_SIZE PAGE_SIZE
#define IOVP_SHIFT PAGE_SHIFT
#define IOVP_MASK PAGE_MASK
#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
#define SBA_PERF_MASK1 0x718
#define SBA_PERF_MASK2 0x730
/*
** Offsets into PCI Performance Counters (functions 12 and 13)
** Controlled by PERF registers in function 2 & 3 respectively.
*/
#define SBA_PERF_CNT1 0x200
#define SBA_PERF_CNT2 0x208
#define SBA_PERF_CNT3 0x210
/*
** lba_device: Per instance Elroy data structure
*/
struct lba_device {
struct pci_hba_data hba;
spinlock_t lba_lock;
void *iosapic_obj;
#ifdef CONFIG_64BIT
void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */
#endif
int flags; /* state/functionality enabled */
int hw_rev; /* HW revision of chip */
};
#define ELROY_HVERS 0x782
#define MERCURY_HVERS 0x783
#define QUICKSILVER_HVERS 0x784
static inline int IS_ELROY(struct parisc_device *d) {
return (d->id.hversion == ELROY_HVERS);
}
static inline int IS_MERCURY(struct parisc_device *d) {
return (d->id.hversion == MERCURY_HVERS);
}
static inline int IS_QUICKSILVER(struct parisc_device *d) {
return (d->id.hversion == QUICKSILVER_HVERS);
}
static inline int agp_mode_mercury(void __iomem *hpa) {
u64 bus_mode;
bus_mode = readl(hpa + 0x0620);
if (bus_mode & 1)
return 1;
return 0;
}
/*
** I/O SAPIC init function
** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
** Call setup as part of per instance initialization.
** (ie *not* init_module() function unless only one is present.)
** fixup_irq is to initialize PCI IRQ line support and
** virtualize pcidev->irq value. To be called by pci_fixup_bus().
*/
extern void *iosapic_register(unsigned long hpa, void __iomem *vaddr);
extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
#define LBA_FUNC_ID 0x0000 /* function id */
#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
#define LBA_CAPABLE 0x0030 /* capabilities register */
#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
#define LBA_ARB_PRI 0x0088 /* firmware sets this. */
#define LBA_ARB_MODE 0x0090 /* firmware sets this. */
#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
#define LBA_STAT_CTL 0x0108 /* Status & Control */
#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
#define LBA_LMMIO_MASK 0x0208
#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
#define LBA_GMMIO_MASK 0x0218
#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
#define LBA_WLMMIO_MASK 0x0228
#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
#define LBA_WGMMIO_MASK 0x0238
#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
#define LBA_IOS_MASK 0x0248
#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
#define LBA_ELMMIO_MASK 0x0258
#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
#define LBA_EIOS_MASK 0x0268
#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
#define LBA_DMA_CTL 0x0278 /* firmware sets this */
#define LBA_IBASE 0x0300 /* SBA DMA support */
#define LBA_IMASK 0x0308
/* FIXME: ignore DMA Hint stuff until we can measure performance */
#define LBA_HINT_CFG 0x0310
#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
#define LBA_BUS_MODE 0x0620
/* ERROR regs are needed for config cycle kluges */
#define LBA_ERROR_CONFIG 0x0680
#define LBA_SMART_MODE 0x20
#define LBA_ERROR_STATUS 0x0688
#define LBA_ROPE_CTL 0x06A0
#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
#endif /*_ASM_PARISC_ROPES_H_*/
linux-7.2.3/arch/parisc/include/asm/rt_sigframe.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_RT_SIGFRAME_H
#define _ASM_PARISC_RT_SIGFRAME_H
struct rt_sigframe {
unsigned int tramp[2]; /* holds original return address */
struct siginfo info;
struct ucontext uc;
};
#define SIGFRAME 128
#define FUNCTIONCALLFRAME 96
#define PARISC_RT_SIGFRAME_SIZE \
(((sizeof(struct rt_sigframe) + FUNCTIONCALLFRAME) + SIGFRAME) & -SIGFRAME)
#endif
linux-7.2.3/arch/parisc/include/asm/runway.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef ASM_PARISC_RUNWAY_H
#define ASM_PARISC_RUNWAY_H
#define RUNWAY_STATUS 0x10
#define RUNWAY_DEBUG 0x40
#endif /* ASM_PARISC_RUNWAY_H */
linux-7.2.3/arch/parisc/include/asm/seccomp.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _ASM_SECCOMP_H
#define _ASM_SECCOMP_H
#include <asm-generic/seccomp.h>
#ifdef CONFIG_64BIT
# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_PARISC64
# define SECCOMP_ARCH_NATIVE_NR NR_syscalls
# define SECCOMP_ARCH_NATIVE_NAME "parisc64"
# ifdef CONFIG_COMPAT
# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_PARISC
# define SECCOMP_ARCH_COMPAT_NR NR_syscalls
# define SECCOMP_ARCH_COMPAT_NAME "parisc"
# endif
#else /* !CONFIG_64BIT */
# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_PARISC
# define SECCOMP_ARCH_NATIVE_NR NR_syscalls
# define SECCOMP_ARCH_NATIVE_NAME "parisc"
#endif
#endif /* _ASM_SECCOMP_H */
linux-7.2.3/arch/parisc/include/asm/sections.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_SECTIONS_H
#define _PARISC_SECTIONS_H
#ifdef CONFIG_HAVE_FUNCTION_DESCRIPTORS
#include <asm/elf.h>
typedef Elf64_Fdesc func_desc_t;
#endif
/* nothing to see, move along */
#include <asm-generic/sections.h>
extern char __alt_instructions[], __alt_instructions_end[];
#endif
linux-7.2.3/arch/parisc/include/asm/serial.h
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/*
* include/asm-parisc/serial.h
*/
/*
* This is used for 16550-compatible UARTs
*/
#define BASE_BAUD ( 1843200 / 16 )
linux-7.2.3/arch/parisc/include/asm/shmparam.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASMPARISC_SHMPARAM_H
#define _ASMPARISC_SHMPARAM_H
/*
* PA-RISC uses virtually indexed & physically tagged (VIPT) caches
* which has strict requirements when two pages to the same physical
* address are accessed through different mappings. Read the section
* "Address Aliasing" in the arch docs for more detail:
* PA-RISC 1.1 (page 3-6):
* https://parisc.wiki.kernel.org/images-parisc/6/68/Pa11_acd.pdf
* PA-RISC 2.0 (page F-5):
* https://parisc.wiki.kernel.org/images-parisc/7/73/Parisc2.0.pdf
*
* For Linux we allow kernel and userspace to map pages on page size
* granularity (SHMLBA) but have to ensure that, if two pages are
* mapped to the same physical address, the virtual and physical
* addresses modulo SHM_COLOUR are identical.
*/
#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
#define SHM_COLOUR 0x00400000 /* shared mappings colouring */
#endif /* _ASMPARISC_SHMPARAM_H */
linux-7.2.3/arch/parisc/include/asm/signal.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_PARISC_SIGNAL_H
#define _ASM_PARISC_SIGNAL_H
#include <uapi/asm/signal.h>
# ifndef __ASSEMBLER__
/* Most things should be clean enough to redefine this at will, if care
is taken to make libc match. */
#include <asm/sigcontext.h>
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_PARISC_SIGNAL_H */
linux-7.2.3/arch/parisc/include/asm/smp.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SMP_H
#define __ASM_SMP_H
extern int init_per_cpu(int cpuid);
#if defined(CONFIG_SMP)
/* Page Zero Location PDC will look for the address to branch to when we poke
** slave CPUs still in "Icache loop".
*/
#define PDC_OS_BOOT_RENDEZVOUS 0x10
#define PDC_OS_BOOT_RENDEZVOUS_HI 0x28
#ifndef __ASSEMBLER__
#include <linux/bitops.h>
#include <linux/threads.h> /* for NR_CPUS */
#include <linux/cpumask.h>
typedef unsigned long address_t;
/*
* Private routines/data
*
* physical and logical are equivalent until we support CPU hotplug.
*/
#define cpu_number_map(cpu) (cpu)
#define cpu_logical_map(cpu) (cpu)
extern void smp_send_all_nop(void);
extern void arch_send_call_function_single_ipi(int cpu);
extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
#define raw_smp_processor_id() (current_thread_info()->cpu)
#endif /* !__ASSEMBLER__ */
#else /* CONFIG_SMP */
static inline void smp_send_all_nop(void) { return; }
#endif
#define NO_PROC_ID 0xFF /* No processor magic marker */
#define ANY_PROC_ID 0xFF /* Any processor magic marker */
int __cpu_disable(void);
void __cpu_die(unsigned int cpu);
#endif /* __ASM_SMP_H */
linux-7.2.3/arch/parisc/include/asm/socket.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_SOCKET_H
#define _ASM_SOCKET_H
#include <uapi/asm/socket.h>
/* O_NONBLOCK clashed with the bits used for socket types. Therefore we
* had to define SOCK_NONBLOCK to a different value here.
*/
#define SOCK_NONBLOCK 0x40000000
#endif /* _ASM_SOCKET_H */
linux-7.2.3/arch/parisc/include/asm/sparsemem.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef ASM_PARISC_SPARSEMEM_H
#define ASM_PARISC_SPARSEMEM_H
/* We have these possible memory map layouts:
* Astro: 0-3.75, 67.75-68, 4-64
* zx1: 0-1, 257-260, 4-256
* Stretch (N-class): 0-2, 4-32, 34-xxx
*/
#define MAX_PHYSMEM_BITS 39 /* 512 GB */
#define SECTION_SIZE_BITS 27 /* 128 MB */
#endif
linux-7.2.3/arch/parisc/include/asm/special_insns.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PARISC_SPECIAL_INSNS_H
#define __PARISC_SPECIAL_INSNS_H
#define lpa(va) ({ \
unsigned long pa; \
__asm__ __volatile__( \
"copy %%r0,%0\n" \
"8:\tlpa %%r0(%1),%0\n" \
"9:\n" \
ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \
"or %%r0,%%r0,%%r0") \
: "=&r" (pa) \
: "r" (va) \
: "memory" \
); \
pa; \
})
#define lpa_user(va) ({ \
unsigned long pa; \
__asm__ __volatile__( \
"copy %%r0,%0\n" \
"8:\tlpa %%r0(%%sr3,%1),%0\n" \
"9:\n" \
ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \
"or %%r0,%%r0,%%r0") \
: "=&r" (pa) \
: "r" (va) \
: "memory" \
); \
pa; \
})
/**
* prober_user() - Probe user read access
* @sr: Space regster.
* @va: Virtual address.
*
* Return: Non-zero if address is accessible.
*
* Due to the way _PAGE_READ is handled in TLB entries, we need
* a special check to determine whether a user address is accessible.
* The ldb instruction does the initial access check. If it is
* successful, the probe instruction checks user access rights.
*/
#define prober_user(sr, va) ({ \
unsigned long read_allowed; \
__asm__ __volatile__( \
"copy %%r0,%0\n" \
"8:\tldb 0(%%sr%1,%2),%%r0\n" \
"\tproberi (%%sr%1,%2),%3,%0\n" \
"9:\n" \
ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \
"or %%r0,%%r0,%%r0") \
: "=&r" (read_allowed) \
: "i" (sr), "r" (va), "i" (PRIV_USER) \
: "memory" \
); \
read_allowed; \
})
#define CR_EIEM 15 /* External Interrupt Enable Mask */
#define CR_CR16 16 /* CR16 Interval Timer */
#define CR_EIRR 23 /* External Interrupt Request Register */
#define mfctl(reg) ({ \
unsigned long cr; \
__asm__ __volatile__( \
"mfctl %1,%0" : \
"=r" (cr) : "i" (reg) \
); \
cr; \
})
#define mtctl(gr, cr) \
__asm__ __volatile__("mtctl %0,%1" \
: /* no outputs */ \
: "r" (gr), "i" (cr) : "memory")
#define get_eiem() mfctl(CR_EIEM)
#define set_eiem(val) mtctl(val, CR_EIEM)
#define mfsp(reg) ({ \
unsigned long cr; \
__asm__ __volatile__( \
"mfsp %%sr%1,%0" \
: "=r" (cr) : "i"(reg) \
); \
cr; \
})
#define mtsp(val, cr) \
{ if (__builtin_constant_p(val) && ((val) == 0)) \
__asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
else \
__asm__ __volatile__("mtsp %0,%1" \
: /* no outputs */ \
: "r" (val), "i" (cr) : "memory"); }
#endif /* __PARISC_SPECIAL_INSNS_H */
linux-7.2.3/arch/parisc/include/asm/spinlock.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SPINLOCK_H
#define __ASM_SPINLOCK_H
#include <asm/barrier.h>
#include <asm/ldcw.h>
#include <asm/processor.h>
#include <asm/spinlock_types.h>
static inline void arch_spin_val_check(int lock_val)
{
if (IS_ENABLED(CONFIG_LIGHTWEIGHT_SPINLOCK_CHECK))
asm volatile( "andcm,= %0,%1,%%r0\n"
".word %2\n"
: : "r" (lock_val), "r" (__ARCH_SPIN_LOCK_UNLOCKED_VAL),
"i" (SPINLOCK_BREAK_INSN));
}
static inline int arch_spin_is_locked(arch_spinlock_t *x)
{
volatile unsigned int *a;
int lock_val;
a = __ldcw_align(x);
lock_val = READ_ONCE(*a);
arch_spin_val_check(lock_val);
return (lock_val == 0);
}
static inline void arch_spin_lock(arch_spinlock_t *x)
{
volatile unsigned int *a;
a = __ldcw_align(x);
do {
int lock_val_old;
lock_val_old = __ldcw(a);
arch_spin_val_check(lock_val_old);
if (lock_val_old)
return; /* got lock */
/* wait until we should try to get lock again */
while (*a == 0)
continue;
} while (1);
}
static inline void arch_spin_unlock(arch_spinlock_t *x)
{
volatile unsigned int *a;
a = __ldcw_align(x);
/* Release with ordered store. */
__asm__ __volatile__("stw,ma %0,0(%1)"
: : "r"(__ARCH_SPIN_LOCK_UNLOCKED_VAL), "r"(a) : "memory");
}
static inline int arch_spin_trylock(arch_spinlock_t *x)
{
volatile unsigned int *a;
int lock_val;
a = __ldcw_align(x);
lock_val = __ldcw(a);
arch_spin_val_check(lock_val);
return lock_val != 0;
}
/*
* Read-write spinlocks, allowing multiple readers but only one writer.
* Unfair locking as Writers could be starved indefinitely by Reader(s)
*
* The spinlock itself is contained in @counter and access to it is
* serialized with @lock_mutex.
*/
/* 1 - lock taken successfully */
static inline int arch_read_trylock(arch_rwlock_t *rw)
{
int ret = 0;
unsigned long flags;
local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
/*
* zero means writer holds the lock exclusively, deny Reader.
* Otherwise grant lock to first/subseq reader
*/
if (rw->counter > 0) {
rw->counter--;
ret = 1;
}
arch_spin_unlock(&(rw->lock_mutex));
local_irq_restore(flags);
return ret;
}
/* 1 - lock taken successfully */
static inline int arch_write_trylock(arch_rwlock_t *rw)
{
int ret = 0;
unsigned long flags;
local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
/*
* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
* deny writer. Otherwise if unlocked grant to writer
* Hence the claim that Linux rwlocks are unfair to writers.
* (can be starved for an indefinite time by readers).
*/
if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
rw->counter = 0;
ret = 1;
}
arch_spin_unlock(&(rw->lock_mutex));
local_irq_restore(flags);
return ret;
}
static inline void arch_read_lock(arch_rwlock_t *rw)
{
while (!arch_read_trylock(rw))
cpu_relax();
}
static inline void arch_write_lock(arch_rwlock_t *rw)
{
while (!arch_write_trylock(rw))
cpu_relax();
}
static inline void arch_read_unlock(arch_rwlock_t *rw)
{
unsigned long flags;
local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
rw->counter++;
arch_spin_unlock(&(rw->lock_mutex));
local_irq_restore(flags);
}
static inline void arch_write_unlock(arch_rwlock_t *rw)
{
unsigned long flags;
local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
arch_spin_unlock(&(rw->lock_mutex));
local_irq_restore(flags);
}
#endif /* __ASM_SPINLOCK_H */
linux-7.2.3/arch/parisc/include/asm/spinlock_types.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SPINLOCK_TYPES_H
#define __ASM_SPINLOCK_TYPES_H
#define __ARCH_SPIN_LOCK_UNLOCKED_VAL 0x1a46
#define SPINLOCK_BREAK_INSN 0x0000c006 /* break 6,6 */
#ifndef __ASSEMBLER__
typedef struct {
volatile unsigned int lock[4];
# define __ARCH_SPIN_LOCK_UNLOCKED \
{ { __ARCH_SPIN_LOCK_UNLOCKED_VAL, __ARCH_SPIN_LOCK_UNLOCKED_VAL, \
__ARCH_SPIN_LOCK_UNLOCKED_VAL, __ARCH_SPIN_LOCK_UNLOCKED_VAL } }
} arch_spinlock_t;
/* counter:
* Unlocked : 0x0100_0000
* Read lock(s) : 0x00FF_FFFF to 0x01 (Multiple Readers decrement it)
* Write lock : 0x0, but only if prior value is "unlocked" 0x0100_0000
*/
typedef struct {
arch_spinlock_t lock_mutex;
volatile unsigned int counter;
} arch_rwlock_t;
#endif /* __ASSEMBLER__ */
#define __ARCH_RW_LOCK_UNLOCKED__ 0x01000000
#define __ARCH_RW_LOCK_UNLOCKED { .lock_mutex = __ARCH_SPIN_LOCK_UNLOCKED, \
.counter = __ARCH_RW_LOCK_UNLOCKED__ }
#endif
linux-7.2.3/arch/parisc/include/asm/string.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PA_STRING_H_
#define _PA_STRING_H_
#define __HAVE_ARCH_MEMSET
extern void * memset(void *, int, size_t);
#define __HAVE_ARCH_MEMCPY
void * memcpy(void * dest,const void *src,size_t count);
#endif
linux-7.2.3/arch/parisc/include/asm/superio.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PARISC_SUPERIO_H
#define _PARISC_SUPERIO_H
#define IC_PIC1 0x20 /* PCI I/O address of master 8259 */
#define IC_PIC2 0xA0 /* PCI I/O address of slave */
/* Config Space Offsets to configuration and base address registers */
#define SIO_CR 0x5A /* Configuration Register */
#define SIO_ACPIBAR 0x88 /* ACPI BAR */
#define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
#define SIO_SP1BAR 0x94 /* Serial 1 BAR */
#define SIO_SP2BAR 0x98 /* Serial 2 BAR */
#define SIO_PPBAR 0x9C /* Parallel BAR */
#define TRIGGER_1 0x67 /* Edge/level trigger register 1 */
#define TRIGGER_2 0x68 /* Edge/level trigger register 2 */
/* Interrupt Routing Control registers */
#define CFG_IR_SER 0x69 /* Serial 1 [0:3] and Serial 2 [4:7] */
#define CFG_IR_PFD 0x6a /* Parallel [0:3] and Floppy [4:7] */
#define CFG_IR_IDE 0x6b /* IDE1 [0:3] and IDE2 [4:7] */
#define CFG_IR_INTAB 0x6c /* PCI INTA [0:3] and INT B [4:7] */
#define CFG_IR_INTCD 0x6d /* PCI INTC [0:3] and INT D [4:7] */
#define CFG_IR_PS2 0x6e /* PS/2 KBINT [0:3] and Mouse [4:7] */
#define CFG_IR_FXBUS 0x6f /* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
#define CFG_IR_USB 0x70 /* FXIRQ[2] [0:3] and USB [4:7] */
#define CFG_IR_ACPI 0x71 /* ACPI SCI [0:3] and reserved [4:7] */
#define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
#define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
/* 8259 operational control words */
#define OCW2_EOI 0x20 /* Non-specific EOI */
#define OCW2_SEOI 0x60 /* Specific EOI */
#define OCW3_IIR 0x0A /* Read request register */
#define OCW3_ISR 0x0B /* Read service register */
#define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
/* Interrupt lines. Only PIC1 is used */
#define USB_IRQ 1 /* USB */
#define SP1_IRQ 3 /* Serial port 1 */
#define SP2_IRQ 4 /* Serial port 2 */
#define PAR_IRQ 5 /* Parallel port */
#define FDC_IRQ 6 /* Floppy controller */
#define IDE_IRQ 7 /* IDE (pri+sec) */
/* ACPI registers */
#define USB_REG_CR 0x1f /* USB Regulator Control Register */
#define SUPERIO_NIRQS 8
struct superio_device {
u32 fdc_base;
u32 sp1_base;
u32 sp2_base;
u32 pp_base;
u32 acpi_base;
int suckyio_irq_enabled;
struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
struct pci_dev *usb_pdev; /* pci device for USB (fn 2) */
};
/*
* Does NS make a 87415 based plug in PCI card? If so, because of this
* macro we currently don't support it being plugged into a machine
* that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
*
* This could be fixed by checking to see if function 1 exists, and
* if it is SuperIO Legacy IO; but really now, is this combination
* going to EVER happen?
*/
#define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
#define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
#define SUPERIO_USB_FN 2 /* Function number of USB controller */
#define is_superio_device(x) \
(((x)->vendor == PCI_VENDOR_ID_NS) && \
( ((x)->device == PCI_DEVICE_ID_NS_87415) \
|| ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
|| ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
#endif /* _PARISC_SUPERIO_H */
linux-7.2.3/arch/parisc/include/asm/switch_to.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PARISC_SWITCH_TO_H
#define __PARISC_SWITCH_TO_H
struct task_struct;
extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
#define switch_to(prev, next, last) do { \
(last) = _switch_to(prev, next); \
} while(0)
#endif /* __PARISC_SWITCH_TO_H */

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