Resguardo inicial

This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
@@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
config PPC_MICROWATT
depends on PPC_BOOK3S_64
bool "Microwatt SoC platform"
select PPC_XICS
select PPC_ICS_NATIVE
select PPC_ICP_NATIVE
select PPC_UDBG_16550
select COMMON_CLK
help
This option enables support for FPGA-based Microwatt implementations.
@@ -0,0 +1,2 @@
obj-y += setup.o rng.o
obj-$(CONFIG_SMP) += smp.o
@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _MICROWATT_H
#define _MICROWATT_H
void microwatt_rng_init(void);
void microwatt_init_smp(void);
#endif /* _MICROWATT_H */
@@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Derived from arch/powerpc/platforms/powernv/rng.c, which is:
* Copyright 2013, Michael Ellerman, IBM Corporation.
*/
#define pr_fmt(fmt) "microwatt-rng: " fmt
#include <linux/kernel.h>
#include <linux/smp.h>
#include <asm/archrandom.h>
#include <asm/cputable.h>
#include <asm/machdep.h>
#include "microwatt.h"
#define DARN_ERR 0xFFFFFFFFFFFFFFFFul
static int microwatt_get_random_darn(unsigned long *v)
{
unsigned long val;
/* Using DARN with L=1 - 64-bit conditioned random number */
asm volatile(PPC_DARN(%0, 1) : "=r"(val));
if (val == DARN_ERR)
return 0;
*v = val;
return 1;
}
void __init microwatt_rng_init(void)
{
unsigned long val;
int i;
for (i = 0; i < 10; i++) {
if (microwatt_get_random_darn(&val)) {
ppc_md.get_random_seed = microwatt_get_random_darn;
return;
}
}
}
@@ -0,0 +1,61 @@
/*
* Microwatt FPGA-based SoC platform setup code.
*
* Copyright 2020 Paul Mackerras (paulus@ozlabs.org), IBM Corp.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/xics.h>
#include <asm/udbg.h>
#include "microwatt.h"
static void __init microwatt_init_IRQ(void)
{
xics_init();
}
static int __init microwatt_populate(void)
{
return of_platform_default_populate(NULL, NULL, NULL);
}
machine_arch_initcall(microwatt, microwatt_populate);
static int __init microwatt_probe(void)
{
/* Main reason for having this is to start the other CPU(s) */
if (IS_ENABLED(CONFIG_SMP))
microwatt_init_smp();
return 1;
}
static void __init microwatt_setup_arch(void)
{
microwatt_rng_init();
}
static void microwatt_idle(void)
{
if (!prep_irq_for_idle_irqsoff())
return;
__asm__ __volatile__ ("wait");
}
define_machine(microwatt) {
.name = "microwatt",
.compatible = "microwatt-soc",
.probe = microwatt_probe,
.init_IRQ = microwatt_init_IRQ,
.setup_arch = microwatt_setup_arch,
.progress = udbg_progress,
.power_save = microwatt_idle,
};
@@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SMP support functions for Microwatt
* Copyright 2025 Paul Mackerras <paulus@ozlabs.org>
*/
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/early_ioremap.h>
#include <asm/ppc-opcode.h>
#include <asm/reg.h>
#include <asm/smp.h>
#include <asm/xics.h>
#include "microwatt.h"
static void __init microwatt_smp_probe(void)
{
xics_smp_probe();
}
static void microwatt_smp_setup_cpu(int cpu)
{
if (cpu != 0)
xics_setup_cpu();
}
static struct smp_ops_t microwatt_smp_ops = {
.probe = microwatt_smp_probe,
.message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
.kick_cpu = smp_generic_kick_cpu,
.setup_cpu = microwatt_smp_setup_cpu,
};
/* XXX get from device tree */
#define SYSCON_BASE 0xc0000000
#define SYSCON_LENGTH 0x100
#define SYSCON_CPU_CTRL 0x58
void __init microwatt_init_smp(void)
{
volatile unsigned char __iomem *syscon;
int ncpus;
int timeout;
syscon = early_ioremap(SYSCON_BASE, SYSCON_LENGTH);
if (syscon == NULL) {
pr_err("Failed to map SYSCON\n");
return;
}
ncpus = (readl(syscon + SYSCON_CPU_CTRL) >> 8) & 0xff;
if (ncpus < 2)
goto out;
smp_ops = &microwatt_smp_ops;
/*
* Write two instructions at location 0:
* mfspr r3, PIR
* b __secondary_hold
*/
*(unsigned int *)KERNELBASE = PPC_RAW_MFSPR(3, SPRN_PIR);
*(unsigned int *)(KERNELBASE+4) = PPC_RAW_BRANCH(&__secondary_hold - (char *)(KERNELBASE+4));
/* enable the other CPUs, they start at location 0 */
writel((1ul << ncpus) - 1, syscon + SYSCON_CPU_CTRL);
timeout = 10000;
while (!__secondary_hold_acknowledge) {
if (--timeout == 0)
break;
barrier();
}
out:
early_iounmap((void *)syscon, SYSCON_LENGTH);
}