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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/riscv/boot/dts/starfive/Makefile
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# SPDX-License-Identifier: GPL-2.0
# Enables support for device-tree overlays
DTC_FLAGS_jh7100-beaglev-starlight := -@
DTC_FLAGS_jh7100-starfive-visionfive-v1 := -@
DTC_FLAGS_jh7110-starfive-visionfive-2-v1.2a := -@
DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b := -@
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-deepcomputing-fml13v01.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-orangepi-rv.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100-common.dtsi"
/ {
model = "BeagleV Starlight Beta";
compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
};
&gmac {
phy-handle = <&phy>;
};
&mdio {
phy: ethernet-phy@7 {
reg = <7>;
reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
};
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
/ {
aliases {
mmc0 = &sdio0;
mmc1 = &sdio1;
serial0 = &uart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <6250000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x0>;
};
leds {
compatible = "gpio-leds";
led-ack {
gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
label = "ack";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-reserved@fa000000 {
reg = <0x0 0xfa000000 0x0 0x1000000>;
no-map;
};
linux,dma@107a000000 {
compatible = "shared-dma-pool";
reg = <0x10 0x7a000000 0x0 0x1000000>;
no-map;
linux,dma-default;
};
};
soc {
dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
<0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
<0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins>;
phy-mode = "rgmii-id";
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
&gpio {
gmac_pins: gmac-0 {
gtxclk-pins {
pins = <PAD_FUNC_SHARE(115)>;
bias-pull-up;
drive-strength = <35>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
miitxclk-pins {
pins = <PAD_FUNC_SHARE(116)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
tx-pins {
pins = <PAD_FUNC_SHARE(117)>,
<PAD_FUNC_SHARE(119)>,
<PAD_FUNC_SHARE(120)>,
<PAD_FUNC_SHARE(121)>,
<PAD_FUNC_SHARE(122)>,
<PAD_FUNC_SHARE(123)>,
<PAD_FUNC_SHARE(124)>,
<PAD_FUNC_SHARE(125)>,
<PAD_FUNC_SHARE(126)>;
bias-pull-up;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rxclk-pins {
pins = <PAD_FUNC_SHARE(127)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <6>;
};
rxer-pins {
pins = <PAD_FUNC_SHARE(129)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = <PAD_FUNC_SHARE(128)>,
<PAD_FUNC_SHARE(130)>,
<PAD_FUNC_SHARE(131)>,
<PAD_FUNC_SHARE(132)>,
<PAD_FUNC_SHARE(133)>,
<PAD_FUNC_SHARE(134)>,
<PAD_FUNC_SHARE(135)>,
<PAD_FUNC_SHARE(136)>,
<PAD_FUNC_SHARE(137)>,
<PAD_FUNC_SHARE(138)>,
<PAD_FUNC_SHARE(139)>,
<PAD_FUNC_SHARE(140)>,
<PAD_FUNC_SHARE(141)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(62, GPO_LOW,
GPO_I2C0_PAD_SCK_OEN,
GPI_I2C0_PAD_SCK_IN)>,
<GPIOMUX(61, GPO_LOW,
GPO_I2C0_PAD_SDA_OEN,
GPI_I2C0_PAD_SDA_IN)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c1_pins: i2c1-0 {
i2c-pins {
pinmux = <GPIOMUX(47, GPO_LOW,
GPO_I2C1_PAD_SCK_OEN,
GPI_I2C1_PAD_SCK_IN)>,
<GPIOMUX(48, GPO_LOW,
GPO_I2C1_PAD_SDA_OEN,
GPI_I2C1_PAD_SDA_IN)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
i2c2_pins: i2c2-0 {
i2c-pins {
pinmux = <GPIOMUX(60, GPO_LOW,
GPO_I2C2_PAD_SCK_OEN,
GPI_I2C2_PAD_SCK_IN)>,
<GPIOMUX(59, GPO_LOW,
GPO_I2C2_PAD_SDA_OEN,
GPI_I2C2_PAD_SDA_IN)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
pwm_pins: pwm-0 {
pwm-pins {
pinmux = <GPIOMUX(7,
GPO_PWM_PAD_OUT_BIT0,
GPO_PWM_PAD_OE_N_BIT0,
GPI_NONE)>,
<GPIOMUX(5,
GPO_PWM_PAD_OUT_BIT1,
GPO_PWM_PAD_OE_N_BIT1,
GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
sdio0_pins: sdio0-0 {
clk-pins {
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
GPI_SDIO0_PAD_CARD_DETECT_N)>,
<GPIOMUX(53,
GPO_SDIO0_PAD_CCMD_OUT,
GPO_SDIO0_PAD_CCMD_OEN,
GPI_SDIO0_PAD_CCMD_IN)>,
<GPIOMUX(49,
GPO_SDIO0_PAD_CDATA_OUT_BIT0,
GPO_SDIO0_PAD_CDATA_OEN_BIT0,
GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(50,
GPO_SDIO0_PAD_CDATA_OUT_BIT1,
GPO_SDIO0_PAD_CDATA_OEN_BIT1,
GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(51,
GPO_SDIO0_PAD_CDATA_OUT_BIT2,
GPO_SDIO0_PAD_CDATA_OEN_BIT2,
GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(52,
GPO_SDIO0_PAD_CDATA_OUT_BIT3,
GPO_SDIO0_PAD_CDATA_OEN_BIT3,
GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
sdio1_pins: sdio1-0 {
clk-pins {
pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(29,
GPO_SDIO1_PAD_CCMD_OUT,
GPO_SDIO1_PAD_CCMD_OEN,
GPI_SDIO1_PAD_CCMD_IN)>,
<GPIOMUX(36,
GPO_SDIO1_PAD_CDATA_OUT_BIT0,
GPO_SDIO1_PAD_CDATA_OEN_BIT0,
GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(30,
GPO_SDIO1_PAD_CDATA_OUT_BIT1,
GPO_SDIO1_PAD_CDATA_OEN_BIT1,
GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(34,
GPO_SDIO1_PAD_CDATA_OUT_BIT2,
GPO_SDIO1_PAD_CDATA_OEN_BIT2,
GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(31,
GPO_SDIO1_PAD_CDATA_OUT_BIT3,
GPO_SDIO1_PAD_CDATA_OEN_BIT3,
GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
GPI_UART3_PAD_SIN)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
tx-pins {
pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&i2c0 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
pmic@5e {
compatible = "ti,tps65086";
reg = <0x5e>;
gpio-controller;
#gpio-cells = <2>;
regulators {
};
};
};
&i2c1 {
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <100>;
i2c-scl-falling-time-ns = <100>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&osc_sys {
clock-frequency = <25000000>;
};
&osc_aud {
clock-frequency = <27000000>;
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&sdio0 {
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_pins>;
status = "okay";
};
&sdio1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
cap-power-off-card;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_pins>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7100-common.dtsi"
/ {
model = "StarFive VisionFive V1";
compatible = "starfive,visionfive-v1", "starfive,jh7100";
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
};
&gmac {
phy-handle = <&phy>;
};
/*
* The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
* manual adjustment of the RX internal delay to work properly. The default
* RX delay provided by the driver (1.95ns) is too high, but applying a 50%
* reduction seems to mitigate the issue.
*
* It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
* which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
* responsible for the misbehaviour, not the GMAC.
*/
&mdio {
phy: ethernet-phy@0 {
reg = <0>;
rx-internal-delay-ps = <900>;
};
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7100.dtsi
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2021 StarFive Technology Co., Ltd.
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100.h>
/ {
compatible = "starfive,jh7100";
#address-cells = <2>;
#size-cells = <2>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
U74_0: cpu@0 {
compatible = "sifive,u74-mc", "riscv";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
reg = <1>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
tlb-split;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&U74_0>;
};
core1 {
cpu = <&U74_1>;
};
};
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <15000>;
thermal-sensors = <&sfctemp>;
trips {
cpu-alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu-crit {
/* milliCelsius */
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
osc_sys: osc-sys {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "osc_sys";
/* This value must be overridden by the board */
clock-frequency = <0>;
};
osc_aud: osc-aud {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "osc_aud";
/* This value must be overridden by the board */
clock-frequency = <0>;
};
gmac_rmii_ref: gmac-rmii-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "gmac_rmii_ref";
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "gmac_gr_mii_rxclk";
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
};
ccache: cache-controller@2010000 {
compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
interrupts = <128>, <130>, <131>, <129>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
riscv,ndev = <133>;
};
sdio0: mmc@10000000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
<&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
clock-names = "biu", "ciu";
interrupts = <4>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
sdio1: mmc@10010000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
<&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
clock-names = "biu", "ciu";
interrupts = <5>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
gmac: ethernet@10020000 {
compatible = "starfive,jh7100-dwmac", "snps,dwmac";
reg = <0x0 0x10020000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
<&clkgen JH7100_CLK_GMAC_AHB>,
<&clkgen JH7100_CLK_GMAC_PTP_REF>,
<&clkgen JH7100_CLK_GMAC_TX_INV>,
<&clkgen JH7100_CLK_GMAC_GTX>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
reset-names = "ahb";
interrupts = <6>, <7>;
interrupt-names = "macirq", "eth_wake_irq";
max-frame-size = <9000>;
snps,multicast-filter-bins = <32>;
snps,perfect-filter-entries = <128>;
starfive,syscon = <&sysmain 0x70 0>;
rx-fifo-depth = <32768>;
tx-fifo-depth = <16384>;
snps,axi-config = <&stmmac_axi_setup>;
snps,fixed-burst;
snps,force_thresh_dma_mode;
status = "disabled";
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <16>;
snps,rd_osr_lmt = <16>;
snps,blen = <256 128 64 32 0 0 0>;
};
};
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
#clock-cells = <1>;
};
rstgen: reset-controller@11840000 {
compatible = "starfive,jh7100-reset";
reg = <0x0 0x11840000 0x0 0x10000>;
#reset-cells = <1>;
};
sysmain: syscon@11850000 {
compatible = "starfive,jh7100-sysmain", "syscon";
reg = <0x0 0x11850000 0x0 0x10000>;
};
i2c0: i2c@118b0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
<&clkgen JH7100_CLK_I2C0_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C0_APB>;
interrupts = <96>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@118c0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x118c0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
<&clkgen JH7100_CLK_I2C1_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C1_APB>;
interrupts = <97>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpio: pinctrl@11910000 {
compatible = "starfive,jh7100-pinctrl";
reg = <0x0 0x11910000 0x0 0x10000>,
<0x0 0x11858000 0x0 0x1000>;
reg-names = "gpio", "padctl";
clocks = <&clkgen JH7100_CLK_GPIO_APB>;
resets = <&rstgen JH7100_RSTN_GPIO_APB>;
interrupts = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart2: serial@12430000 {
compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
reg = <0x0 0x12430000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_UART2_CORE>,
<&clkgen JH7100_CLK_UART2_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&rstgen JH7100_RSTN_UART2_APB>;
interrupts = <72>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart3: serial@12440000 {
compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
reg = <0x0 0x12440000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_UART3_CORE>,
<&clkgen JH7100_CLK_UART3_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&rstgen JH7100_RSTN_UART3_APB>;
interrupts = <73>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c2: i2c@12450000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12450000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
<&clkgen JH7100_CLK_I2C2_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C2_APB>;
interrupts = <74>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@12460000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12460000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
<&clkgen JH7100_CLK_I2C3_APB>;
clock-names = "ref", "pclk";
resets = <&rstgen JH7100_RSTN_I2C3_APB>;
interrupts = <75>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog@12480000 {
compatible = "starfive,jh7100-wdt";
reg = <0x0 0x12480000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
<&clkgen JH7100_CLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
pwm: pwm@12490000 {
compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
reg = <0x0 0x12490000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};
sfctemp: temperature-sensor@124a0000 {
compatible = "starfive,jh7100-temp";
reg = <0x0 0x124a0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
<&clkgen JH7100_CLK_TEMP_APB>;
clock-names = "sense", "bus";
resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
<&rstgen JH7100_RSTN_TEMP_APB>;
reset-names = "sense", "bus";
#thermal-sensor-cells = <0>;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+631
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@@ -0,0 +1,631 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110.dtsi"
#include "jh7110-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
/ {
aliases {
ethernet0 = &gmac0;
i2c0 = &i2c0;
i2c2 = &i2c2;
i2c5 = &i2c5;
i2c6 = &i2c6;
mmc0 = &mmc0;
mmc1 = &mmc1;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x1 0x0>;
bootph-pre-ram;
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
priority = <224>;
};
leds {
compatible = "gpio-leds";
led_status_power: led-0 {
gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
};
};
pwmdac_codec: audio-codec {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
format = "left_j";
bitclock-master = <&sndcpu0>;
frame-master = <&sndcpu0>;
sndcpu0: cpu {
sound-dai = <&pwmdac>;
};
codec {
sound-dai = <&pwmdac_codec>;
};
};
};
};
&cpus {
timebase-frequency = <4000000>;
};
&dvp_clk {
clock-frequency = <74250000>;
};
&gmac0_rgmii_rxin {
clock-frequency = <125000000>;
};
&gmac0_rmii_refin {
clock-frequency = <50000000>;
};
&gmac1_rgmii_rxin {
clock-frequency = <125000000>;
};
&gmac1_rmii_refin {
clock-frequency = <50000000>;
};
&hdmitx0_pixelclk {
clock-frequency = <297000000>;
};
&i2srx_bclk_ext {
clock-frequency = <12288000>;
};
&i2srx_lrck_ext {
clock-frequency = <192000>;
};
&i2stx_bclk_ext {
clock-frequency = <12288000>;
};
&i2stx_lrck_ext {
clock-frequency = <192000>;
};
&mclk_ext {
clock-frequency = <12288000>;
};
&osc {
clock-frequency = <24000000>;
};
&rtc_osc {
clock-frequency = <32768>;
};
&tdm_ext {
clock-frequency = <49152000>;
};
&csi2rx {
assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
assigned-clock-rates = <297000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
/* remote MIPI sensor endpoint */
};
port@1 {
reg = <1>;
/* remote CAMSS endpoint */
};
};
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&i2c0 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
};
&i2c2 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&i2c5 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
axp15060: pmic@36 {
compatible = "x-powers,axp15060";
reg = <0x36>;
interrupt-controller;
#interrupt-cells = <1>;
regulators {
vcc_3v3: dcdc1 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3";
};
vdd_cpu: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1540000>;
regulator-name = "vdd_cpu";
};
emmc_vdd: aldo4 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "emmc_vdd";
};
};
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
bootph-pre-ram;
pagesize = <16>;
};
};
&i2c6 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <510>;
i2c-scl-falling-time-ns = <510>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
status = "okay";
};
&mmc0 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <8>;
bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "okay";
};
&mmc1 {
max-frequency = <100000000>;
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
assigned-clock-rates = <50000000>;
bus-width = <4>;
bootph-pre-ram;
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "okay";
};
&pcie0 {
perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
phys = <&pciephy0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
};
&pcie1 {
perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
};
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac_pins>;
};
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nor_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
bootph-pre-ram;
cdns,read-delay = <2>;
spi-max-frequency = <100000000>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
spl@0 {
reg = <0x0 0xf0000>;
};
uboot-env@f0000 {
reg = <0xf0000 0x10000>;
};
uboot@100000 {
reg = <0x100000 0xf00000>;
};
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
};
&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
<&syscrg JH7110_SYSCLK_PERH_ROOT>,
<&syscrg JH7110_SYSCLK_QSPI_REF>,
<&syscrg JH7110_SYSCLK_CPU_CORE>,
<&pllclk JH7110_PLLCLK_PLL0_OUT>;
assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
<&pllclk JH7110_PLLCLK_PLL2_OUT>,
<&pllclk JH7110_PLLCLK_PLL2_OUT>,
<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
};
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(57, GPOUT_LOW,
GPOEN_SYS_I2C0_CLK,
GPI_SYS_I2C0_CLK)>,
<GPIOMUX(58, GPOUT_LOW,
GPOEN_SYS_I2C0_DATA,
GPI_SYS_I2C0_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c2_pins: i2c2-0 {
i2c-pins {
pinmux = <GPIOMUX(3, GPOUT_LOW,
GPOEN_SYS_I2C2_CLK,
GPI_SYS_I2C2_CLK)>,
<GPIOMUX(2, GPOUT_LOW,
GPOEN_SYS_I2C2_DATA,
GPI_SYS_I2C2_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c5_pins: i2c5-0 {
bootph-pre-ram;
i2c-pins {
pinmux = <GPIOMUX(19, GPOUT_LOW,
GPOEN_SYS_I2C5_CLK,
GPI_SYS_I2C5_CLK)>,
<GPIOMUX(20, GPOUT_LOW,
GPOEN_SYS_I2C5_DATA,
GPI_SYS_I2C5_DATA)>;
bias-disable; /* external pull-up */
bootph-pre-ram;
input-enable;
input-schmitt-enable;
};
};
i2c6_pins: i2c6-0 {
i2c-pins {
pinmux = <GPIOMUX(16, GPOUT_LOW,
GPOEN_SYS_I2C6_CLK,
GPI_SYS_I2C6_CLK)>,
<GPIOMUX(17, GPOUT_LOW,
GPOEN_SYS_I2C6_DATA,
GPI_SYS_I2C6_DATA)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
mmc0_pins: mmc0-0 {
mmc-pins {
pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
<PINMUX(PAD_SD0_CMD, 0)>,
<PINMUX(PAD_SD0_DATA0, 0)>,
<PINMUX(PAD_SD0_DATA1, 0)>,
<PINMUX(PAD_SD0_DATA2, 0)>,
<PINMUX(PAD_SD0_DATA3, 0)>,
<PINMUX(PAD_SD0_DATA4, 0)>,
<PINMUX(PAD_SD0_DATA5, 0)>,
<PINMUX(PAD_SD0_DATA6, 0)>,
<PINMUX(PAD_SD0_DATA7, 0)>;
bias-pull-up;
drive-strength = <12>;
input-enable;
};
};
mmc1_pins: mmc1-0 {
clk-pins {
pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
mmc-pins {
pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
GPOEN_SYS_SDIO1_CMD,
GPI_SYS_SDIO1_CMD)>,
<GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
GPOEN_SYS_SDIO1_DATA0,
GPI_SYS_SDIO1_DATA0)>,
<GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
GPOEN_SYS_SDIO1_DATA1,
GPI_SYS_SDIO1_DATA1)>,
<GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
GPOEN_SYS_SDIO1_DATA2,
GPI_SYS_SDIO1_DATA2)>,
<GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
GPOEN_SYS_SDIO1_DATA3,
GPI_SYS_SDIO1_DATA3)>;
bias-pull-up;
drive-strength = <12>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
pcie0_pins: pcie0-0 {
clkreq-pins {
pinmux = <GPIOMUX(27, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(32, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pcie1_pins: pcie1-0 {
clkreq-pins {
pinmux = <GPIOMUX(29, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(21, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pwmdac_pins: pwmdac-0 {
pwmdac-pins {
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
GPOEN_ENABLE,
GPI_NONE)>,
<GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <2>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pwm_pins: pwm-0 {
pwm-pins {
pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
GPOEN_SYS_PWM0_CHANNEL0,
GPI_NONE)>,
<GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
GPOEN_SYS_PWM0_CHANNEL1,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
spi0_pins: spi0-0 {
mosi-pins {
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
miso-pins {
pinmux = <GPIOMUX(53, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_SPI0_RXD)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
sck-pins {
pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
GPOEN_ENABLE,
GPI_SYS_SPI0_CLK)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
ss-pins {
pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
};
uart0_pins: uart0-0 {
tx-pins {
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pinmux = <GPIOMUX(6, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART0_RX)>;
bias-disable; /* external pull-up */
drive-strength = <2>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&uart0 {
bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&U74_1 {
cpu-supply = <&vdd_cpu>;
};
&U74_2 {
cpu-supply = <&vdd_cpu>;
};
&U74_3 {
cpu-supply = <&vdd_cpu>;
};
&U74_4 {
cpu-supply = <&vdd_cpu>;
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+97
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@@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 DeepComputing (HK) Limited
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
model = "DeepComputing FML13V01";
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
};
&mmc0 {
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
};
&mmc0_pins {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
&mmc1 {
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
disable-wp;
};
&pcie1 {
perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&sysgpio {
pcie1_pins: pcie1-0 {
clkreq-pins {
pinmux = <GPIOMUX(29, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(28, GPOUT_HIGH,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
usb0_pins: usb0-0 {
vbus-pins {
pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
model = "Milk-V Mars";
compatible = "milkv,mars", "starfive,jh7110";
};
&gmac0 {
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
starfive,tx-use-rgmii-clk;
status = "okay";
};
&i2c0 {
status = "okay";
};
&mmc0 {
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
};
&mmc0_pins {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
&mmc1 {
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
disable-wp;
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&phy0 {
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
motorcomm,tx-clk-10-inverted;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,tx-clk-adj-enabled;
};
&pwm {
status = "okay";
};
&pwmdac {
status = "okay";
};
&spi0 {
status = "okay";
};
&sysgpio {
usb0_pins: usb0-0 {
vbus-pins {
pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 E Shattow <e@freeshell.de>
*/
/dts-v1/;
#include "jh7110-milkv-marscm.dtsi"
/ {
model = "Milk-V Mars CM";
compatible = "milkv,marscm-emmc", "starfive,jh7110";
};
&mmc0 {
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 E Shattow <e@freeshell.de>
*/
/dts-v1/;
#include "jh7110-milkv-marscm.dtsi"
/ {
model = "Milk-V Mars CM Lite";
compatible = "milkv,marscm-lite", "starfive,jh7110";
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
disable-wp;
};
&mmc0_pins {
pwren-pins {
pinmux = <GPIOMUX(22, GPOUT_HIGH,
GPOEN_ENABLE,
GPI_NONE)>;
};
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 E Shattow <e@freeshell.de>
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include "jh7110-common.dtsi"
/ {
aliases {
i2c1 = &i2c1;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial3 = &uart3;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&sysgpio 33 GPIO_ACTIVE_LOW>;
};
};
&gmac0 {
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
starfive,tx-use-rgmii-clk;
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c2 {
status = "disabled";
};
&i2c6 {
status = "disabled";
};
&mmc0_pins {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
&mmc1 {
#address-cells = <1>;
#size-cells = <0>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
status = "okay";
ap6256: wifi@1 {
compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&sysgpio>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-0 = <&wifi_host_wake_irq>;
pinctrl-names = "default";
};
};
&pcie0 {
status = "okay";
};
&phy0 {
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
motorcomm,tx-clk-10-inverted;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,tx-clk-adj-enabled;
};
&pwm {
status = "okay";
};
&spi0 {
status = "okay";
};
&sysgpio {
uart1_pins: uart1-0 {
tx-pins {
pinmux = <GPIOMUX(16, GPOUT_SYS_UART1_TX,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
};
rx-pins {
pinmux = <GPIOMUX(17, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART1_RX)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
cts-pins {
pinmux = <GPIOMUX(3, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART1_CTS)>;
bias-disable;
input-enable;
input-schmitt-enable;
};
rts-pins {
pinmux = <GPIOMUX(2, GPOUT_SYS_UART1_RTS,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
};
usb0_pins: usb0-0 {
vbus-pins {
pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
wifi_host_wake_irq: wifi-host-wake-irq-0 {
wake-pins {
pinmux = <GPIOMUX(34, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
input-enable;
};
};
};
&uart1 {
uart-has-rtscts;
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-orangepi-rv.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
model = "Xunlong Orange Pi RV";
compatible = "xunlong,orangepi-rv", "starfive,jh7110";
/* This regulator is always on by hardware */
reg_vcc3v3_pcie: regulator-vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3-pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&sysgpio 62 GPIO_ACTIVE_LOW>;
};
};
&gmac0 {
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
starfive,tx-use-rgmii-clk;
status = "okay";
};
&mmc0 {
#address-cells = <1>;
#size-cells = <0>;
cap-sd-highspeed;
mmc-pwrseq = <&wifi_pwrseq>;
vmmc-supply = <&reg_vcc3v3_pcie>;
vqmmc-supply = <&vcc_3v3>;
status = "okay";
ap6256: wifi@1 {
compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* TODO: out-of-band IRQ on GPIO21, lacking pinctrl support */
};
};
&mmc1 {
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&phy0 {
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-10-inverted;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
};
&pwmdac {
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
model = "Pine64 Star64";
compatible = "pine64,star64", "starfive,jh7110";
aliases {
ethernet1 = &gmac1;
};
};
&gmac0 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
status = "okay";
};
&gmac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
starfive,tx-use-rgmii-clk;
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
&i2c0 {
status = "okay";
};
&mmc0 {
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
};
&mmc0_pins {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
&mmc1 {
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
disable-wp;
};
&pcie1 {
status = "okay";
};
&phy0 {
rx-internal-delay-ps = <1500>;
motorcomm,rx-clk-drv-microamp = <2910>;
motorcomm,rx-data-drv-microamp = <2910>;
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-10-inverted;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
};
&phy1 {
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <300>;
motorcomm,rx-clk-drv-microamp = <2910>;
motorcomm,rx-data-drv-microamp = <2910>;
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-10-inverted;
motorcomm,tx-clk-100-inverted;
};
&pwm {
status = "okay";
};
&pwmdac {
status = "okay";
};
&spi0 {
status = "okay";
};
&sysgpio {
usb0_pins: usb0-0 {
vbus-pins {
pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __JH7110_PINFUNC_H__
#define __JH7110_PINFUNC_H__
/*
* mux bits:
* | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
* | din | dout | doen | function | gpio nr |
*
* dout: output signal
* doen: output enable signal
* din: optional input signal, 0xff = none
* function: function selector
* gpio nr: gpio number, 0 - 63
*/
#define GPIOMUX(n, dout, doen, din) ( \
(((din) & 0xff) << 24) | \
(((dout) & 0xff) << 16) | \
(((doen) & 0x3f) << 10) | \
((n) & 0x3f))
#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
/* sys_iomux dout */
#define GPOUT_LOW 0
#define GPOUT_HIGH 1
#define GPOUT_SYS_WAVE511_UART_TX 2
#define GPOUT_SYS_CAN0_STBY 3
#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4
#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5
#define GPOUT_SYS_CAN0_TXD 6
#define GPOUT_SYS_USB_DRIVE_VBUS 7
#define GPOUT_SYS_QSPI_CS1 8
#define GPOUT_SYS_SPDIF 9
#define GPOUT_SYS_HDMI_CEC_SDA 10
#define GPOUT_SYS_HDMI_DDC_SCL 11
#define GPOUT_SYS_HDMI_DDC_SDA 12
#define GPOUT_SYS_WATCHDOG 13
#define GPOUT_SYS_I2C0_CLK 14
#define GPOUT_SYS_I2C0_DATA 15
#define GPOUT_SYS_SDIO0_BACK_END_POWER 16
#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17
#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18
#define GPOUT_SYS_SDIO0_RST 19
#define GPOUT_SYS_UART0_TX 20
#define GPOUT_SYS_HIFI4_JTAG_TDO 21
#define GPOUT_SYS_JTAG_TDO 22
#define GPOUT_SYS_PDM_MCLK 23
#define GPOUT_SYS_PWM_CHANNEL0 24
#define GPOUT_SYS_PWM_CHANNEL1 25
#define GPOUT_SYS_PWM_CHANNEL2 26
#define GPOUT_SYS_PWM_CHANNEL3 27
#define GPOUT_SYS_PWMDAC_LEFT 28
#define GPOUT_SYS_PWMDAC_RIGHT 29
#define GPOUT_SYS_SPI0_CLK 30
#define GPOUT_SYS_SPI0_FSS 31
#define GPOUT_SYS_SPI0_TXD 32
#define GPOUT_SYS_GMAC_PHYCLK 33
#define GPOUT_SYS_I2SRX_BCLK 34
#define GPOUT_SYS_I2SRX_LRCK 35
#define GPOUT_SYS_I2STX0_BCLK 36
#define GPOUT_SYS_I2STX0_LRCK 37
#define GPOUT_SYS_MCLK 38
#define GPOUT_SYS_TDM_CLK 39
#define GPOUT_SYS_TDM_SYNC 40
#define GPOUT_SYS_TDM_TXD 41
#define GPOUT_SYS_TRACE_DATA0 42
#define GPOUT_SYS_TRACE_DATA1 43
#define GPOUT_SYS_TRACE_DATA2 44
#define GPOUT_SYS_TRACE_DATA3 45
#define GPOUT_SYS_TRACE_REF 46
#define GPOUT_SYS_CAN1_STBY 47
#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48
#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49
#define GPOUT_SYS_CAN1_TXD 50
#define GPOUT_SYS_I2C1_CLK 51
#define GPOUT_SYS_I2C1_DATA 52
#define GPOUT_SYS_SDIO1_BACK_END_POWER 53
#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54
#define GPOUT_SYS_SDIO1_CLK 55
#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56
#define GPOUT_SYS_SDIO1_CMD 57
#define GPOUT_SYS_SDIO1_DATA0 58
#define GPOUT_SYS_SDIO1_DATA1 59
#define GPOUT_SYS_SDIO1_DATA2 60
#define GPOUT_SYS_SDIO1_DATA3 61
#define GPOUT_SYS_SDIO1_DATA4 62
#define GPOUT_SYS_SDIO1_DATA5 63
#define GPOUT_SYS_SDIO1_DATA6 64
#define GPOUT_SYS_SDIO1_DATA7 65
#define GPOUT_SYS_SDIO1_RST 66
#define GPOUT_SYS_UART1_RTS 67
#define GPOUT_SYS_UART1_TX 68
#define GPOUT_SYS_I2STX1_SDO0 69
#define GPOUT_SYS_I2STX1_SDO1 70
#define GPOUT_SYS_I2STX1_SDO2 71
#define GPOUT_SYS_I2STX1_SDO3 72
#define GPOUT_SYS_SPI1_CLK 73
#define GPOUT_SYS_SPI1_FSS 74
#define GPOUT_SYS_SPI1_TXD 75
#define GPOUT_SYS_I2C2_CLK 76
#define GPOUT_SYS_I2C2_DATA 77
#define GPOUT_SYS_UART2_RTS 78
#define GPOUT_SYS_UART2_TX 79
#define GPOUT_SYS_SPI2_CLK 80
#define GPOUT_SYS_SPI2_FSS 81
#define GPOUT_SYS_SPI2_TXD 82
#define GPOUT_SYS_I2C3_CLK 83
#define GPOUT_SYS_I2C3_DATA 84
#define GPOUT_SYS_UART3_TX 85
#define GPOUT_SYS_SPI3_CLK 86
#define GPOUT_SYS_SPI3_FSS 87
#define GPOUT_SYS_SPI3_TXD 88
#define GPOUT_SYS_I2C4_CLK 89
#define GPOUT_SYS_I2C4_DATA 90
#define GPOUT_SYS_UART4_RTS 91
#define GPOUT_SYS_UART4_TX 92
#define GPOUT_SYS_SPI4_CLK 93
#define GPOUT_SYS_SPI4_FSS 94
#define GPOUT_SYS_SPI4_TXD 95
#define GPOUT_SYS_I2C5_CLK 96
#define GPOUT_SYS_I2C5_DATA 97
#define GPOUT_SYS_UART5_RTS 98
#define GPOUT_SYS_UART5_TX 99
#define GPOUT_SYS_SPI5_CLK 100
#define GPOUT_SYS_SPI5_FSS 101
#define GPOUT_SYS_SPI5_TXD 102
#define GPOUT_SYS_I2C6_CLK 103
#define GPOUT_SYS_I2C6_DATA 104
#define GPOUT_SYS_SPI6_CLK 105
#define GPOUT_SYS_SPI6_FSS 106
#define GPOUT_SYS_SPI6_TXD 107
/* aon_iomux dout */
#define GPOUT_AON_CLK_32K_OUT 2
#define GPOUT_AON_PTC0_PWM4 3
#define GPOUT_AON_PTC0_PWM5 4
#define GPOUT_AON_PTC0_PWM6 5
#define GPOUT_AON_PTC0_PWM7 6
#define GPOUT_AON_CLK_GCLK0 7
#define GPOUT_AON_CLK_GCLK1 8
#define GPOUT_AON_CLK_GCLK2 9
/* sys_iomux doen */
#define GPOEN_ENABLE 0
#define GPOEN_DISABLE 1
#define GPOEN_SYS_HDMI_CEC_SDA 2
#define GPOEN_SYS_HDMI_DDC_SCL 3
#define GPOEN_SYS_HDMI_DDC_SDA 4
#define GPOEN_SYS_I2C0_CLK 5
#define GPOEN_SYS_I2C0_DATA 6
#define GPOEN_SYS_HIFI4_JTAG_TDO 7
#define GPOEN_SYS_JTAG_TDO 8
#define GPOEN_SYS_PWM0_CHANNEL0 9
#define GPOEN_SYS_PWM0_CHANNEL1 10
#define GPOEN_SYS_PWM0_CHANNEL2 11
#define GPOEN_SYS_PWM0_CHANNEL3 12
#define GPOEN_SYS_SPI0_NSSPCTL 13
#define GPOEN_SYS_SPI0_NSSP 14
#define GPOEN_SYS_TDM_SYNC 15
#define GPOEN_SYS_TDM_TXD 16
#define GPOEN_SYS_I2C1_CLK 17
#define GPOEN_SYS_I2C1_DATA 18
#define GPOEN_SYS_SDIO1_CMD 19
#define GPOEN_SYS_SDIO1_DATA0 20
#define GPOEN_SYS_SDIO1_DATA1 21
#define GPOEN_SYS_SDIO1_DATA2 22
#define GPOEN_SYS_SDIO1_DATA3 23
#define GPOEN_SYS_SDIO1_DATA4 24
#define GPOEN_SYS_SDIO1_DATA5 25
#define GPOEN_SYS_SDIO1_DATA6 26
#define GPOEN_SYS_SDIO1_DATA7 27
#define GPOEN_SYS_SPI1_NSSPCTL 28
#define GPOEN_SYS_SPI1_NSSP 29
#define GPOEN_SYS_I2C2_CLK 30
#define GPOEN_SYS_I2C2_DATA 31
#define GPOEN_SYS_SPI2_NSSPCTL 32
#define GPOEN_SYS_SPI2_NSSP 33
#define GPOEN_SYS_I2C3_CLK 34
#define GPOEN_SYS_I2C3_DATA 35
#define GPOEN_SYS_SPI3_NSSPCTL 36
#define GPOEN_SYS_SPI3_NSSP 37
#define GPOEN_SYS_I2C4_CLK 38
#define GPOEN_SYS_I2C4_DATA 39
#define GPOEN_SYS_SPI4_NSSPCTL 40
#define GPOEN_SYS_SPI4_NSSP 41
#define GPOEN_SYS_I2C5_CLK 42
#define GPOEN_SYS_I2C5_DATA 43
#define GPOEN_SYS_SPI5_NSSPCTL 44
#define GPOEN_SYS_SPI5_NSSP 45
#define GPOEN_SYS_I2C6_CLK 46
#define GPOEN_SYS_I2C6_DATA 47
#define GPOEN_SYS_SPI6_NSSPCTL 48
#define GPOEN_SYS_SPI6_NSSP 49
/* aon_iomux doen */
#define GPOEN_AON_PTC0_OE_N_4 2
#define GPOEN_AON_PTC0_OE_N_5 3
#define GPOEN_AON_PTC0_OE_N_6 4
#define GPOEN_AON_PTC0_OE_N_7 5
/* sys_iomux gin */
#define GPI_NONE 255
#define GPI_SYS_WAVE511_UART_RX 0
#define GPI_SYS_CAN0_RXD 1
#define GPI_SYS_USB_OVERCURRENT 2
#define GPI_SYS_SPDIF 3
#define GPI_SYS_JTAG_RST 4
#define GPI_SYS_HDMI_CEC_SDA 5
#define GPI_SYS_HDMI_DDC_SCL 6
#define GPI_SYS_HDMI_DDC_SDA 7
#define GPI_SYS_HDMI_HPD 8
#define GPI_SYS_I2C0_CLK 9
#define GPI_SYS_I2C0_DATA 10
#define GPI_SYS_SDIO0_CD 11
#define GPI_SYS_SDIO0_INT 12
#define GPI_SYS_SDIO0_WP 13
#define GPI_SYS_UART0_RX 14
#define GPI_SYS_HIFI4_JTAG_TCK 15
#define GPI_SYS_HIFI4_JTAG_TDI 16
#define GPI_SYS_HIFI4_JTAG_TMS 17
#define GPI_SYS_HIFI4_JTAG_RST 18
#define GPI_SYS_JTAG_TDI 19
#define GPI_SYS_JTAG_TMS 20
#define GPI_SYS_PDM_DMIC0 21
#define GPI_SYS_PDM_DMIC1 22
#define GPI_SYS_I2SRX_SDIN0 23
#define GPI_SYS_I2SRX_SDIN1 24
#define GPI_SYS_I2SRX_SDIN2 25
#define GPI_SYS_SPI0_CLK 26
#define GPI_SYS_SPI0_FSS 27
#define GPI_SYS_SPI0_RXD 28
#define GPI_SYS_JTAG_TCK 29
#define GPI_SYS_MCLK_EXT 30
#define GPI_SYS_I2SRX_BCLK 31
#define GPI_SYS_I2SRX_LRCK 32
#define GPI_SYS_I2STX1_BCLK 33
#define GPI_SYS_I2STX1_LRCK 34
#define GPI_SYS_TDM_CLK 35
#define GPI_SYS_TDM_RXD 36
#define GPI_SYS_TDM_SYNC 37
#define GPI_SYS_CAN1_RXD 38
#define GPI_SYS_I2C1_CLK 39
#define GPI_SYS_I2C1_DATA 40
#define GPI_SYS_SDIO1_CD 41
#define GPI_SYS_SDIO1_INT 42
#define GPI_SYS_SDIO1_WP 43
#define GPI_SYS_SDIO1_CMD 44
#define GPI_SYS_SDIO1_DATA0 45
#define GPI_SYS_SDIO1_DATA1 46
#define GPI_SYS_SDIO1_DATA2 47
#define GPI_SYS_SDIO1_DATA3 48
#define GPI_SYS_SDIO1_DATA4 49
#define GPI_SYS_SDIO1_DATA5 50
#define GPI_SYS_SDIO1_DATA6 51
#define GPI_SYS_SDIO1_DATA7 52
#define GPI_SYS_SDIO1_STRB 53
#define GPI_SYS_UART1_CTS 54
#define GPI_SYS_UART1_RX 55
#define GPI_SYS_SPI1_CLK 56
#define GPI_SYS_SPI1_FSS 57
#define GPI_SYS_SPI1_RXD 58
#define GPI_SYS_I2C2_CLK 59
#define GPI_SYS_I2C2_DATA 60
#define GPI_SYS_UART2_CTS 61
#define GPI_SYS_UART2_RX 62
#define GPI_SYS_SPI2_CLK 63
#define GPI_SYS_SPI2_FSS 64
#define GPI_SYS_SPI2_RXD 65
#define GPI_SYS_I2C3_CLK 66
#define GPI_SYS_I2C3_DATA 67
#define GPI_SYS_UART3_RX 68
#define GPI_SYS_SPI3_CLK 69
#define GPI_SYS_SPI3_FSS 70
#define GPI_SYS_SPI3_RXD 71
#define GPI_SYS_I2C4_CLK 72
#define GPI_SYS_I2C4_DATA 73
#define GPI_SYS_UART4_CTS 74
#define GPI_SYS_UART4_RX 75
#define GPI_SYS_SPI4_CLK 76
#define GPI_SYS_SPI4_FSS 77
#define GPI_SYS_SPI4_RXD 78
#define GPI_SYS_I2C5_CLK 79
#define GPI_SYS_I2C5_DATA 80
#define GPI_SYS_UART5_CTS 81
#define GPI_SYS_UART5_RX 82
#define GPI_SYS_SPI5_CLK 83
#define GPI_SYS_SPI5_FSS 84
#define GPI_SYS_SPI5_RXD 85
#define GPI_SYS_I2C6_CLK 86
#define GPI_SYS_I2C6_DATA 87
#define GPI_SYS_SPI6_CLK 88
#define GPI_SYS_SPI6_FSS 89
#define GPI_SYS_SPI6_RXD 90
/* aon_iomux gin */
#define GPI_AON_PMU_GPIO_WAKEUP_0 0
#define GPI_AON_PMU_GPIO_WAKEUP_1 1
#define GPI_AON_PMU_GPIO_WAKEUP_2 2
#define GPI_AON_PMU_GPIO_WAKEUP_3 3
#endif
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 StarFive Technology Co., Ltd.
* Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
*/
/dts-v1/;
#include "jh7110-starfive-visionfive-2-lite.dtsi"
/ {
model = "StarFive VisionFive 2 Lite eMMC";
compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s", "starfive,jh7110";
};
&mmc0 {
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 StarFive Technology Co., Ltd.
* Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
*/
/dts-v1/;
#include "jh7110-starfive-visionfive-2-lite.dtsi"
/ {
model = "StarFive VisionFive 2 Lite";
compatible = "starfive,visionfive-2-lite", "starfive,jh7110s", "starfive,jh7110";
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
disable-wp;
cap-sd-highspeed;
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 StarFive Technology Co., Ltd.
* Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
vcc_3v3_pcie: regulator-vcc-3v3-pcie {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc_3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cpu_opp {
/delete-node/ opp-375000000;
/delete-node/ opp-500000000;
/delete-node/ opp-750000000;
/delete-node/ opp-1500000000;
opp-312500000 {
opp-hz = /bits/ 64 <312500000>;
opp-microvolt = <800000>;
};
opp-417000000 {
opp-hz = /bits/ 64 <417000000>;
opp-microvolt = <800000>;
};
opp-625000000 {
opp-hz = /bits/ 64 <625000000>;
opp-microvolt = <800000>;
};
opp-1250000000 {
opp-hz = /bits/ 64 <1250000000>;
opp-microvolt = <1000000>;
};
};
&gmac0 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&mmc1 {
max-frequency = <50000000>;
keep-power-in-suspend;
non-removable;
};
&pcie1 {
vpcie3v3-supply = <&vcc_3v3_pcie>;
status = "okay";
};
&phy0 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
};
&pwm {
status = "okay";
};
&spi0 {
status = "okay";
};
&syscrg {
assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
};
&sysgpio {
uart1_pins: uart1-0 {
tx-pins {
pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pinmux = <GPIOMUX(23, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART1_RX)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
cts-pins {
pinmux = <GPIOMUX(24, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART1_CTS)>;
input-enable;
};
rts-pins {
pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
GPOEN_ENABLE,
GPI_NONE)>;
input-enable;
};
};
usb0_pins: usb0-0 {
power-pins {
pinmux = <GPIOMUX(26, GPOUT_HIGH,
GPOEN_ENABLE,
GPI_NONE)>;
input-disable;
};
switch-pins {
pinmux = <GPIOMUX(62, GPOUT_LOW,
GPOEN_ENABLE,
GPI_NONE)>;
input-disable;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110-starfive-visionfive-2.dtsi"
/ {
model = "StarFive VisionFive 2 v1.2A";
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
};
&gmac1 {
phy-mode = "rmii";
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
<&syscrg JH7110_SYSCLK_GMAC1_RX>;
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
<&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
};
&phy0 {
rx-internal-delay-ps = <1900>;
tx-internal-delay-ps = <1350>;
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110-starfive-visionfive-2.dtsi"
/ {
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
};
&gmac0 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
};
&gmac1 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
};
&phy0 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
};
&phy1 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
rx-internal-delay-ps = <300>;
tx-internal-delay-ps = <0>;
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
aliases {
ethernet1 = &gmac1;
};
};
&gmac0 {
status = "okay";
};
&gmac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@1 {
reg = <0>;
};
};
};
&i2c0 {
status = "okay";
};
&mmc0 {
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&emmc_vdd>;
non-removable;
};
&mmc0_pins {
rst-pins {
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
GPOEN_ENABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
&mmc1 {
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
disable-wp;
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pwm {
status = "okay";
};
&pwmdac {
status = "okay";
};
&spi0 {
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/starfive/jh7110.dtsi
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