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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/riscv/boot/dts/thead/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb
linux-7.2.3/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Drew Fustini <dfustini@baylibre.com>
*/
/dts-v1/;
#include "th1520.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
model = "BeagleV Ahead";
compatible = "beagle,beaglev-ahead", "thead,th1520";
aliases {
ethernet0 = &gmac0;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
spi0 = &spi0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x1 0x00000000>;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
compatible = "gpio-leds";
led-1 {
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led1";
};
led-2 {
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led2";
};
led-3 {
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led3";
};
led-4 {
gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led4";
};
led-5 {
gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
label = "led5";
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "d";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
};
};
&osc {
clock-frequency = <24000000>;
};
&osc_32k {
clock-frequency = <32768>;
};
&dmac0 {
status = "okay";
};
&emmc {
bus-width = <8>;
max-frequency = <198000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&gmac0 {
pinctrl-names = "default";
pinctrl-0 = <&gmac0_pins>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&mdio0 {
phy0: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
reset-post-delay-us = <50000>;
};
};
&padctrl_aosys {
led_pins: led-0 {
led-pins {
pins = "AUDIO_PA8", /* GPIO4_8 */
"AUDIO_PA9", /* GPIO4_9 */
"AUDIO_PA10", /* GPIO4_10 */
"AUDIO_PA11", /* GPIO4_11 */
"AUDIO_PA12"; /* GPIO4_12 */
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&padctrl0_apsys {
gmac0_pins: gmac0-0 {
tx-pins {
pins = "GMAC0_TX_CLK",
"GMAC0_TXEN",
"GMAC0_TXD0",
"GMAC0_TXD1",
"GMAC0_TXD2",
"GMAC0_TXD3";
function = "gmac0";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "GMAC0_RX_CLK",
"GMAC0_RXDV",
"GMAC0_RXD0",
"GMAC0_RXD1",
"GMAC0_RXD2",
"GMAC0_RXD3";
function = "gmac0";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
mdc-pins {
pins = "GMAC0_MDC";
function = "gmac0";
bias-disable;
drive-strength = <13>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
mdio-pins {
pins = "GMAC0_MDIO";
function = "gmac0";
bias-disable;
drive-strength = <13>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
phy-reset-pins {
pins = "GMAC0_COL"; /* GPIO3_21 */
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
phy-interrupt-pins {
pins = "GMAC0_CRS"; /* GPIO3_22 */
function = "gpio";
bias-pull-up;
drive-strength = <1>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
uart0_pins: uart0-0 {
tx-pins {
pins = "UART0_TXD";
function = "uart";
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "UART0_RXD";
function = "uart";
bias-pull-up;
drive-strength = <1>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
wifi_pins: wifi-0 {
host-wake-pins {
pins = "GPIO2_25";
function = "gpio";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
reg-on-pins {
pins = "GPIO2_31";
function = "gpio";
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;
status = "okay";
};
&sdio1 {
bus-width = <4>;
max-frequency = <198000000>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins>;
#address-cells = <1>;
#size-cells = <0>;
non-removable;
keep-power-in-suspend;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
wifi@1 {
compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "host-wake";
};
};
&dpu {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out_port {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
/dts-v1/;
#include "th1520.dtsi"
/ {
model = "Sipeed Lichee Module 4A";
compatible = "sipeed,lichee-module-4a", "thead,th1520";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x2 0x00000000>;
};
};
&osc {
clock-frequency = <24000000>;
};
&osc_32k {
clock-frequency = <32768>;
};
&aogpio {
gpio-line-names = "", "", "",
"GPIO00",
"GPIO04";
};
&dmac0 {
status = "okay";
};
&emmc {
bus-width = <8>;
max-frequency = <198000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&gmac0 {
pinctrl-names = "default";
pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&gmac1 {
pinctrl-names = "default";
pinctrl-0 = <&gmac1_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};
&gpio0 {
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "",
"GPIO07",
"GPIO08",
"",
"GPIO01",
"GPIO02";
};
&gpio1 {
gpio-line-names = "", "", "",
"GPIO11",
"GPIO12",
"GPIO13",
"GPIO14",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "",
"GPIO06";
};
&gpio2 {
gpio-line-names = "GPIO03",
"GPIO05";
};
&gpio3 {
gpio-line-names = "", "",
"GPIO09",
"GPIO10";
};
&mdio0 {
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@2 {
reg = <2>;
};
};
&padctrl0_apsys {
gmac0_pins: gmac0-0 {
tx-pins {
pins = "GMAC0_TX_CLK",
"GMAC0_TXEN",
"GMAC0_TXD0",
"GMAC0_TXD1",
"GMAC0_TXD2",
"GMAC0_TXD3";
function = "gmac0";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "GMAC0_RX_CLK",
"GMAC0_RXDV",
"GMAC0_RXD0",
"GMAC0_RXD1",
"GMAC0_RXD2",
"GMAC0_RXD3";
function = "gmac0";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
gmac1_pins: gmac1-0 {
tx-pins {
pins = "GPIO2_18", /* GMAC1_TX_CLK */
"GPIO2_20", /* GMAC1_TXEN */
"GPIO2_21", /* GMAC1_TXD0 */
"GPIO2_22", /* GMAC1_TXD1 */
"GPIO2_23", /* GMAC1_TXD2 */
"GPIO2_24"; /* GMAC1_TXD3 */
function = "gmac1";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "GPIO2_19", /* GMAC1_RX_CLK */
"GPIO2_25", /* GMAC1_RXDV */
"GPIO2_30", /* GMAC1_RXD0 */
"GPIO2_31", /* GMAC1_RXD1 */
"GPIO3_0", /* GMAC1_RXD2 */
"GPIO3_1"; /* GMAC1_RXD3 */
function = "gmac1";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
mdio0_pins: mdio0-0 {
mdc-pins {
pins = "GMAC0_MDC";
function = "gmac0";
bias-disable;
drive-strength = <13>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
mdio-pins {
pins = "GMAC0_MDIO";
function = "gmac0";
bias-disable;
drive-strength = <13>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&sdio0 {
bus-width = <4>;
max-frequency = <198000000>;
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include "th1520-lichee-module-4a.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Sipeed Lichee Pi 4A";
compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
spi0 = &spi0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&ioexp2 4 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <200>;
};
thermal-zones {
cpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&pvt 0>;
trips {
fan_config0: fan-trip0 {
temperature = <39000>;
hysteresis = <5000>;
type = "active";
};
fan_config1: fan-trip1 {
temperature = <50000>;
hysteresis = <5000>;
type = "active";
};
fan_config2: fan-trip2 {
temperature = <60000>;
hysteresis = <5000>;
type = "active";
};
};
cooling-maps {
map-active-0 {
cooling-device = <&fan 1 1>;
trip = <&fan_config0>;
};
map-active-1 {
cooling-device = <&fan 2 2>;
trip = <&fan_config1>;
};
map-active-2 {
cooling-device = <&fan 3 3>;
trip = <&fan_config2>;
};
};
};
};
fan: pwm-fan {
pinctrl-names = "default";
pinctrl-0 = <&fan_pins>;
compatible = "pwm-fan";
#cooling-cells = <2>;
pwms = <&pwm 1 10000000 0>;
cooling-levels = <0 66 196 255>;
};
};
&padctrl1_apsys {
i2c1_pins: i2c1-0 {
i2c-pins {
pins = "I2C1_SCL", "I2C1_SDA";
function = "i2c";
bias-pull-up = <2100>;
drive-strength = <7>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&padctrl0_apsys {
fan_pins: fan-0 {
pwm1-pins {
pins = "GPIO3_3"; /* PWM1 */
function = "pwm";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
uart0_pins: uart0-0 {
tx-pins {
pins = "UART0_TXD";
function = "uart";
bias-disable;
drive-strength = <3>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = "UART0_RXD";
function = "uart";
bias-disable;
drive-strength = <1>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
ioexp2: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
};
&sdio1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
max-frequency = <198000000>;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
};
&dpu {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out_port {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/thead/th1520.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
#include <dt-bindings/power/thead,th1520-power.h>
#include <dt-bindings/reset/thead,th1520-reset.h>
/ {
compatible = "thead,th1520";
#address-cells = <2>;
#size-cells = <2>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <3000000>;
c910_0: cpu@0 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
next-level-cache = <&l2_cache>;
mmu-type = "riscv,sv39";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
c910_1: cpu@1 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
next-level-cache = <&l2_cache>;
mmu-type = "riscv,sv39";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
c910_2: cpu@2 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
next-level-cache = <&l2_cache>;
mmu-type = "riscv,sv39";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
c910_3: cpu@3 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
next-level-cache = <&l2_cache>;
mmu-type = "riscv,sv39";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
l2_cache: l2-cache {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <1048576>;
cache-sets = <1024>;
cache-unified;
};
};
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmcounters =
<0x00003 0x00003 0x0007fff8>,
<0x00004 0x00004 0x0007fff8>,
<0x00005 0x00005 0x0007fff8>,
<0x00006 0x00006 0x0007fff8>,
<0x00007 0x00007 0x0007fff8>,
<0x00008 0x00008 0x0007fff8>,
<0x00009 0x00009 0x0007fff8>,
<0x0000a 0x0000a 0x0007fff8>,
<0x10000 0x10000 0x0007fff8>,
<0x10001 0x10001 0x0007fff8>,
<0x10002 0x10002 0x0007fff8>,
<0x10003 0x10003 0x0007fff8>,
<0x10010 0x10010 0x0007fff8>,
<0x10011 0x10011 0x0007fff8>,
<0x10012 0x10012 0x0007fff8>,
<0x10013 0x10013 0x0007fff8>;
riscv,event-to-mhpmevent =
<0x00003 0x00000000 0x00000001>,
<0x00004 0x00000000 0x00000002>,
<0x00006 0x00000000 0x00000006>,
<0x00005 0x00000000 0x00000007>,
<0x00007 0x00000000 0x00000008>,
<0x00008 0x00000000 0x00000009>,
<0x00009 0x00000000 0x0000000a>,
<0x0000a 0x00000000 0x0000000b>,
<0x10000 0x00000000 0x0000000c>,
<0x10001 0x00000000 0x0000000d>,
<0x10002 0x00000000 0x0000000e>,
<0x10003 0x00000000 0x0000000f>,
<0x10010 0x00000000 0x00000010>,
<0x10011 0x00000000 0x00000011>,
<0x10012 0x00000000 0x00000012>,
<0x10013 0x00000000 0x00000013>;
riscv,raw-event-to-mhpmcounters =
<0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>,
<0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>;
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_24m";
#clock-cells = <0>;
};
osc_32k: 32k-oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_32k";
#clock-cells = <0>;
};
aonsys_clk: clock-73728000 {
compatible = "fixed-clock";
clock-frequency = <73728000>;
clock-output-names = "aonsys_clk";
#clock-cells = <0>;
};
gpu_mem_clk: mem-clk {
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "gpu_mem_clk";
#clock-cells = <0>;
};
stmmac_axi_config: stmmac-axi-config {
snps,wr_osr_lmt = <15>;
snps,rd_osr_lmt = <15>;
snps,blen = <0 0 64 32 0 0 0>;
};
aon: aon {
compatible = "thead,th1520-aon";
mboxes = <&mbox_910t 1>;
mbox-names = "aon";
resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>;
reset-names = "gpu-clkgen";
#power-domain-cells = <1>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
plic: interrupt-controller@ffd8000000 {
compatible = "thead,th1520-plic", "thead,c900-plic";
reg = <0xff 0xd8000000 0x0 0x01000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <240>;
};
clint: timer@ffdc000000 {
compatible = "thead,th1520-clint", "thead,c900-clint";
reg = <0xff 0xdc000000 0x0 0x00010000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>;
};
rst_vi: reset-controller@ffe4040100 {
compatible = "thead,th1520-reset-vi";
reg = <0xff 0xe4040100 0x0 0x8>;
#reset-cells = <1>;
};
spi0: spi@ffe700c000 {
compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
reg = <0xff 0xe700c000 0x0 0x1000>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
gmac1: ethernet@ffe7060000 {
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
reg-names = "dwmac", "apb";
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>,
<&clk CLK_PERISYS_APB4_HCLK>;
clock-names = "stmmaceth", "pclk", "apb";
snps,pbl = <32>;
snps,fixed-burst;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
snps,axi-config = <&stmmac_axi_config>;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
gmac0: ethernet@ffe7070000 {
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
reg-names = "dwmac", "apb";
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>,
<&clk CLK_PERISYS_APB4_HCLK>;
clock-names = "stmmaceth", "pclk", "apb";
snps,pbl = <32>;
snps,fixed-burst;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <32>;
snps,axi-config = <&stmmac_axi_config>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
emmc: mmc@ffe7080000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
sdio0: mmc@ffe7090000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
sdio1: mmc@ffe70a0000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
uart1: serial@ffe7f00000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f00000 0x0 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@ffe7f04000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f04000 0x0 0x100>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
i2c1: i2c@ffe7f24000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xe7f24000 0x0 0x4000>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>;
clock-names = "ref", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO2>;
clock-names = "bus";
gpio2: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&padctrl0_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio@ffe7f38000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO3>;
clock-names = "bus";
gpio3: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <23>;
gpio-ranges = <&padctrl0_apsys 0 32 23>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
};
};
padctrl1_apsys: pinctrl@ffe7f3c000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xe7f3c000 0x0 0x1000>;
clocks = <&clk CLK_PADCTRL1>;
thead,pad-group = <2>;
};
gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO0>;
clock-names = "bus";
gpio0: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
gpio-ranges = <&padctrl1_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO1>;
clock-names = "bus";
gpio1: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <31>;
gpio-ranges = <&padctrl1_apsys 0 32 31>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
};
};
padctrl0_apsys: pinctrl@ffec007000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xec007000 0x0 0x1000>;
clocks = <&clk CLK_PADCTRL0>;
thead,pad-group = <3>;
};
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
pwm: pwm@ffec01c000 {
compatible = "thead,th1520-pwm";
reg = <0xff 0xec01c000 0x0 0x4000>;
clocks = <&clk CLK_PWM>;
#pwm-cells = <3>;
};
rst_misc: reset-controller@ffec02c000 {
compatible = "thead,th1520-reset-misc";
reg = <0xff 0xec02c000 0x0 0x18>;
#reset-cells = <1>;
};
rst_vp: reset-controller@ffecc30000 {
compatible = "thead,th1520-reset-vp";
reg = <0xff 0xecc30000 0x0 0x14>;
#reset-cells = <1>;
};
clk: clock-controller@ffef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xff 0xef010000 0x0 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
rst_ap: reset-controller@ffef014000 {
compatible = "thead,th1520-reset-ap";
reg = <0xff 0xef014000 0x0 0x1000>;
#reset-cells = <1>;
};
rst_dsp: reset-controller@ffef040028 {
compatible = "thead,th1520-reset-dsp";
reg = <0xff 0xef040028 0x0 0x4>;
#reset-cells = <1>;
};
gpu: gpu@ffef400000 {
compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
"img,img-rogue";
reg = <0xff 0xef400000 0x0 0x100000>;
interrupt-parent = <&plic>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_GPU_CORE>,
<&gpu_mem_clk>,
<&clk_vo CLK_GPU_CFG_ACLK>;
clock-names = "core", "mem", "sys";
power-domains = <&aon TH1520_GPU_PD>;
resets = <&rst TH1520_RESET_ID_GPU>;
};
rst: reset-controller@ffef528000 {
compatible = "thead,th1520-reset";
reg = <0xff 0xef528000 0x0 0x4f>;
#reset-cells = <1>;
};
clk_vo: clock-controller@ffef528050 {
compatible = "thead,th1520-clk-vo";
reg = <0xff 0xef528050 0x0 0xfb0>;
clocks = <&clk CLK_VIDEO_PLL>;
#clock-cells = <1>;
};
hdmi: hdmi@ffef540000 {
compatible = "thead,th1520-dw-hdmi";
reg = <0xff 0xef540000 0x0 0x40000>;
reg-io-width = <4>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_HDMI_PCLK>,
<&clk_vo CLK_HDMI_SFR>,
<&clk_vo CLK_HDMI_CEC>,
<&clk_vo CLK_HDMI_PIXCLK>;
clock-names = "iahb", "isfr", "cec", "pix";
resets = <&rst TH1520_RESET_ID_HDMI>,
<&rst TH1520_RESET_ID_HDMI_APB>;
reset-names = "main", "apb";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&dpu_out_dp1>;
};
};
hdmi_out_port: port@1 {
reg = <1>;
};
};
};
dpu: display@ffef600000 {
compatible = "thead,th1520-dc8200", "verisilicon,dc";
reg = <0xff 0xef600000 0x0 0x100000>;
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_DPU_CCLK>,
<&clk_vo CLK_DPU_ACLK>,
<&clk_vo CLK_DPU_HCLK>,
<&clk_vo CLK_DPU_PIXELCLK0>,
<&clk_vo CLK_DPU_PIXELCLK1>;
clock-names = "core", "axi", "ahb", "pix0", "pix1";
resets = <&rst TH1520_RESET_ID_DPU_CORE>,
<&rst TH1520_RESET_ID_DPU_AXI>,
<&rst TH1520_RESET_ID_DPU_AHB>;
reset-names = "core", "axi", "ahb";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dpu_port1: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dpu_out_dp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in>;
};
};
};
};
dmac0: dma-controller@ffefc00000 {
compatible = "snps,axi-dma-1.01a";
reg = <0xff 0xefc00000 0x0 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
snps,block-size = <65536 65536 65536 65536>;
snps,priority = <0 1 2 3>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,axi-max-burst-len = <16>;
status = "disabled";
};
timer0: timer@ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer1: timer@ffefc32014 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32014 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer2: timer@ffefc32028 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32028 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer3: timer@ffefc3203c {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc3203c 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@fff7f08000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f08000 0x0 0x4000>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart5: serial@fff7f0c000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f0c000 0x0 0x4000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer5: timer@ffffc33014 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33014 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer6: timer@ffffc33028 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33028 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer7: timer@ffffc3303c {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc3303c 0x0 0x14>;
clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mbox_910t: mailbox@ffffc38000 {
compatible = "thead,th1520-mbox";
reg = <0xff 0xffc38000 0x0 0x6000>,
<0xff 0xffc40000 0x0 0x6000>,
<0xff 0xffc4c000 0x0 0x2000>,
<0xff 0xffc54000 0x0 0x2000>;
reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2";
clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>,
<&clk CLK_MBOX3>;
clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1",
"clk-remote-icu2";
interrupt-parent = <&plic>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
gpio@fffff41000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff41000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
aogpio: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
gpio-ranges = <&padctrl_aosys 0 9 16>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
};
};
rst_ao: reset-controller@fffff44000 {
compatible = "thead,th1520-reset-ao";
reg = <0xff 0xfff44000 0x0 0x2000>;
#reset-cells = <1>;
status = "reserved";
};
padctrl_aosys: pinctrl@fffff4a000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xfff4a000 0x0 0x2000>;
clocks = <&aonsys_clk>;
thead,pad-group = <1>;
};
pvt: pvt@fffff4e000 {
compatible = "moortec,mr75203";
reg = <0xff 0xfff4e000 0x0 0x80>,
<0xff 0xfff4e080 0x0 0x100>,
<0xff 0xfff4e180 0x0 0x680>,
<0xff 0xfff4e800 0x0 0x600>;
reg-names = "common", "ts", "pd", "vm";
clocks = <&aonsys_clk>;
#thermal-sensor-cells = <1>;
moortec,ts-coeff-g = <42740>;
moortec,ts-coeff-h = <220500>;
moortec,ts-coeff-j = <(-160)>;
moortec,ts-coeff-cal5 = <4094>;
};
gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
gpio4: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <23>;
gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};