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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/arch/x86/include/asm/uv/bios.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _ASM_X86_UV_BIOS_H
#define _ASM_X86_UV_BIOS_H
/*
* UV BIOS layer definitions.
*
* (C) Copyright 2020 Hewlett Packard Enterprise Development LP
* Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
* Copyright (c) Russ Anderson <rja@sgi.com>
*/
#include <linux/efi.h>
#include <linux/rtc.h>
/*
* Values for the BIOS calls. It is passed as the first * argument in the
* BIOS call. Passing any other value in the first argument will result
* in a BIOS_STATUS_UNIMPLEMENTED return status.
*/
enum uv_bios_cmd {
UV_BIOS_COMMON,
UV_BIOS_GET_SN_INFO,
UV_BIOS_FREQ_BASE,
UV_BIOS_WATCHLIST_ALLOC,
UV_BIOS_WATCHLIST_FREE,
UV_BIOS_MEMPROTECT,
UV_BIOS_GET_PARTITION_ADDR,
UV_BIOS_SET_LEGACY_VGA_TARGET
};
#define UV_BIOS_EXTRA 0x10000
#define UV_BIOS_GET_PCI_TOPOLOGY 0x10001
#define UV_BIOS_GET_GEOINFO 0x10003
#define UV_BIOS_EXTRA_OP_MEM_COPYIN 0x1000
#define UV_BIOS_EXTRA_OP_MEM_COPYOUT 0x2000
#define UV_BIOS_EXTRA_OP_MASK 0x0fff
#define UV_BIOS_EXTRA_GET_HEAPSIZE 1
#define UV_BIOS_EXTRA_INSTALL_HEAP 2
#define UV_BIOS_EXTRA_MASTER_NASID 3
#define UV_BIOS_EXTRA_OBJECT_COUNT (10|UV_BIOS_EXTRA_OP_MEM_COPYOUT)
#define UV_BIOS_EXTRA_ENUM_OBJECTS (12|UV_BIOS_EXTRA_OP_MEM_COPYOUT)
#define UV_BIOS_EXTRA_ENUM_PORTS (13|UV_BIOS_EXTRA_OP_MEM_COPYOUT)
/*
* Status values returned from a BIOS call.
*/
enum {
BIOS_STATUS_MORE_PASSES = 1,
BIOS_STATUS_SUCCESS = 0,
BIOS_STATUS_UNIMPLEMENTED = -ENOSYS,
BIOS_STATUS_EINVAL = -EINVAL,
BIOS_STATUS_UNAVAIL = -EBUSY,
BIOS_STATUS_ABORT = -EINTR,
};
/* Address map parameters */
struct uv_gam_parameters {
u64 mmr_base;
u64 gru_base;
u8 mmr_shift; /* Convert PNode to MMR space offset */
u8 gru_shift; /* Convert PNode to GRU space offset */
u8 gpa_shift; /* Size of offset field in GRU phys addr */
u8 unused1;
};
/* UV_TABLE_GAM_RANGE_ENTRY values */
#define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */
#define UV_GAM_RANGE_TYPE_RAM 1 /* Normal RAM */
#define UV_GAM_RANGE_TYPE_NVRAM 2 /* Non-volatile memory */
#define UV_GAM_RANGE_TYPE_NV_WINDOW 3 /* NVMDIMM block window */
#define UV_GAM_RANGE_TYPE_NV_MAILBOX 4 /* NVMDIMM mailbox */
#define UV_GAM_RANGE_TYPE_HOLE 5 /* Unused address range */
#define UV_GAM_RANGE_TYPE_MAX 6
/* The structure stores PA bits 56:26, for 64MB granularity */
#define UV_GAM_RANGE_SHFT 26 /* 64MB */
struct uv_gam_range_entry {
char type; /* Entry type: GAM_RANGE_TYPE_UNUSED, etc. */
char unused1;
u16 nasid; /* HNasid */
u16 sockid; /* Socket ID, high bits of APIC ID */
u16 pnode; /* Index to MMR and GRU spaces */
u32 unused2;
u32 limit; /* PA bits 56:26 (UV_GAM_RANGE_SHFT) */
};
#define UV_AT_SIZE 8 /* 7 character arch type + NULL char */
struct uv_arch_type_entry {
char archtype[UV_AT_SIZE];
};
#define UV_SYSTAB_SIG "UVST"
#define UV_SYSTAB_VERSION_1 1 /* UV2/3 BIOS version */
#define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */
#define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */
#define UV_SYSTAB_VERSION_UV4_2 0x402 /* + TYPE_NVRAM/WINDOW/MBOX */
#define UV_SYSTAB_VERSION_UV4_3 0x403 /* - GAM Range PXM Value */
#define UV_SYSTAB_VERSION_UV4_LATEST UV_SYSTAB_VERSION_UV4_3
#define UV_SYSTAB_VERSION_UV5 0x500 /* UV5 GAM base version */
#define UV_SYSTAB_VERSION_UV5_LATEST UV_SYSTAB_VERSION_UV5
#define UV_SYSTAB_TYPE_UNUSED 0 /* End of table (offset == 0) */
#define UV_SYSTAB_TYPE_GAM_PARAMS 1 /* GAM PARAM conversions */
#define UV_SYSTAB_TYPE_GAM_RNG_TBL 2 /* GAM entry table */
#define UV_SYSTAB_TYPE_ARCH_TYPE 3 /* UV arch type */
#define UV_SYSTAB_TYPE_MAX 4
/*
* The UV system table describes specific firmware
* capabilities available to the Linux kernel at runtime.
*/
struct uv_systab {
char signature[4]; /* must be UV_SYSTAB_SIG */
u32 revision; /* distinguish different firmware revs */
u64 (__efiapi *function)(enum uv_bios_cmd, ...);
/* BIOS runtime callback function ptr */
u32 size; /* systab size (starting with _VERSION_UV4) */
struct {
u32 type:8; /* type of entry */
u32 offset:24; /* byte offset from struct start to entry */
} entry[]; /* additional entries follow */
};
extern struct uv_systab *uv_systab;
#define UV_BIOS_MAXSTRING 128
struct uv_bios_hub_info {
unsigned int id;
union {
struct {
unsigned long long this_part:1;
unsigned long long is_shared:1;
unsigned long long is_disabled:1;
} fields;
struct {
unsigned long long flags;
unsigned long long reserved;
} b;
} f;
char name[UV_BIOS_MAXSTRING];
char location[UV_BIOS_MAXSTRING];
unsigned int ports;
};
struct uv_bios_port_info {
unsigned int port;
unsigned int conn_id;
unsigned int conn_port;
};
/* (... end of definitions from UV BIOS ...) */
enum {
BIOS_FREQ_BASE_PLATFORM = 0,
BIOS_FREQ_BASE_INTERVAL_TIMER = 1,
BIOS_FREQ_BASE_REALTIME_CLOCK = 2
};
union partition_info_u {
u64 val;
struct {
u64 hub_version : 8,
partition_id : 16,
coherence_id : 16,
region_size : 24;
};
};
enum uv_memprotect {
UV_MEMPROT_RESTRICT_ACCESS,
UV_MEMPROT_ALLOW_AMO,
UV_MEMPROT_ALLOW_RW
};
extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *, long *);
extern s64 uv_bios_freq_base(u64, u64 *);
extern int uv_bios_mq_watchlist_alloc(unsigned long, unsigned int,
unsigned long *);
extern int uv_bios_mq_watchlist_free(int, int);
extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect);
extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *);
extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus);
extern s64 uv_bios_get_master_nasid(u64 sz, u64 *nasid);
extern s64 uv_bios_get_heapsize(u64 nasid, u64 sz, u64 *heap_sz);
extern s64 uv_bios_install_heap(u64 nasid, u64 sz, u64 *heap);
extern s64 uv_bios_obj_count(u64 nasid, u64 sz, u64 *objcnt);
extern s64 uv_bios_enum_objs(u64 nasid, u64 sz, u64 *objbuf);
extern s64 uv_bios_enum_ports(u64 nasid, u64 obj_id, u64 sz, u64 *portbuf);
extern s64 uv_bios_get_geoinfo(u64 nasid, u64 sz, u64 *geo);
extern s64 uv_bios_get_pci_topology(u64 sz, u64 *buf);
extern int uv_bios_init(void);
extern unsigned long get_uv_systab_phys(bool msg);
extern unsigned long sn_rtc_cycles_per_second;
extern int uv_type;
extern long sn_partition_id;
extern long sn_coherency_id;
extern long sn_region_size;
extern long system_serial_number;
extern ssize_t uv_get_archtype(char *buf, int len);
extern int uv_get_hubless_system(void);
extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */
/*
* EFI runtime lock; cf. firmware/efi/runtime-wrappers.c for details
*/
extern struct semaphore __efi_uv_runtime_lock;
#endif /* _ASM_X86_UV_BIOS_H */
linux-7.2.3/arch/x86/include/asm/uv/uv.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_UV_UV_H
#define _ASM_X86_UV_UV_H
enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC};
#ifdef CONFIG_X86_UV
#include <linux/efi.h>
#define UV_PROC_NODE "sgi_uv"
static inline int uv(int uvtype)
{
/* uv(0) is "any" */
if (uvtype >= 0 && uvtype <= 30)
return 1 << uvtype;
return 1;
}
extern unsigned long uv_systab_phys;
extern enum uv_system_type get_uv_system_type(void);
static inline bool is_early_uv_system(void)
{
return uv_systab_phys && uv_systab_phys != EFI_INVALID_TABLE_ADDR;
}
extern int is_uv_system(void);
extern int is_uv_hubbed(int uvtype);
extern void uv_cpu_init(void);
extern void uv_nmi_init(void);
extern void uv_system_init(void);
#else /* !X86_UV */
static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }
static inline bool is_early_uv_system(void) { return 0; }
static inline int is_uv_system(void) { return 0; }
static inline int is_uv_hubbed(int uv) { return 0; }
static inline void uv_cpu_init(void) { }
static inline void uv_system_init(void) { }
#endif /* X86_UV */
#endif /* _ASM_X86_UV_UV_H */
linux-7.2.3/arch/x86/include/asm/uv/uv_geo.h
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/* SPDX-License-Identifier: GPL-2.0-or-later
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2020 Hewlett Packard Enterprise Development LP. All rights reserved.
*/
#ifndef _ASM_UV_GEO_H
#define _ASM_UV_GEO_H
/* Type declarations */
/* Size of a geoid_s structure (must be before decl. of geoid_u) */
#define GEOID_SIZE 8
/* Fields common to all substructures */
struct geo_common_s {
unsigned char type; /* What type of h/w is named by this geoid_s */
unsigned char blade;
unsigned char slot; /* slot is IRU */
unsigned char upos;
unsigned char rack;
};
/* Additional fields for particular types of hardware */
struct geo_node_s {
struct geo_common_s common; /* No additional fields needed */
};
struct geo_rtr_s {
struct geo_common_s common; /* No additional fields needed */
};
struct geo_iocntl_s {
struct geo_common_s common; /* No additional fields needed */
};
struct geo_pcicard_s {
struct geo_iocntl_s common;
char bus; /* Bus/widget number */
char slot; /* PCI slot number */
};
/* Subcomponents of a node */
struct geo_cpu_s {
struct geo_node_s node;
unsigned char socket:4, /* Which CPU on the node */
thread:4;
unsigned char core;
};
struct geo_mem_s {
struct geo_node_s node;
char membus; /* The memory bus on the node */
char memslot; /* The memory slot on the bus */
};
union geoid_u {
struct geo_common_s common;
struct geo_node_s node;
struct geo_iocntl_s iocntl;
struct geo_pcicard_s pcicard;
struct geo_rtr_s rtr;
struct geo_cpu_s cpu;
struct geo_mem_s mem;
char padsize[GEOID_SIZE];
};
/* Defined constants */
#define GEO_MAX_LEN 48
#define GEO_TYPE_INVALID 0
#define GEO_TYPE_MODULE 1
#define GEO_TYPE_NODE 2
#define GEO_TYPE_RTR 3
#define GEO_TYPE_IOCNTL 4
#define GEO_TYPE_IOCARD 5
#define GEO_TYPE_CPU 6
#define GEO_TYPE_MEM 7
#define GEO_TYPE_MAX (GEO_TYPE_MEM+1)
static inline int geo_rack(union geoid_u g)
{
return (g.common.type == GEO_TYPE_INVALID) ?
-1 : g.common.rack;
}
static inline int geo_slot(union geoid_u g)
{
return (g.common.type == GEO_TYPE_INVALID) ?
-1 : g.common.upos;
}
static inline int geo_blade(union geoid_u g)
{
return (g.common.type == GEO_TYPE_INVALID) ?
-1 : g.common.blade * 2 + g.common.slot;
}
#endif /* _ASM_UV_GEO_H */
linux-7.2.3/arch/x86/include/asm/uv/uv_hub.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV architectural definitions
*
* (C) Copyright 2020 Hewlett Packard Enterprise Development LP
* Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_X86_UV_UV_HUB_H
#define _ASM_X86_UV_UV_HUB_H
#ifdef CONFIG_X86_64
#include <linux/numa.h>
#include <linux/percpu.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/topology.h>
#include <asm/types.h>
#include <asm/percpu.h>
#include <asm/uv/uv.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/bios.h>
#include <asm/irq_vectors.h>
#include <asm/io_apic.h>
/*
* Addressing Terminology
*
* M - The low M bits of a physical address represent the offset
* into the blade local memory. RAM memory on a blade is physically
* contiguous (although various IO spaces may punch holes in
* it)..
*
* N - Number of bits in the node portion of a socket physical
* address.
*
* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
* routers always have low bit of 1, C/MBricks have low bit
* equal to 0. Most addressing macros that target UV hub chips
* right shift the NASID by 1 to exclude the always-zero bit.
* NASIDs contain up to 15 bits.
*
* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
* of nasids.
*
* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
* of the nasid for socket usage.
*
* GPA - (global physical address) a socket physical address converted
* so that it can be used by the GRU as a global address. Socket
* physical addresses 1) need additional NASID (node) bits added
* to the high end of the address, and 2) unaliased if the
* partition does not have a physical address 0. In addition, on
* UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40.
*
*
* NumaLink Global Physical Address Format:
* +--------------------------------+---------------------+
* |00..000| GNODE | NodeOffset |
* +--------------------------------+---------------------+
* |<-------53 - M bits --->|<--------M bits ----->
*
* M - number of node offset bits (35 .. 40)
*
*
* Memory/UV-HUB Processor Socket Address Format:
* +----------------+---------------+---------------------+
* |00..000000000000| PNODE | NodeOffset |
* +----------------+---------------+---------------------+
* <--- N bits --->|<--------M bits ----->
*
* M - number of node offset bits (35 .. 40)
* N - number of PNODE bits (0 .. 10)
*
* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
* The actual values are configuration dependent and are set at
* boot time. M & N values are set by the hardware/BIOS at boot.
*
*
* APICID format
* NOTE!!!!!! This is the current format of the APICID. However, code
* should assume that this will change in the future. Use functions
* in this file for all APICID bit manipulations and conversion.
*
* 1111110000000000
* 5432109876543210
* pppppppppplc0cch Nehalem-EX (12 bits in hdw reg)
* ppppppppplcc0cch Westmere-EX (12 bits in hdw reg)
* pppppppppppcccch SandyBridge (15 bits in hdw reg)
* sssssssssss
*
* p = pnode bits
* l = socket number on board
* c = core
* h = hyperthread
* s = bits that are in the SOCKET_ID CSR
*
* Note: Processor may support fewer bits in the APICID register. The ACPI
* tables hold all 16 bits. Software needs to be aware of this.
*
* Unless otherwise specified, all references to APICID refer to
* the FULL value contained in ACPI tables, not the subset in the
* processor APICID register.
*/
/*
* Maximum number of bricks in all partitions and in all coherency domains.
* This is the total number of bricks accessible in the numalink fabric. It
* includes all C & M bricks. Routers are NOT included.
*
* This value is also the value of the maximum number of non-router NASIDs
* in the numalink fabric.
*
* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
*/
#define UV_MAX_NUMALINK_BLADES 16384
/*
* Maximum number of C/Mbricks within a software SSI (hardware may support
* more).
*/
#define UV_MAX_SSI_BLADES 256
/*
* The largest possible NASID of a C or M brick (+ 2)
*/
#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
/* GAM (globally addressed memory) range table */
struct uv_gam_range_s {
u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */
u16 nasid; /* node's global physical address */
s8 base; /* entry index of node's base addr */
u8 reserved;
};
/*
* The following defines attributes of the HUB chip. These attributes are
* frequently referenced and are kept in a common per hub struct.
* After setup, the struct is read only, so it should be readily
* available in the L3 cache on the cpu socket for the node.
*/
struct uv_hub_info_s {
unsigned int hub_type;
unsigned char hub_revision;
unsigned long global_mmr_base;
unsigned long global_mmr_shift;
unsigned long gpa_mask;
unsigned short *socket_to_node;
unsigned short *socket_to_pnode;
unsigned short *pnode_to_socket;
struct uv_gam_range_s *gr_table;
unsigned short min_socket;
unsigned short min_pnode;
unsigned char m_val;
unsigned char n_val;
unsigned char gr_table_len;
unsigned char apic_pnode_shift;
unsigned char gpa_shift;
unsigned char nasid_shift;
unsigned char m_shift;
unsigned char n_lshift;
unsigned int gnode_extra;
unsigned long gnode_upper;
unsigned long lowmem_remap_top;
unsigned long lowmem_remap_base;
unsigned long global_gru_base;
unsigned long global_gru_shift;
unsigned short pnode;
unsigned short pnode_mask;
unsigned short coherency_domain_number;
unsigned short numa_blade_id;
unsigned short nr_possible_cpus;
unsigned short nr_online_cpus;
short memory_nid;
unsigned short *node_to_socket;
};
/* CPU specific info with a pointer to the hub common info struct */
struct uv_cpu_info_s {
void *p_uv_hub_info;
unsigned char blade_cpu_id;
void *reserved;
};
DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
#define uv_cpu_info this_cpu_ptr(&__uv_cpu_info)
#define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu))
/* Node specific hub common info struct */
extern void **__uv_hub_info_list;
static inline struct uv_hub_info_s *uv_hub_info_list(int node)
{
return (struct uv_hub_info_s *)__uv_hub_info_list[node];
}
static inline struct uv_hub_info_s *_uv_hub_info(void)
{
return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info;
}
#define uv_hub_info _uv_hub_info()
static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu)
{
return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;
}
static inline int uv_hub_type(void)
{
return uv_hub_info->hub_type;
}
static inline __init void uv_hub_type_set(int uvmask)
{
uv_hub_info->hub_type = uvmask;
}
/*
* HUB revision ranges for each UV HUB architecture.
* This is a software convention - NOT the hardware revision numbers in
* the hub chip.
*/
#define UV2_HUB_REVISION_BASE 3
#define UV3_HUB_REVISION_BASE 5
#define UV4_HUB_REVISION_BASE 7
#define UV4A_HUB_REVISION_BASE 8 /* UV4 (fixed) rev 2 */
#define UV5_HUB_REVISION_BASE 9
static inline int is_uv(int uvmask) { return uv_hub_type() & uvmask; }
static inline int is_uv1_hub(void) { return 0; }
static inline int is_uv2_hub(void) { return is_uv(UV2); }
static inline int is_uv3_hub(void) { return is_uv(UV3); }
static inline int is_uv4a_hub(void) { return is_uv(UV4A); }
static inline int is_uv4_hub(void) { return is_uv(UV4); }
static inline int is_uv5_hub(void) { return is_uv(UV5); }
/*
* UV4A is a revision of UV4. So on UV4A, both is_uv4_hub() and
* is_uv4a_hub() return true, While on UV4, only is_uv4_hub()
* returns true. So to get true results, first test if is UV4A,
* then test if is UV4.
*/
/* UVX class: UV2,3,4 */
static inline int is_uvx_hub(void) { return is_uv(UVX); }
/* UVY class: UV5,..? */
static inline int is_uvy_hub(void) { return is_uv(UVY); }
/* Any UV Hubbed System */
static inline int is_uv_hub(void) { return is_uv(UV_ANY); }
union uvh_apicid {
unsigned long v;
struct uvh_apicid_s {
unsigned long local_apic_mask : 24;
unsigned long local_apic_shift : 5;
unsigned long unused1 : 3;
unsigned long pnode_mask : 24;
unsigned long pnode_shift : 5;
unsigned long unused2 : 3;
} s;
};
/*
* Local & Global MMR space macros.
* Note: macros are intended to be used ONLY by inline functions
* in this file - not by other kernel code.
* n - NASID (full 15-bit global nasid)
* g - GNODE (full 15-bit global nasid, right shifted 1)
* p - PNODE (local part of nsids, right shifted 1)
*/
#define UV_NASID_TO_PNODE(n) \
(((n) >> uv_hub_info->nasid_shift) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
#define UV_PNODE_TO_NASID(p) \
(UV_PNODE_TO_GNODE(p) << uv_hub_info->nasid_shift)
#define UV2_LOCAL_MMR_BASE 0xfa000000UL
#define UV2_GLOBAL_MMR32_BASE 0xfc000000UL
#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
#define UV3_LOCAL_MMR_BASE 0xfa000000UL
#define UV3_GLOBAL_MMR32_BASE 0xfc000000UL
#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
#define UV4_LOCAL_MMR_BASE 0xfa000000UL
#define UV4_GLOBAL_MMR32_BASE 0
#define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
#define UV4_GLOBAL_MMR32_SIZE 0
#define UV5_LOCAL_MMR_BASE 0xfa000000UL
#define UV5_GLOBAL_MMR32_BASE 0
#define UV5_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
#define UV5_GLOBAL_MMR32_SIZE 0
#define UV_LOCAL_MMR_BASE ( \
is_uv(UV2) ? UV2_LOCAL_MMR_BASE : \
is_uv(UV3) ? UV3_LOCAL_MMR_BASE : \
is_uv(UV4) ? UV4_LOCAL_MMR_BASE : \
is_uv(UV5) ? UV5_LOCAL_MMR_BASE : \
0)
#define UV_GLOBAL_MMR32_BASE ( \
is_uv(UV2) ? UV2_GLOBAL_MMR32_BASE : \
is_uv(UV3) ? UV3_GLOBAL_MMR32_BASE : \
is_uv(UV4) ? UV4_GLOBAL_MMR32_BASE : \
is_uv(UV5) ? UV5_GLOBAL_MMR32_BASE : \
0)
#define UV_LOCAL_MMR_SIZE ( \
is_uv(UV2) ? UV2_LOCAL_MMR_SIZE : \
is_uv(UV3) ? UV3_LOCAL_MMR_SIZE : \
is_uv(UV4) ? UV4_LOCAL_MMR_SIZE : \
is_uv(UV5) ? UV5_LOCAL_MMR_SIZE : \
0)
#define UV_GLOBAL_MMR32_SIZE ( \
is_uv(UV2) ? UV2_GLOBAL_MMR32_SIZE : \
is_uv(UV3) ? UV3_GLOBAL_MMR32_SIZE : \
is_uv(UV4) ? UV4_GLOBAL_MMR32_SIZE : \
is_uv(UV5) ? UV5_GLOBAL_MMR32_SIZE : \
0)
#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
#define _UV_GLOBAL_MMR64_PNODE_SHIFT 26
#define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift)
#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
#define UVH_APICID 0x002D0E00L
#define UV_APIC_PNODE_SHIFT 6
/* Local Bus from cpu's perspective */
#define LOCAL_BUS_BASE 0x1c00000
#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
/*
* System Controller Interface Reg
*
* Note there are NO leds on a UV system. This register is only
* used by the system controller to monitor system-wide operation.
* There are 64 regs per node. With Nehalem cpus (2 cores per node,
* 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
* a node.
*
* The window is located at top of ACPI MMR space
*/
#define SCIR_WINDOW_COUNT 64
#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
LOCAL_BUS_SIZE - \
SCIR_WINDOW_COUNT)
#define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
#define SCIR_CPU_ACTIVITY 0x02 /* not idle */
#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
/* Loop through all installed blades */
#define for_each_possible_blade(bid) \
for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
/*
* Macros for converting between kernel virtual addresses, socket local physical
* addresses, and UV global physical addresses.
* Note: use the standard __pa() & __va() macros for converting
* between socket virtual and socket physical addresses.
*/
/* global bits offset - number of local address bits in gpa for this UV arch */
static inline unsigned int uv_gpa_shift(void)
{
return uv_hub_info->gpa_shift;
}
#define _uv_gpa_shift
/* Find node that has the address range that contains global address */
static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa)
{
struct uv_gam_range_s *gr = uv_hub_info->gr_table;
unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT;
int i, num = uv_hub_info->gr_table_len;
if (gr) {
for (i = 0; i < num; i++, gr++) {
if (pal < gr->limit)
return gr;
}
}
pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr);
BUG();
}
/* Return base address of node that contains global address */
static inline unsigned long uv_gam_range_base(unsigned long pa)
{
struct uv_gam_range_s *gr = uv_gam_range(pa);
int base = gr->base;
if (base < 0)
return 0UL;
return uv_hub_info->gr_table[base].limit;
}
/* socket phys RAM --> UV global NASID (UV4+) */
static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr)
{
return uv_gam_range(paddr)->nasid;
}
#define _uv_soc_phys_ram_to_nasid
/* socket virtual --> UV global NASID (UV4+) */
static inline unsigned long uv_gpa_nasid(void *v)
{
return uv_soc_phys_ram_to_nasid(__pa(v));
}
/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
unsigned int m_val = uv_hub_info->m_val;
if (paddr < uv_hub_info->lowmem_remap_top)
paddr |= uv_hub_info->lowmem_remap_base;
if (m_val) {
paddr |= uv_hub_info->gnode_upper;
paddr = ((paddr << uv_hub_info->m_shift)
>> uv_hub_info->m_shift) |
((paddr >> uv_hub_info->m_val)
<< uv_hub_info->n_lshift);
} else {
paddr |= uv_soc_phys_ram_to_nasid(paddr)
<< uv_hub_info->gpa_shift;
}
return paddr;
}
/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
return uv_soc_phys_ram_to_gpa(__pa(v));
}
/* Top two bits indicate the requested address is in MMR space. */
static inline int
uv_gpa_in_mmr_space(unsigned long gpa)
{
return (gpa >> 62) == 0x3UL;
}
/* UV global physical address --> socket phys RAM */
static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
{
unsigned long paddr;
unsigned long remap_base = uv_hub_info->lowmem_remap_base;
unsigned long remap_top = uv_hub_info->lowmem_remap_top;
unsigned int m_val = uv_hub_info->m_val;
if (m_val)
gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
paddr = gpa & uv_hub_info->gpa_mask;
if (paddr >= remap_base && paddr < remap_base + remap_top)
paddr -= remap_base;
return paddr;
}
/* gpa -> gnode */
static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
{
unsigned int n_lshift = uv_hub_info->n_lshift;
if (n_lshift)
return gpa >> n_lshift;
return uv_gam_range(gpa)->nasid >> 1;
}
/* gpa -> pnode */
static inline int uv_gpa_to_pnode(unsigned long gpa)
{
return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask;
}
/* gpa -> node offset */
static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
{
unsigned int m_shift = uv_hub_info->m_shift;
if (m_shift)
return (gpa << m_shift) >> m_shift;
return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa);
}
/* Convert socket to node */
static inline int _uv_socket_to_node(int socket, unsigned short *s2nid)
{
return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket;
}
static inline int uv_socket_to_node(int socket)
{
return _uv_socket_to_node(socket, uv_hub_info->socket_to_node);
}
static inline int uv_pnode_to_socket(int pnode)
{
unsigned short *p2s = uv_hub_info->pnode_to_socket;
return p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode;
}
/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
unsigned int m_val = uv_hub_info->m_val;
unsigned long base;
unsigned short sockid;
if (m_val)
return __va(((unsigned long)pnode << m_val) | offset);
sockid = uv_pnode_to_socket(pnode);
/* limit address of previous socket is our base, except node 0 is 0 */
if (sockid == 0)
return __va((unsigned long)offset);
base = (unsigned long)(uv_hub_info->gr_table[sockid - 1].limit);
return __va(base << UV_GAM_RANGE_SHFT | offset);
}
/* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */
static inline int uv_apicid_to_pnode(int apicid)
{
int pnode = apicid >> uv_hub_info->apic_pnode_shift;
unsigned short *s2pn = uv_hub_info->socket_to_pnode;
return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode;
}
/*
* Access global MMRs using the low memory MMR32 space. This region supports
* faster MMR access but not all MMRs are accessible in this space.
*/
static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
{
return __va(UV_GLOBAL_MMR32_BASE |
UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}
static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
{
writeq(val, uv_global_mmr32_address(pnode, offset));
}
static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
{
return readq(uv_global_mmr32_address(pnode, offset));
}
/*
* Access Global MMR space using the MMR space located at the top of physical
* memory.
*/
static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
{
return __va(UV_GLOBAL_MMR64_BASE |
UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}
static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
{
writeq(val, uv_global_mmr64_address(pnode, offset));
}
static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
{
return readq(uv_global_mmr64_address(pnode, offset));
}
static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
{
writeb(val, uv_global_mmr64_address(pnode, offset));
}
static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
{
return readb(uv_global_mmr64_address(pnode, offset));
}
/*
* Access hub local MMRs. Faster than using global space but only local MMRs
* are accessible.
*/
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
return __va(UV_LOCAL_MMR_BASE | offset);
}
static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
return readq(uv_local_mmr_address(offset));
}
static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
writeq(val, uv_local_mmr_address(offset));
}
static inline unsigned char uv_read_local_mmr8(unsigned long offset)
{
return readb(uv_local_mmr_address(offset));
}
static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
{
writeb(val, uv_local_mmr_address(offset));
}
/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
return uv_cpu_info->blade_cpu_id;
}
/* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */
static inline int uv_cpu_blade_processor_id(int cpu)
{
return uv_cpu_info_per(cpu)->blade_cpu_id;
}
/* Blade number to Node number (UV2..UV4 is 1:1) */
static inline int uv_blade_to_node(int blade)
{
return uv_socket_to_node(blade);
}
/* Blade number of current cpu. Numbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
return uv_hub_info->numa_blade_id;
}
/*
* Convert linux node number to the UV blade number.
* .. Currently for UV2 thru UV4 the node and the blade are identical.
* .. UV5 needs conversion when sub-numa clustering is enabled.
*/
static inline int uv_node_to_blade_id(int nid)
{
unsigned short *n2s = uv_hub_info->node_to_socket;
return n2s ? n2s[nid] : nid;
}
/* Convert a CPU number to the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
return uv_cpu_hub_info(cpu)->numa_blade_id;
}
/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
unsigned short *s2p = uv_hub_info->socket_to_pnode;
return s2p ? s2p[bid] : bid;
}
/* Nid of memory node on blade. -1 if no blade-local memory */
static inline int uv_blade_to_memory_nid(int bid)
{
return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid;
}
/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus;
}
/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus;
}
/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
return uv_cpu_hub_info(cpu)->pnode;
}
/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
return uv_hub_info_list(nid)->pnode;
}
/* Maximum possible number of blades */
extern short uv_possible_blades;
static inline int uv_num_possible_blades(void)
{
return uv_possible_blades;
}
/* Per Hub NMI support */
extern void uv_nmi_setup(void);
extern void uv_nmi_setup_hubless(void);
/* BIOS/Kernel flags exchange MMR */
#define UVH_BIOS_KERNEL_MMR UVH_SCRATCH5
#define UVH_BIOS_KERNEL_MMR_ALIAS UVH_SCRATCH5_ALIAS
#define UVH_BIOS_KERNEL_MMR_ALIAS_2 UVH_SCRATCH5_ALIAS_2
/* TSC sync valid, set by BIOS */
#define UVH_TSC_SYNC_MMR UVH_BIOS_KERNEL_MMR
#define UVH_TSC_SYNC_SHIFT 10
#define UVH_TSC_SYNC_SHIFT_UV2K 16 /* UV2/3k have different bits */
#define UVH_TSC_SYNC_MASK 3 /* 0011 */
#define UVH_TSC_SYNC_VALID 3 /* 0011 */
#define UVH_TSC_SYNC_UNKNOWN 0 /* 0000 */
/* BMC sets a bit this MMR non-zero before sending an NMI */
#define UVH_NMI_MMR UVH_BIOS_KERNEL_MMR
#define UVH_NMI_MMR_CLEAR UVH_BIOS_KERNEL_MMR_ALIAS
#define UVH_NMI_MMR_SHIFT 63
#define UVH_NMI_MMR_TYPE "SCRATCH5"
struct uv_hub_nmi_s {
raw_spinlock_t nmi_lock;
atomic_t in_nmi; /* flag this node in UV NMI IRQ */
atomic_t cpu_owner; /* last locker of this struct */
atomic_t read_mmr_count; /* count of MMR reads */
atomic_t nmi_count; /* count of true UV NMIs */
unsigned long nmi_value; /* last value read from NMI MMR */
bool hub_present; /* false means UV hubless system */
bool pch_owner; /* indicates this hub owns PCH */
};
struct uv_cpu_nmi_s {
struct uv_hub_nmi_s *hub;
int state;
int pinging;
int queries;
int pings;
};
DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
#define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub)
#define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu))
#define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub)
/* uv_cpu_nmi_states */
#define UV_NMI_STATE_OUT 0
#define UV_NMI_STATE_IN 1
#define UV_NMI_STATE_DUMP 2
#define UV_NMI_STATE_DUMP_DONE 3
/*
* Get the minimum revision number of the hub chips within the partition.
* (See UVx_HUB_REVISION_BASE above for specific values.)
*/
static inline int uv_get_min_hub_revision_id(void)
{
return uv_hub_info->hub_revision;
}
#endif /* CONFIG_X86_64 */
#endif /* _ASM_X86_UV_UV_HUB_H */
linux-7.2.3/arch/x86/include/asm/uv/uv_irq.h
+37
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI UV IRQ definitions
*
* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_X86_UV_UV_IRQ_H
#define _ASM_X86_UV_UV_IRQ_H
/* If a generic version of this structure gets defined, eliminate this one. */
struct uv_IO_APIC_route_entry {
__u64 vector : 8,
delivery_mode : 3,
dest_mode : 1,
delivery_status : 1,
polarity : 1,
__reserved_1 : 1,
trigger : 1,
mask : 1,
__reserved_2 : 15,
dest : 32;
};
enum {
UV_AFFINITY_ALL,
UV_AFFINITY_NODE,
UV_AFFINITY_CPU
};
extern int uv_setup_irq(char *, int, int, unsigned long, int);
extern void uv_teardown_irq(unsigned int);
#endif /* _ASM_X86_UV_UV_IRQ_H */
linux-7.2.3/arch/x86/include/asm/uv/uv_mmrs.h
+4651
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