Resguardo inicial

This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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#
# arch/xtensa/boot/dts/Makefile
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
#
dtb-$(CONFIG_OF) += $(addsuffix .dtb, $(CONFIG_BUILTIN_DTB_NAME))
# for CONFIG_OF_ALL_DTBS test
dtb- := $(patsubst $(src)/%.dts,%.dtb, $(wildcard $(src)/*.dts))
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/ {
compatible = "cdns,xtensa-xtfpga";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&pic>;
chosen {
bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "cdns,xtensa-cpu";
reg = <0>;
};
};
pic: pic {
compatible = "cdns,xtensa-pic";
#interrupt-cells = <2>;
interrupt-controller;
};
clocks {
osc: main-oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x00000000 0xf0000000 0x10000000>;
uart0: serial@0d000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
clocks = <&osc>, <&osc>;
clock-names = "uart_clk", "pclk";
reg = <0x0d000000 0x1000>;
interrupts = <0 1>;
};
};
};
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "xtfpga.dtsi"
/include/ "xtfpga-flash-128m.dtsi"
/ {
compatible = "cdns,xtensa-kc705";
chosen {
bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x38000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x04000000>;
alignment = <0x2000>;
alloc-ranges = <0x00000000 0x20000000>;
linux,cma-default;
};
};
};
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "xtfpga.dtsi"
/include/ "xtfpga-flash-128m.dtsi"
/ {
compatible = "cdns,xtensa-kc705";
chosen {
bootargs = "earlycon=uart8250,mmio32,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
};
memory@0 {
device_type = "memory";
reg = <0x60000000 0x10000000>;
};
soc {
ranges = <0x00000000 0x90000000 0x10000000>;
};
};
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "xtfpga.dtsi"
/include/ "xtfpga-flash-16m.dtsi"
/ {
compatible = "cdns,xtensa-lx200";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x06000000>;
};
pic: pic {
compatible = "cdns,xtensa-mx";
#interrupt-cells = <2>;
interrupt-controller;
};
};
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "xtfpga.dtsi"
/include/ "xtfpga-flash-4m.dtsi"
/ {
compatible = "cdns,xtensa-lx60";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x04000000>;
};
};
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "xtfpga.dtsi"
/include/ "xtfpga-flash-16m.dtsi"
/ {
compatible = "cdns,xtensa-ml605";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
};
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/ {
compatible = "cdns,xtensa-iss";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&pic>;
chosen {
bootargs = "console=ttyS0,115200n8 debug";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x80000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "cdns,xtensa-cpu";
reg = <0>;
clocks = <&osc>;
};
};
clocks {
osc: osc {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
};
};
pic: pic {
compatible = "cdns,xtensa-pic";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
};
pci {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <0x1>;
bus-range = <0x0 0x3e>;
reg = <0xf0100000 0x03f00000>;
// BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
ranges = <0x01000000 0x0 0x00000000 0xf0000000 0x0 0x00010000>,
<0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x08000000>;
// PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2)
interrupt-map = <
0x0000 0x0 0x0 0x1 &pic 0x0 0x1
0x0800 0x0 0x0 0x1 &pic 0x1 0x1
0x1000 0x0 0x0 0x1 &pic 0x2 0x1
0x1800 0x0 0x0 0x1 &pic 0x3 0x1
>;
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
};
};
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// SPDX-License-Identifier: GPL-2.0
/ {
soc {
flash: flash@00000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x00000000 0x08000000>;
bank-width = <2>;
device-width = <2>;
partition@0 {
label = "data";
reg = <0x00000000 0x06000000>;
};
partition@6000000 {
label = "boot loader area";
reg = <0x06000000 0x00800000>;
};
partition@6800000 {
label = "kernel image";
reg = <0x06800000 0x017e0000>;
};
partition@7fe0000 {
label = "boot environment";
reg = <0x07fe0000 0x00020000>;
};
};
};
};
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// SPDX-License-Identifier: GPL-2.0
/ {
soc {
flash: flash@08000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x08000000 0x01000000>;
bank-width = <2>;
device-width = <2>;
partition@0 {
label = "boot loader area";
reg = <0x00000000 0x00400000>;
};
partition@400000 {
label = "kernel image";
reg = <0x00400000 0x00600000>;
};
partition@a00000 {
label = "data";
reg = <0x00a00000 0x005e0000>;
};
partition@fe0000 {
label = "boot environment";
reg = <0x00fe0000 0x00020000>;
};
};
};
};
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// SPDX-License-Identifier: GPL-2.0
/ {
soc {
flash: flash@08000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x08000000 0x00400000>;
bank-width = <2>;
device-width = <2>;
partition@0 {
label = "boot loader area";
reg = <0x00000000 0x003f0000>;
};
partition@3f0000 {
label = "boot environment";
reg = <0x003f0000 0x00010000>;
};
};
};
};
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// SPDX-License-Identifier: GPL-2.0
/ {
compatible = "cdns,xtensa-xtfpga";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&pic>;
chosen {
bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x06000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "cdns,xtensa-cpu";
reg = <0>;
clocks = <&osc>;
};
};
pic: pic {
compatible = "cdns,xtensa-pic";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#interrupt-cells = <2>;
interrupt-controller;
};
clocks {
clk54: clk54 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <54000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x00000000 0xf0000000 0x10000000>;
osc: main-oscillator {
#clock-cells = <0>;
compatible = "cdns,xtfpga-clock";
reg = <0x0d020004 0x4>;
};
serial0: serial@0d050020 {
device_type = "serial";
compatible = "ns16550a";
no-loopback-test;
reg = <0x0d050020 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
native-endian;
interrupts = <0 1>; /* external irq 0 */
clocks = <&osc>;
};
enet0: ethoc@0d030000 {
compatible = "opencores,ethoc";
reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
native-endian;
interrupts = <1 1>; /* external irq 1 */
local-mac-address = [00 50 c2 13 6f 00];
clocks = <&osc>;
};
i2s0: xtfpga-i2s@0d080000 {
#sound-dai-cells = <0>;
compatible = "cdns,xtfpga-i2s";
reg = <0x0d080000 0x40>;
interrupts = <2 1>; /* external irq 2 */
clocks = <&cdce706 4>;
};
i2c0: i2c-master@0d090000 {
compatible = "opencores,i2c-ocores";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0d090000 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
native-endian;
interrupts = <4 1>;
clocks = <&osc>;
cdce706: clock-synth@69 {
compatible = "ti,cdce706";
#clock-cells = <1>;
reg = <0x69>;
clocks = <&clk54>;
clock-names = "clk_in0";
};
};
spi0: spi@0d0a0000 {
compatible = "cdns,xtfpga-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0d0a0000 0xc>;
tlv320aic23: sound-codec@0 {
#sound-dai-cells = <0>;
compatible = "tlv320aic23";
reg = <0>;
spi-max-frequency = <12500000>;
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic23>;
simple-audio-card,bitclock-master = <0>;
simple-audio-card,frame-master = <0>;
clocks = <&cdce706 4>;
};
};
};