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linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/Makefile

@@ -0,0 +1,250 @@
+
+# Copyright 2022 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+# Makefile for the 'resource' sub-component of DAL.
+#
+
+
+###############################################################################
+#  DCE
+###############################################################################
+
+ifdef CONFIG_DRM_AMD_DC_SI
+RESOURCE_DCE60 = dce60_resource.o
+
+AMD_DAL_RESOURCE_DCE60 = $(addprefix $(AMDDALPATH)/dc/resource/dce60/,$(RESOURCE_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE60)
+endif
+
+###############################################################################
+
+RESOURCE_DCE80 = dce80_resource.o
+
+AMD_DAL_RESOURCE_DCE80 = $(addprefix $(AMDDALPATH)/dc/resource/dce80/,$(RESOURCE_DCE80))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE80)
+
+###############################################################################
+
+RESOURCE_DCE100 = dce100_resource.o
+
+AMD_DAL_RESOURCE_DCE100 = $(addprefix $(AMDDALPATH)/dc/resource/dce100/,$(RESOURCE_DCE100))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE100)
+
+###############################################################################
+
+RESOURCE_DCE110 = dce110_resource.o
+
+AMD_DAL_RESOURCE_DCE110 = $(addprefix $(AMDDALPATH)/dc/resource/dce110/,$(RESOURCE_DCE110))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE110)
+
+###############################################################################
+
+RESOURCE_DCE112 = dce112_resource.o
+
+AMD_DAL_RESOURCE_DCE112 = $(addprefix $(AMDDALPATH)/dc/resource/dce112/,$(RESOURCE_DCE112))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE112)
+
+###############################################################################
+
+RESOURCE_DCE120 = dce120_resource.o
+
+AMD_DAL_RESOURCE_DCE120 = $(addprefix $(AMDDALPATH)/dc/resource/dce120/,$(RESOURCE_DCE120))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE120)
+
+ifdef CONFIG_DRM_AMD_DC_FP
+###############################################################################
+# DCN
+###############################################################################
+
+RESOURCE_DCN10 = dcn10_resource.o
+
+AMD_DAL_RESOURCE_DCN10 = $(addprefix $(AMDDALPATH)/dc/resource/dcn10/,$(RESOURCE_DCN10))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN10)
+
+###############################################################################
+
+RESOURCE_DCN20 = dcn20_resource.o
+
+AMD_DAL_RESOURCE_DCN20 = $(addprefix $(AMDDALPATH)/dc/resource/dcn20/,$(RESOURCE_DCN20))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN20)
+
+###############################################################################
+
+RESOURCE_DCN201 = dcn201_resource.o
+
+AMD_DAL_RESOURCE_DCN201 = $(addprefix $(AMDDALPATH)/dc/resource/dcn201/,$(RESOURCE_DCN201))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN201)
+
+###############################################################################
+
+RESOURCE_DCN21 = dcn21_resource.o
+
+AMD_DAL_RESOURCE_DCN21 = $(addprefix $(AMDDALPATH)/dc/resource/dcn21/,$(RESOURCE_DCN21))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN21)
+
+###############################################################################
+
+RESOURCE_DCN30 = dcn30_resource.o
+
+AMD_DAL_RESOURCE_DCN30 = $(addprefix $(AMDDALPATH)/dc/resource/dcn30/,$(RESOURCE_DCN30))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN30)
+
+###############################################################################
+
+RESOURCE_DCN301 = dcn301_resource.o
+
+AMD_DAL_RESOURCE_DCN301 = $(addprefix $(AMDDALPATH)/dc/resource/dcn301/,$(RESOURCE_DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN301)
+
+###############################################################################
+
+RESOURCE_DCN302 = dcn302_resource.o
+
+AMD_DAL_RESOURCE_DCN302 = $(addprefix $(AMDDALPATH)/dc/resource/dcn302/,$(RESOURCE_DCN302))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN302)
+
+###############################################################################
+
+RESOURCE_DCN303 = dcn303_resource.o
+
+AMD_DAL_RESOURCE_DCN303 = $(addprefix $(AMDDALPATH)/dc/resource/dcn303/,$(RESOURCE_DCN303))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN303)
+
+###############################################################################
+
+RESOURCE_DCN31 = dcn31_resource.o
+
+AMD_DAL_RESOURCE_DCN31 = $(addprefix $(AMDDALPATH)/dc/resource/dcn31/,$(RESOURCE_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN31)
+
+###############################################################################
+
+RESOURCE_DCN314 = dcn314_resource.o
+
+AMD_DAL_RESOURCE_DCN314 = $(addprefix $(AMDDALPATH)/dc/resource/dcn314/,$(RESOURCE_DCN314))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN314)
+
+###############################################################################
+
+RESOURCE_DCN315 = dcn315_resource.o
+
+AMD_DAL_RESOURCE_DCN315 = $(addprefix $(AMDDALPATH)/dc/resource/dcn315/,$(RESOURCE_DCN315))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN315)
+
+###############################################################################
+
+RESOURCE_DCN316 = dcn316_resource.o
+
+AMD_DAL_RESOURCE_DCN316 = $(addprefix $(AMDDALPATH)/dc/resource/dcn316/,$(RESOURCE_DCN316))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN316)
+
+###############################################################################
+
+RESOURCE_DCN32 = dcn32_resource.o dcn32_resource_helpers.o
+
+AMD_DAL_RESOURCE_DCN32 = $(addprefix $(AMDDALPATH)/dc/resource/dcn32/,$(RESOURCE_DCN32))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN32)
+
+###############################################################################
+
+RESOURCE_DCN321 = dcn321_resource.o
+
+AMD_DAL_RESOURCE_DCN321 = $(addprefix $(AMDDALPATH)/dc/resource/dcn321/,$(RESOURCE_DCN321))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN321)
+
+###############################################################################
+
+RESOURCE_DCN35 = dcn35_resource.o
+
+AMD_DAL_RESOURCE_DCN35 = $(addprefix $(AMDDALPATH)/dc/resource/dcn35/,$(RESOURCE_DCN35))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN35)
+
+###############################################################################
+
+RESOURCE_DCN351 = dcn351_resource.o
+
+AMD_DAL_RESOURCE_DCN351 = $(addprefix $(AMDDALPATH)/dc/resource/dcn351/,$(RESOURCE_DCN351))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN351)
+
+###############################################################################
+
+RESOURCE_DCN36 = dcn36_resource.o
+
+AMD_DAL_RESOURCE_DCN36 = $(addprefix $(AMDDALPATH)/dc/resource/dcn36/,$(RESOURCE_DCN36))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN36)
+
+###############################################################################
+
+RESOURCE_DCN401 = dcn401_resource.o
+
+AMD_DAL_RESOURCE_DCN401 = $(addprefix $(AMDDALPATH)/dc/resource/dcn401/,$(RESOURCE_DCN401))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN401)
+
+###############################################################################
+# DCN42
+###############################################################################
+RESOURCE_DCN42 = dcn42_resource.o dcn42_resource_fpu.o
+
+AMD_DAL_RESOURCE_DCN42 = $(addprefix $(AMDDALPATH)/dc/resource/dcn42/,$(RESOURCE_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN42)
+
+# FPU Compile Flags for FPU files
+resource_ccflags := $(CC_FLAGS_FPU)
+resource_rcflags := $(CC_FLAGS_NO_FPU)
+
+CFLAGS_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_ccflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_rcflags)
+
+###############################################################################
+# DCN42B
+###############################################################################
+RESOURCE_DCN42B = dcn42b_resource.o
+
+AMD_DAL_RESOURCE_DCN42B = $(addprefix $(AMDDALPATH)/dc/resource/dcn42b/,$(RESOURCE_DCN42B))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN42B)
+endif
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+/*
+ * dce100_resource.h
+ *
+ *  Created on: 2016-01-20
+ *      Author: qyang
+ */
+
+#ifndef DCE100_RESOURCE_H_
+#define DCE100_RESOURCE_H_
+
+struct dc;
+struct resource_pool;
+struct dc_validation_set;
+
+struct resource_pool *dce100_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);
+
+enum dc_status dce100_validate_global(
+		struct dc  *dc,
+		struct dc_state *context);
+
+enum dc_status dce100_validate_bandwidth(
+		struct dc  *dc,
+		struct dc_state *context,
+		enum dc_validate_mode validate_mode);
+
+enum dc_status dce100_add_stream_to_ctx(
+		struct dc *dc,
+		struct dc_state *new_ctx,
+		struct dc_stream_state *dc_stream);
+
+struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_stream_state *stream);
+
+#endif /* DCE100_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h

@@ -0,0 +1,54 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE110_H__
+#define __DC_RESOURCE_DCE110_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+#define TO_DCE110_RES_POOL(pool)\
+	container_of(pool, struct dce110_resource_pool, base)
+
+struct dce110_resource_pool {
+	struct resource_pool base;
+};
+
+void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
+
+struct resource_pool *dce110_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct hw_asic_id asic_id);
+
+struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_stream_state *stream);
+
+#endif /* __DC_RESOURCE_DCE110_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

@@ -0,0 +1,57 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE112_H__
+#define __DC_RESOURCE_DCE112_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+struct resource_pool *dce112_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+enum dc_status dce112_validate_with_context(
+		struct dc *dc,
+		const struct dc_validation_set set[],
+		int set_count,
+		struct dc_state *context,
+		struct dc_state *old_context);
+
+enum dc_status dce112_validate_bandwidth(
+	struct dc *dc,
+	struct dc_state *context,
+	enum dc_validate_mode validate_mode);
+
+enum dc_status dce112_add_stream_to_ctx(
+		struct dc *dc,
+		struct dc_state *new_ctx,
+		struct dc_stream_state *dc_stream);
+
+
+#endif /* __DC_RESOURCE_DCE112_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h

@@ -0,0 +1,39 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE120_H__
+#define __DC_RESOURCE_DCE120_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+struct resource_pool *dce120_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+#endif /* __DC_RESOURCE_DCE120_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE60_H__
+#define __DC_RESOURCE_DCE60_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+struct resource_pool *dce60_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+struct resource_pool *dce61_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+struct resource_pool *dce64_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+#endif /* __DC_RESOURCE_DCE60_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

@@ -0,0 +1,47 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE80_H__
+#define __DC_RESOURCE_DCE80_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+struct resource_pool *dce80_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+struct resource_pool *dce81_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+struct resource_pool *dce83_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+#endif /* __DC_RESOURCE_DCE80_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

@@ -0,0 +1,59 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCN10_H__
+#define __DC_RESOURCE_DCN10_H__
+
+#include "core_types.h"
+#include "dml/dcn10/dcn10_fpu.h"
+
+#define TO_DCN10_RES_POOL(pool)\
+	container_of(pool, struct dcn10_resource_pool, base)
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+extern struct _vcs_dpi_ip_params_st dcn1_0_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc;
+
+struct dcn10_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn10_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_stream_state *stream);
+
+unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
+
+void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info);
+
+#endif /* __DC_RESOURCE_DCN10_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

@@ -0,0 +1,171 @@
+/*
+* Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCN20_H__
+#define __DC_RESOURCE_DCN20_H__
+
+#include "core_types.h"
+#include "dml/dcn20/dcn20_fpu.h"
+
+#define TO_DCN20_RES_POOL(pool)\
+	container_of(pool, struct dcn20_resource_pool, base)
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+extern struct _vcs_dpi_ip_params_st dcn2_0_ip;
+extern struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc;
+extern struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc;
+extern struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc;
+
+struct dcn20_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn20_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+struct link_encoder *dcn20_link_encoder_create(
+	struct dc_context *ctx,
+	const struct encoder_init_data *enc_init_data);
+
+unsigned int dcn20_calc_max_scaled_time(
+		unsigned int time_per_pixel,
+		enum mmhubbub_wbif_mode mode,
+		unsigned int urgent_watermark);
+
+struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
+		const struct dc_state *cur_ctx,
+		struct dc_state *new_ctx,
+		const struct resource_pool *pool,
+		const struct pipe_ctx *opp_head_pipe);
+void dcn20_release_pipe(struct dc_state *context,
+			struct pipe_ctx *pipe,
+			const struct resource_pool *pool);
+struct stream_encoder *dcn20_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx);
+
+struct dce_hwseq *dcn20_hwseq_create(
+	struct dc_context *ctx);
+
+bool dcn20_get_dcc_compression_cap(const struct dc *dc,
+		const struct dc_dcc_surface_param *input,
+		struct dc_surface_dcc_cap *output);
+
+void dcn20_dpp_destroy(struct dpp **dpp);
+
+struct dpp *dcn20_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst);
+
+struct input_pixel_processor *dcn20_ipp_create(
+	struct dc_context *ctx, uint32_t inst);
+
+struct output_pixel_processor *dcn20_opp_create(
+	struct dc_context *ctx, uint32_t inst);
+
+struct dce_aux *dcn20_aux_engine_create(
+	struct dc_context *ctx, uint32_t inst);
+
+struct dce_i2c_hw *dcn20_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst);
+
+void dcn20_clock_source_destroy(struct clock_source **clk_src);
+
+struct display_stream_compressor *dcn20_dsc_create(
+	struct dc_context *ctx, uint32_t inst);
+void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
+
+struct hubp *dcn20_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst);
+struct timing_generator *dcn20_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance);
+struct mpc *dcn20_mpc_create(struct dc_context *ctx);
+struct hubbub *dcn20_hubbub_create(struct dc_context *ctx);
+
+bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
+bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool);
+
+void dcn20_set_mcif_arb_params(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt);
+enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);
+void dcn20_merge_pipes_for_validate(
+		struct dc *dc,
+		struct dc_state *context);
+int dcn20_validate_apply_pipe_split_flags(
+		struct dc *dc,
+		struct dc_state *context,
+		int vlevel,
+		int *split,
+		bool *merge);
+void dcn20_release_dsc(struct resource_context *res_ctx,
+			const struct resource_pool *pool,
+			struct display_stream_compressor **dsc);
+bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
+void dcn20_split_stream_for_mpc(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct pipe_ctx *primary_pipe,
+		struct pipe_ctx *secondary_pipe);
+bool dcn20_split_stream_for_odm(
+		const struct dc *dc,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *prev_odm_pipe,
+		struct pipe_ctx *next_odm_pipe);
+void dcn20_acquire_dsc(const struct dc *dc,
+			struct resource_context *res_ctx,
+			struct display_stream_compressor **dsc,
+			int pipe_idx);
+struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		const struct pipe_ctx *primary_pipe);
+bool dcn20_fast_validate_bw(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *pipe_cnt_out,
+		int *pipe_split_from,
+		int *vlevel_out,
+		enum dc_validate_mode validate_mode);
+
+enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
+enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);
+enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);
+void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx);
+
+#endif /* __DC_RESOURCE_DCN20_H__ */
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

@@ -0,0 +1,50 @@
+/*
+* Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCN201_H__
+#define __DC_RESOURCE_DCN201_H__
+
+#include "core_types.h"
+
+#define RRDPCS_PHY_DP_TX_PSTATE_POWER_UP    0x00000000
+#define RRDPCS_PHY_DP_TX_PSTATE_HOLD        0x00000001
+#define RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF    0x00000002
+#define RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN  0x00000003
+
+#define TO_DCN201_RES_POOL(pool)\
+	container_of(pool, struct dcn201_resource_pool, base)
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+struct dcn201_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn201_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* __DC_RESOURCE_DCN201_H__ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN21_RESOURCE_H_
+#define _DCN21_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN21_RES_POOL(pool)\
+	container_of(pool, struct dcn21_resource_pool, base)
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+extern struct _vcs_dpi_ip_params_st dcn2_1_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc;
+
+struct dcn21_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn21_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+bool dcn21_fast_validate_bw(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *pipe_cnt_out,
+		int *pipe_split_from,
+		int *vlevel_out,
+		enum dc_validate_mode validate_mode,
+		bool allow_self_refresh_only);
+
+#endif /* _DCN21_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

@@ -0,0 +1,108 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN30_RESOURCE_H_
+#define _DCN30_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN30_RES_POOL(pool)\
+	container_of(pool, struct dcn30_resource_pool, base)
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+extern struct _vcs_dpi_ip_params_st dcn3_0_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc;
+
+struct dcn30_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn30_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+void dcn30_set_mcif_arb_params(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt);
+
+unsigned int dcn30_calc_max_scaled_time(
+		unsigned int time_per_pixel,
+		enum mmhubbub_wbif_mode mode,
+		unsigned int urgent_watermark);
+
+enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
+		enum dc_validate_mode validate_mode);
+bool dcn30_internal_validate_bw(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *pipe_cnt_out,
+		int *vlevel_out,
+		enum dc_validate_mode validate_mode,
+		bool allow_self_refresh_only);
+void dcn30_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel);
+void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
+void dcn30_populate_dml_writeback_from_context(
+		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
+
+int dcn30_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	enum dc_validate_mode validate_mode);
+
+bool dcn30_acquire_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		int mpcc_id,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper);
+
+bool dcn30_release_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper);
+
+enum dc_status dcn30_add_stream_to_ctx(
+		struct dc *dc,
+		struct dc_state *new_ctx,
+		struct dc_stream_state *dc_stream);
+
+void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+
+bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
+void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
+int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
+
+#endif /* _DCN30_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN301_RESOURCE_H_
+#define _DCN301_RESOURCE_H_
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+extern struct _vcs_dpi_ip_params_st dcn3_01_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc;
+
+struct dcn301_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn301_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN301_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN302_RESOURCE_H_
+#define _DCN302_RESOURCE_H_
+
+#include "core_types.h"
+
+extern struct _vcs_dpi_ip_params_st dcn3_02_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc;
+
+struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);
+
+void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+
+#endif /* _DCN302_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h

@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _DCN303_RESOURCE_H_
+#define _DCN303_RESOURCE_H_
+
+#include "core_types.h"
+
+extern struct _vcs_dpi_ip_params_st dcn3_03_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc;
+
+struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);
+
+void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+
+#endif /* _DCN303_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

@@ -0,0 +1,106 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN31_RESOURCE_H_
+#define _DCN31_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN31_RES_POOL(pool)\
+	container_of(pool, struct dcn31_resource_pool, base)
+
+extern struct _vcs_dpi_ip_params_st dcn3_1_ip;
+
+struct dcn31_resource_pool {
+	struct resource_pool base;
+};
+
+enum dc_status dcn31_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		enum dc_validate_mode validate_mode);
+void dcn31_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel);
+int dcn31_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	enum dc_validate_mode validate_mode);
+void
+dcn31_populate_dml_writeback_from_context(struct dc *dc,
+					  struct resource_context *res_ctx,
+					  display_e2e_pipe_params_st *pipes);
+void
+dcn31_set_mcif_arb_params(struct dc *dc,
+			  struct dc_state *context,
+			  display_e2e_pipe_params_st *pipes,
+			  int pipe_cnt);
+
+struct resource_pool *dcn31_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+unsigned int dcn31_get_det_buffer_size(
+	const struct dc_state *context);
+
+enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,
+	struct dc_link_settings *link_setting,
+	uint8_t pipe_count,
+	struct pipe_ctx *pipes,
+	struct audio_output *audio_output);
+
+/*temp: B0 specific before switch to dcn313 headers*/
+#ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL
+#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
+#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
+#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+
+//PHYPLLF_PIXCLK_RESYNC_CNTL
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+
+//PHYPLLG_PIXCLK_RESYNC_CNTL
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+#endif
+#endif /* _DCN31_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN314_RESOURCE_H_
+#define _DCN314_RESOURCE_H_
+
+#include "core_types.h"
+
+extern struct _vcs_dpi_ip_params_st dcn3_14_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc;
+
+#define TO_DCN314_RES_POOL(pool)\
+	container_of(pool, struct dcn314_resource_pool, base)
+
+struct dcn314_resource_pool {
+	struct resource_pool base;
+};
+
+enum dc_status dcn314_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		enum dc_validate_mode validate_mode);
+
+struct resource_pool *dcn314_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN314_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN315_RESOURCE_H_
+#define _DCN315_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN315_RES_POOL(pool)\
+	container_of(pool, struct dcn315_resource_pool, base)
+
+extern struct _vcs_dpi_ip_params_st dcn3_15_ip;
+
+struct dcn315_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn315_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN315_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN316_RESOURCE_H_
+#define _DCN316_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN316_RES_POOL(pool)\
+	container_of(pool, struct dcn316_resource_pool, base)
+
+extern struct _vcs_dpi_ip_params_st dcn3_16_ip;
+
+struct dcn316_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn316_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN316_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

@@ -0,0 +1,783 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+// header file of functions being implemented
+#include "dcn32/dcn32_resource.h"
+#include "dcn20/dcn20_resource.h"
+#include "dml/dcn32/display_mode_vba_util_32.h"
+#include "dml/dcn32/dcn32_fpu.h"
+#include "dc_state_priv.h"
+#include "dc_stream_priv.h"
+
+static bool is_dual_plane(enum surface_pixel_format format)
+{
+	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
+}
+
+uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
+		struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		bool ignore_cursor_buf)
+{
+	(void)dc;
+	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+	uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
+	uint32_t cursor_mall_size_bytes = 0;
+
+	switch (pipe_ctx->stream->cursor_attributes.color_format) {
+	case CURSOR_MODE_MONO:
+		cursor_size /= 2;
+		break;
+	case CURSOR_MODE_COLOR_1BIT_AND:
+	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+		cursor_size *= 4;
+		break;
+
+	case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+	case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+		cursor_size *= 8;
+		break;
+	}
+
+	/* only count if cursor is enabled, and if additional allocation needed outside of the
+	 * DCN cursor buffer
+	 */
+	if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||
+			cursor_size > 16384)) {
+		/* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1)
+		 * Note: add 1 mblk in case of cursor misalignment
+		 */
+		cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) /
+				DCN3_2_MALL_MBLK_SIZE_BYTES + 1) * DCN3_2_MALL_MBLK_SIZE_BYTES;
+	}
+
+	return cursor_mall_size_bytes;
+}
+
+/**
+ * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways needed for SubVP
+ *
+ * Gets total allocation required for the phantom viewport calculated by DML in bytes and
+ * converts to number of cache ways.
+ *
+ * @dc: current dc state
+ * @context: new dc state
+ *
+ * Return: number of ways required for SubVP
+ */
+uint32_t dcn32_helper_calculate_num_ways_for_subvp(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) {
+		if (dc->debug.force_subvp_num_ways) {
+			return dc->debug.force_subvp_num_ways;
+		} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
+			return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
+		} else {
+			return 0;
+		}
+	} else {
+		return 0;
+	}
+}
+
+void dcn32_merge_pipes_for_subvp(struct dc *dc,
+		struct dc_state *context)
+{
+	uint32_t i;
+
+	/* merge pipes if necessary */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		// For now merge all pipes for SubVP since pipe split case isn't supported yet
+
+		/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
+		if (pipe->prev_odm_pipe) {
+			/*split off odm pipe*/
+			pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
+			if (pipe->next_odm_pipe)
+				pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
+
+			pipe->bottom_pipe = NULL;
+			pipe->next_odm_pipe = NULL;
+			pipe->plane_state = NULL;
+			pipe->stream = NULL;
+			pipe->top_pipe = NULL;
+			pipe->prev_odm_pipe = NULL;
+			if (pipe->stream_res.dsc)
+				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
+			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
+			struct pipe_ctx *top_pipe = pipe->top_pipe;
+			struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
+
+			top_pipe->bottom_pipe = bottom_pipe;
+			if (bottom_pipe)
+				bottom_pipe->top_pipe = top_pipe;
+
+			pipe->top_pipe = NULL;
+			pipe->bottom_pipe = NULL;
+			pipe->plane_state = NULL;
+			pipe->stream = NULL;
+			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+		}
+	}
+}
+
+bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
+		struct dc_state *context)
+{
+	uint32_t i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe->stream)
+			continue;
+
+		if (!pipe->plane_state)
+			return false;
+	}
+	return true;
+}
+
+bool dcn32_subvp_in_use(struct dc *dc,
+		struct dc_state *context)
+{
+	uint32_t i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)
+			return true;
+	}
+	return false;
+}
+
+bool dcn32_mpo_in_use(struct dc_state *context)
+{
+	uint32_t i;
+
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->stream_status[i].plane_count > 1)
+			return true;
+	}
+	return false;
+}
+
+
+bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)
+{
+	uint32_t i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe->stream)
+			continue;
+
+		if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)
+			return true;
+	}
+	return false;
+}
+
+bool dcn32_is_center_timing(struct pipe_ctx *pipe)
+{
+	bool is_center_timing = false;
+
+	if (pipe->stream) {
+		if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
+				pipe->stream->timing.v_addressable != pipe->stream->src.height) {
+			is_center_timing = true;
+		}
+
+		if (pipe->plane_state) {
+			if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
+					pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
+				is_center_timing = true;
+			}
+		}
+	}
+
+	return is_center_timing;
+}
+
+bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
+{
+	bool psr_capable = false;
+
+	if (pipe->stream && pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
+		psr_capable = true;
+	}
+	return psr_capable;
+}
+
+static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])
+{
+	uint32_t i;
+	uint8_t fhd_count = 0;
+	uint8_t subvp_high_refresh_count = 0;
+	uint8_t stream_count = 0;
+
+	// Do not override if a stream has multiple planes
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->stream_status[i].plane_count > 1)
+			return;
+
+		if (dc_state_get_stream_subvp_type(context, context->streams[i]) != SUBVP_PHANTOM)
+			stream_count++;
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
+			if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {
+
+				if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
+					fhd_count++;
+				}
+				subvp_high_refresh_count++;
+			}
+		}
+	}
+
+	if (stream_count == 2 && subvp_high_refresh_count == 2 && fhd_count == 1) {
+		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+			if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
+				if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
+					if (pipe_segments[i] > 4)
+						pipe_segments[i] = 4;
+				}
+			}
+		}
+	}
+}
+
+/**
+ * dcn32_determine_det_override(): Determine DET allocation for each pipe
+ *
+ * This function determines how much DET to allocate for each pipe. The total number of
+ * DET segments will be split equally among each of the streams, and after that the DET
+ * segments per stream will be split equally among the planes for the given stream.
+ *
+ * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the
+ * number of DET for that given plane will be split among the pipes driving that plane.
+ *
+ *
+ * High level algorithm:
+ * 1. Split total DET among number of streams
+ * 2. For each stream, split DET among the planes
+ * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation
+ *    among those pipes.
+ * 4. Assign the DET override to the DML pipes.
+ *
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ * @pipes: Array of DML pipes
+ *
+ * Return: void
+ */
+void dcn32_determine_det_override(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes)
+{
+	uint32_t i, j, k;
+	uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};
+	uint8_t pipe_counted[MAX_PIPES] = {0};
+	uint8_t pipe_cnt = 0;
+	struct dc_plane_state *current_plane = NULL;
+	uint8_t stream_count = 0;
+
+	for (i = 0; i < context->stream_count; i++) {
+		/* Don't count SubVP streams for DET allocation */
+		if (dc_state_get_stream_subvp_type(context, context->streams[i]) != SUBVP_PHANTOM)
+			stream_count++;
+	}
+
+	if (stream_count > 0) {
+		stream_segments = 18 / stream_count;
+		for (i = 0; i < context->stream_count; i++) {
+			if (dc_state_get_stream_subvp_type(context, context->streams[i]) == SUBVP_PHANTOM)
+				continue;
+
+			if (context->stream_status[i].plane_count > 0)
+				plane_segments = (uint8_t)(stream_segments / context->stream_status[i].plane_count);
+			else
+				plane_segments = stream_segments;
+			for (j = 0; j < dc->res_pool->pipe_count; j++) {
+				pipe_plane_count = 0;
+				if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&
+						pipe_counted[j] != 1) {
+					/* Note: pipe_plane_count indicates the number of pipes to be used for a
+					 * given plane. e.g. pipe_plane_count = 1 means single pipe (i.e. not split),
+					 * pipe_plane_count = 2 means 2:1 split, etc.
+					 */
+					pipe_plane_count++;
+					pipe_counted[j] = 1;
+					current_plane = context->res_ctx.pipe_ctx[j].plane_state;
+					for (k = 0; k < dc->res_pool->pipe_count; k++) {
+						if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
+								context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
+							pipe_plane_count++;
+							pipe_counted[k] = 1;
+						}
+					}
+
+					pipe_segments[j] = plane_segments / pipe_plane_count;
+					for (k = 0; k < dc->res_pool->pipe_count; k++) {
+						if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
+								context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
+							pipe_segments[k] = plane_segments / pipe_plane_count;
+						}
+					}
+				}
+			}
+		}
+
+		override_det_for_subvp(dc, context, pipe_segments);
+		for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+			if (!context->res_ctx.pipe_ctx[i].stream)
+				continue;
+			pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE;
+			pipe_cnt++;
+		}
+	} else {
+		for (i = 0; i < dc->res_pool->pipe_count; i++)
+			pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE
+	}
+}
+
+void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes)
+{
+	unsigned int i;
+	int pipe_cnt;
+	struct resource_context *res_ctx = &context->res_ctx;
+	struct pipe_ctx *pipe = 0;
+	bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
+
+	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+
+		if (!res_ctx->pipe_ctx[i].stream)
+			continue;
+
+		pipe = &res_ctx->pipe_ctx[i];
+		pipe_cnt++;
+	}
+
+	/* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
+	 * the DET available for each pipe). Use the DET override input to maintain our driver
+	 * policy.
+	 */
+	if (pipe_cnt == 1) {
+		pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
+		if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
+			if (!is_dual_plane(pipe->plane_state->format)) {
+				pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
+				pipes[0].pipe.src.unbounded_req_mode = true;
+				if (pipe->plane_state->src_rect.width >= 5120 &&
+					pipe->plane_state->src_rect.height >= 2880)
+					pipes[0].pipe.src.det_size_override = 320; // 5K or higher
+			}
+		}
+	} else
+		dcn32_determine_det_override(dc, context, pipes);
+}
+
+#define MAX_STRETCHED_V_BLANK 1000 // in micro-seconds (must ensure to match value in FW)
+/*
+ * Scaling factor for v_blank stretch calculations considering timing in
+ * micro-seconds and pixel clock in 100hz.
+ * Note: the parenthesis are necessary to ensure the correct order of
+ * operation where V_SCALE is used.
+ */
+#define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
+
+static int get_frame_rate_at_max_stretch_100hz(
+		struct dc_stream_state *fpo_candidate_stream,
+		uint32_t fpo_vactive_margin_us)
+{
+	struct dc_crtc_timing *timing = NULL;
+	uint32_t sec_per_100_lines;
+	uint32_t max_v_blank;
+	uint32_t curr_v_blank;
+	uint32_t v_stretch_max;
+	uint32_t stretched_frame_pix_cnt;
+	uint32_t scaled_stretched_frame_pix_cnt;
+	uint32_t scaled_refresh_rate;
+	uint32_t v_scale;
+
+	if (fpo_candidate_stream == NULL)
+		return 0;
+
+	/* check if refresh rate at least 120hz */
+	timing = &fpo_candidate_stream->timing;
+	if (timing == NULL)
+		return 0;
+
+	v_scale = 10000 / (MAX_STRETCHED_V_BLANK + fpo_vactive_margin_us);
+
+	sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
+	max_v_blank = sec_per_100_lines / v_scale + 1;
+	curr_v_blank = timing->v_total - timing->v_addressable;
+	v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
+	stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
+	scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
+	scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
+
+	return scaled_refresh_rate;
+
+}
+
+static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(
+		struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us, int current_refresh_rate)
+{
+	int refresh_rate_max_stretch_100hz;
+	int min_refresh_100hz;
+
+	if (fpo_candidate_stream == NULL)
+		return false;
+
+	refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(fpo_candidate_stream, fpo_vactive_margin_us);
+	min_refresh_100hz = fpo_candidate_stream->timing.min_refresh_in_uhz / 10000;
+
+	if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
+		return false;
+
+	if (fpo_candidate_stream->ctx->dc->config.enable_fpo_flicker_detection == 1 &&
+			!dc_stream_is_refresh_rate_range_flickerless(fpo_candidate_stream, (refresh_rate_max_stretch_100hz / 100), current_refresh_rate, false))
+		return false;
+
+	return true;
+}
+
+static int get_refresh_rate(struct dc_stream_state *fpo_candidate_stream)
+{
+	int refresh_rate = 0;
+	int h_v_total = 0;
+	struct dc_crtc_timing *timing = NULL;
+
+	if (fpo_candidate_stream == NULL)
+		return 0;
+
+	/* check if refresh rate at least 120hz */
+	timing = &fpo_candidate_stream->timing;
+	if (timing == NULL)
+		return 0;
+
+	h_v_total = timing->h_total * timing->v_total;
+	if (h_v_total == 0)
+		return 0;
+
+	refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
+	return refresh_rate;
+}
+
+/**
+ * dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch() - Determines if config can
+ *								    support FPO
+ *
+ * @dc: current dc state
+ * @context: new dc state
+ *
+ * Return: Pointer to FPO stream candidate if config can support FPO, otherwise NULL
+ */
+struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
+{
+	int refresh_rate = 0;
+	const int minimum_refreshrate_supported = 120;
+	struct dc_stream_state *fpo_candidate_stream = NULL;
+	bool is_fpo_vactive = false;
+	uint32_t fpo_vactive_margin_us = 0;
+	struct dc_stream_status *fpo_stream_status = NULL;
+
+	if (context == NULL)
+		return NULL;
+
+	if (dc->debug.disable_fams)
+		return NULL;
+
+	if (!dc->caps.dmub_caps.mclk_sw)
+		return NULL;
+
+	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
+		return NULL;
+
+	/* For FPO we can support up to 2 display configs if:
+	 * - first display uses FPO
+	 * - Second display switches in VACTIVE */
+	if (context->stream_count > 2)
+		return NULL;
+	else if (context->stream_count == 2) {
+		DC_FP_START();
+		dcn32_assign_fpo_vactive_candidate(dc, context, &fpo_candidate_stream);
+		DC_FP_END();
+		if (fpo_candidate_stream)
+			fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);
+		DC_FP_START();
+		is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, fpo_candidate_stream, dc->debug.fpo_vactive_min_active_margin_us);
+		DC_FP_END();
+		if (!is_fpo_vactive || dc->debug.disable_fpo_vactive)
+			return NULL;
+	} else {
+		fpo_candidate_stream = context->streams[0];
+		if (fpo_candidate_stream)
+			fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);
+	}
+
+	/* In DCN32/321, FPO uses per-pipe P-State force.
+	 * If there's no planes, HUBP is power gated and
+	 * therefore programming UCLK_PSTATE_FORCE does
+	 * nothing (P-State will always be asserted naturally
+	 * on a pipe that has HUBP power gated. Therefore we
+	 * only want to enable FPO if the FPO pipe has both
+	 * a stream and a plane.
+	 */
+	if (!fpo_candidate_stream || !fpo_stream_status || fpo_stream_status->plane_count == 0)
+		return NULL;
+
+	if (fpo_candidate_stream->sink->edid_caps.panel_patch.disable_fams)
+		return NULL;
+
+	refresh_rate = get_refresh_rate(fpo_candidate_stream);
+	if (refresh_rate < minimum_refreshrate_supported)
+		return NULL;
+
+	fpo_vactive_margin_us = is_fpo_vactive ? dc->debug.fpo_vactive_margin_us : 0; // For now hardcode the FPO + Vactive stretch margin to be 2000us
+	if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(fpo_candidate_stream, fpo_vactive_margin_us, refresh_rate))
+		return NULL;
+
+	if (!fpo_candidate_stream->allow_freesync)
+		return NULL;
+
+	if (fpo_candidate_stream->vrr_active_variable &&
+	((dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE) ||
+	(context->stream_count > 1 && !(dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_ENABLE))))
+		return NULL;
+
+	return fpo_candidate_stream;
+}
+
+bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)
+{
+	bool is_native_scaling = false;
+
+	if (pipe->stream->timing.h_addressable == width &&
+			pipe->stream->timing.v_addressable == height &&
+			pipe->plane_state->src_rect.width == width &&
+			pipe->plane_state->src_rect.height == height &&
+			pipe->plane_state->dst_rect.width == width &&
+			pipe->plane_state->dst_rect.height == height)
+		is_native_scaling = true;
+
+	return is_native_scaling;
+}
+
+/**
+ * disallow_subvp_in_active_plus_blank() - Function to determine disallowed subvp + drr/vblank configs
+ *
+ * @pipe: subvp pipe to be used for the subvp + drr/vblank config
+ *
+ * Since subvp is being enabled on more configs (such as 1080p60), we want
+ * to explicitly block any configs that we don't want to enable. We do not
+ * want to enable any 1080p60 (SubVP) + drr / vblank configs since these
+ * are already convered by FPO.
+ *
+ * Return: True if disallowed, false otherwise
+ */
+static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)
+{
+	bool disallow = false;
+
+	if (resource_is_pipe_type(pipe, OPP_HEAD) &&
+			resource_is_pipe_type(pipe, DPP_PIPE)) {
+		if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920)
+			disallow = true;
+	}
+	return disallow;
+}
+
+/**
+ * dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible
+ *
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ *
+ * SubVP + DRR is admissible under the following conditions:
+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
+ * - One display is SubVP
+ * - Other display must have Freesync enabled
+ * - The potential DRR display must not be PSR capable
+ *
+ * Return: True if admissible, false otherwise
+ */
+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
+{
+	bool result = false;
+	uint32_t i;
+	uint8_t subvp_count = 0;
+	uint8_t non_subvp_pipes = 0;
+	bool drr_pipe_found = false;
+	bool drr_psr_capable = false;
+	uint64_t refresh_rate = 0;
+	bool subvp_disallow = false;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
+
+		if (resource_is_pipe_type(pipe, OPP_HEAD) &&
+				resource_is_pipe_type(pipe, DPP_PIPE)) {
+			if (pipe_mall_type == SUBVP_MAIN) {
+				subvp_count++;
+
+				subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);
+				refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
+					pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);
+				refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
+				refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+			}
+			if (pipe_mall_type == SUBVP_NONE) {
+				non_subvp_pipes++;
+				drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));
+				if (pipe->stream->ignore_msa_timing_param &&
+						(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
+					drr_pipe_found = true;
+				}
+			}
+		}
+	}
+
+	if (subvp_count == 1 && !subvp_disallow && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable &&
+		((uint32_t)refresh_rate < 120))
+		result = true;
+
+	return result;
+}
+
+/**
+ * dcn32_subvp_vblank_admissable() - Determine if SubVP + Vblank config is admissible
+ *
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ * @vlevel: Voltage level calculated by DML
+ *
+ * SubVP + Vblank is admissible under the following conditions:
+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
+ * - One display is SubVP
+ * - Other display must not have Freesync capability
+ * - DML must have output DRAM clock change support as SubVP + Vblank
+ * - The potential vblank display must not be PSR capable
+ *
+ * Return: True if admissible, false otherwise
+ */
+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)
+{
+	bool result = false;
+	uint32_t i;
+	uint8_t subvp_count = 0;
+	uint8_t non_subvp_pipes = 0;
+	bool drr_pipe_found = false;
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	bool vblank_psr_capable = false;
+	uint64_t refresh_rate = 0;
+	bool subvp_disallow = false;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
+
+		if (resource_is_pipe_type(pipe, OPP_HEAD) &&
+				resource_is_pipe_type(pipe, DPP_PIPE)) {
+			if (pipe_mall_type == SUBVP_MAIN) {
+				subvp_count++;
+
+				subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);
+				refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
+					pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1);
+				refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
+				refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+			}
+			if (pipe_mall_type == SUBVP_NONE) {
+				non_subvp_pipes++;
+				vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));
+				if (pipe->stream->ignore_msa_timing_param &&
+						(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
+					drr_pipe_found = true;
+				}
+			}
+		}
+	}
+
+	if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found && !vblank_psr_capable &&
+		((uint32_t)refresh_rate < 120) && !subvp_disallow &&
+		vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
+		result = true;
+
+	return result;
+}
+
+void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes)
+{
+	unsigned int i;
+	int pipe_cnt;
+	struct resource_context *res_ctx = &context->res_ctx;
+	struct pipe_ctx *pipe = NULL;
+
+	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+		int odm_slice_count = 0;
+
+		if (!res_ctx->pipe_ctx[i].stream)
+			continue;
+		pipe = &res_ctx->pipe_ctx[i];
+		odm_slice_count = resource_get_odm_slice_count(pipe);
+
+		if (odm_slice_count == 1)
+			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
+		else if (odm_slice_count == 2)
+			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
+		else if (odm_slice_count == 4)
+			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
+
+		pipe_cnt++;
+	}
+}
+
+void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context)
+{
+	if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)
+		context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ;
+}

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN321_RESOURCE_H_
+#define _DCN321_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN321_RES_POOL(pool)\
+	container_of(pool, struct dcn321_resource_pool, base)
+
+extern struct _vcs_dpi_ip_params_st dcn3_21_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc;
+
+struct dcn321_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn321_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN321_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

@@ -0,0 +1,316 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN35_RESOURCE_H_
+#define _DCN35_RESOURCE_H_
+
+#include "core_types.h"
+
+#define DCN3_5_VMIN_DISPCLK_HZ 717000000
+#define TO_DCN35_RES_POOL(pool)\
+	container_of(pool, struct dcn35_resource_pool, base)
+
+extern struct _vcs_dpi_ip_params_st dcn3_5_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc;
+enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);
+
+struct dcn35_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn35_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+/* Defs for runtime init of registers */
+
+#define OPP_REG_LIST_DCN20_RI(id) \
+	OPP_REG_LIST_DCN10_RI(id), \
+	OPP_DPG_REG_LIST_RI(id), \
+	SRI_ARR(FMT_422_CONTROL, FMT, id), \
+	SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)
+
+#define OPP_REG_LIST_DCN35_RI(id) \
+	OPP_REG_LIST_DCN20_RI(id), \
+	SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)
+
+#define VPG_DCN31_REG_LIST_RI(id) \
+	SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \
+	SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
+	SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \
+	SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
+	SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
+	SRI_ARR(VPG_MEM_PWR, VPG, id)
+
+#define AFMT_DCN31_REG_LIST_RI(id) \
+	SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
+	SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
+	SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \
+	SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \
+	SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
+	SRI_ARR(AFMT_60958_0, AFMT, id), \
+	SRI_ARR(AFMT_60958_1, AFMT, id), \
+	SRI_ARR(AFMT_60958_2, AFMT, id), \
+	SRI_ARR(AFMT_MEM_PWR, AFMT, id)
+
+/* Stream encoder */
+#define SE_DCN35_REG_LIST_RI(id) \
+	SRI_ARR(AFMT_CNTL, DIG, id), \
+	SRI_ARR(DIG_FE_CNTL, DIG, id), \
+	SRI_ARR(HDMI_CONTROL, DIG, id), \
+	SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
+	SRI_ARR(HDMI_GC, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
+	SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \
+	SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \
+	SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \
+	SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
+	SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\
+	SRI_ARR(HDMI_ACR_32_0, DIG, id),\
+	SRI_ARR(HDMI_ACR_32_1, DIG, id),\
+	SRI_ARR(HDMI_ACR_44_0, DIG, id),\
+	SRI_ARR(HDMI_ACR_44_1, DIG, id),\
+	SRI_ARR(HDMI_ACR_48_0, DIG, id),\
+	SRI_ARR(HDMI_ACR_48_1, DIG, id),\
+	SRI_ARR(DP_DB_CNTL, DP, id), \
+	SRI_ARR(DP_MSA_MISC, DP, id), \
+	SRI_ARR(DP_MSA_VBID_MISC, DP, id), \
+	SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
+	SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
+	SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
+	SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
+	SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
+	SRI_ARR(DP_MSE_RATE_CNTL, DP, id), \
+	SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
+	SRI_ARR(DP_PIXEL_FORMAT, DP, id), \
+	SRI_ARR(DP_SEC_CNTL, DP, id), \
+	SRI_ARR(DP_SEC_CNTL1, DP, id), \
+	SRI_ARR(DP_SEC_CNTL2, DP, id), \
+	SRI_ARR(DP_SEC_CNTL5, DP, id), \
+	SRI_ARR(DP_SEC_CNTL6, DP, id), \
+	SRI_ARR(DP_STEER_FIFO, DP, id), \
+	SRI_ARR(DP_VID_M, DP, id), \
+	SRI_ARR(DP_VID_N, DP, id), \
+	SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
+	SRI_ARR(DP_VID_TIMING, DP, id), \
+	SRI_ARR(DP_SEC_AUD_N, DP, id), \
+	SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \
+	SRI_ARR(DP_DSC_CNTL, DP, id), \
+	SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \
+	SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
+	SRI_ARR(DP_SEC_FRAMING4, DP, id), \
+	SRI_ARR(DP_GSP11_CNTL, DP, id), \
+	SRI_ARR(DME_CONTROL, DME, id),\
+	SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \
+	SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
+	SRI_ARR(DIG_FE_CNTL, DIG, id), \
+	SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \
+	SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \
+	SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \
+	SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
+	SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)
+
+#define LE_DCN35_REG_LIST_RI(id)\
+	LE_DCN3_REG_LIST_RI(id),\
+	SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \
+	SR_ARR(DIO_LINKA_CNTL, id), \
+	SR_ARR(DIO_LINKB_CNTL, id), \
+	SR_ARR(DIO_LINKC_CNTL, id), \
+	SR_ARR(DIO_LINKD_CNTL, id), \
+	SR_ARR(DIO_LINKE_CNTL, id), \
+	SR_ARR(DIO_LINKF_CNTL, id),\
+	SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\
+	SR_ARR(DIO_CLK_CNTL, id)
+
+#define MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(inst)  \
+	MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst), \
+		SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst)
+
+#define HWSEQ_DCN35_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCCG_GATE_DISABLE_CNTL4), \
+	SR(DCCG_GATE_DISABLE_CNTL5), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+	SR(HPO_TOP_HW_CONTROL),\
+	SR(DMU_CLK_CNTL)
+
+/* OPTC */
+#define OPTC_COMMON_REG_LIST_DCN3_5_RI(inst)                                   \
+	SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\
+	SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\
+	SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\
+	SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+	SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\
+	SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\
+	SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_H_TOTAL, OTG, inst),\
+	SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\
+	SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
+	SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\
+	SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\
+	SRI_ARR(OTG_V_TOTAL, OTG, inst),\
+	SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\
+	SRI_ARR(OTG_V_SYNC_A, OTG, inst),\
+	SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\
+	SRI_ARR(OTG_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\
+	SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\
+	SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\
+	SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\
+	SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\
+	SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+	SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+	SRI_ARR(OTG_STATUS, OTG, inst),\
+	SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\
+	SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\
+	SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\
+	SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\
+	SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+	SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+	SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+	SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+	SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+	SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+	SRI_ARR(CONTROL, VTG, inst),\
+	SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC_CNTL, OTG, inst),\
+	SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\
+	SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\
+	SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\
+	SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\
+	SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\
+	SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\
+	SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\
+	SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
+	SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
+	SR_ARR(GSL_SOURCE_SELECT, inst),\
+	SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\
+	SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\
+	SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+	SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\
+	SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+	SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+	SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+	SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+	SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\
+	SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\
+	SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\
+	SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
+	SRI_ARR(INTERRUPT_DEST, OTG, inst)
+
+/* DPP */
+#define DPP_REG_LIST_DCN35_RI(id)\
+	DPP_REG_LIST_DCN30_COMMON_RI(id)
+
+void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+#endif /* _DCN35_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2024 Advanced Micro Devices, Inc. */
+
+#ifndef _DCN351_RESOURCE_H_
+#define _DCN351_RESOURCE_H_
+
+#include "core_types.h"
+
+extern struct _vcs_dpi_ip_params_st dcn3_51_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc;
+
+#define TO_DCN351_RES_POOL(pool)\
+	container_of(pool, struct dcn351_resource_pool, base)
+
+struct dcn351_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn351_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN351_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h

@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2025 Advanced Micro Devices, Inc. */
+
+#ifndef _DCN36_RESOURCE_H_
+#define _DCN36_RESOURCE_H_
+
+#include "core_types.h"
+
+extern struct _vcs_dpi_ip_params_st dcn3_6_ip;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_6_soc;
+
+#define TO_DCN36_RES_POOL(pool)\
+	container_of(pool, struct dcn36_resource_pool, base)
+
+struct dcn36_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn36_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#define HWSEQ_DCN36_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCCG_GATE_DISABLE_CNTL4), \
+	SR(DCCG_GATE_DISABLE_CNTL5), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(MPC_CRC_CTRL), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+	SR(HPO_TOP_HW_CONTROL),\
+	SR(DMU_CLK_CNTL)
+
+#endif /* _DCN36_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

@@ -0,0 +1,662 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2024 Advanced Micro Devices, Inc.
+
+#ifndef _DCN401_RESOURCE_H_
+#define _DCN401_RESOURCE_H_
+
+#include "core_types.h"
+#include "dcn32/dcn32_resource.h"
+#include "dcn401/dcn401_hubp.h"
+
+#define TO_DCN401_RES_POOL(pool)\
+	container_of(pool, struct dcn401_resource_pool, base)
+
+struct dcn401_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn401_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state);
+
+enum dc_status dcn401_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		enum dc_validate_mode validate_mode);
+
+void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
+
+void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info);
+
+unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
+
+int dcn401_get_power_profile(const struct dc_state *context);
+/* Following are definitions for run time init of reg offsets */
+
+/* HUBP */
+#define HUBP_REG_LIST_DCN401_RI(id)                                             \
+	SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id),                                  \
+	SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id),                                  \
+	SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id),                                  \
+	SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id),                                  \
+	SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),                             \
+	SRI_ARR(DCHUBP_CNTL, HUBP, id),                                          \
+	SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id),                                     \
+	SRI_ARR(HUBPREQ_DEBUG, HUBP, id),                                        \
+	SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id),                                   \
+	SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id),                                 \
+	SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id),                              \
+	SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),                            \
+	SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id),                                \
+	SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id),                               \
+	SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id),                        \
+	SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id),                            \
+	SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id),                        \
+	SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id),                            \
+	SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id),                      \
+	SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id),                          \
+	SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id),                      \
+	SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id),                          \
+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),               \
+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),                    \
+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),             \
+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),                  \
+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),             \
+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),                  \
+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),           \
+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),                \
+	SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id),                              \
+	SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),                         \
+	SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),                            \
+	SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),                       \
+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),                     \
+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),                \
+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),                   \
+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),              \
+	SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id),                            \
+	SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),                     \
+	SRI_ARR(HUBPRET_CONTROL, HUBPRET, id),                                   \
+	SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id),                          \
+	SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id),                                \
+	SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),                               \
+	SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),                             \
+	SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id),                                    \
+	SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id),                                    \
+	SRI_ARR(DST_DIMENSIONS, HUBPREQ, id),                                    \
+	SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id),                                  \
+	SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id),                               \
+	SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),                              \
+	SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id),                               \
+	SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id),                               \
+	SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id),                                  \
+	SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id),                                  \
+	SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id),                             \
+	SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id),                                 \
+	SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id),                               \
+	SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id),                               \
+	SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id),                                  \
+	SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id),                                  \
+	SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id),                                    \
+	SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),                               \
+	SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),                               \
+	SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),                               \
+	SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),                               \
+	SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),                               \
+	SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),                                \
+	SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),                                \
+	SRI_ARR(HUBP_CLK_CNTL, HUBP, id),                                        \
+	SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id),                                 \
+	SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id),                               \
+	SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),                   \
+	SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),                  \
+	SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id),                                   \
+	SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id),                      \
+	SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id),                           \
+	SRI_ARR(CURSOR_SIZE, CURSOR0_, id),                                      \
+	SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \
+	SRI_ARR(CURSOR_POSITION, CURSOR0_, id),                                  \
+	SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id),                                  \
+	SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id),                                \
+	SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id),                              \
+	SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id),                               \
+	SRI_ARR(DMDATA_CNTL, CURSOR0_, id),                                      \
+	SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id),                                   \
+	SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id),                                  \
+	SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id),                                   \
+	SRI_ARR(DMDATA_STATUS, CURSOR0_, id),                                    \
+	SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id),                                 \
+	SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id),                                 \
+	SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id),                                 \
+	SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),                                \
+	SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),                                \
+	SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id),                              \
+	SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id),                                   \
+	SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id),                                 \
+	SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id),                                 \
+	SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id),                                 \
+	SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id),                                 \
+	SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id),                               \
+	SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id),                               \
+	SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id),                                \
+	SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id),                                   \
+	SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id),                                   \
+	SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id),                                 \
+	HUBP_3DLUT_FL_REG_LIST_DCN401(id),                                       \
+	SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id),              \
+	SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id),								 \
+	SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
+
+/* ABM */
+#define ABM_DCN401_REG_LIST_RI(id)                                            \
+	SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id),                                \
+	SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id),                                \
+	SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id),                                  \
+	SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id),                               \
+	SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id),                         \
+	SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id),                             \
+	SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id),                              \
+	SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id),                                    \
+	SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id),                  \
+	SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id),                        \
+	SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id),                      \
+	SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id),                       \
+	SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id),                      \
+	SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id),                      \
+	SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id),                      \
+	SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id),                                \
+	SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id),                               \
+	SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id),                         \
+	SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id),                                  \
+	SRI_ARR(DC_ABM1_ACE_THRES_DATA, ABM, id),                                \
+	NBIO_SR_ARR(BIOS_SCRATCH_2, id)
+
+/* VPG */
+#define VPG_DCN401_REG_LIST_RI(id)                                             \
+	VPG_DCN3_REG_LIST_RI(id),                                                  \
+	SRI_ARR(VPG_MEM_PWR, VPG, id)
+
+/* Stream encoder */
+#define SE_DCN4_01_REG_LIST_RI(id)                                               \
+	SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id),                  \
+	SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id),       \
+	SRI_ARR(HDMI_GC, DIG, id),                                               \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id),                          \
+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id),                         \
+	SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id),                               \
+	SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id),                               \
+	SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id),                               \
+	SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),                             \
+	SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),                               \
+	SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id),        \
+	SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id),        \
+	SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id),        \
+	SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id),               \
+	SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id),  \
+	SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id),                                   \
+	SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id),                                   \
+	SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id),                                   \
+	SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id),                                   \
+	SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id),  \
+	SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id),          \
+	SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id),            \
+	SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id),            \
+	SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id),               \
+	SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id),          \
+	SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id),           \
+	SRI_ARR(DP_SEC_TIMESTAMP, DP, id),                                       \
+	SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                           \
+	SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                          \
+	SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id),        \
+	SRI_ARR(DME_CONTROL, DME, id),                                           \
+	SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                           \
+	SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                          \
+	SRI_ARR(DIG_FE_CNTL, DIG, id),                                           \
+	SRI_ARR(DIG_FE_EN_CNTL, DIG, id),                                        \
+	SRI_ARR(DIG_FE_CLK_CNTL, DIG, id),                                       \
+	SRI_ARR(DIG_CLOCK_PATTERN, DIG, id),                                     \
+	SRI_ARR(DIG_FIFO_CTRL0, DIG, id),                                        \
+	SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)
+
+/* Link encoder */
+#define LE_DCN401_REG_LIST_RI(id)                                            \
+	LE_DCN3_REG_LIST_RI(id), \
+	SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \
+	SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\
+	SR_ARR(DIO_CLK_CNTL, id)
+
+/* DPP */
+#define DPP_REG_LIST_DCN401_COMMON_RI(id)                                    \
+	SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id),         \
+	SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id),        \
+	SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id),    \
+	SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id),                                  \
+	SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                    \
+	SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                    \
+	SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id),                                     \
+	SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),                      \
+	SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),                      \
+	SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),                      \
+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id),                              \
+	SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id),                                \
+	SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id),                                \
+	SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id),                                \
+	SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),                       \
+	SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),                       \
+	SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),                       \
+	SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),                      \
+	SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),                      \
+	SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),                      \
+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),                             \
+	SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id),                              \
+	SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id),                            \
+	SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id),                                \
+	SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id),                                \
+	SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id),                                \
+	SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),                       \
+	SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),                       \
+	SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),                       \
+	SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id),                         \
+	SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id),                         \
+	SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id),          \
+	SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id),          \
+	SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id),      \
+	SRI_ARR(SCL_TAP_CONTROL, DSCL, id),                                      \
+	SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id),                              \
+	SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id),                                \
+	SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id),       \
+	SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id),                          \
+	SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id),                          \
+	SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id),                        \
+	SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id),                        \
+	SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id),                                 \
+	SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id),                               \
+	SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id),                                 \
+	SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id),                               \
+	SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id),         \
+	SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id),  \
+	SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id),                                     \
+	SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id),                                  \
+	SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id),                                  \
+	SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id),                                \
+	SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id),                                \
+	SRI_ARR(CM_POST_CSC_CONTROL, CM, id),                                    \
+	SRI_ARR(CM_POST_CSC_C11_C12, CM, id),                                    \
+	SRI_ARR(CM_POST_CSC_C33_C34, CM, id),                                    \
+	SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                  \
+	SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                  \
+	SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),           \
+	SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id),                                    \
+	SRI_ARR(CM_TEST_DEBUG_DATA, CM, id),                                     \
+	SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                   \
+	SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                        \
+	SRI_ARR(CURSOR0_CONTROL, CM_CUR, id),                                    \
+	SRI_ARR(CURSOR0_COLOR0, CM_CUR, id),                                     \
+	SRI_ARR(CURSOR0_COLOR1, CM_CUR, id),                                     \
+	SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id),                          \
+	SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id),                      \
+	SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id),                                   \
+	SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id),                              \
+	SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id),                              \
+	SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id),    \
+	SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \
+	SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id),                                   \
+	SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id),                                   \
+	SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id),                                   \
+	SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id),                                   \
+	SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id),                                  \
+	SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id),                                  \
+	SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id),                                  \
+	SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id),                              \
+	SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id),                                \
+	SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id),                                  \
+	SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id),                                \
+	SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id),                                 \
+	SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id),                                    \
+	SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id),                                  \
+	SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id),                                    \
+	SRI_ARR(DSCL_CONTROL, DSCL, id),                                         \
+	SRI_ARR(DSCL_SC_MODE, DSCL, id),                                         \
+	SRI_ARR(DSCL_EASF_H_MODE, DSCL, id),                                     \
+	SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id),                                  \
+	SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id),                   \
+	SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id),                     \
+	SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id),                         \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_MODE, DSCL, id),                                     \
+	SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id),                                  \
+	SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id),                       \
+	SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id),                       \
+	SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id),                       \
+	SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id),                   \
+	SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id),                     \
+	SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id),                         \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id),                             \
+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id),                             \
+	SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id),                                  \
+	SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id),                                  \
+	SRI_ARR(ISHARP_MODE, DSCL, id),                                          \
+	SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id),                                          \
+	SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id),                            \
+	SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id),                                \
+	SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id),                                  \
+	SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id),                                  \
+	SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id),                                  \
+	SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id),                                  \
+	SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id),                                  \
+	SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id),                                  \
+	SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id),                                    \
+	SRI_ARR(ISHARP_DELTA_DATA, DSCL, id),                                    \
+	SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id),                                   \
+	SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id),                             \
+	SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id),                             \
+	SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)
+
+/* OPP */
+#define OPP_REG_LIST_DCN401_RI(id)                                              \
+  OPP_REG_LIST_DCN10_RI(id), OPP_DPG_REG_LIST_RI(id),                          \
+      SRI_ARR(FMT_422_CONTROL, FMT, id)
+
+/* DSC */
+#define DSC_REG_LIST_DCN401_RI(id)                                          \
+	SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id),                                   \
+	SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id),                                 \
+	SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id),        \
+	SRI_ARR(DSCC_STATUS, DSCC, id),                                          \
+	SRI_ARR(DSCC_INTERRUPT_CONTROL0, DSCC, id),                              \
+	SRI_ARR(DSCC_INTERRUPT_CONTROL1, DSCC, id),                              \
+	SRI_ARR(DSCC_INTERRUPT_STATUS0, DSCC, id),                               \
+	SRI_ARR(DSCC_INTERRUPT_STATUS1, DSCC, id),                               \
+	SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id),                                     \
+	SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id),                                    \
+	SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id),                                    \
+	SRI_ARR(DSCC_MEM_POWER_CONTROL0, DSCC, id),                              \
+	SRI_ARR(DSCC_MEM_POWER_CONTROL1, DSCC, id),                              \
+	SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),                         \
+	SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),                         \
+	SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),                        \
+	SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),                        \
+	SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),                        \
+	SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),                        \
+	SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id),                                  \
+	SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id),                                  \
+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC, id),           \
+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC, id),           \
+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC, id),           \
+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC, id),           \
+	SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),                           \
+	SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id),                                     \
+	SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
+
+/* MPC */
+#define MPC_DWB_MUX_REG_LIST_DCN4_01_RI(inst)                                  \
+	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst)
+
+#define MPC_OUT_MUX_COMMON_REG_LIST_DCN4_01_RI(inst)                           \
+	MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst)
+
+#define MPC_OUT_MUX_REG_LIST_DCN4_01_RI(inst)                                   \
+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst)
+
+/* OPTC */
+#define OPTC_COMMON_REG_LIST_DCN401_RI(inst)                                   \
+	SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),                                      \
+	SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),                                   \
+	SRI_ARR(OTG_VREADY_PARAM, OTG, inst),                                    \
+	SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),                              \
+	SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),                                 \
+	SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
+	SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
+	SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),                                 \
+	SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),                           \
+	SRI_ARR(OTG_H_TOTAL, OTG, inst),                                         \
+	SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),                               \
+	SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
+	SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst),  \
+	SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),                               \
+	SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
+	SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
+	SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),                            \
+	SRI_ARR(OTG_STEREO_STATUS, OTG, inst),                                   \
+	SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),                                     \
+	SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),                                     \
+	SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),                                 \
+	SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),                                      \
+	SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),                            \
+	SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),                           \
+	SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),                              \
+	SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
+	SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),                               \
+	SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),                                    \
+	SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),                                    \
+	SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),                                   \
+	SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),                     \
+	SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),                    \
+	SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),                     \
+	SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),                    \
+	SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),                     \
+	SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),                    \
+	SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),                            \
+	SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),                             \
+	SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),                           \
+	SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),  \
+	SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst),   \
+	SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),                                    \
+	SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),                                     \
+	SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),                          \
+	SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),                          \
+	SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),                          \
+	SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),                          \
+	SR_ARR(GSL_SOURCE_SELECT, inst),                                         \
+	SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),                               \
+	SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
+	SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
+	SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),                                    \
+	SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),                                    \
+	SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),                                 \
+	SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),                              \
+	SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),                              \
+	SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),                            \
+	SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),                                \
+	SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \
+	SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst),                                 \
+	SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \
+	SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \
+	SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst),                                 \
+	SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),                              \
+	SRI_ARR(INTERRUPT_DEST, OTG, inst)
+
+/* HUBBUB */
+#define HUBBUB_REG_LIST_DCN4_01_RI(id)                                       \
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),                               \
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),                               \
+	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),                                  \
+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),                                        \
+	SR(DCHUBBUB_ARB_SAT_LEVEL),                                              \
+	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),                                        \
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL),                                          \
+	SR(DCHUBBUB_TEST_DEBUG_INDEX),                                           \
+	SR(DCHUBBUB_TEST_DEBUG_DATA),                                            \
+	SR(DCHUBBUB_SOFT_RESET),                                                 \
+	SR(DCHUBBUB_CRC_CTRL),                                                   \
+	SR(DCN_VM_FB_LOCATION_BASE),                                             \
+	SR(DCN_VM_FB_LOCATION_TOP),                                              \
+	SR(DCN_VM_FB_OFFSET),                                                    \
+	SR(DCN_VM_AGP_BOT),                                                      \
+	SR(DCN_VM_AGP_TOP),                                                      \
+	SR(DCN_VM_AGP_BASE),                                                     \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),                              \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),                              \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A),                            \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B),                            \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A),                            \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B),                            \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A),                            \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A),                             \
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B),                            \
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B),                             \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),                                      \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),                                      \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),                                     \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),                                     \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A),                                     \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B),                                     \
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),                            \
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),                            \
+	SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A),                                 \
+	SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B),                                 \
+	SR(DCHUBBUB_DET0_CTRL),                                                  \
+	SR(DCHUBBUB_DET1_CTRL),                                                  \
+	SR(DCHUBBUB_DET2_CTRL),                                                  \
+	SR(DCHUBBUB_DET3_CTRL),                                                  \
+	SR(DCHUBBUB_COMPBUF_CTRL),                                               \
+	SR(COMPBUF_RESERVED_SPACE),                                              \
+	SR(DCHUBBUB_DEBUG_CTRL_0),                                               \
+	SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),                                    \
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),                             \
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),                             \
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),                         \
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),                         \
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A),                        \
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B),                        \
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),                         \
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),                         \
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A),                        \
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B),                        \
+	SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB),                    \
+	SR(DCN_VM_FAULT_CNTL),                                                   \
+	SR(DCN_VM_FAULT_STATUS),                                                 \
+	SR(SDPIF_REQUEST_RATE_LIMIT),                                            \
+	SR(DCHUBBUB_CLOCK_CNTL),                                                 \
+	SR(DCHUBBUB_SDPIF_CFG0),                                                 \
+	SR(DCHUBBUB_SDPIF_CFG1),                                                 \
+	SR(DCHUBBUB_MEM_PWR_MODE_CTRL),                                          \
+	SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1),                                    \
+	SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2),									 \
+	SR(DCHUBBUB_CTRL_STATUS)
+
+/* DCCG */
+
+#define DCCG_REG_LIST_DCN401_RI()                                            \
+	SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0),                        \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2),        \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),  \
+	SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL),                    \
+	SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL),                    \
+	SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL),                            \
+	SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL),                              \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),  \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),  \
+	SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL),                               \
+	SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL),                     \
+	SR(DPPCLK_CTRL),							                             \
+	DCCG_SRII(MODULO, DP_DTO, 0), DCCG_SRII(MODULO, DP_DTO, 1),      \
+	DCCG_SRII(MODULO, DP_DTO, 2), DCCG_SRII(MODULO, DP_DTO, 3),      \
+	DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1),        \
+	DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3),        \
+	SR(DSCCLK0_DTO_PARAM),\
+	SR(DSCCLK1_DTO_PARAM),\
+	SR(DSCCLK2_DTO_PARAM),\
+	SR(DSCCLK3_DTO_PARAM),\
+	SR(DSCCLK_DTO_CTRL),\
+	SR(DCCG_GATE_DISABLE_CNTL),\
+	SR(DCCG_GATE_DISABLE_CNTL2),\
+	SR(DCCG_GATE_DISABLE_CNTL3),\
+	SR(DCCG_GATE_DISABLE_CNTL4),\
+	SR(DCCG_GATE_DISABLE_CNTL5),\
+	SR(DCCG_GATE_DISABLE_CNTL6),\
+	SR(SYMCLKA_CLOCK_ENABLE),\
+	SR(SYMCLKB_CLOCK_ENABLE),\
+	SR(SYMCLKC_CLOCK_ENABLE),\
+	SR(SYMCLKD_CLOCK_ENABLE)
+
+#endif /* _DCN401_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

@@ -0,0 +1,599 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN42_RESOURCE_H_
+#define _DCN42_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN42_RES_POOL(pool) \
+	container_of(pool, struct dcn42_resource_pool, base)
+
+/* DPP */
+#define DPP_REG_LIST_DCN42_COMMON_RI(id)                                        \
+	SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id),            \
+		SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id),       \
+		SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id),   \
+		SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id),                                 \
+		SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                   \
+		SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                   \
+		SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id),                                    \
+		SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id),                             \
+		SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id),                             \
+		SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),                      \
+		SRI_ARR(CM_HIST_CNTL, CM, id),                                          \
+		SRI_ARR(CM_HIST_LOCK, CM, id),                                          \
+		SRI_ARR(CM_HIST_INDEX, CM, id),                                         \
+		SRI_ARR(CM_HIST_DATA, CM, id),                                          \
+		SRI_ARR(CM_HIST_STATUS, CM, id),                                        \
+		SRI_ARR(CM_HIST_SCALE_SRC1, CM, id),                                    \
+		SRI_ARR(CM_HIST_COEFA_SRC2, CM, id),                                    \
+		SRI_ARR(CM_HIST_COEFB_SRC2, CM, id),                                    \
+		SRI_ARR(CM_HIST_COEFC_SRC2, CM, id),                                    \
+		SRI_ARR(CM_HIST_SCALE_SRC3, CM, id),                                    \
+		SRI_ARR(CM_HIST_BIAS_SRC1, CM, id),                                     \
+		SRI_ARR(CM_HIST_BIAS_SRC2, CM, id),                                     \
+		SRI_ARR(CM_HIST_BIAS_SRC3, CM, id),                                     \
+		SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id),                        \
+		SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id),                        \
+		SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id),         \
+		SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id),         \
+		SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id),     \
+		SRI_ARR(SCL_TAP_CONTROL, DSCL, id),                                     \
+		SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id),                             \
+		SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id),                               \
+		SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id),      \
+		SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id),                         \
+		SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id),                         \
+		SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id),                       \
+		SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id),                       \
+		SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id),                                \
+		SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id),                              \
+		SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id),                                \
+		SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id),                              \
+		SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id),        \
+		SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \
+		SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id),                                    \
+		SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id),                                 \
+		SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id),                                 \
+		SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id),                               \
+		SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id),                               \
+		SRI_ARR(CM_POST_CSC_CONTROL, CM, id),                                   \
+		SRI_ARR(CM_POST_CSC_C11_C12, CM, id),                                   \
+		SRI_ARR(CM_POST_CSC_C33_C34, CM, id),                                   \
+		SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                 \
+		SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                 \
+		SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),          \
+		SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id),                                   \
+		SRI_ARR(CM_TEST_DEBUG_DATA, CM, id),                                    \
+		SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                  \
+		SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                       \
+		SRI_ARR(CURSOR0_CONTROL, CM_CUR, id),                                   \
+		SRI_ARR(CURSOR0_COLOR0, CM_CUR, id),                                    \
+		SRI_ARR(CURSOR0_COLOR1, CM_CUR, id),                                    \
+		SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id),                         \
+		SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id),                     \
+		SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id),                                  \
+		SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id),                             \
+		SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id),   \
+		SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                  \
+		SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id),                                \
+		SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id),                                \
+		SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id),                                  \
+		SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id),                                  \
+		SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id),                                  \
+		SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id),                                 \
+		SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id),                                 \
+		SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id),                                 \
+		SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id),                             \
+		SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id),                               \
+		SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id),                                 \
+		SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id),                               \
+		SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id),                                \
+		SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id),                                   \
+		SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id),                                 \
+		SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id),                                   \
+		SRI_ARR(DSCL_CONTROL, DSCL, id),                                        \
+		SRI_ARR(DSCL_SC_MODE, DSCL, id),                                        \
+		SRI_ARR(DSCL_EASF_H_MODE, DSCL, id),                                    \
+		SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id),                                 \
+		SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id),                  \
+		SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id),                    \
+		SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id),                        \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_MODE, DSCL, id),                                    \
+		SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id),                                 \
+		SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id),                      \
+		SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id),                      \
+		SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id),                      \
+		SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id),                  \
+		SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id),                    \
+		SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id),                        \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id),                                 \
+		SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id),                                 \
+		SRI_ARR(ISHARP_MODE, DSCL, id),                                         \
+		SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id),                       \
+		SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id),                           \
+		SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id),                               \
+		SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id),                                 \
+		SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id),                                   \
+		SRI_ARR(ISHARP_DELTA_DATA, DSCL, id),                                   \
+		SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id),                                  \
+		SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id),                            \
+		SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id),                            \
+		SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)
+
+/* Stream encoder */
+#define SE_DCN42_REG_LIST_RI(id)                                                \
+	SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id),          \
+		SRI_ARR(HDMI_GC, DIG, id),                                              \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id),                        \
+		SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id),                              \
+		SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id),                              \
+		SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),                            \
+		SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),                              \
+		SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id),       \
+		SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id),       \
+		SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id),       \
+		SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id),              \
+		SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
+		SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id),                                  \
+		SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id),                                  \
+		SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id),                                  \
+		SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id),                                  \
+		SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
+		SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id),         \
+		SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id),           \
+		SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id),           \
+		SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id),              \
+		SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id),         \
+		SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id),          \
+		SRI_ARR(DP_SEC_TIMESTAMP, DP, id),                                      \
+		SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                          \
+		SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                         \
+		SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id),       \
+		SRI_ARR(DME_CONTROL, DME, id),                                          \
+		SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                          \
+		SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                         \
+		SRI_ARR(DIG_FE_CNTL, DIG, id),                                          \
+		SRI_ARR(DIG_FE_EN_CNTL, DIG, id),                                       \
+		SRI_ARR(DIG_FE_CLK_CNTL, DIG, id),                                      \
+		SRI_ARR(DIG_CLOCK_PATTERN, DIG, id),                                    \
+		SRI_ARR(DIG_FIFO_CTRL0, DIG, id),                                       \
+		SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\
+		SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id)
+
+/* HPO DP stream encoder */
+#define DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id)                                             \
+	SR_ARR(DP_STREAM_MAPPER_CONTROL0, id),                                                  \
+		SR_ARR(DP_STREAM_MAPPER_CONTROL1, id),                                              \
+		SR_ARR(DP_STREAM_MAPPER_CONTROL2, id),                                              \
+		SR_ARR(DP_STREAM_MAPPER_CONTROL3, id),                                              \
+		SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),                            \
+		SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),                        \
+		SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),                            \
+		SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \
+		SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),                                    \
+		SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),     \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),                            \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),              \
+		SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),                         \
+		SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),                                \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),                          \
+		SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),                \
+		SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),                         \
+		SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id),                            \
+		SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
+
+/*HPO DP link encoder regs */
+#define DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id)                    \
+	SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id),         \
+		SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id),        \
+		SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id),     \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id),   \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id),   \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)
+
+#define VPG_DCN42_REG_LIST_RI(id) \
+	SRI(VPG_GENERIC_STATUS, VPG, id), \
+	SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
+	SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
+	SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
+	SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
+	SRI(VPG_MEM_PWR, VPG, id)
+
+/* DCCG */
+#define DCCG_REG_LIST_DCN42_RI()               \
+	SR(DPPCLK_DTO_CTRL),                       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),       \
+	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
+	SR(HDMISTREAMCLK0_DTO_PARAM),\
+	SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(PHYASYMCLK_CLOCK_CNTL),  \
+	SR(PHYBSYMCLK_CLOCK_CNTL), \
+	SR(PHYCSYMCLK_CLOCK_CNTL), \
+	SR(PHYDSYMCLK_CLOCK_CNTL), \
+	SR(PHYESYMCLK_CLOCK_CNTL), \
+	SR(DPSTREAMCLK_CNTL), \
+	SR(HDMISTREAMCLK_CNTL), \
+	SR(SYMCLK32_SE_CNTL), \
+	SR(SYMCLK32_LE_CNTL), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
+	SR(OTG_PIXEL_RATE_DIV), \
+	SR(DTBCLK_P_CNTL), \
+	SR(DCCG_AUDIO_DTO_SOURCE), \
+	SR(DENTIST_DISPCLK_CNTL), \
+	SR(DPPCLK_CTRL), \
+	DCCG_SRII(MODULO, DP_DTO, 0), \
+	DCCG_SRII(MODULO, DP_DTO, 1), \
+	DCCG_SRII(MODULO, DP_DTO, 2), \
+	DCCG_SRII(MODULO, DP_DTO, 3), \
+	DCCG_SRII(PHASE, DP_DTO, 0), \
+	DCCG_SRII(PHASE, DP_DTO, 1), \
+	DCCG_SRII(PHASE, DP_DTO, 2), \
+	DCCG_SRII(PHASE, DP_DTO, 3), \
+	SR(OTG_ADD_DROP_PIXEL_CNTL), \
+	SR(DSCCLK0_DTO_PARAM), \
+	SR(DSCCLK1_DTO_PARAM), \
+	SR(DSCCLK2_DTO_PARAM), \
+	SR(DSCCLK3_DTO_PARAM), \
+	SR(DSCCLK_DTO_CTRL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCCG_GATE_DISABLE_CNTL3), \
+	SR(DCCG_GATE_DISABLE_CNTL4), \
+	SR(DCCG_GATE_DISABLE_CNTL5), \
+	SR(DCCG_GATE_DISABLE_CNTL6), \
+	SR(SYMCLKA_CLOCK_ENABLE), \
+	SR(SYMCLKB_CLOCK_ENABLE), \
+	SR(SYMCLKC_CLOCK_ENABLE), \
+	SR(SYMCLKD_CLOCK_ENABLE), \
+	SR(SYMCLKE_CLOCK_ENABLE)
+
+#define DCN42_AUD_COMMON_MASK_SH_LIST(mask_sh)                                             \
+	SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),   \
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
+		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
+		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
+		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
+		SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
+
+	/* HPO FRL stream encoder */
+#define DCN42_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)                                 \
+	DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id),                               \
+	SR_ARR(HDMI_STREAM_ENC_AUDIO_CONTROL, id),\
+	SR_ARR(HDMI_TB_ENC_MEM_CTRL, id),\
+	SR_ARR(HDMI_FRL_ENC_MEM_CTRL, id)
+/* OPTC */
+#define OPTC_COMMON_REG_LIST_DCN42_RI(inst)                                      \
+		SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),                                      \
+		SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),                                   \
+		SRI_ARR(OTG_VREADY_PARAM, OTG, inst),                                    \
+		SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),                              \
+		SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst),                              \
+		SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),                            \
+		SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),                           \
+		SRI_ARR(OTG_GSL_CONTROL, OTG, inst),					 \
+		SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
+		SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),                                 \
+		SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),                           \
+		SRI_ARR(OTG_H_TOTAL, OTG, inst),                                         \
+		SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),                               \
+		SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
+		SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
+		SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \
+		SRI_ARR(OTG_V_TOTAL, OTG, inst),  \
+		SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),                               \
+		SRI_ARR(OTG_V_SYNC_A, OTG, inst), \
+		SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
+		SRI_ARR(OTG_CONTROL, OTG, inst), \
+		SRI_ARR(OTG_MASTER_EN, OTG, inst), \
+		SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \
+		SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
+		SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),                            \
+		SRI_ARR(OTG_STEREO_STATUS, OTG, inst),                                   \
+		SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),                                     \
+		SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),                                     \
+		SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),                                 \
+		SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),                                      \
+		SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),                            \
+		SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),                           \
+		SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),                              \
+		SRI_ARR(OTG_STATUS, OTG, inst), 										\
+		SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
+		SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),                               \
+		SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),                                    \
+		SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),                                    \
+		SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),                                   \
+		SRI_ARR(OTG_COUNT_CONTROL, OTG, inst),                                   \
+		SRI_ARR(OTG_COUNT_RESET, OTG, inst),                                   \
+		SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst),                      \
+		SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst),                      \
+		SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst),                      \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),                     \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),                    \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),                     \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),                    \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),                     \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),                    \
+		SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),                            \
+		SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),                             \
+		SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),                           \
+		SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst),                                 \
+		SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst),                            \
+		SRI_ARR(CONTROL, VTG, inst), \
+		SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),  \
+		SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
+		SRI_ARR(OTG_CRC_CNTL, OTG, inst),   \
+		SRI_ARR(OTG_CRC0_DATA_R, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC0_DATA_G, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC1_DATA_R, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC1_DATA_G, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
+		SR_ARR(GSL_SOURCE_SELECT, inst),                                         \
+		SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),                               \
+		SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
+		SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),                                    \
+		SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),                                    \
+		SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),                                 \
+		SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),                              \
+		SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),                              \
+		SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),                            \
+		SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),                                \
+		SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \
+		SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst),                                 \
+		SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \
+		SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \
+		SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst),                                 \
+		SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\
+		SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
+		SRI_ARR(INTERRUPT_DEST, OTG, inst)
+
+/* CLK SRC */
+#define CS_COMMON_REG_LIST_DCN42_RI(index, pllid)               \
+	SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \
+		SRII_ARR_2(PHASE, DP_DTO, 0, index),                    \
+		SRII_ARR_2(PHASE, DP_DTO, 1, index),                    \
+		SRII_ARR_2(PHASE, DP_DTO, 2, index),                    \
+		SRII_ARR_2(PHASE, DP_DTO, 3, index),                    \
+		SRII_ARR_2(MODULO, DP_DTO, 0, index),                   \
+		SRII_ARR_2(MODULO, DP_DTO, 1, index),                   \
+		SRII_ARR_2(MODULO, DP_DTO, 2, index),                   \
+		SRII_ARR_2(MODULO, DP_DTO, 3, index),                   \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index),             \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index),             \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index),             \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index),             \
+		SR_ARR(OTG_PIXEL_RATE_DIV, index)
+
+/* ABM */
+#define ABM_DCN42_REG_LIST_RI(id)                               \
+	SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id),                   \
+		SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id),               \
+		SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id),                 \
+		SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id),              \
+		SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id),        \
+		SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id),            \
+		SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id),             \
+		SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id),                   \
+		SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+		SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id),       \
+		SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id),      \
+		SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id),               \
+		SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id),              \
+		SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id),        \
+		SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id)
+
+/* HUBP */
+#define HUBP_REG_LIST_DCN42_RI(id)                                     \
+	HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \
+		SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id),                         \
+		SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id),                       \
+		SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id),                   \
+		HUBP_3DLUT_FL_REG_LIST_DCN401(id)
+struct dcn42_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn42_create_resource_pool(
+	const struct dc_init_data *init_data,
+	struct dc *dc);
+
+enum dc_status dcn42_validate_bandwidth(struct dc *dc,
+							  struct dc_state *context,
+							  enum dc_validate_mode validate_mode);
+
+void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
+int dcn42_get_power_profile(const struct dc_state *context);
+
+#endif /* _DCN42_RESOURCE_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2026 Advanced Micro Devices, Inc.
+
+
+
+#include "dc.h"
+#include "dcn42_resource_fpu.h"
+
+#define DC_LOGGER_INIT(logger)
+
+
+void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context)
+{
+	enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;
+	unsigned int i, plane_count = 0;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	dc_assert_fp_enabled();
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (context->res_ctx.pipe_ctx[i].plane_state)
+			plane_count++;
+	}
+	/*dcn42 has no z10*/
+	if (context->stream_count == 0 || plane_count == 0) {
+		support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
+	} else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
+		struct dc_link *link = context->streams[0]->sink->link;
+		bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
+								link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
+		bool is_replay = link && link->replay_settings.replay_feature_enabled;
+
+		if (is_psr || is_replay)
+			support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
+		else {
+			/*here we allow z8 for eDP based on dml21 output*/
+			support = context->bw_ctx.bw.dcn.clk.zstate_support ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;
+		}
+
+		DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n, z8_stutter_efficiency: %d\n",
+			 support, (int)context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period,
+			 (int)context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency);
+	}
+	context->bw_ctx.bw.dcn.clk.zstate_support = support;
+
+}
+
+bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context)
+{
+	bool odm_override = false;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+	if (dc->ctx->dce_environment == DCE_ENV_DIAG)
+		return false;
+
+	if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
+
+		if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 &&
+			context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) {
+			odm_override = true;
+			context->streams[0]->debug.force_odm_combine_segments = 2;
+		}
+		DC_LOG_SMU("odm_override: %d, eDP pixelclock: %d, force_odm2to1_for_edp_pixclk_mhz: %d\n",
+			odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz);
+	}
+	return odm_override;
+}
+

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+
+#ifndef _DCN42_RESOURCE_FPU_H_
+#define _DCN42_RESOURCE_FPU_H_
+
+#include "core_types.h"
+
+void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context);
+bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context);
+#endif /* _DCN42_RESOURCE_FPU_H_ */

linux-7.2.3/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2026 Advanced Micro Devices, Inc.
+
+#ifndef _DCN42B_RESOURCE_H_
+#define _DCN42B_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN42B_RES_POOL(pool) \
+	container_of(pool, struct dcn42b_resource_pool, base)
+
+/* DPP */
+#define DPP_REG_LIST_DCN42B_COMMON_RI(id)	                                    \
+	SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id),            \
+		SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id),       \
+		SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id),   \
+		SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id),                                 \
+		SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                   \
+		SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                   \
+		SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id),                                    \
+		SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id),                             \
+		SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),                     \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),                            \
+		SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id),                             \
+		SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id),                           \
+		SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id),                               \
+		SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),                      \
+		SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),                      \
+		SRI_ARR(CM_HIST_CNTL, CM, id),                                          \
+		SRI_ARR(CM_HIST_LOCK, CM, id),                                          \
+		SRI_ARR(CM_HIST_INDEX, CM, id),                                         \
+		SRI_ARR(CM_HIST_DATA, CM, id),                                          \
+		SRI_ARR(CM_HIST_STATUS, CM, id),                                        \
+		SRI_ARR(CM_HIST_SCALE_SRC1, CM, id),                                    \
+		SRI_ARR(CM_HIST_COEFA_SRC2, CM, id),                                    \
+		SRI_ARR(CM_HIST_COEFB_SRC2, CM, id),                                    \
+		SRI_ARR(CM_HIST_COEFC_SRC2, CM, id),                                    \
+		SRI_ARR(CM_HIST_SCALE_SRC3, CM, id),                                    \
+		SRI_ARR(CM_HIST_BIAS_SRC1, CM, id),                                     \
+		SRI_ARR(CM_HIST_BIAS_SRC2, CM, id),                                     \
+		SRI_ARR(CM_HIST_BIAS_SRC3, CM, id),                                     \
+		SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id),                        \
+		SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id),                        \
+		SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id),         \
+		SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id),         \
+		SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id),     \
+		SRI_ARR(SCL_TAP_CONTROL, DSCL, id),                                     \
+		SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id),                             \
+		SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id),                               \
+		SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id),      \
+		SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id),                         \
+		SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id),                         \
+		SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id),                       \
+		SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id),                       \
+		SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id),                                \
+		SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id),                              \
+		SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id),                                \
+		SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id),                              \
+		SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id),        \
+		SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \
+		SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id),                                    \
+		SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id),                                 \
+		SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id),                                 \
+		SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id),                               \
+		SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id),                               \
+		SRI_ARR(CM_POST_CSC_CONTROL, CM, id),                                   \
+		SRI_ARR(CM_POST_CSC_C11_C12, CM, id),                                   \
+		SRI_ARR(CM_POST_CSC_C33_C34, CM, id),                                   \
+		SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                 \
+		SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                 \
+		SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),          \
+		SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id),                                   \
+		SRI_ARR(CM_TEST_DEBUG_DATA, CM, id),                                    \
+		SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                  \
+		SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                       \
+		SRI_ARR(CURSOR0_CONTROL, CM_CUR, id),                                   \
+		SRI_ARR(CURSOR0_COLOR0, CM_CUR, id),                                    \
+		SRI_ARR(CURSOR0_COLOR1, CM_CUR, id),                                    \
+		SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id),                         \
+		SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id),                     \
+		SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id),                                  \
+		SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id),                             \
+		SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id),                             \
+		SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id),   \
+		SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                  \
+		SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id),                                \
+		SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id),                                \
+		SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id),                                  \
+		SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id),                                  \
+		SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id),                                  \
+		SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id),                                 \
+		SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id),                                 \
+		SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id),                                 \
+		SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id),                             \
+		SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id),                               \
+		SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id),                                 \
+		SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id),                               \
+		SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id),                                \
+		SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id),                                   \
+		SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id),                                 \
+		SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id),                                   \
+		SRI_ARR(DSCL_CONTROL, DSCL, id),										\
+		SRI_ARR(DSCL_SC_MODE, DSCL, id),                                        \
+		SRI_ARR(DSCL_EASF_H_MODE, DSCL, id),                                    \
+		SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id),                                 \
+		SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id),                  \
+		SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id),                    \
+		SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id),                        \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_MODE, DSCL, id),                                    \
+		SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id),                                 \
+		SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id),                      \
+		SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id),                      \
+		SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id),                      \
+		SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id),                  \
+		SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id),                    \
+		SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id),                        \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id),                            \
+		SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id),                            \
+		SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id),                                 \
+		SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id),                                 \
+		SRI_ARR(ISHARP_MODE, DSCL, id),                                         \
+		SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id),                        \
+		SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id),                           \
+		SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id),                               \
+		SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id),                                 \
+		SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id),                                 \
+		SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id),                                   \
+		SRI_ARR(ISHARP_DELTA_DATA, DSCL, id),                                   \
+		SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id),                                  \
+		SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id),                            \
+		SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id),                            \
+		SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)
+
+/* Stream encoder */
+#define SE_DCN42B_REG_LIST_RI(id)                                                \
+	SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id),          \
+		SRI_ARR(HDMI_GC, DIG, id),                                              \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id),                         \
+		SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id),                        \
+		SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id),                              \
+		SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id),                              \
+		SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),                            \
+		SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),                              \
+		SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id),       \
+		SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id),       \
+		SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id),       \
+		SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id),              \
+		SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
+		SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id),                                  \
+		SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id),                                  \
+		SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id),                                  \
+		SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id),                                  \
+		SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
+		SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id),         \
+		SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id),           \
+		SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id),           \
+		SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id),              \
+		SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id),         \
+		SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id),          \
+		SRI_ARR(DP_SEC_TIMESTAMP, DP, id),                                      \
+		SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                          \
+		SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                         \
+		SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id),       \
+		SRI_ARR(DME_CONTROL, DME, id),                                          \
+		SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                          \
+		SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                         \
+		SRI_ARR(DIG_FE_CNTL, DIG, id),                                          \
+		SRI_ARR(DIG_FE_EN_CNTL, DIG, id),                                       \
+		SRI_ARR(DIG_FE_CLK_CNTL, DIG, id),                                      \
+		SRI_ARR(DIG_CLOCK_PATTERN, DIG, id),                                    \
+		SRI_ARR(DIG_FIFO_CTRL0, DIG, id),                                       \
+		SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\
+		SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id)
+
+/* HPO DP stream encoder */
+/* Not in DCN42B:
+ * SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id),
+ * SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id),
+ */
+#define DCN42B_HPO_DP_STREAM_ENC_REG_LIST_RI(id)                                             \
+	SR_ARR(DP_STREAM_MAPPER_CONTROL0, id),                                                  \
+		SR_ARR(DP_STREAM_MAPPER_CONTROL1, id),                                              \
+		SR_ARR(DP_STREAM_MAPPER_CONTROL2, id),                                              \
+		SR_ARR(DP_STREAM_MAPPER_CONTROL3, id),                                              \
+		SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),                            \
+		SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),                        \
+		SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),                            \
+		SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \
+		SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),                                    \
+		SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),     \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),                                   \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),                            \
+		SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),              \
+		SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),                         \
+		SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),                                \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),                           \
+		SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),                          \
+		SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),                \
+		SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id)
+
+/*HPO DP link encoder regs */
+#define DCN42B_HPO_DP_LINK_ENC_REG_LIST_RI(id)                    \
+	SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id),         \
+		SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id),        \
+		SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id),     \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id),   \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id),    \
+		SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id),   \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id),       \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
+		SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)
+
+#define VPG_DCN42B_REG_LIST_RI(id) \
+	SRI(VPG_GENERIC_STATUS, VPG, id), \
+	SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
+	SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
+	SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
+	SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
+	SRI(VPG_MEM_PWR, VPG, id)
+
+/* DCCG */
+/*
+ *  Following registers are not used in DCN42B.
+ *
+ *  DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),
+ *	SR(PHYDSYMCLK_CLOCK_CNTL),
+ *  DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),
+ *  DCCG_SRII(PHASE, DP_DTO, 3),
+ *  DCCG_SRII(MODULO, DP_DTO, 3),
+ *	SR(DSCCLK3_DTO_PARAM),
+ *  SR(SYMCLKD_CLOCK_ENABLE),
+ *  SR(SYMCLKE_CLOCK_ENABLE)
+ */
+#define DCCG_REG_LIST_DCN42B_RI()               \
+	SR(DPPCLK_DTO_CTRL),                       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),       \
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),       \
+	SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(PHYASYMCLK_CLOCK_CNTL),  \
+	SR(PHYBSYMCLK_CLOCK_CNTL), \
+	SR(PHYCSYMCLK_CLOCK_CNTL), \
+	SR(DPSTREAMCLK_CNTL), \
+	SR(HDMISTREAMCLK_CNTL), \
+	SR(SYMCLK32_SE_CNTL), \
+	SR(SYMCLK32_LE_CNTL), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), \
+	SR(OTG_PIXEL_RATE_DIV), \
+	SR(DTBCLK_P_CNTL), \
+	SR(DCCG_AUDIO_DTO_SOURCE), \
+	SR(DENTIST_DISPCLK_CNTL), \
+	SR(DPPCLK_CTRL), \
+	DCCG_SRII(MODULO, DP_DTO, 0), \
+	DCCG_SRII(MODULO, DP_DTO, 1), \
+	DCCG_SRII(MODULO, DP_DTO, 2), \
+	DCCG_SRII(PHASE, DP_DTO, 0), \
+	DCCG_SRII(PHASE, DP_DTO, 1), \
+	DCCG_SRII(PHASE, DP_DTO, 2), \
+	SR(OTG_ADD_DROP_PIXEL_CNTL), \
+	SR(DSCCLK0_DTO_PARAM), \
+	SR(DSCCLK1_DTO_PARAM), \
+	SR(DSCCLK2_DTO_PARAM), \
+	SR(DSCCLK_DTO_CTRL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCCG_GATE_DISABLE_CNTL3), \
+	SR(DCCG_GATE_DISABLE_CNTL4), \
+	SR(DCCG_GATE_DISABLE_CNTL5), \
+	SR(DCCG_GATE_DISABLE_CNTL6), \
+	SR(SYMCLKA_CLOCK_ENABLE), \
+	SR(SYMCLKB_CLOCK_ENABLE), \
+	SR(SYMCLKC_CLOCK_ENABLE)
+
+
+/* OPTC */
+#define OPTC_COMMON_REG_LIST_DCN42B_RI(inst)                                      \
+		SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),                                      \
+		SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),                                   \
+		SRI_ARR(OTG_VREADY_PARAM, OTG, inst),                                    \
+		SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),                              \
+		SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst),                              \
+		SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),                            \
+		SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),                           \
+		SRI_ARR(OTG_GSL_CONTROL, OTG, inst),									 \
+		SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
+		SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),                                 \
+		SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),                           \
+		SRI_ARR(OTG_H_TOTAL, OTG, inst),                                         \
+		SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),                               \
+		SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
+		SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
+		SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \
+		SRI_ARR(OTG_V_TOTAL, OTG, inst),  \
+		SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),                               \
+		SRI_ARR(OTG_V_SYNC_A, OTG, inst), \
+		SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
+		SRI_ARR(OTG_CONTROL, OTG, inst), \
+		SRI_ARR(OTG_MASTER_EN, OTG, inst), \
+		SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \
+		SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
+		SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),                            \
+		SRI_ARR(OTG_STEREO_STATUS, OTG, inst),                                   \
+		SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),                                     \
+		SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),                                     \
+		SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),                                 \
+		SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),                                      \
+		SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),                            \
+		SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),                           \
+		SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),                              \
+		SRI_ARR(OTG_STATUS, OTG, inst), 										\
+		SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
+		SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),                               \
+		SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),                                    \
+		SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),                                    \
+		SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),                                   \
+		SRI_ARR(OTG_COUNT_CONTROL, OTG, inst),                                   \
+		SRI_ARR(OTG_COUNT_RESET, OTG, inst),                                   \
+		SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst),                      \
+		SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst),                      \
+		SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst),                      \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),					 \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),                    \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),                     \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),                    \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),                     \
+		SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),                    \
+		SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),                            \
+		SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),                             \
+		SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),                           \
+		SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst),                           \
+		SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst),                           \
+		SRI_ARR(CONTROL, VTG, inst), \
+		SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),  \
+		SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
+		SRI_ARR(OTG_CRC_CNTL, OTG, inst),   \
+		SRI_ARR(OTG_CRC0_DATA_R, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC0_DATA_G, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC1_DATA_R, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC1_DATA_G, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),                                     \
+		SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),                          \
+		SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
+		SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
+		SR_ARR(GSL_SOURCE_SELECT, inst),                                         \
+		SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),                               \
+		SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_CONTROL3, OTG, inst),                                 \
+		SRI_ARR(OTG_GLOBAL_SYNC_STATUS, OTG, inst),                                 \
+		SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),                                    \
+		SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),                                    \
+		SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),                                 \
+		SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),                              \
+		SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),                              \
+		SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),                            \
+		SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),                                \
+		SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \
+		SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst),                                 \
+		SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \
+		SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \
+		SRI_ARR(OTG_DRR_CONTOL2, OTG, inst),                                     \
+		SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst),                                 \
+		SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\
+		SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
+		SRI_ARR(INTERRUPT_DEST, OTG, inst)
+
+/* CLK SRC */
+/**
+ *	 Not used in DCN42B:
+ *   SRII_ARR_2(PHASE, DP_DTO, 3, index),                                     \
+ *   SRII_ARR_2(MODULO, DP_DTO, 3, index),                                    \
+ *   SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index)
+ */
+#define CS_COMMON_REG_LIST_DCN42B_RI(index, pllid)               \
+	SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \
+		SRII_ARR_2(PHASE, DP_DTO, 0, index),                    \
+		SRII_ARR_2(PHASE, DP_DTO, 1, index),                    \
+		SRII_ARR_2(PHASE, DP_DTO, 2, index),                    \
+		SRII_ARR_2(MODULO, DP_DTO, 0, index),                   \
+		SRII_ARR_2(MODULO, DP_DTO, 1, index),                   \
+		SRII_ARR_2(MODULO, DP_DTO, 2, index),                   \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index),             \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index),             \
+		SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index)
+
+/* ABM */
+#define ABM_DCN42B_REG_LIST_RI(id)                               \
+	SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id),                   \
+		SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id),               \
+		SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id),                 \
+		SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id),              \
+		SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id),        \
+		SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id),            \
+		SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id),             \
+		SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id),                   \
+		SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+		SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id),       \
+		SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id),      \
+		SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id),     \
+		SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id),               \
+		SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id),              \
+		SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id),        \
+		SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id)
+
+struct dcn42b_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn42b_create_resource_pool(
+	const struct dc_init_data *init_data,
+	struct dc *dc);
+
+enum dc_status dcn42b_validate_bandwidth(struct dc *dc,
+							  struct dc_state *context,
+							  enum dc_validate_mode validate_mode);
+
+void dcn42b_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
+
+#endif /* _DCN42B_RESOURCE_H_ */