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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/amd/display/include/audio_types.h
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __AUDIO_TYPES_H__
#define __AUDIO_TYPES_H__
#include "signal_types.h"
#include "fixed31_32.h"
#include "dc_dp_types.h"
#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
#define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18
#define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF
struct audio_dp_link_info {
uint32_t link_bandwidth_kbps;
uint32_t hblank_min_symbol_width;
enum dp_link_encoding encoding;
enum dc_link_rate link_rate;
enum dc_lane_count lane_count;
bool is_mst;
};
struct audio_crtc_info {
uint32_t h_total;
uint32_t h_active;
uint32_t v_active;
uint32_t requested_pixel_clock_100Hz; /* in 100Hz */
uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */
uint32_t dsc_bits_per_pixel;
uint32_t dsc_num_slices;
enum dc_color_depth color_depth;
enum dc_pixel_encoding pixel_encoding;
uint16_t refresh_rate;
uint8_t pixel_repetition;
bool interlaced;
uint32_t frl_character_clock_kHz; /* in KHz */
};
struct azalia_clock_info {
uint32_t pixel_clock_in_10khz;
uint32_t audio_dto_phase;
uint32_t audio_dto_module;
uint32_t audio_dto_wall_clock_ratio;
};
enum audio_dto_source {
DTO_SOURCE_UNKNOWN = 0,
DTO_SOURCE_ID0,
DTO_SOURCE_ID1,
DTO_SOURCE_ID2,
DTO_SOURCE_ID3,
DTO_SOURCE_ID4,
DTO_SOURCE_ID5
};
/* PLL information required for AZALIA DTO calculation */
struct audio_pll_info {
uint32_t audio_dto_source_clock_in_khz;
uint32_t ss_percentage;
enum audio_dto_source dto_source;
bool ss_enabled;
};
struct audio_channel_associate_info {
union {
struct {
uint32_t ALL_CHANNEL_FL:4;
uint32_t ALL_CHANNEL_FR:4;
uint32_t ALL_CHANNEL_FC:4;
uint32_t ALL_CHANNEL_Sub:4;
uint32_t ALL_CHANNEL_SL:4;
uint32_t ALL_CHANNEL_SR:4;
uint32_t ALL_CHANNEL_BL:4;
uint32_t ALL_CHANNEL_BR:4;
} bits;
uint32_t u32all;
};
};
struct audio_output {
/* Front DIG id. */
enum engine_id engine_id;
/* encoder output signal */
enum signal_type signal;
/* video timing */
struct audio_crtc_info crtc_info;
/* DP link info */
struct audio_dp_link_info dp_link_info;
/* PLL for audio */
struct audio_pll_info pll_info;
};
enum audio_payload {
CHANNEL_SPLIT_MAPPINGCHANG = 0x9,
};
#endif /* __AUDIO_TYPES_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/bios_parser_interface.h
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_INTERFACE_H__
#define __DAL_BIOS_PARSER_INTERFACE_H__
#include "dc_bios_types.h"
struct bios_parser;
struct bp_init_data {
struct dc_context *ctx;
uint8_t *bios;
};
struct dc_bios *dal_bios_parser_create(
struct bp_init_data *init,
enum dce_version dce_version);
void dal_bios_parser_destroy(struct dc_bios **dcb);
#endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/bios_parser_types.h
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_TYPES_H__
#define __DAL_BIOS_PARSER_TYPES_H__
#include "dm_services.h"
#include "include/signal_types.h"
#include "include/grph_object_ctrl_defs.h"
#include "include/gpio_types.h"
#include "include/link_service_types.h"
/* TODO: include signal_types.h and remove this enum */
enum as_signal_type {
AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
AS_SIGNAL_TYPE_DVI,
AS_SIGNAL_TYPE_HDMI,
AS_SIGNAL_TYPE_LVDS,
AS_SIGNAL_TYPE_DISPLAY_PORT,
AS_SIGNAL_TYPE_GPU_PLL,
AS_SIGNAL_TYPE_XGMI,
AS_SIGNAL_TYPE_UNKNOWN
};
enum bp_result {
BP_RESULT_OK = 0, /* There was no error */
BP_RESULT_BADINPUT, /*Bad input parameter */
BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
BP_RESULT_NORECORD, /* Record can't be found */
BP_RESULT_FAILURE
};
enum bp_encoder_control_action {
/* direct VBIOS translation! Just to simplify the translation */
ENCODER_CONTROL_DISABLE = 0,
ENCODER_CONTROL_ENABLE,
ENCODER_CONTROL_SETUP,
ENCODER_CONTROL_INIT
};
enum bp_transmitter_control_action {
/* direct VBIOS translation! Just to simplify the translation */
TRANSMITTER_CONTROL_DISABLE = 0,
TRANSMITTER_CONTROL_ENABLE,
TRANSMITTER_CONTROL_BACKLIGHT_OFF,
TRANSMITTER_CONTROL_BACKLIGHT_ON,
TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
TRANSMITTER_CONTROL_INIT,
TRANSMITTER_CONTROL_DEACTIVATE,
TRANSMITTER_CONTROL_ACTIAVATE,
TRANSMITTER_CONTROL_SETUP,
TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
/* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
* (power up the panel)
*/
TRANSMITTER_CONTROL_POWER_ON,
/* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
* (power down the panel)
*/
TRANSMITTER_CONTROL_POWER_OFF
};
enum bp_external_encoder_control_action {
EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT = 0x12,
EXTERNAL_ENCODER_CONTROL_DDC_SETUP = 0x14,
};
enum bp_pipe_control_action {
ASIC_PIPE_DISABLE = 0,
ASIC_PIPE_ENABLE,
ASIC_PIPE_INIT
};
enum bp_lvtma_control_action {
LVTMA_CONTROL_LCD_BLOFF = 2,
LVTMA_CONTROL_LCD_BLON = 3,
LVTMA_CONTROL_POWER_ON = 12,
LVTMA_CONTROL_POWER_OFF = 13
};
struct bp_encoder_control {
enum bp_encoder_control_action action;
enum engine_id engine_id;
enum transmitter transmitter;
enum signal_type signal;
enum dc_lane_count lanes_number;
enum dc_color_depth color_depth;
bool enable_dp_audio;
uint32_t pixel_clock; /* khz */
};
struct bp_external_encoder_control {
enum bp_external_encoder_control_action action;
enum engine_id engine_id;
enum dc_link_rate link_rate;
enum dc_lane_count lanes_number;
enum signal_type signal;
enum dc_color_depth color_depth;
bool coherent;
struct graphics_object_id encoder_id;
struct graphics_object_id connector_obj_id;
uint32_t pixel_clock; /* in KHz */
};
struct bp_crtc_source_select {
enum engine_id engine_id;
enum controller_id controller_id;
enum signal_type sink_signal;
enum dc_color_depth color_depth;
};
struct bp_transmitter_control {
enum bp_transmitter_control_action action;
enum engine_id engine_id;
enum transmitter transmitter; /* PhyId */
enum dc_lane_count lanes_number;
enum clock_source_id pll_id; /* needed for DCE 4.0 */
enum signal_type signal;
enum dc_color_depth color_depth; /* not used for DCE6.0 */
enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
enum tx_ffe_id txffe_sel; /* used for DCN3 */
enum engine_id hpo_engine_id; /* used for DCN3 */
struct graphics_object_id connector_obj_id;
/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
* be pixel clock * deep_color_ratio (in KHz)
*/
uint32_t pixel_clock;
uint32_t lane_select;
uint32_t lane_settings;
bool coherent;
bool multi_path;
bool single_pll_mode;
};
struct bp_load_detection_parameters {
enum engine_id engine_id;
uint16_t device_id;
};
struct bp_hw_crtc_timing_parameters {
enum controller_id controller_id;
/* horizontal part */
uint32_t h_total;
uint32_t h_addressable;
uint32_t h_overscan_left;
uint32_t h_overscan_right;
uint32_t h_sync_start;
uint32_t h_sync_width;
/* vertical part */
uint32_t v_total;
uint32_t v_addressable;
uint32_t v_overscan_top;
uint32_t v_overscan_bottom;
uint32_t v_sync_start;
uint32_t v_sync_width;
struct timing_flags {
uint32_t INTERLACE:1;
uint32_t PIXEL_REPETITION:4;
uint32_t HSYNC_POSITIVE_POLARITY:1;
uint32_t VSYNC_POSITIVE_POLARITY:1;
uint32_t HORZ_COUNT_BY_TWO:1;
} flags;
};
struct bp_adjust_pixel_clock_parameters {
/* Input: Signal Type - to be converted to Encoder mode */
enum signal_type signal_type;
/* Input: Encoder object id */
struct graphics_object_id encoder_object_id;
/* Input: Pixel Clock (requested Pixel clock based on Video timing
* standard used) in KHz
*/
uint32_t pixel_clock;
/* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
uint32_t adjusted_pixel_clock;
/* Output: If non-zero, this refDiv value should be used to calculate
* other ppll params */
uint32_t reference_divider;
/* Output: If non-zero, this postDiv value should be used to calculate
* other ppll params */
uint32_t pixel_clock_post_divider;
/* Input: Enable spread spectrum */
bool ss_enable;
};
struct bp_pixel_clock_parameters {
enum controller_id controller_id; /* (Which CRTC uses this PLL) */
enum clock_source_id pll_id; /* Clock Source Id */
/* signal_type -> Encoder Mode - needed by VBIOS Exec table */
enum signal_type signal_type;
/* Adjusted Pixel Clock (after VBIOS exec table)
* that becomes Target Pixel Clock (100 Hz units) */
uint32_t target_pixel_clock_100hz;
/* Calculated Reference divider of Display PLL */
uint32_t reference_divider;
/* Calculated Feedback divider of Display PLL */
uint32_t feedback_divider;
/* Calculated Fractional Feedback divider of Display PLL */
uint32_t fractional_feedback_divider;
/* Calculated Pixel Clock Post divider of Display PLL */
uint32_t pixel_clock_post_divider;
struct graphics_object_id encoder_object_id; /* Encoder object id */
/* VBIOS returns a fixed display clock when DFS-bypass feature
* is enabled (KHz) */
uint32_t dfs_bypass_display_clock;
/* color depth to support HDMI deep color */
enum transmitter_color_depth color_depth;
struct program_pixel_clock_flags {
uint32_t FORCE_PROGRAMMING_OF_PLL:1;
/* Use Engine Clock as source for Display Clock when
* programming PLL */
uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
/* Use external reference clock (refDivSrc for PLL) */
uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
/* Use DFS bypass for Display clock. */
uint32_t SET_DISPCLK_DFS_BYPASS:1;
/* Force program PHY PLL only */
uint32_t PROGRAM_PHY_PLL_ONLY:1;
/* Support for YUV420 */
uint32_t SUPPORT_YUV_420:1;
/* Use XTALIN reference clock source */
uint32_t SET_XTALIN_REF_SRC:1;
/* Use GENLK reference clock source */
uint32_t SET_GENLOCK_REF_DIV_SRC:1;
} flags;
};
enum bp_dce_clock_type {
DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
DCECLOCK_TYPE_DPREFCLK = 1
};
/* DCE Clock Parameters structure for SetDceClock Exec command table */
struct bp_set_dce_clock_parameters {
enum clock_source_id pll_id; /* Clock Source Id */
/* Display clock or DPREFCLK value */
uint32_t target_clock_frequency;
/* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */
enum bp_dce_clock_type clock_type;
struct set_dce_clock_flags {
uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
/* Use XTALIN reference clock source */
uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
/* Use PCIE reference clock source */
uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
/* Use GENLK reference clock source */
uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
} flags;
};
struct spread_spectrum_flags {
/* 1 = Center Spread; 0 = down spread */
uint32_t CENTER_SPREAD:1;
/* 1 = external; 0 = internal */
uint32_t EXTERNAL_SS:1;
/* 1 = delta-sigma type parameter; 0 = ver1 */
uint32_t DS_TYPE:1;
};
struct bp_spread_spectrum_parameters {
enum clock_source_id pll_id;
uint32_t percentage;
uint32_t ds_frac_amount;
union {
struct {
uint32_t step;
uint32_t delay;
uint32_t range; /* In Hz unit */
} ver1;
struct {
uint32_t feedback_amount;
uint32_t nfrac_amount;
uint32_t ds_frac_size;
} ds;
};
struct spread_spectrum_flags flags;
};
struct bp_disp_connector_caps_info {
uint32_t INTERNAL_DISPLAY : 1;
uint32_t INTERNAL_DISPLAY_BL : 1;
uint32_t NO_DDC_PIN : 1;
};
struct bp_encoder_cap_info {
uint32_t DP_HBR2_CAP:1;
uint32_t DP_HBR2_EN:1;
uint32_t DP_HBR3_EN:1;
uint32_t HDMI_6GB_EN:1;
uint32_t IS_DP2_CAPABLE:1;
uint32_t DP_UHBR10_EN:1;
uint32_t DP_UHBR13_5_EN:1;
uint32_t DP_UHBR20_EN:1;
uint32_t DP_IS_USB_C:1;
uint32_t IS_HDMI_FRL_CAPABLE:1;
uint32_t FRL_8G_EN:1;
uint32_t FRL_10G_EN:1;
uint32_t FRL_12G_EN:1;
uint32_t RESERVED:19;
};
struct bp_soc_bb_info {
uint32_t dram_clock_change_latency_100ns;
uint32_t dram_sr_exit_latency_100ns;
uint32_t dram_sr_enter_exit_latency_100ns;
};
struct bp_connector_speed_cap_info {
uint32_t DP_HBR2_EN:1;
uint32_t DP_HBR3_EN:1;
uint32_t HDMI_6GB_EN:1;
uint32_t DP_UHBR10_EN:1;
uint32_t DP_UHBR13_5_EN:1;
uint32_t DP_UHBR20_EN:1;
uint32_t DP_IS_USB_C:1;
uint32_t FRL_8G_EN:1;
uint32_t FRL_10G_EN:1;
uint32_t FRL_12G_EN:1;
uint32_t FRL_16G_EN:1;
uint32_t FRL_20G_EN:1;
uint32_t FRL_24G_EN:1;
uint32_t RESERVED:19;
};
#endif /*__DAL_BIOS_PARSER_TYPES_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+318
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_ASIC_ID_H__
#define __DAL_ASIC_ID_H__
/*
* ASIC internal revision ID
*/
/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
#define SI_TAHITI_P_A0 0x01
#define SI_TAHITI_P_B0 0x05
#define SI_TAHITI_P_B1 0x06
#define SI_PITCAIRN_PM_A0 0x14
#define SI_PITCAIRN_PM_A1 0x15
#define SI_CAPEVERDE_M_A0 0x28
#define SI_CAPEVERDE_M_A1 0x29
#define SI_OLAND_M_A0 0x3C
#define SI_HAINAN_V_A0 0x46
#define SI_UNKNOWN 0xFF
#define ASIC_REV_IS_TAHITI_P(rev) \
((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
#define ASIC_REV_IS_PITCAIRN_PM(rev) \
((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
#define ASIC_REV_IS_CAPEVERDE_M(rev) \
((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
#define ASIC_REV_IS_OLAND_M(rev) \
((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
#define ASIC_REV_IS_HAINAN_V(rev) \
((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
/* DCE80 (based on ci_id.h in Perforce) */
#define CI_BONAIRE_M_A0 0x14
#define CI_BONAIRE_M_A1 0x15
#define CI_HAWAII_P_A0 0x28
#define CI_UNKNOWN 0xFF
#define ASIC_REV_IS_BONAIRE_M(rev) \
((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
#define ASIC_REV_IS_HAWAII_P(rev) \
(rev >= CI_HAWAII_P_A0)
/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
#define KV_SPECTRE_A0 0x01
/* KV2 with Spooky GFX core, including downgraded from Spectre core,
* 3-4-1-1 (CU-Pix-Primitive-RB) */
#define KV_SPOOKY_A0 0x41
/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define KB_KALINDI_A0 0x81
/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define KB_KALINDI_A1 0x82
/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define BV_KALINDI_A2 0x85
/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define ML_GODAVARI_A0 0xA1
/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
#define ML_GODAVARI_A1 0xA2
#define KV_UNKNOWN 0xFF
#define ASIC_REV_IS_KALINDI(rev) \
((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
#define ASIC_REV_IS_BHAVANI(rev) \
((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
#define ASIC_REV_IS_GODAVARI(rev) \
((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
/* VI Family */
/* DCE10 */
#define VI_TONGA_P_A0 20
#define VI_TONGA_P_A1 21
#define VI_FIJI_P_A0 60
/* DCE112 */
#define VI_POLARIS10_P_A0 80
#define VI_POLARIS11_M_A0 90
#define VI_POLARIS12_V_A0 100
#define VI_VEGAM_A0 110
#define VI_UNKNOWN 0xFF
#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
(eChipRev < 40))
#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
(eChipRev < 80))
#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
(eChipRev < VI_POLARIS11_M_A0))
#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \
(eChipRev < VI_POLARIS12_V_A0))
#define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
(eChipRev < VI_VEGAM_A0))
#define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
/* DCE11 */
#define CZ_CARRIZO_A0 0x01
#define STONEY_A0 0x61
#define CZ_UNKNOWN 0xFF
#define ASIC_REV_IS_STONEY(rev) \
((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
/* DCE12 */
#define AI_UNKNOWN 0xFF
#define AI_GREENLAND_P_A0 1
#define AI_GREENLAND_P_A1 2
#define AI_UNKNOWN 0xFF
#define AI_VEGA12_P_A0 20
#define AI_VEGA20_P_A0 40
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0))
#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN))
/* DCN1_0 */
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
#define RAVEN_A0 0x01
#define RAVEN_B0 0x21
#define PICASSO_A0 0x41
/* DCN1_01 */
#define RAVEN2_A0 0x81
#define RAVEN1_F0 0xF0
#define RAVEN_UNKNOWN 0xFF
#define RENOIR_A0 0x91
#ifndef ASICREV_IS_RAVEN
#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
#endif
#define PRID_DALI_DE 0xDE
#define PRID_DALI_DF 0xDF
#define PRID_DALI_E3 0xE3
#define PRID_DALI_E4 0xE4
#define PRID_POLLOCK_94 0x94
#define PRID_POLLOCK_95 0x95
#define PRID_POLLOCK_E9 0xE9
#define PRID_POLLOCK_EA 0xEA
#define PRID_POLLOCK_EB 0xEB
#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
#ifndef ASICREV_IS_RAVEN2
#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0))
#endif
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
#define FAMILY_RV 142 /* DCN 1*/
#define FAMILY_NV 143 /* DCN 2*/
enum {
NV_NAVI10_P_A0 = 1,
NV_NAVI12_P_A0 = 10,
NV_NAVI14_M_A0 = 20,
NV_SIENNA_CICHLID_P_A0 = 40,
NV_DIMGREY_CAVEFISH_P_A0 = 60,
NV_BEIGE_GOBY_P_A0 = 70,
NV_UNKNOWN = 0xFF
};
#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0)
#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0))
#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_BEIGE_GOBY_P_A0))
#define ASICREV_IS_BEIGE_GOBY_P(eChipRev) ((eChipRev >= NV_BEIGE_GOBY_P_A0) && (eChipRev < NV_UNKNOWN))
#define GREEN_SARDINE_A0 0xA1
#ifndef ASICREV_IS_GREEN_SARDINE
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
#endif
#define DEVICE_ID_NV_13FE 0x13FE // CYAN_SKILLFISH
#define DEVICE_ID_NV_143F 0x143F
#define DEVICE_ID_NV_13F9 0x13F9
#define DEVICE_ID_NV_13FA 0x13FA
#define DEVICE_ID_NV_13FB 0x13FB
#define DEVICE_ID_NV_13FC 0x13FC
#define DEVICE_ID_NV_13DB 0x13DB
#define FAMILY_VGH 144
#define DEVICE_ID_VGH_163F 0x163F
#define DEVICE_ID_VGH_1435 0x1435
#define VANGOGH_A0 0x01
#define VANGOGH_UNKNOWN 0xFF
#ifndef ASICREV_IS_VANGOGH
#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
#endif
#define FAMILY_YELLOW_CARP 146
#define YELLOW_CARP_A0 0x01
#define YELLOW_CARP_B0 0x20
#define YELLOW_CARP_UNKNOWN 0xFF
#ifndef ASICREV_IS_YELLOW_CARP
#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
#endif
#define AMDGPU_FAMILY_GC_10_3_6 149
#define GC_10_3_6_A0 0x01
#define GC_10_3_6_UNKNOWN 0xFF
#define ASICREV_IS_GC_10_3_6(eChipRev) ((eChipRev >= GC_10_3_6_A0) && (eChipRev < GC_10_3_6_UNKNOWN))
#define AMDGPU_FAMILY_GC_10_3_7 151
#define GC_10_3_7_A0 0x01
#define GC_10_3_7_UNKNOWN 0xFF
#define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN))
#define AMDGPU_FAMILY_GC_11_0_0 145
#define AMDGPU_FAMILY_GC_11_0_1 148
#define AMDGPU_FAMILY_GC_11_5_0 150
#define AMDGPU_FAMILY_GC_11_5_4 154
#define GC_11_0_0_A0 0x1
#define GC_11_0_2_A0 0x10
#define GC_11_0_3_A0 0x20
#define GC_11_0_4_A0 0xC0
#define GC_11_UNKNOWN 0xFF
#define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0)
#define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < GC_11_0_3_A0)
#define ASICREV_IS_GC_11_0_3(eChipRev) (eChipRev >= GC_11_0_3_A0 && eChipRev < GC_11_0_4_A0)
#define ASICREV_IS_GC_11_0_4(eChipRev) (eChipRev >= GC_11_0_4_A0 && eChipRev < DCN4A_SOC_VAR_B_A0)
#define ASICREV_IS_DCN36(eChipRev) ((eChipRev) >= 0x50 && (eChipRev) < 0xC0)
#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
enum {
GC_12_0_0_A0 = 0x50,
GC_12_0_1_A0 = 0x40,
GC_12_UNKNOWN = 0xFF,
};
#define ASICREV_IS_GC_12_0_1_A0(eChipRev) (eChipRev >= GC_12_0_1_A0 && eChipRev < GC_12_0_0_A0)
#define ASICREV_IS_GC_12_0_0_A0(eChipRev) (eChipRev >= GC_12_0_0_A0 && eChipRev < 0xFF)
#define ASICREV_IS_DCN4(eChipRev) (eChipRev >= GC_12_0_1_A0 && eChipRev < GC_12_0_0_A0)
#define ASICREV_IS_DCN401(eChipRev) (eChipRev >= GC_12_0_0_A0 && eChipRev < GC_12_UNKNOWN)
#define DCN4A_SOC_VAR_B_A0 0xD0
#define ASICREV_IS_DCN4A_SOC_VAR_B(eChipRev) ((eChipRev >= DCN4A_SOC_VAR_B_A0) && (eChipRev < 0xE0))
/*
* ASIC chip ID
*/
/* DCE60 */
#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
#define DEVICE_ID_SI_OLAND_M_6600 0x6600
#define DEVICE_ID_SI_OLAND_M_6608 0x6608
#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
/* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839
#define DEVICE_ID_TEMASH_983D 0x983D
/* RENOIR */
#define DEVICE_ID_RENOIR_1636 0x1636
/* Asic Family IDs for different asic family. */
#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
#define FAMILY_CZ 135 /* Carrizo */
#define FAMILY_AI 141
#define FAMILY_UNKNOWN 0xFF
#endif /* __DAL_ASIC_ID_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/dal_types.h
+73
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_TYPES_H__
#define __DAL_TYPES_H__
#include "signal_types.h"
struct dal_logger;
struct dc_bios;
enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
DCE_VERSION_6_0,
DCE_VERSION_6_1,
DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
DCE_VERSION_10_0,
DCE_VERSION_11_0,
DCE_VERSION_11_2,
DCE_VERSION_11_22,
DCE_VERSION_12_0,
DCE_VERSION_12_1,
DCE_VERSION_MAX,
DCN_VERSION_1_0,
DCN_VERSION_1_01,
DCN_VERSION_2_0,
DCN_VERSION_2_01,
DCN_VERSION_2_1,
DCN_VERSION_3_0,
DCN_VERSION_3_01,
DCN_VERSION_3_02,
DCN_VERSION_3_03,
DCN_VERSION_3_1,
DCN_VERSION_3_14,
DCN_VERSION_3_15,
DCN_VERSION_3_16,
DCN_VERSION_3_2,
DCN_VERSION_3_21,
DCN_VERSION_3_5,
DCN_VERSION_3_51,
DCN_VERSION_3_6,
DCN_VERSION_4_01,
DCN_VERSION_4_2,
DCN_VERSION_4_2B,
DCN_VERSION_MAX
};
#endif /* __DAL_TYPES_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+135
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@@ -0,0 +1,135 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_DDC_SERVICE_TYPES_H__
#define __DAL_DDC_SERVICE_TYPES_H__
/* 0010FA dongles (ST Micro) external converter chip id */
#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA
/* 0022B9 external converter chip id */
#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
#define DP_BRANCH_DEVICE_ID_00001A 0x00001A
#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
#define DP_BRANCH_DEVICE_ID_006037 0x006037
#define DP_BRANCH_DEVICE_ID_001CF8 0x001CF8
#define DP_BRANCH_DEVICE_ID_0060AD 0x0060AD
#define DP_BRANCH_DEVICE_ID_001FF2 0x001FF2
#define DP_BRANCH_HW_REV_10 0x10
#define DP_BRANCH_HW_REV_20 0x20
#define DP_DEVICE_ID_0022B9 0x0022B9
#define DP_DEVICE_ID_38EC11 0x38EC11
#define DP_DEVICE_ID_BA4159 0xBA4159
#define DP_FORCE_PSRSU_CAPABILITY 0x40F
#define DP_SINK_PSR_ACTIVE_VTOTAL 0x373
#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375
#define DP_SOURCE_PSR_ACTIVE_VTOTAL 0x376
enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
DDC_RESULT_SUCESSFULL,
DDC_RESULT_FAILED_CHANNEL_BUSY,
DDC_RESULT_FAILED_TIMEOUT,
DDC_RESULT_FAILED_PROTOCOL_ERROR,
DDC_RESULT_FAILED_NACK,
DDC_RESULT_FAILED_INCOMPLETE,
DDC_RESULT_FAILED_OPERATION,
DDC_RESULT_FAILED_INVALID_OPERATION,
DDC_RESULT_FAILED_BUFFER_OVERFLOW,
DDC_RESULT_FAILED_HPD_DISCON
};
enum ddc_service_type {
DDC_SERVICE_TYPE_CONNECTOR,
DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
};
/**
* display sink capability
*/
struct display_sink_capability {
/* dongle type (DP converter, CV smart dongle) */
enum display_dongle_type dongle_type;
bool is_dongle_type_one;
/**********************************************************
capabilities going INTO SINK DEVICE (stream capabilities)
**********************************************************/
/* Dongle's downstream count. */
uint32_t downstrm_sink_count;
/* Is dongle's downstream count info field (downstrm_sink_count)
* valid. */
bool downstrm_sink_count_valid;
/* Maximum additional audio delay in microsecond (us) */
uint32_t additional_audio_delay;
/* Audio latency value in microsecond (us) */
uint32_t audio_latency;
/* Interlace video latency value in microsecond (us) */
uint32_t video_latency_interlace;
/* Progressive video latency value in microsecond (us) */
uint32_t video_latency_progressive;
/* Dongle caps: Maximum pixel clock supported over dongle for HDMI */
uint32_t max_hdmi_pixel_clock;
/* Dongle caps: Maximum deep color supported over dongle for HDMI */
enum dc_color_depth max_hdmi_deep_color;
/************************************************************
capabilities going OUT OF SOURCE DEVICE (link capabilities)
************************************************************/
/* support for Spread Spectrum(SS) */
bool ss_supported;
/* DP link settings (laneCount, linkRate, Spread) */
uint32_t dp_link_lane_count;
uint32_t dp_link_rate;
uint32_t dp_link_spead;
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
bool is_dp_hdmi_s3d_converter;
/* to check if we have queried the display capability
* for eDP panel already. */
bool is_edp_sink_cap_valid;
enum ddc_transaction_type transaction_type;
enum signal_type signal;
};
struct av_sync_data {
uint8_t av_granularity;/* DPCD 00023h */
uint8_t aud_dec_lat1;/* DPCD 00024h */
uint8_t aud_dec_lat2;/* DPCD 00025h */
uint8_t aud_pp_lat1;/* DPCD 00026h */
uint8_t aud_pp_lat2;/* DPCD 00027h */
uint8_t vid_inter_lat;/* DPCD 00028h */
uint8_t vid_prog_lat;/* DPCD 00029h */
uint8_t aud_del_ins1;/* DPCD 0002Bh */
uint8_t aud_del_ins2;/* DPCD 0002Ch */
uint8_t aud_del_ins3;/* DPCD 0002Dh */
};
#endif /* __DAL_DDC_SERVICE_TYPES_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+237
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_DPCD_DEFS_H__
#define __DAL_DPCD_DEFS_H__
#include <drm/display/drm_dp_helper.h>
#ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
#define DP_SINK_HW_REVISION_START 0x409
#endif
/* Panel Replay*/
#ifndef DP_PANEL_REPLAY_CAPABILITY_SUPPORT // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PANEL_REPLAY_CAPABILITY_SUPPORT 0x0b0
#endif /* DP_PANEL_REPLAY_CAPABILITY_SUPPORT */
#ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PANEL_REPLAY_CAPABILITY 0x0b1
#endif /* DP_PANEL_REPLAY_CAPABILITY */
#ifndef DP_PR_SU_X_GRANULARITY_LOW // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_SU_X_GRANULARITY_LOW 0x0b2
#endif /* DP_PR_SU_X_GRANULARITY_LOW */
#ifndef DP_PR_SU_X_GRANULARITY_HIGH // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_SU_X_GRANULARITY_HIGH 0x0b3
#endif /* DP_PR_SU_X_GRANULARITY_HIGH */
#ifndef DP_PR_SU_Y_GRANULARITY // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_SU_Y_GRANULARITY 0x0b4
#endif /* DP_PR_SU_Y_GRANULARITY */
#ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW 0x0b5
#endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW */
#ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH 0x0b6
#endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH */
#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 0x1b0
#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */
#ifndef DP_PANEL_REPLAY_ENABLE // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PANEL_REPLAY_ENABLE (1 << 0)
#endif /* DP_PANEL_REPLAY_ENABLE */
#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1
#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */
#ifndef DP_PR_ERROR_STATUS // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_ERROR_STATUS 0x2020 /* DP 2.0 */
#endif /* DP_PR_ERROR_STATUS */
#ifndef DP_PR_REPLAY_SINK_STATUS // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_REPLAY_SINK_STATUS 0x2022
#endif /* DP_PR_REPLAY_SINK_STATUS */
#ifndef DP_PR_LINK_CRC_ERROR // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_LINK_CRC_ERROR (1 << 0)
#endif /* DP_PR_LINK_CRC_ERROR */
#ifndef DP_PR_RFB_STORAGE_ERROR // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_RFB_STORAGE_ERROR (1 << 1)
#endif /* DP_PR_RFB_STORAGE_ERROR */
#ifndef DP_PR_VSC_SDP_UNCORRECTABLE_ERROR // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
#endif /* DP_PR_VSC_SDP_UNCORRECTABLE_ERROR */
#ifndef DP_PR_ASSDP_MISSING_ERROR // can remove this once the define gets into linux drm_dp_helper.h
#define DP_PR_ASSDP_MISSING_ERROR (1 << 3) /* eDP 1.5 */
#endif /* DP_PR_ASSDP_MISSING_ERROR */
enum dpcd_revision {
DPCD_REV_10 = 0x10,
DPCD_REV_11 = 0x11,
DPCD_REV_12 = 0x12,
DPCD_REV_13 = 0x13,
DPCD_REV_14 = 0x14
};
/* these are the types stored at DOWNSTREAMPORT_PRESENT */
enum dpcd_downstream_port_type {
DOWNSTREAM_DP = 0,
DOWNSTREAM_VGA,
DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
};
enum dpcd_link_test_patterns {
LINK_TEST_PATTERN_NONE = 0,
LINK_TEST_PATTERN_COLOR_RAMP,
LINK_TEST_PATTERN_VERTICAL_BARS,
LINK_TEST_PATTERN_COLOR_SQUARES
};
enum dpcd_test_color_format {
TEST_COLOR_FORMAT_RGB = 0,
TEST_COLOR_FORMAT_YCBCR422,
TEST_COLOR_FORMAT_YCBCR444
};
enum dpcd_test_bit_depth {
TEST_BIT_DEPTH_6 = 0,
TEST_BIT_DEPTH_8,
TEST_BIT_DEPTH_10,
TEST_BIT_DEPTH_12,
TEST_BIT_DEPTH_16
};
/* PHY (encoder) test patterns
The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
*/
enum dpcd_phy_test_patterns {
PHY_TEST_PATTERN_NONE = 0,
PHY_TEST_PATTERN_D10_2,
PHY_TEST_PATTERN_SYMBOL_ERROR,
PHY_TEST_PATTERN_PRBS7,
PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
PHY_TEST_PATTERN_CP2520_1,
PHY_TEST_PATTERN_CP2520_2,
PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
PHY_TEST_PATTERN_128b_132b_TPS1 = 0x8,
PHY_TEST_PATTERN_128b_132b_TPS2 = 0x10,
PHY_TEST_PATTERN_PRBS9 = 0x18,
PHY_TEST_PATTERN_PRBS11 = 0x20,
PHY_TEST_PATTERN_PRBS15 = 0x28,
PHY_TEST_PATTERN_PRBS23 = 0x30,
PHY_TEST_PATTERN_PRBS31 = 0x38,
PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,
PHY_TEST_PATTERN_SQUARE = 0x48,
PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,
PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,
PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,
};
enum dpcd_test_dyn_range {
TEST_DYN_RANGE_VESA = 0,
TEST_DYN_RANGE_CEA
};
enum dpcd_audio_test_pattern {
AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
AUDIO_TEST_PATTERN_SAWTOOTH
};
enum dpcd_audio_sampling_rate {
AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
AUDIO_SAMPLING_RATE_44_1KHZ,
AUDIO_SAMPLING_RATE_48KHZ,
AUDIO_SAMPLING_RATE_88_2KHZ,
AUDIO_SAMPLING_RATE_96KHZ,
AUDIO_SAMPLING_RATE_176_4KHZ,
AUDIO_SAMPLING_RATE_192KHZ
};
enum dpcd_audio_channels {
AUDIO_CHANNELS_1 = 0,/* direct HW translation */
AUDIO_CHANNELS_2,
AUDIO_CHANNELS_3,
AUDIO_CHANNELS_4,
AUDIO_CHANNELS_5,
AUDIO_CHANNELS_6,
AUDIO_CHANNELS_7,
AUDIO_CHANNELS_8,
AUDIO_CHANNELS_COUNT
};
enum dpcd_audio_test_pattern_periods {
DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
};
/* This enum is for programming DPCD TRAINING_PATTERN_SET */
enum dpcd_training_patterns {
DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
DPCD_TRAINING_PATTERN_1,
DPCD_TRAINING_PATTERN_2,
DPCD_TRAINING_PATTERN_3,
DPCD_TRAINING_PATTERN_4 = 7,
DPCD_128b_132b_TPS1 = 1,
DPCD_128b_132b_TPS2 = 2,
DPCD_128b_132b_TPS2_CDS = 3,
};
/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
It defines the possible PSR states. */
enum dpcd_psr_sink_states {
PSR_SINK_STATE_INACTIVE = 0,
PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
};
#define DP_SOURCE_SEQUENCE 0x30C
#define DP_SOURCE_TABLE_REVISION 0x310
#define DP_SOURCE_PAYLOAD_SIZE 0x311
#define DP_SOURCE_SINK_CAP 0x317
#define DP_SOURCE_BACKLIGHT_LEVEL 0x320
#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326
#define DP_SOURCE_BACKLIGHT_CONTROL 0x32E
#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F
#define DP_SINK_DRR_GRANULARITY 0x33B
#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340
#define DP_SINK_PR_REPLAY_STATUS 0x378
#define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379
#define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
#define DP_SINK_EMISSION_RATE 0x37E
#define DP_SINK_PR_FRAME_SKIP_COUNT 0x337
/* Remove once drm_dp_helper.h is updated upstream */
#ifndef DP_TOTAL_LTTPR_CNT
#define DP_TOTAL_LTTPR_CNT 0xF000A /* 2.1 */
#endif
#endif /* __DAL_DPCD_DEFS_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/fixed31_32.h
+540
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@@ -0,0 +1,540 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_FIXED31_32_H__
#define __DAL_FIXED31_32_H__
#ifndef LLONG_MAX
#define LLONG_MAX 9223372036854775807ll
#endif
#ifndef LLONG_MIN
#define LLONG_MIN (-LLONG_MAX - 1ll)
#endif
#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
#ifndef LLONG_MIN
#define LLONG_MIN (1LL<<63)
#endif
#ifndef LLONG_MAX
#define LLONG_MAX (-1LL>>1)
#endif
/*
* @brief
* Arithmetic operations on real numbers
* represented as fixed-point numbers.
* There are: 1 bit for sign,
* 31 bit for integer part,
* 32 bits for fractional part.
*
* @note
* Currently, overflows and underflows are asserted;
* no special result returned.
*/
struct fixed31_32 {
long long value;
};
/*
* @brief
* Useful constants
*/
static const struct fixed31_32 dc_fixpt_zero = { 0 };
static const struct fixed31_32 dc_fixpt_epsilon = { 1LL };
static const struct fixed31_32 dc_fixpt_half = { 0x80000000LL };
static const struct fixed31_32 dc_fixpt_one = { 0x100000000LL };
/*
* @brief
* Initialization routines
*/
/*
* @brief
* result = numerator / denominator
*/
struct fixed31_32 dc_fixpt_from_fraction(long long numerator, long long denominator);
/*
* @brief
* result = arg
*/
static inline struct fixed31_32 dc_fixpt_from_int(int arg)
{
struct fixed31_32 res;
res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
return res;
}
/*
* @brief
* Unary operators
*/
/*
* @brief
* result = -arg
*/
static inline struct fixed31_32 dc_fixpt_neg(struct fixed31_32 arg)
{
struct fixed31_32 res;
res.value = -arg.value;
return res;
}
/*
* @brief
* result = abs(arg) := (arg >= 0) ? arg : -arg
*/
static inline struct fixed31_32 dc_fixpt_abs(struct fixed31_32 arg)
{
if (arg.value < 0)
return dc_fixpt_neg(arg);
else
return arg;
}
/*
* @brief
* Binary relational operators
*/
/*
* @brief
* result = arg1 < arg2
*/
static inline bool dc_fixpt_lt(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
return arg1.value < arg2.value;
}
/*
* @brief
* result = arg1 <= arg2
*/
static inline bool dc_fixpt_le(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
return arg1.value <= arg2.value;
}
/*
* @brief
* result = arg1 == arg2
*/
static inline bool dc_fixpt_eq(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
return arg1.value == arg2.value;
}
/*
* @brief
* result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2
*/
static inline struct fixed31_32 dc_fixpt_min(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
if (arg1.value <= arg2.value)
return arg1;
else
return arg2;
}
/*
* @brief
* result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1
*/
static inline struct fixed31_32 dc_fixpt_max(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
if (arg1.value <= arg2.value)
return arg2;
else
return arg1;
}
/*
* @brief
* | min_value, when arg <= min_value
* result = | arg, when min_value < arg < max_value
* | max_value, when arg >= max_value
*/
static inline struct fixed31_32 dc_fixpt_clamp(
struct fixed31_32 arg,
struct fixed31_32 min_value,
struct fixed31_32 max_value)
{
if (dc_fixpt_le(arg, min_value))
return min_value;
else if (dc_fixpt_le(max_value, arg))
return max_value;
else
return arg;
}
/*
* @brief
* Binary shift operators
*/
/*
* @brief
* result = arg << shift
*/
static inline struct fixed31_32 dc_fixpt_shl(struct fixed31_32 arg, unsigned char shift)
{
ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift))));
arg.value = arg.value << shift;
return arg;
}
/*
* @brief
* result = arg >> shift
*/
static inline struct fixed31_32 dc_fixpt_shr(struct fixed31_32 arg, unsigned char shift)
{
bool negative = arg.value < 0;
if (negative)
arg.value = -arg.value;
arg.value = arg.value >> shift;
if (negative)
arg.value = -arg.value;
return arg;
}
/*
* @brief
* Binary additive operators
*/
/*
* @brief
* result = arg1 + arg2
*/
static inline struct fixed31_32 dc_fixpt_add(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
struct fixed31_32 res;
ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
res.value = arg1.value + arg2.value;
return res;
}
/*
* @brief
* result = arg1 + arg2
*/
static inline struct fixed31_32 dc_fixpt_add_int(struct fixed31_32 arg1, int arg2)
{
return dc_fixpt_add(arg1, dc_fixpt_from_int(arg2));
}
/*
* @brief
* result = arg1 - arg2
*/
static inline struct fixed31_32 dc_fixpt_sub(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
struct fixed31_32 res;
ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
res.value = arg1.value - arg2.value;
return res;
}
/*
* @brief
* result = arg1 - arg2
*/
static inline struct fixed31_32 dc_fixpt_sub_int(struct fixed31_32 arg1, int arg2)
{
return dc_fixpt_sub(arg1, dc_fixpt_from_int(arg2));
}
/*
* @brief
* Binary multiplicative operators
*/
/*
* @brief
* result = arg1 * arg2
*/
struct fixed31_32 dc_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2);
/*
* @brief
* result = arg1 * arg2
*/
static inline struct fixed31_32 dc_fixpt_mul_int(struct fixed31_32 arg1, int arg2)
{
return dc_fixpt_mul(arg1, dc_fixpt_from_int(arg2));
}
/*
* @brief
* result = square(arg) := arg * arg
*/
struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg);
/*
* @brief
* result = arg1 / arg2
*/
static inline struct fixed31_32 dc_fixpt_div_int(struct fixed31_32 arg1, long long arg2)
{
return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int((int)arg2).value);
}
/*
* @brief
* result = arg1 / arg2
*/
static inline struct fixed31_32 dc_fixpt_div(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
return dc_fixpt_from_fraction(arg1.value, arg2.value);
}
/*
* @brief
* Reciprocal function
*/
/*
* @brief
* result = reciprocal(arg) := 1 / arg
*
* @note
* No special actions taken in case argument is zero.
*/
struct fixed31_32 dc_fixpt_recip(struct fixed31_32 arg);
/*
* @brief
* Trigonometric functions
*/
/*
* @brief
* result = sinc(arg) := sin(arg) / arg
*
* @note
* Argument specified in radians,
* internally it's normalized to [-2pi...2pi] range.
*/
struct fixed31_32 dc_fixpt_sinc(struct fixed31_32 arg);
/*
* @brief
* result = sin(arg)
*
* @note
* Argument specified in radians,
* internally it's normalized to [-2pi...2pi] range.
*/
struct fixed31_32 dc_fixpt_sin(struct fixed31_32 arg);
/*
* @brief
* result = cos(arg)
*
* @note
* Argument specified in radians
* and should be in [-2pi...2pi] range -
* passing arguments outside that range
* will cause incorrect result!
*/
struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg);
/*
* @brief
* Transcendent functions
*/
/*
* @brief
* result = exp(arg)
*
* @note
* Currently, function is verified for abs(arg) <= 1.
*/
struct fixed31_32 dc_fixpt_exp(struct fixed31_32 arg);
/*
* @brief
* result = log(arg)
*
* @note
* Currently, abs(arg) should be less than 1.
* No normalization is done.
* Currently, no special actions taken
* in case of invalid argument(s). Take care!
*/
struct fixed31_32 dc_fixpt_log(struct fixed31_32 arg);
/*
* @brief
* Power function
*/
/*
* @brief
* result = pow(arg1, arg2)
*
* @note
* Currently, abs(arg1) should be less than 1. Take care!
*/
static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixed31_32 arg2)
{
if (arg1.value == 0)
return arg2.value == 0 ? dc_fixpt_one : dc_fixpt_zero;
return dc_fixpt_exp(
dc_fixpt_mul(
dc_fixpt_log(arg1),
arg2));
}
/*
* @brief
* Rounding functions
*/
/*
* @brief
* result = floor(arg) := greatest integer lower than or equal to arg
*/
static inline int dc_fixpt_floor(struct fixed31_32 arg)
{
unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
if (arg.value >= 0)
return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
else
return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
}
/*
* @brief
* result = round(arg) := integer nearest to arg
*/
static inline int dc_fixpt_round(struct fixed31_32 arg)
{
unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
const long long summand = dc_fixpt_half.value;
ASSERT(LLONG_MAX - (long long)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
else
return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
}
/*
* @brief
* result = ceil(arg) := lowest integer greater than or equal to arg
*/
static inline int dc_fixpt_ceil(struct fixed31_32 arg)
{
unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
const long long summand = dc_fixpt_one.value -
dc_fixpt_epsilon.value;
ASSERT(LLONG_MAX - (long long)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
else
return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
}
/* the following two function are used in scaler hw programming to convert fixed
* point value to format 2 bits from integer part and 19 bits from fractional
* part. The same applies for u0d19, 0 bits from integer part and 19 bits from
* fractional
*/
unsigned int dc_fixpt_u4d19(struct fixed31_32 arg);
unsigned int dc_fixpt_u3d19(struct fixed31_32 arg);
unsigned int dc_fixpt_u2d19(struct fixed31_32 arg);
unsigned int dc_fixpt_u0d19(struct fixed31_32 arg);
unsigned int dc_fixpt_clamp_u0d14(struct fixed31_32 arg);
unsigned int dc_fixpt_clamp_u0d10(struct fixed31_32 arg);
int dc_fixpt_s4d19(struct fixed31_32 arg);
static inline struct fixed31_32 dc_fixpt_truncate(struct fixed31_32 arg, unsigned int frac_bits)
{
bool negative = arg.value < 0;
if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) {
ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART);
return arg;
}
if (negative)
arg.value = -arg.value;
arg.value &= (~0ULL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits);
if (negative)
arg.value = -arg.value;
return arg;
}
struct fixed31_32 dc_fixpt_from_ux_dy(unsigned int value, unsigned int integer_bits, unsigned int fractional_bits);
struct fixed31_32 dc_fixpt_from_int_dy(unsigned int int_value,
unsigned int frac_value,
unsigned int integer_bits,
unsigned int fractional_bits);
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/gpio_interface.h
+109
View File
@@ -0,0 +1,109 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GPIO_INTERFACE_H__
#define __DAL_GPIO_INTERFACE_H__
#include "gpio_types.h"
#include "grph_object_defs.h"
struct gpio;
/* Open the handle for future use */
enum gpio_result dal_gpio_open(
struct gpio *gpio,
enum gpio_mode mode);
enum gpio_result dal_gpio_open_ex(
struct gpio *gpio,
enum gpio_mode mode);
/* Get high or low from the pin */
enum gpio_result dal_gpio_get_value(
const struct gpio *gpio,
uint32_t *value);
/* Set pin high or low */
enum gpio_result dal_gpio_set_value(
const struct gpio *gpio,
uint32_t value);
/* Get current mode */
enum gpio_mode dal_gpio_get_mode(
const struct gpio *gpio);
/* Change mode of the handle */
enum gpio_result dal_gpio_change_mode(
struct gpio *gpio,
enum gpio_mode mode);
/* Lock Pin */
enum gpio_result dal_gpio_lock_pin(
struct gpio *gpio);
/* Unlock Pin */
enum gpio_result dal_gpio_unlock_pin(
struct gpio *gpio);
/* Get the GPIO id */
enum gpio_id dal_gpio_get_id(
const struct gpio *gpio);
/* Get the GPIO enum */
uint32_t dal_gpio_get_enum(
const struct gpio *gpio);
/* Set the GPIO pin configuration */
enum gpio_result dal_gpio_set_config(
struct gpio *gpio,
const struct gpio_config_data *config_data);
/* Obtain GPIO pin info */
enum gpio_result dal_gpio_get_pin_info(
const struct gpio *gpio,
struct gpio_pin_info *pin_info);
/* Obtain GPIO sync source */
enum sync_source dal_gpio_get_sync_source(
const struct gpio *gpio);
/* Obtain GPIO pin output state (active low or active high) */
enum gpio_pin_output_state dal_gpio_get_output_state(
const struct gpio *gpio);
struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio);
struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio);
struct hw_generic *dal_gpio_get_generic(struct gpio *gpio);
/* Close the handle */
void dal_gpio_close(
struct gpio *gpio);
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
+124
View File
@@ -0,0 +1,124 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GPIO_SERVICE_INTERFACE_H__
#define __DAL_GPIO_SERVICE_INTERFACE_H__
#include "gpio_types.h"
#include "gpio_interface.h"
#include "hw/gpio.h"
struct gpio_service;
struct gpio *dal_gpio_create(
struct gpio_service *service,
enum gpio_id id,
uint32_t en,
enum gpio_pin_output_state output_state);
void dal_gpio_destroy(
struct gpio **ptr);
struct gpio_service *dal_gpio_service_create(
enum dce_version dce_version,
enum dce_environment dce_environment,
struct dc_context *ctx);
struct gpio *dal_gpio_service_create_irq(
struct gpio_service *service,
uint32_t offset,
uint32_t mask);
struct gpio *dal_gpio_service_create_generic_mux(
struct gpio_service *service,
uint32_t offset,
uint32_t mask);
void dal_gpio_destroy_generic_mux(
struct gpio **mux);
enum gpio_result dal_mux_setup_config(
struct gpio *mux,
struct gpio_generic_mux_config *config);
struct gpio_pin_info dal_gpio_get_generic_pin_info(
struct gpio_service *service,
enum gpio_id id,
uint32_t en);
struct ddc *dal_gpio_create_ddc(
struct gpio_service *service,
uint32_t offset,
uint32_t mask,
struct gpio_ddc_hw_info *info);
void dal_gpio_destroy_ddc(
struct ddc **ddc);
void dal_gpio_service_destroy(
struct gpio_service **ptr);
enum dc_irq_source dal_irq_get_source(
const struct gpio *irq);
enum dc_irq_source dal_irq_get_rx_source(
const struct gpio *irq);
enum dc_irq_source dal_irq_get_read_request(
const struct gpio *irq);
enum gpio_result dal_irq_setup_hpd_filter(
struct gpio *irq,
struct gpio_hpd_config *config);
struct gpio *dal_gpio_create_irq(
struct gpio_service *service,
enum gpio_id id,
uint32_t en);
void dal_gpio_destroy_irq(
struct gpio **ptr);
enum gpio_result dal_ddc_open(
struct ddc *ddc,
enum gpio_mode mode,
enum gpio_ddc_config_type config_type);
enum gpio_result dal_ddc_change_mode(
struct ddc *ddc,
enum gpio_mode mode);
enum gpio_ddc_line dal_ddc_get_line(
const struct ddc *ddc);
enum gpio_result dal_ddc_set_config(
struct ddc *ddc,
enum gpio_ddc_config_type config_type);
void dal_ddc_close(
struct ddc *ddc);
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/gpio_types.h
+332
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GPIO_TYPES_H__
#define __DAL_GPIO_TYPES_H__
#define BUNDLE_A_MASK 0x00FFF000L
#define BUNDLE_B_MASK 0x00000FFFL
/*
* gpio_result
*
* @brief
* The possible return codes that the GPIO object can return.
* These return codes can be generated
* directly by the GPIO object or from the GPIOPin object.
*/
enum gpio_result {
GPIO_RESULT_OK,
GPIO_RESULT_NULL_HANDLE,
GPIO_RESULT_INVALID_DATA,
GPIO_RESULT_DEVICE_BUSY,
GPIO_RESULT_OPEN_FAILED,
GPIO_RESULT_ALREADY_OPENED,
GPIO_RESULT_NON_SPECIFIC_ERROR
};
/*
* @brief
* Used to identify the specific GPIO device
*
* @notes
* These constants are used as indices in a vector.
* Thus they should start from zero and be contiguous.
*/
enum gpio_id {
GPIO_ID_UNKNOWN = (-1),
GPIO_ID_DDC_DATA,
GPIO_ID_DDC_CLOCK,
GPIO_ID_GENERIC,
GPIO_ID_HPD,
GPIO_ID_GPIO_PAD,
GPIO_ID_VIP_PAD,
GPIO_ID_SYNC,
GPIO_ID_GSL, /* global swap lock */
GPIO_ID_COUNT,
GPIO_ID_MIN = GPIO_ID_DDC_DATA,
GPIO_ID_MAX = GPIO_ID_GSL
};
#define GPIO_ENUM_UNKNOWN \
32
struct gpio_pin_info {
uint32_t offset;
uint32_t offset_y;
uint32_t offset_en;
uint32_t offset_mask;
uint32_t mask;
uint32_t mask_y;
uint32_t mask_en;
uint32_t mask_mask;
};
enum gpio_pin_output_state {
GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW,
GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH,
GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
};
enum gpio_generic {
GPIO_GENERIC_UNKNOWN = (-1),
GPIO_GENERIC_A,
GPIO_GENERIC_B,
GPIO_GENERIC_C,
GPIO_GENERIC_D,
GPIO_GENERIC_E,
GPIO_GENERIC_F,
GPIO_GENERIC_G,
GPIO_GENERIC_COUNT,
GPIO_GENERIC_MIN = GPIO_GENERIC_A,
GPIO_GENERIC_MAX = GPIO_GENERIC_B
};
enum gpio_hpd {
GPIO_HPD_UNKNOWN = (-1),
GPIO_HPD_1,
GPIO_HPD_2,
GPIO_HPD_3,
GPIO_HPD_4,
GPIO_HPD_5,
GPIO_HPD_6,
GPIO_HPD_COUNT,
GPIO_HPD_MIN = GPIO_HPD_1,
GPIO_HPD_MAX = GPIO_HPD_6
};
enum gpio_gpio_pad {
GPIO_GPIO_PAD_UNKNOWN = (-1),
GPIO_GPIO_PAD_0,
GPIO_GPIO_PAD_1,
GPIO_GPIO_PAD_2,
GPIO_GPIO_PAD_3,
GPIO_GPIO_PAD_4,
GPIO_GPIO_PAD_5,
GPIO_GPIO_PAD_6,
GPIO_GPIO_PAD_7,
GPIO_GPIO_PAD_8,
GPIO_GPIO_PAD_9,
GPIO_GPIO_PAD_10,
GPIO_GPIO_PAD_11,
GPIO_GPIO_PAD_12,
GPIO_GPIO_PAD_13,
GPIO_GPIO_PAD_14,
GPIO_GPIO_PAD_15,
GPIO_GPIO_PAD_16,
GPIO_GPIO_PAD_17,
GPIO_GPIO_PAD_18,
GPIO_GPIO_PAD_19,
GPIO_GPIO_PAD_20,
GPIO_GPIO_PAD_21,
GPIO_GPIO_PAD_22,
GPIO_GPIO_PAD_23,
GPIO_GPIO_PAD_24,
GPIO_GPIO_PAD_25,
GPIO_GPIO_PAD_26,
GPIO_GPIO_PAD_27,
GPIO_GPIO_PAD_28,
GPIO_GPIO_PAD_29,
GPIO_GPIO_PAD_30,
GPIO_GPIO_PAD_COUNT,
GPIO_GPIO_PAD_MIN = GPIO_GPIO_PAD_0,
GPIO_GPIO_PAD_MAX = GPIO_GPIO_PAD_30
};
enum gpio_vip_pad {
GPIO_VIP_PAD_UNKNOWN = (-1),
/* following never used -
* GPIO_ID_DDC_CLOCK::GPIO_DDC_LINE_VIP_PAD defined instead */
GPIO_VIP_PAD_SCL,
/* following never used -
* GPIO_ID_DDC_DATA::GPIO_DDC_LINE_VIP_PAD defined instead */
GPIO_VIP_PAD_SDA,
GPIO_VIP_PAD_VHAD,
GPIO_VIP_PAD_VPHCTL,
GPIO_VIP_PAD_VIPCLK,
GPIO_VIP_PAD_VID,
GPIO_VIP_PAD_VPCLK0,
GPIO_VIP_PAD_DVALID,
GPIO_VIP_PAD_PSYNC,
GPIO_VIP_PAD_COUNT,
GPIO_VIP_PAD_MIN = GPIO_VIP_PAD_SCL,
GPIO_VIP_PAD_MAX = GPIO_VIP_PAD_PSYNC
};
enum gpio_sync {
GPIO_SYNC_UNKNOWN = (-1),
GPIO_SYNC_HSYNC_A,
GPIO_SYNC_VSYNC_A,
GPIO_SYNC_HSYNC_B,
GPIO_SYNC_VSYNC_B,
GPIO_SYNC_COUNT,
GPIO_SYNC_MIN = GPIO_SYNC_HSYNC_A,
GPIO_SYNC_MAX = GPIO_SYNC_VSYNC_B
};
enum gpio_gsl {
GPIO_GSL_UNKNOWN = (-1),
GPIO_GSL_GENLOCK_CLOCK,
GPIO_GSL_GENLOCK_VSYNC,
GPIO_GSL_SWAPLOCK_A,
GPIO_GSL_SWAPLOCK_B,
GPIO_GSL_COUNT,
GPIO_GSL_MIN = GPIO_GSL_GENLOCK_CLOCK,
GPIO_GSL_MAX = GPIO_GSL_SWAPLOCK_B
};
/*
* @brief
* Unique Id for DDC handle.
* Values are meaningful (used as indexes to array)
*/
enum gpio_ddc_line {
GPIO_DDC_LINE_UNKNOWN = (-1),
GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_DDC2,
GPIO_DDC_LINE_DDC3,
GPIO_DDC_LINE_DDC4,
GPIO_DDC_LINE_DDC5,
GPIO_DDC_LINE_DDC6,
GPIO_DDC_LINE_DDC_VGA,
GPIO_DDC_LINE_VIP_PAD,
GPIO_DDC_LINE_I2C_PAD = GPIO_DDC_LINE_VIP_PAD,
GPIO_DDC_LINE_COUNT,
GPIO_DDC_LINE_MIN = GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_MAX = GPIO_DDC_LINE_I2C_PAD
};
/*
* @brief
* Identifies the mode of operation to open a GPIO device.
* A GPIO device (pin) can be programmed in only one of these modes at a time.
*/
enum gpio_mode {
GPIO_MODE_UNKNOWN = (-1),
GPIO_MODE_INPUT,
GPIO_MODE_OUTPUT,
GPIO_MODE_FAST_OUTPUT,
GPIO_MODE_HARDWARE,
GPIO_MODE_INTERRUPT
};
/*
* @brief
* Identifies the source of the signal when GPIO is in HW mode.
* get_signal_source() will return GPIO_SYGNAL_SOURCE__UNKNOWN
* when one of the following holds:
* 1. GPIO is input GPIO
* 2. GPIO is not opened in HW mode
* 3. GPIO does not have fixed signal source
* (like DC_GenericA have mux instead fixed)
*/
enum gpio_signal_source {
GPIO_SIGNAL_SOURCE_UNKNOWN = (-1),
GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC,
GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC,
GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC,
GPIO_SIGNAL_SOURCE_DACA_HSYNC,
GPIO_SIGNAL_SOURCE_DACB_HSYNC,
GPIO_SIGNAL_SOURCE_DACA_VSYNC,
GPIO_SIGNAL_SOURCE_DACB_VSYNC,
};
enum gpio_stereo_source {
GPIO_STEREO_SOURCE_UNKNOWN = (-1),
GPIO_STEREO_SOURCE_D1,
GPIO_STEREO_SOURCE_D2,
GPIO_STEREO_SOURCE_D3,
GPIO_STEREO_SOURCE_D4,
GPIO_STEREO_SOURCE_D5,
GPIO_STEREO_SOURCE_D6
};
/*
* GPIO config
*/
enum gpio_config_type {
GPIO_CONFIG_TYPE_NONE,
GPIO_CONFIG_TYPE_DDC,
GPIO_CONFIG_TYPE_HPD,
GPIO_CONFIG_TYPE_GENERIC_MUX,
GPIO_CONFIG_TYPE_GSL_MUX,
GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE
};
/* DDC configuration */
enum gpio_ddc_config_type {
GPIO_DDC_CONFIG_TYPE_MODE_AUX,
GPIO_DDC_CONFIG_TYPE_MODE_I2C,
GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT,
GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT,
GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING
};
struct gpio_ddc_config {
enum gpio_ddc_config_type type;
bool data_en_bit_present;
bool clock_en_bit_present;
};
/* HPD configuration */
struct gpio_hpd_config {
uint32_t delay_on_connect; /* milliseconds */
uint32_t delay_on_disconnect; /* milliseconds */
};
struct gpio_generic_mux_config {
bool enable_output_from_mux;
enum gpio_signal_source mux_select;
enum gpio_stereo_source stereo_select;
};
enum gpio_gsl_mux_config_type {
GPIO_GSL_MUX_CONFIG_TYPE_DISABLE,
GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC,
GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC
};
struct gpio_gsl_mux_config {
enum gpio_gsl_mux_config_type type;
/* Actually sync_source type,
* however we want to avoid inter-component includes here */
uint32_t gsl_group;
};
struct gpio_config_data {
enum gpio_config_type type;
union {
struct gpio_ddc_config ddc;
struct gpio_hpd_config hpd;
struct gpio_generic_mux_config generic_mux;
struct gpio_gsl_mux_config gsl_mux;
} config;
};
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+438
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
#include "grph_object_defs.h"
/*
* #####################################################
* #####################################################
*
* These defines shared between asic_control/bios_parser and other
* DAL components
*
* #####################################################
* #####################################################
*/
enum display_output_bit_depth {
PANEL_UNDEFINE = 0,
PANEL_6BIT_COLOR = 1,
PANEL_8BIT_COLOR = 2,
PANEL_10BIT_COLOR = 3,
PANEL_12BIT_COLOR = 4,
PANEL_16BIT_COLOR = 5,
};
/* Device type as abstracted by ATOM BIOS */
enum dal_device_type {
DEVICE_TYPE_UNKNOWN = 0,
DEVICE_TYPE_LCD,
DEVICE_TYPE_CRT,
DEVICE_TYPE_DFP,
DEVICE_TYPE_CV,
DEVICE_TYPE_TV,
DEVICE_TYPE_CF,
DEVICE_TYPE_WIRELESS
};
/* Device ID as abstracted by ATOM BIOS */
struct device_id {
enum dal_device_type device_type:16;
uint32_t enum_id:16; /* 1 based enum */
uint16_t raw_device_tag;
};
struct graphics_object_i2c_info {
struct gpio_info {
uint32_t clk_mask_register_index;
uint32_t clk_en_register_index;
uint32_t clk_y_register_index;
uint32_t clk_a_register_index;
uint32_t data_mask_register_index;
uint32_t data_en_register_index;
uint32_t data_y_register_index;
uint32_t data_a_register_index;
uint32_t clk_mask_shift;
uint32_t clk_en_shift;
uint32_t clk_y_shift;
uint32_t clk_a_shift;
uint32_t data_mask_shift;
uint32_t data_en_shift;
uint32_t data_y_shift;
uint32_t data_a_shift;
} gpio_info;
bool i2c_hw_assist;
uint32_t i2c_line;
uint32_t i2c_engine_id;
uint32_t i2c_slave_address;
};
struct graphics_object_hpd_info {
uint8_t hpd_int_gpio_uid;
uint8_t hpd_active;
};
struct connector_device_tag_info {
uint32_t acpi_device;
struct device_id dev_id;
};
struct device_timing {
struct misc_info {
uint32_t HORIZONTAL_CUT_OFF:1;
/* 0=Active High, 1=Active Low */
uint32_t H_SYNC_POLARITY:1;
/* 0=Active High, 1=Active Low */
uint32_t V_SYNC_POLARITY:1;
uint32_t VERTICAL_CUT_OFF:1;
uint32_t H_REPLICATION_BY2:1;
uint32_t V_REPLICATION_BY2:1;
uint32_t COMPOSITE_SYNC:1;
uint32_t INTERLACE:1;
uint32_t DOUBLE_CLOCK:1;
uint32_t RGB888:1;
uint32_t GREY_LEVEL:2;
uint32_t SPATIAL:1;
uint32_t TEMPORAL:1;
uint32_t API_ENABLED:1;
} misc_info;
uint32_t pixel_clk; /* in KHz */
uint32_t horizontal_addressable;
uint32_t horizontal_blanking_time;
uint32_t vertical_addressable;
uint32_t vertical_blanking_time;
uint32_t horizontal_sync_offset;
uint32_t horizontal_sync_width;
uint32_t vertical_sync_offset;
uint32_t vertical_sync_width;
uint32_t horizontal_border;
uint32_t vertical_border;
};
struct supported_refresh_rate {
uint32_t REFRESH_RATE_30HZ:1;
uint32_t REFRESH_RATE_40HZ:1;
uint32_t REFRESH_RATE_48HZ:1;
uint32_t REFRESH_RATE_50HZ:1;
uint32_t REFRESH_RATE_60HZ:1;
};
struct embedded_panel_info {
struct device_timing lcd_timing;
uint32_t ss_id;
struct supported_refresh_rate supported_rr;
uint32_t drr_enabled;
uint32_t min_drr_refresh_rate;
bool realtek_eDPToLVDS;
uint16_t panel_width_mm;
uint16_t panel_height_mm;
uint16_t fake_edid_size;
const uint8_t *fake_edid;
};
struct dc_firmware_info {
struct pll_info {
uint32_t crystal_frequency; /* in KHz */
uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
} pll_info;
struct firmware_feature {
uint32_t memory_clk_ss_percentage;
uint32_t engine_clk_ss_percentage;
} feature;
uint32_t max_pixel_clock; /* in KHz */
uint32_t default_display_engine_pll_frequency; /* in KHz */
uint32_t external_clock_source_frequency_for_dp; /* in KHz */
uint32_t smu_gpu_pll_output_freq; /* in KHz */
uint8_t min_allowed_bl_level;
uint8_t remote_display_config;
uint32_t default_memory_clk; /* in KHz */
uint32_t default_engine_clk; /* in KHz */
uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
bool oem_i2c_present;
uint8_t oem_i2c_obj_id;
};
struct dc_vram_info {
unsigned int num_chans;
unsigned int dram_channel_width_bytes;
};
struct step_and_delay_info {
uint32_t step;
uint32_t delay;
uint32_t recommended_ref_div;
};
struct spread_spectrum_info {
struct spread_spectrum_type {
bool CENTER_MODE:1;
bool EXTERNAL:1;
bool STEP_AND_DELAY_INFO:1;
} type;
/* in unit of 0.01% (spreadPercentageDivider = 100),
otherwise in 0.001% units (spreadPercentageDivider = 1000); */
uint32_t spread_spectrum_percentage;
uint32_t spread_percentage_divider; /* 100 or 1000 */
uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
union {
struct step_and_delay_info step_and_delay_info;
/* For mem/engine/uvd, Clock Out frequence (VCO ),
in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
for DP, it is link clock ( 270000 or 162000 ) */
uint32_t target_clock_range; /* in KHz */
};
};
struct graphics_object_encoder_cap_info {
uint32_t dp_hbr2_cap:1;
uint32_t dp_hbr2_validated:1;
/*
* TODO: added MST and HDMI 6G capable flags
*/
uint32_t reserved:15;
};
struct din_connector_info {
uint32_t gpio_id;
bool gpio_tv_active_state;
};
/* Invalid channel mapping */
enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
/**
* DDI PHY channel mapping reflecting XBAR setting
*/
union ddi_channel_mapping {
struct mapping {
uint8_t lane0:2; /* Mapping for lane 0 */
uint8_t lane1:2; /* Mapping for lane 1 */
uint8_t lane2:2; /* Mapping for lane 2 */
uint8_t lane3:2; /* Mapping for lane 3 */
} mapping;
uint8_t raw;
};
/**
* Transmitter output configuration description
*/
struct transmitter_configuration_info {
/* DDI PHY ID for the transmitter */
enum transmitter transmitter_phy_id;
/* DDI PHY channel mapping reflecting crossbar setting */
union ddi_channel_mapping output_channel_mapping;
};
struct transmitter_configuration {
/* Configuration for the primary transmitter */
struct transmitter_configuration_info primary_transmitter_config;
/* Secondary transmitter configuration for Dual-link DVI */
struct transmitter_configuration_info secondary_transmitter_config;
};
/* These size should be sufficient to store info coming from BIOS */
#define NUMBER_OF_UCHAR_FOR_GUID 16
#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
#define NUMBER_OF_CSR_M3_ARB 10
#define NUMBER_OF_AVAILABLE_SCLK 5
struct i2c_reg_info {
unsigned char i2c_reg_index;
unsigned char i2c_reg_val;
};
struct ext_hdmi_settings {
unsigned char slv_addr;
unsigned char reg_num;
struct i2c_reg_info reg_settings[9];
unsigned char reg_num_6g;
struct i2c_reg_info reg_settings_6g[3];
};
struct edp_info {
uint16_t edp_backlight_pwm_hz;
uint16_t edp_ss_percentage;
uint16_t edp_ss_rate_10hz;
uint8_t edp_pwr_on_off_delay;
uint8_t edp_pwr_on_vary_bl_to_blon;
uint8_t edp_pwr_down_bloff_to_vary_bloff;
uint8_t edp_panel_bpc;
uint8_t edp_bootup_bl_level;
};
/* V6 */
struct integrated_info {
struct display_connection_info {
struct external_display_path {
/* A bit vector to show what devices are supported */
uint32_t device_tag;
/* 16bit device ACPI id. */
uint32_t device_acpi_enum;
/* A physical connector for displays to plug in,
using object connector definitions */
struct graphics_object_id device_connector_id;
/* An index into external AUX/DDC channel LUT */
uint8_t ext_aux_ddc_lut_index;
/* An index into external HPD pin LUT */
uint8_t ext_hpd_pin_lut_index;
/* external encoder object id */
struct graphics_object_id ext_encoder_obj_id;
/* XBAR mapping of the PHY channels */
union ddi_channel_mapping channel_mapping;
unsigned short caps;
} path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
uint8_t checksum;
uint8_t fixdpvoltageswing;
} ext_disp_conn_info; /* exiting long long time */
struct available_s_clk_list {
/* Maximum clock supported with specified voltage index */
uint32_t supported_s_clk; /* in KHz */
/* The Voltage Index indicated by FUSE for specified SCLK */
uint32_t voltage_index;
/* The Voltage ID indicated by FUSE for specified SCLK */
uint32_t voltage_id;
} avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
uint8_t memory_type;
uint8_t ma_channel_number;
uint32_t boot_up_engine_clock; /* in KHz */
uint32_t dentist_vco_freq; /* in KHz */
uint32_t boot_up_uma_clock; /* in KHz */
uint32_t boot_up_req_display_vector;
uint32_t other_display_misc;
uint32_t gpu_cap_info;
uint32_t sb_mmio_base_addr;
uint32_t system_config;
uint32_t cpu_cap_info;
uint32_t max_nb_voltage;
uint32_t min_nb_voltage;
uint32_t boot_up_nb_voltage;
uint32_t ext_disp_conn_info_offset;
uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
uint32_t gmc_restore_reset_time;
uint32_t minimum_n_clk;
uint32_t idle_n_clk;
uint32_t ddr_dll_power_up_time;
uint32_t ddr_pll_power_up_time;
/* start for V6 */
uint32_t pcie_clk_ss_type;
uint32_t lvds_ss_percentage;
uint32_t lvds_sspread_rate_in_10hz;
uint32_t hdmi_ss_percentage;
uint32_t hdmi_sspread_rate_in_10hz;
uint32_t dvi_ss_percentage;
uint32_t dvi_sspread_rate_in_10_hz;
uint32_t sclk_dpm_boost_margin;
uint32_t sclk_dpm_throttle_margin;
uint32_t sclk_dpm_tdp_limit_pg;
uint32_t sclk_dpm_tdp_limit_boost;
uint32_t boost_engine_clock;
uint32_t boost_vid_2bit;
uint32_t enable_boost;
uint32_t gnb_tdp_limit;
/* Start from V7 */
uint32_t max_lvds_pclk_freq_in_single_link;
uint32_t lvds_misc;
uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
uint32_t lvds_off_to_on_delay_in_4ms;
uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
uint32_t lvds_reserved1;
uint32_t lvds_bit_depth_control_val;
//Start from V9
unsigned char dp0_ext_hdmi_slv_addr;
unsigned char dp0_ext_hdmi_reg_num;
struct i2c_reg_info dp0_ext_hdmi_reg_settings[9];
unsigned char dp0_ext_hdmi_6g_reg_num;
struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3];
unsigned char dp1_ext_hdmi_slv_addr;
unsigned char dp1_ext_hdmi_reg_num;
struct i2c_reg_info dp1_ext_hdmi_reg_settings[9];
unsigned char dp1_ext_hdmi_6g_reg_num;
struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3];
unsigned char dp2_ext_hdmi_slv_addr;
unsigned char dp2_ext_hdmi_reg_num;
struct i2c_reg_info dp2_ext_hdmi_reg_settings[9];
unsigned char dp2_ext_hdmi_6g_reg_num;
struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3];
unsigned char dp3_ext_hdmi_slv_addr;
unsigned char dp3_ext_hdmi_reg_num;
struct i2c_reg_info dp3_ext_hdmi_reg_settings[9];
unsigned char dp3_ext_hdmi_6g_reg_num;
struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];
/* V11 */
uint32_t dp_ss_control;
/* V2.1 */
struct edp_info edp1_info;
struct edp_info edp2_info;
uint32_t gpuclk_ss_percentage;
uint32_t gpuclk_ss_type;
};
/*
* DFS-bypass flag
*/
/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
enum {
DFS_BYPASS_ENABLE = 0x10
};
enum {
INVALID_BACKLIGHT = -1
};
struct panel_backlight_boundaries {
uint32_t min_signal_level;
uint32_t max_signal_level;
};
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/grph_object_defs.h
+196
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GRPH_OBJECT_DEFS_H__
#define __DAL_GRPH_OBJECT_DEFS_H__
#include "grph_object_id.h"
/* ********************************************************************
* ********************************************************************
*
* These defines shared between All Graphics Objects
*
* ********************************************************************
* ********************************************************************
*/
#define MAX_CONNECTOR_NUMBER_PER_SLOT (16)
#define MAX_BOARD_SLOTS (4)
#define INVALID_CONNECTOR_INDEX ((unsigned int)(-1))
/* HPD unit id - HW direct translation */
enum hpd_source_id {
HPD_SOURCEID1 = 0,
HPD_SOURCEID2,
HPD_SOURCEID3,
HPD_SOURCEID4,
HPD_SOURCEID5,
HPD_SOURCEID6,
HPD_SOURCEID_COUNT,
HPD_SOURCEID_UNKNOWN
};
/* DDC unit id - HW direct translation */
enum channel_id {
CHANNEL_ID_UNKNOWN = 0,
CHANNEL_ID_DDC1,
CHANNEL_ID_DDC2,
CHANNEL_ID_DDC3,
CHANNEL_ID_DDC4,
CHANNEL_ID_DDC5,
CHANNEL_ID_DDC6,
CHANNEL_ID_DDC_VGA,
CHANNEL_ID_I2C_PAD,
CHANNEL_ID_COUNT
};
#define DECODE_CHANNEL_ID(ch_id) \
(ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
(ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
(ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
(ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
(ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
(ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
(ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
(ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
enum transmitter {
TRANSMITTER_UNKNOWN = (-1L),
TRANSMITTER_UNIPHY_A,
TRANSMITTER_UNIPHY_B,
TRANSMITTER_UNIPHY_C,
TRANSMITTER_UNIPHY_D,
TRANSMITTER_UNIPHY_E,
TRANSMITTER_UNIPHY_F,
TRANSMITTER_NUTMEG_CRT,
TRANSMITTER_TRAVIS_CRT,
TRANSMITTER_TRAVIS_LCD,
TRANSMITTER_UNIPHY_G,
TRANSMITTER_COUNT
};
/* Generic source of the synchronisation input/output signal */
/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
enum sync_source {
SYNC_SOURCE_NONE = 0,
/* Source based on controllers */
SYNC_SOURCE_CONTROLLER0,
SYNC_SOURCE_CONTROLLER1,
SYNC_SOURCE_CONTROLLER2,
SYNC_SOURCE_CONTROLLER3,
SYNC_SOURCE_CONTROLLER4,
SYNC_SOURCE_CONTROLLER5,
/* Source based on GSL group */
SYNC_SOURCE_GSL_GROUP0,
SYNC_SOURCE_GSL_GROUP1,
SYNC_SOURCE_GSL_GROUP2,
/* Source based on GSL IOs */
/* These IOs normally used as GSL input/output */
SYNC_SOURCE_GSL_IO_FIRST,
SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
/* Source based on regular IOs */
SYNC_SOURCE_IO_FIRST,
SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
SYNC_SOURCE_IO_GENERIC_B,
SYNC_SOURCE_IO_GENERIC_C,
SYNC_SOURCE_IO_GENERIC_D,
SYNC_SOURCE_IO_GENERIC_E,
SYNC_SOURCE_IO_GENERIC_F,
SYNC_SOURCE_IO_HPD1,
SYNC_SOURCE_IO_HPD2,
SYNC_SOURCE_IO_HSYNC_A,
SYNC_SOURCE_IO_VSYNC_A,
SYNC_SOURCE_IO_HSYNC_B,
SYNC_SOURCE_IO_VSYNC_B,
SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
/* Misc. flow control sources */
SYNC_SOURCE_DUAL_GPU_PIN
};
enum tx_ffe_id {
TX_FFE0 = 0,
TX_FFE1,
TX_FFE2,
TX_FFE3,
TX_FFE_DeEmphasis_Only,
TX_FFE_PreShoot_Only,
TX_FFE_No_FFE,
};
/* connector sizes in millimeters - from BiosParserTypes.hpp */
#define CONNECTOR_SIZE_DVI 40
#define CONNECTOR_SIZE_VGA 32
#define CONNECTOR_SIZE_HDMI 16
#define CONNECTOR_SIZE_DP 16
#define CONNECTOR_SIZE_MINI_DP 9
#define CONNECTOR_SIZE_UNKNOWN 30
enum connector_layout_type {
CONNECTOR_LAYOUT_TYPE_UNKNOWN,
CONNECTOR_LAYOUT_TYPE_DVI_D,
CONNECTOR_LAYOUT_TYPE_DVI_I,
CONNECTOR_LAYOUT_TYPE_VGA,
CONNECTOR_LAYOUT_TYPE_HDMI,
CONNECTOR_LAYOUT_TYPE_DP,
CONNECTOR_LAYOUT_TYPE_MINI_DP,
};
struct connector_layout_info {
struct graphics_object_id connector_id;
enum connector_layout_type connector_type;
unsigned int length;
unsigned int position; /* offset in mm from right side of the board */
};
/* length and width in mm */
struct slot_layout_info {
unsigned int length;
unsigned int width;
unsigned int num_of_connectors;
struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT];
};
struct board_layout_info {
unsigned int num_of_slots;
/* indicates valid information in bracket layout structure. */
unsigned int is_number_of_slots_valid : 1;
unsigned int is_slots_size_valid : 1;
unsigned int is_connector_offsets_valid : 1;
unsigned int is_connector_lengths_valid : 1;
struct slot_layout_info slots[MAX_BOARD_SLOTS];
};
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/grph_object_id.h
+320
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_GRPH_OBJECT_ID_H__
#define __DAL_GRPH_OBJECT_ID_H__
/* Types of graphics objects */
enum object_type {
OBJECT_TYPE_UNKNOWN = 0,
/* Direct ATOM BIOS translation */
OBJECT_TYPE_GPU,
OBJECT_TYPE_ENCODER,
OBJECT_TYPE_CONNECTOR,
OBJECT_TYPE_ROUTER,
OBJECT_TYPE_GENERIC,
/* Driver specific */
OBJECT_TYPE_AUDIO,
OBJECT_TYPE_CONTROLLER,
OBJECT_TYPE_CLOCK_SOURCE,
OBJECT_TYPE_ENGINE,
OBJECT_TYPE_COUNT
};
/* Enumeration inside one type of graphics objects */
enum object_enum_id {
ENUM_ID_UNKNOWN = 0,
ENUM_ID_1,
ENUM_ID_2,
ENUM_ID_3,
ENUM_ID_4,
ENUM_ID_5,
ENUM_ID_6,
ENUM_ID_7,
ENUM_ID_COUNT
};
/* Generic object ids */
enum generic_id {
GENERIC_ID_UNKNOWN = 0,
GENERIC_ID_MXM_OPM,
GENERIC_ID_GLSYNC,
GENERIC_ID_STEREO,
GENERIC_ID_COUNT
};
/* Controller object ids */
enum controller_id {
CONTROLLER_ID_UNDEFINED = 0,
CONTROLLER_ID_D0,
CONTROLLER_ID_D1,
CONTROLLER_ID_D2,
CONTROLLER_ID_D3,
CONTROLLER_ID_D4,
CONTROLLER_ID_D5,
CONTROLLER_ID_UNDERLAY0,
CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
};
#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
/*
* ClockSource object ids.
* We maintain the order matching (more or less) ATOM BIOS
* to improve optimized acquire
*/
enum clock_source_id {
CLOCK_SOURCE_ID_UNDEFINED = 0,
CLOCK_SOURCE_ID_PLL0,
CLOCK_SOURCE_ID_PLL1,
CLOCK_SOURCE_ID_PLL2,
CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
CLOCK_SOURCE_ID_DCPLL,
CLOCK_SOURCE_ID_DFS, /* DENTIST */
CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */
/* Used to distinguish between programming pixel clock and ID (Phy) clock */
CLOCK_SOURCE_ID_DP_DTO,
CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
CLOCK_SOURCE_COMBO_PHY_PLL1,
CLOCK_SOURCE_COMBO_PHY_PLL2,
CLOCK_SOURCE_COMBO_PHY_PLL3,
CLOCK_SOURCE_COMBO_PHY_PLL4,
CLOCK_SOURCE_COMBO_PHY_PLL5,
CLOCK_SOURCE_COMBO_DISPLAY_PLL0
};
/* Encoder object ids */
enum encoder_id {
ENCODER_ID_UNKNOWN = 0,
/* Radeon Class Display Hardware */
ENCODER_ID_INTERNAL_LVDS,
ENCODER_ID_INTERNAL_TMDS1,
ENCODER_ID_INTERNAL_TMDS2,
ENCODER_ID_INTERNAL_DAC1,
ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */
/* External Third Party Encoders */
ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */
ENCODER_ID_INTERNAL_HDMI,
/* Kaledisope (KLDSCP) Class Display Hardware */
ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
ENCODER_ID_INTERNAL_KLDSCP_DAC1,
ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */
/* External TMDS (dual link) */
ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */
ENCODER_ID_INTERNAL_DDI,
ENCODER_ID_INTERNAL_UNIPHY,
ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
ENCODER_ID_INTERNAL_UNIPHY1,
ENCODER_ID_INTERNAL_UNIPHY2,
ENCODER_ID_EXTERNAL_NUTMEG,
ENCODER_ID_EXTERNAL_TRAVIS,
ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */
ENCODER_ID_INTERNAL_UNIPHY3,
ENCODER_ID_INTERNAL_VIRTUAL,
};
/* Connector object ids */
enum connector_id {
CONNECTOR_ID_UNKNOWN = 0,
CONNECTOR_ID_SINGLE_LINK_DVII = 1,
CONNECTOR_ID_DUAL_LINK_DVII = 2,
CONNECTOR_ID_SINGLE_LINK_DVID = 3,
CONNECTOR_ID_DUAL_LINK_DVID = 4,
CONNECTOR_ID_VGA = 5,
CONNECTOR_ID_HDMI_TYPE_A = 12,
CONNECTOR_ID_LVDS = 14,
CONNECTOR_ID_PCIE = 16,
CONNECTOR_ID_HARDCODE_DVI = 18,
CONNECTOR_ID_DISPLAY_PORT = 19,
CONNECTOR_ID_EDP = 20,
CONNECTOR_ID_MXM = 21,
CONNECTOR_ID_WIRELESS = 22,
CONNECTOR_ID_MIRACAST = 23,
CONNECTOR_ID_USBC = 24,
CONNECTOR_ID_VIRTUAL = 100
};
/* Audio object ids */
enum audio_id {
AUDIO_ID_UNKNOWN = 0,
AUDIO_ID_INTERNAL_AZALIA
};
/* Engine object ids */
enum engine_id {
ENGINE_ID_DIGA,
ENGINE_ID_DIGB,
ENGINE_ID_DIGC,
ENGINE_ID_DIGD,
ENGINE_ID_DIGE,
ENGINE_ID_DIGF,
ENGINE_ID_DIGG,
ENGINE_ID_DACA,
ENGINE_ID_DACB,
ENGINE_ID_VCE, /* wireless display pseudo-encoder */
ENGINE_ID_HPO_0,
ENGINE_ID_HPO_1,
ENGINE_ID_HPO_DP_0,
ENGINE_ID_HPO_DP_1,
ENGINE_ID_HPO_DP_2,
ENGINE_ID_HPO_DP_3,
ENGINE_ID_VIRTUAL,
ENGINE_ID_COUNT,
ENGINE_ID_UNKNOWN = (-1L)
};
enum transmitter_color_depth {
TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */
TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */
TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */
TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */
};
enum dp_alt_mode {
DP_Alt_mode__Unknown = 0,
DP_Alt_mode__Connect,
DP_Alt_mode__NoConnect,
};
/*
*****************************************************************************
* graphics_object_id struct
*
* graphics_object_id is a very simple struct wrapping 32bit Graphics
* Object identication
*
* This struct should stay very simple
* No dependencies at all (no includes)
* No debug messages or asserts
* No #ifndef and preprocessor directives
* No grow in space (no more data member)
*****************************************************************************
*/
struct graphics_object_id {
uint32_t id:8;
enum object_enum_id enum_id :4;
enum object_type type :4;
uint32_t reserved:16; /* for padding. total size should be u32 */
};
/* some simple functions for convenient graphics_object_id handle */
static inline struct graphics_object_id dal_graphics_object_id_init(
uint32_t id,
enum object_enum_id enum_id,
enum object_type type)
{
struct graphics_object_id result = {
id, enum_id, type, 0
};
return result;
}
/* Based on internal data members memory layout */
static inline uint32_t dal_graphics_object_id_to_uint(
struct graphics_object_id id)
{
return id.id + (id.enum_id << 0x8) + (id.type << 0xc);
}
static inline enum controller_id dal_graphics_object_id_get_controller_id(
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_CONTROLLER)
return (enum controller_id) id.id;
return CONTROLLER_ID_UNDEFINED;
}
static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id(
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
return (enum clock_source_id) id.id;
return CLOCK_SOURCE_ID_UNDEFINED;
}
static inline enum encoder_id dal_graphics_object_id_get_encoder_id(
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_ENCODER)
return (enum encoder_id) id.id;
return ENCODER_ID_UNKNOWN;
}
static inline enum connector_id dal_graphics_object_id_get_connector_id(
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_CONNECTOR)
return (enum connector_id) id.id;
return CONNECTOR_ID_UNKNOWN;
}
static inline enum audio_id dal_graphics_object_id_get_audio_id(
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_AUDIO)
return (enum audio_id) id.id;
return AUDIO_ID_UNKNOWN;
}
static inline enum engine_id dal_graphics_object_id_get_engine_id(
struct graphics_object_id id)
{
if (id.type == OBJECT_TYPE_ENGINE)
return (enum engine_id) id.id;
return ENGINE_ID_UNKNOWN;
}
static inline bool dal_graphics_object_id_equal(
struct graphics_object_id id_1,
struct graphics_object_id id_2)
{
if ((id_1.id == id_2.id) && (id_1.enum_id == id_2.enum_id) &&
(id_1.type == id_2.type)) {
return true;
}
return false;
}
static inline bool dc_connector_supports_analog(const enum connector_id conn)
{
return conn == CONNECTOR_ID_VGA ||
conn == CONNECTOR_ID_SINGLE_LINK_DVII ||
conn == CONNECTOR_ID_DUAL_LINK_DVII;
}
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h
+108
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/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_HDCP_TYPES_H__
#define __DC_HDCP_TYPES_H__
enum hdcp_message_id {
HDCP_MESSAGE_ID_INVALID = -1,
/* HDCP 1.4 */
HDCP_MESSAGE_ID_READ_BKSV = 0,
/* HDMI is called Ri', DP is called R0' */
HDCP_MESSAGE_ID_READ_RI_R0,
HDCP_MESSAGE_ID_READ_PJ,
HDCP_MESSAGE_ID_WRITE_AKSV,
HDCP_MESSAGE_ID_WRITE_AINFO,
HDCP_MESSAGE_ID_WRITE_AN,
HDCP_MESSAGE_ID_READ_VH_X,
HDCP_MESSAGE_ID_READ_VH_0,
HDCP_MESSAGE_ID_READ_VH_1,
HDCP_MESSAGE_ID_READ_VH_2,
HDCP_MESSAGE_ID_READ_VH_3,
HDCP_MESSAGE_ID_READ_VH_4,
HDCP_MESSAGE_ID_READ_BCAPS,
HDCP_MESSAGE_ID_READ_BSTATUS,
HDCP_MESSAGE_ID_READ_KSV_FIFO,
HDCP_MESSAGE_ID_READ_BINFO,
/* HDCP 2.2 */
HDCP_MESSAGE_ID_HDCP2VERSION,
HDCP_MESSAGE_ID_RX_CAPS,
HDCP_MESSAGE_ID_WRITE_AKE_INIT,
HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
HDCP_MESSAGE_ID_WRITE_LC_INIT,
HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
HDCP_MESSAGE_ID_READ_RXSTATUS,
HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
/* PS175 chip */
HDCP_MESSAGE_ID_WRITE_PS175_CMD,
HDCP_MESSAGE_ID_READ_PS175_RSP,
HDCP_MESSAGE_ID_MAX
};
enum hdcp_version {
HDCP_Unknown = 0,
HDCP_VERSION_14,
HDCP_VERSION_22,
};
enum hdcp_link {
HDCP_LINK_PRIMARY,
HDCP_LINK_SECONDARY
};
enum hdcp_message_status {
HDCP_MESSAGE_SUCCESS,
HDCP_MESSAGE_FAILURE,
HDCP_MESSAGE_UNSUPPORTED
};
struct hdcp_protection_message {
enum hdcp_version version;
/* relevant only for DVI */
enum hdcp_link link;
enum hdcp_message_id msg_id;
uint32_t length;
uint8_t max_retries;
uint8_t *data;
enum hdcp_message_status status;
};
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/irq_service_interface.h
+51
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@@ -0,0 +1,51 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_IRQ_SERVICE_INTERFACE_H__
#define __DAL_IRQ_SERVICE_INTERFACE_H__
struct irq_service_init_data {
struct dc_context *ctx;
};
struct irq_service;
void dal_irq_service_destroy(struct irq_service **irq_service);
bool dal_irq_service_set(
struct irq_service *irq_service,
enum dc_irq_source source,
bool enable);
bool dal_irq_service_ack(
struct irq_service *irq_service,
enum dc_irq_source source);
enum dc_irq_source dal_irq_service_to_irq_source(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id);
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/link_service_types.h
+263
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LINK_SERVICE_TYPES_H__
#define __DAL_LINK_SERVICE_TYPES_H__
#include "grph_object_id.h"
#include "dal_types.h"
#include "irq_types.h"
/*struct mst_mgr_callback_object;*/
struct ddc;
struct irq_manager;
enum dp_power_state {
DP_POWER_STATE_D0 = 1,
DP_POWER_STATE_D3
};
enum edp_revision {
/* eDP version 1.1 or lower */
EDP_REVISION_11 = 0x00,
/* eDP version 1.2 */
EDP_REVISION_12 = 0x01,
/* eDP version 1.3 */
EDP_REVISION_13 = 0x02
};
enum {
LINK_RATE_REF_FREQ_IN_KHZ = 27000, /*27MHz*/
BITS_PER_DP_BYTE = 10,
DATA_EFFICIENCY_8b_10b_x10000 = 8000, /* 80% data efficiency */
DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100 = 97, /* 97% data efficiency when FEC is enabled */
DATA_EFFICIENCY_128b_132b_x10000 = 9641, /* 96.71% data efficiency x 99.7% downspread factor */
};
enum lttpr_mode {
LTTPR_MODE_UNKNOWN,
LTTPR_MODE_NON_LTTPR,
LTTPR_MODE_TRANSPARENT,
LTTPR_MODE_NON_TRANSPARENT,
};
struct link_training_settings {
struct dc_link_settings link_settings;
/* TODO: turn lane settings below into mandatory fields
* as initial lane configuration
*/
enum dc_voltage_swing *voltage_swing;
enum dc_pre_emphasis *pre_emphasis;
enum dc_post_cursor2 *post_cursor2;
bool should_set_fec_ready;
union dc_dp_ffe_preset *ffe_preset;
uint16_t cr_pattern_time;
uint16_t eq_pattern_time;
uint16_t cds_pattern_time;
enum dc_dp_training_pattern pattern_for_cr;
enum dc_dp_training_pattern pattern_for_eq;
enum dc_dp_training_pattern pattern_for_cds;
uint32_t eq_wait_time_limit;
uint8_t eq_loop_count_limit;
uint32_t cds_wait_time_limit;
bool enhanced_framing;
enum lttpr_mode lttpr_mode;
bool lttpr_early_tps2;
/* disallow different lanes to have different lane settings */
bool disallow_per_lane_settings;
/* dpcd lane settings will always use the same hw lane settings
* even if it doesn't match requested lane adjust */
bool always_match_dpcd_with_hw_lane_settings;
/*****************************************************************
* training states - parameters that can change in link training
*****************************************************************/
/* TODO: Move hw_lane_settings and dpcd_lane_settings
* along with lane adjust, lane align, offset and all
* other training states into a new structure called
* training states, so link_training_settings becomes
* a constant input pre-decided prior to link training.
*
* The goal is to strictly decouple link training settings
* decision making process from link training states to
* prevent it from messy code practice of changing training
* decision on the fly.
*/
struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX];
};
/*TODO: Move this enum test harness*/
/* Test patterns*/
enum dp_test_pattern {
/* Input data is pass through Scrambler
* and 8b10b Encoder straight to output*/
DP_TEST_PATTERN_VIDEO_MODE = 0,
/* phy test patterns*/
DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
DP_TEST_PATTERN_SYMBOL_ERROR,
DP_TEST_PATTERN_PRBS7,
DP_TEST_PATTERN_80BIT_CUSTOM,
DP_TEST_PATTERN_CP2520_1,
DP_TEST_PATTERN_CP2520_2,
DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
DP_TEST_PATTERN_CP2520_3,
DP_TEST_PATTERN_128b_132b_TPS1,
DP_TEST_PATTERN_128b_132b_TPS2,
DP_TEST_PATTERN_PRBS9,
DP_TEST_PATTERN_PRBS11,
DP_TEST_PATTERN_PRBS15,
DP_TEST_PATTERN_PRBS23,
DP_TEST_PATTERN_PRBS31,
DP_TEST_PATTERN_264BIT_CUSTOM,
DP_TEST_PATTERN_SQUARE_BEGIN,
DP_TEST_PATTERN_SQUARE = DP_TEST_PATTERN_SQUARE_BEGIN,
DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED,
DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED,
DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,
DP_TEST_PATTERN_SQUARE_END = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,
/* Link Training Patterns */
DP_TEST_PATTERN_TRAINING_PATTERN1,
DP_TEST_PATTERN_TRAINING_PATTERN2,
DP_TEST_PATTERN_TRAINING_PATTERN3,
DP_TEST_PATTERN_TRAINING_PATTERN4,
DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE,
DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE,
DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE,
/* link test patterns*/
DP_TEST_PATTERN_COLOR_SQUARES,
DP_TEST_PATTERN_COLOR_SQUARES_CEA,
DP_TEST_PATTERN_VERTICAL_BARS,
DP_TEST_PATTERN_HORIZONTAL_BARS,
DP_TEST_PATTERN_COLOR_RAMP,
/* audio test patterns*/
DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
DP_TEST_PATTERN_AUDIO_SAWTOOTH,
DP_TEST_PATTERN_UNSUPPORTED
};
#define IS_DP_PHY_SQUARE_PATTERN(test_pattern)\
(DP_TEST_PATTERN_SQUARE_BEGIN <= test_pattern &&\
test_pattern <= DP_TEST_PATTERN_SQUARE_END)
#define IS_DP_PHY_PATTERN(test_pattern)\
((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&\
test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||\
test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
enum dp_test_pattern_color_space {
DP_TEST_PATTERN_COLOR_SPACE_RGB,
DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
};
enum dp_panel_mode {
/* not required */
DP_PANEL_MODE_DEFAULT,
/* standard mode for eDP */
DP_PANEL_MODE_EDP,
/* external chips specific settings */
DP_PANEL_MODE_SPECIAL
};
enum dpcd_source_sequence {
DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG = 1, /*done in apply_single_controller_ctx_to_hw */
DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR, /*done in core_link_enable_stream */
DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME, /*done in core_link_enable_stream/dcn20_enable_stream */
DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE, /*done in perform_link_training_with_retries/dcn20_enable_stream */
DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY, /*done in dp_enable_link_phy */
DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN, /*done in dp_set_hw_test_pattern */
DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM, /*done in dce110_enable_audio_stream */
DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_unblank */
DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_blank */
DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET, /*done in enc1_stream_encoder_dp_blank */
DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM, /*done in dce110_disable_audio_stream */
DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY, /*done in dp_disable_link_phy */
DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE, /*done in dce110_disable_stream */
};
/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
union dpcd_training_lane_set {
struct {
#if defined(LITTLEENDIAN_CPU)
uint8_t VOLTAGE_SWING_SET:2;
uint8_t MAX_SWING_REACHED:1;
uint8_t PRE_EMPHASIS_SET:2;
uint8_t MAX_PRE_EMPHASIS_REACHED:1;
/* following is reserved in DP 1.1 */
uint8_t POST_CURSOR2_SET:2;
#elif defined(BIGENDIAN_CPU)
uint8_t POST_CURSOR2_SET:2;
uint8_t MAX_PRE_EMPHASIS_REACHED:1;
uint8_t PRE_EMPHASIS_SET:2;
uint8_t MAX_SWING_REACHED:1;
uint8_t VOLTAGE_SWING_SET:2;
#else
#error ARCH not defined!
#endif
} bits;
uint8_t raw;
};
/* AMD's copy of various payload data for MST. We have two copies of the payload table (one in DRM,
* one in DC) since DRM's MST helpers can't be accessed here. This stream allocation table should
* _ONLY_ be filled out from DM and then passed to DC, do NOT use these for _any_ kind of atomic
* state calculations in DM, or you will break something.
*/
struct drm_dp_mst_port;
/* DP MST stream allocation (payload bandwidth number) */
struct dc_dp_mst_stream_allocation {
uint8_t vcp_id;
/* number of slots required for the DP stream in
* transport packet */
uint8_t slot_count;
};
/* DP MST stream allocation table */
struct dc_dp_mst_stream_allocation_table {
/* number of DP video streams */
int stream_count;
/* array of stream allocations */
struct dc_dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
};
#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
linux-7.2.3/drivers/gpu/drm/amd/display/include/logger_interface.h
+147
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LOGGER_INTERFACE_H__
#define __DAL_LOGGER_INTERFACE_H__
#include "logger_types.h"
struct dc_context;
struct dc_link;
struct dc_surface_update;
struct resource_context;
struct dc_state;
/*
*
* DAL logger functionality
*
*/
void update_surface_trace(
struct dc *dc,
const struct dc_surface_update *updates,
int surface_count);
void post_surface_trace(struct dc *dc);
void context_clock_trace(
struct dc *dc,
struct dc_state *context);
/* Any function which is empty or have incomplete implementation should be
* marked by this macro.
* Note that the message will be printed exactly once for every function
* it is used in order to avoid repeating of the same message. */
#define DAL_LOGGER_NOT_IMPL(fmt, ...) \
do { \
static bool print_not_impl = true; \
if (print_not_impl == true) { \
print_not_impl = false; \
DRM_WARN("DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
} \
} while (0)
/******************************************************************************
* Convenience macros to save on typing.
*****************************************************************************/
#define DC_ERROR(...) \
do { \
(void)(dc_ctx); \
DC_LOG_ERROR(__VA_ARGS__); \
} while (0)
#define DC_SYNC_INFO(...) \
do { \
(void)(dc_ctx); \
DC_LOG_SYNC(__VA_ARGS__); \
} while (0)
/* Connectivity log format:
* [time stamp] [drm] [Major_minor] [connector name] message.....
* eg:
* [ 26.590965] [drm] [Conn_LKTN] [DP-1] HBRx4 pass VS=0, PE=0^
* [ 26.881060] [drm] [Conn_Mode] [DP-1] {2560x1080, 2784x1111@185580Khz}^
*/
#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \
do { \
(void)(link); \
DC_LOG_EVENT_DETECTION(__VA_ARGS__); \
} while (0)
#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \
do { \
(void)(link); \
DC_LOG_EVENT_LINK_LOSS(__VA_ARGS__); \
} while (0)
#define CONN_MSG_LT(link, ...) \
do { \
(void)(link); \
DC_LOG_EVENT_LINK_TRAINING(__VA_ARGS__); \
} while (0)
#define CONN_MSG_MODE(link, ...) \
do { \
(void)(link); \
DC_LOG_EVENT_MODE_SET(__VA_ARGS__); \
} while (0)
/*
* Display Test Next logging
*/
#define DTN_INFO_BEGIN() \
dm_dtn_log_begin(dc_ctx, log_ctx)
#define DTN_INFO(msg, ...) \
dm_dtn_log_append_v(dc_ctx, log_ctx, msg, ##__VA_ARGS__)
#define DTN_INFO_END() \
dm_dtn_log_end(dc_ctx, log_ctx)
#define PERFORMANCE_TRACE_START() \
unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)
#define PERFORMANCE_TRACE_END() \
do { \
unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \
if (dc->debug.performance_trace) { \
DC_LOG_PERF_TRACE("%s duration: %lld ticks\n", __func__, \
perf_trc_end_stmp - perf_trc_start_stmp); \
} \
} while (0)
#define DISPLAY_STATS_BEGIN(entry) (void)(entry)
#define DISPLAY_STATS(msg, ...) DC_LOG_PERF_TRACE(msg, __VA_ARGS__)
#define DISPLAY_STATS_END(entry) (void)(entry)
#define LOG_GAMMA_WRITE(msg, ...)
#endif /* __DAL_LOGGER_INTERFACE_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/logger_types.h
+85
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@@ -0,0 +1,85 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LOGGER_TYPES_H__
#define __DAL_LOGGER_TYPES_H__
#include "os_types.h"
#define DC_LOG_ERROR(...) drm_err((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_WARNING(...) drm_warn((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DEBUG(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DC(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_INFO(...) drm_info((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_SURFACE(...) pr_debug("[SURFACE]:"__VA_ARGS__)
#define DC_LOG_HW_HOTPLUG(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__)
#define DC_LOG_HW_RESUME_S3(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_HW_AUDIO(...) pr_debug("[HW_AUDIO]:"__VA_ARGS__)
#define DC_LOG_HW_HPD_IRQ(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_MST(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_SCALER(...) pr_debug("[SCALER]:"__VA_ARGS__)
#define DC_LOG_BIOS(...) pr_debug("[BIOS]:"__VA_ARGS__)
#define DC_LOG_BANDWIDTH_CALCS(...) pr_debug("[BANDWIDTH_CALCS]:"__VA_ARGS__)
#define DC_LOG_BANDWIDTH_VALIDATION(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_SYNC(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_BACKLIGHT(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DETECTION_EDID_PARSER(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DETECTION_DP_CAPS(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DML(...) pr_debug("[DML]:"__VA_ARGS__)
#define DC_LOG_EVENT_MODE_SET(...) drm_dbg_kms((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_EVENT_DETECTION(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_EVENT_LINK_TRAINING(...) \
drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_EVENT_LINK_LOSS(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__)
#define DC_LOG_PERF_TRACE(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_RETIMER_REDRIVER(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
#define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
#define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__)
#define DC_LOG_DSC(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_SMU(...) pr_debug("[SMU_MSG]:"__VA_ARGS__)
#define DC_LOG_HDMI_FRL(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_HDMI_FRL_LTP(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DWB(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_DP2(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
#define DC_LOG_AUTO_DPM_TEST(...) pr_debug("[AutoDPMTest]: "__VA_ARGS__)
#define DC_LOG_IPS(...) pr_debug("[IPS]: "__VA_ARGS__)
#define DC_LOG_MALL(...) pr_debug("[MALL]:"__VA_ARGS__)
#define DC_LOG_REGISTER_READ(...) pr_debug("[REGISTER_READ]: "__VA_ARGS__)
#define DC_LOG_REGISTER_WRITE(...) pr_debug("[REGISTER_WRITE]: "__VA_ARGS__)
struct dc_log_buffer_ctx {
char *buf;
size_t pos;
size_t size;
};
struct dal_logger {
struct drm_device *dev;
};
#endif /* __DAL_LOGGER_TYPES_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/set_mode_types.h
+102
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@@ -0,0 +1,102 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_SET_MODE_TYPES_H__
#define __DAL_SET_MODE_TYPES_H__
#include "dc_types.h"
#include <linux/hdmi.h>
/* Info frame packet status */
enum info_frame_flag {
INFO_PACKET_PACKET_INVALID = 0,
INFO_PACKET_PACKET_VALID = 1,
INFO_PACKET_PACKET_RESET = 2,
INFO_PACKET_PACKET_UPDATE_SCAN_TYPE = 8
};
struct hdmi_info_frame_header {
uint8_t info_frame_type;
uint8_t version;
uint8_t length;
};
#pragma pack(push)
#pragma pack(1)
struct info_packet_raw_data {
uint8_t hb0;
uint8_t hb1;
uint8_t hb2;
uint8_t sb[28]; /* sb0~sb27 */
};
union hdmi_info_packet {
struct avi_info_frame {
struct hdmi_info_frame_header header;
uint8_t CHECK_SUM:8;
uint8_t S0_S1:2;
uint8_t B0_B1:2;
uint8_t A0:1;
uint8_t Y0_Y1_Y2:3;
uint8_t R0_R3:4;
uint8_t M0_M1:2;
uint8_t C0_C1:2;
uint8_t SC0_SC1:2;
uint8_t Q0_Q1:2;
uint8_t EC0_EC2:3;
uint8_t ITC:1;
uint8_t VIC0_VIC7:8;
uint8_t PR0_PR3:4;
uint8_t CN0_CN1:2;
uint8_t YQ0_YQ1:2;
uint16_t bar_top;
uint16_t bar_bottom;
uint16_t bar_left;
uint16_t bar_right;
uint8_t FR0_FR3:4;
uint8_t ACE0_ACE3:4;
uint8_t RID0_RID5:6;
uint8_t FR4:1;
uint8_t F157:1;
uint8_t reserved[12];
} bits;
struct info_packet_raw_data packet_raw_data;
};
#pragma pack(pop)
#endif /* __DAL_SET_MODE_TYPES_H__ */
linux-7.2.3/drivers/gpu/drm/amd/display/include/signal_types.h
+178
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@@ -0,0 +1,178 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_SIGNAL_TYPES_H__
#define __DC_SIGNAL_TYPES_H__
/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
#define TMDS_MIN_PIXEL_CLOCK 25000
/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
#define TMDS_MAX_PIXEL_CLOCK 165000
/* Maximum pixel clock, in KHz. For HDMI2 TMDS signal is 600 MHz */
#define HDMI2_TMDS_MAX_PIXEL_CLOCK 600000
enum signal_type {
SIGNAL_TYPE_NONE = 0L, /* no signal */
SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),
SIGNAL_TYPE_DVI_DUAL_LINK = (1 << 1),
SIGNAL_TYPE_HDMI_TYPE_A = (1 << 2),
SIGNAL_TYPE_LVDS = (1 << 3),
SIGNAL_TYPE_RGB = (1 << 4),
SIGNAL_TYPE_DISPLAY_PORT = (1 << 5),
SIGNAL_TYPE_DISPLAY_PORT_MST = (1 << 6),
SIGNAL_TYPE_EDP = (1 << 7),
SIGNAL_TYPE_HDMI_FRL = (1 << 8),
SIGNAL_TYPE_VIRTUAL = (1 << 9), /* Virtual Display */
};
static inline const char *signal_type_to_string(const int type)
{
switch (type) {
case SIGNAL_TYPE_NONE:
return "No signal";
case SIGNAL_TYPE_DVI_SINGLE_LINK:
return "DVI: Single Link";
case SIGNAL_TYPE_DVI_DUAL_LINK:
return "DVI: Dual Link";
case SIGNAL_TYPE_HDMI_TYPE_A:
return "HDMI: TYPE A";
case SIGNAL_TYPE_LVDS:
return "LVDS";
case SIGNAL_TYPE_RGB:
return "RGB";
case SIGNAL_TYPE_DISPLAY_PORT:
return "Display Port";
case SIGNAL_TYPE_DISPLAY_PORT_MST:
return "Display Port: MST";
case SIGNAL_TYPE_EDP:
return "Embedded Display Port";
case SIGNAL_TYPE_HDMI_FRL:
return "HDMI: FRL";
case SIGNAL_TYPE_VIRTUAL:
return "Virtual";
default:
return "Unknown";
}
}
/* help functions for signal types manipulation */
static inline bool dc_is_hdmi_tmds_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
}
static inline bool dc_is_hdmi_frl_signal(enum signal_type signal)
{
return ((signal == SIGNAL_TYPE_HDMI_FRL));
}
static inline bool dc_is_hdmi_signal(enum signal_type signal)
{
return (dc_is_hdmi_tmds_signal(signal) || dc_is_hdmi_frl_signal(signal));
}
static inline bool dc_is_dp_sst_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_EDP);
}
static inline bool dc_is_dp_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_EDP ||
signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
}
static inline bool dc_is_embedded_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
}
static inline bool dc_is_lvds_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_LVDS);
}
static inline bool dc_is_dvi_signal(enum signal_type signal)
{
switch (signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
return true;
break;
default:
return false;
}
}
/**
* dc_is_rgb_signal() - Whether the signal is analog RGB.
*
* Returns whether the given signal type is an analog RGB signal
* that is used with a DAC on VGA or DVI-I connectors.
* Not to be confused with other uses of "RGB", such as RGB color space.
*/
static inline bool dc_is_rgb_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_RGB);
}
static inline bool dc_is_tmds_signal(enum signal_type signal)
{
switch (signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
return true;
break;
default:
return false;
}
}
static inline bool dc_is_dvi_single_link_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
}
static inline bool dc_is_dual_link_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DVI_DUAL_LINK);
}
static inline bool dc_is_audio_capable_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
dc_is_hdmi_signal(signal));
}
static inline bool dc_is_virtual_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_VIRTUAL);
}
#endif
linux-7.2.3/drivers/gpu/drm/amd/display/include/vector.h
+150
View File
@@ -0,0 +1,150 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_VECTOR_H__
#define __DAL_VECTOR_H__
struct vector {
uint8_t *container;
uint32_t struct_size;
uint32_t count;
uint32_t capacity;
struct dc_context *ctx;
};
bool dal_vector_construct(
struct vector *vector,
struct dc_context *ctx,
uint32_t capacity,
uint32_t struct_size);
struct vector *dal_vector_create(
struct dc_context *ctx,
uint32_t capacity,
uint32_t struct_size);
/* 'initial_value' is optional. If initial_value not supplied,
* each "structure" in the vector will contain zeros by default. */
struct vector *dal_vector_presized_create(
struct dc_context *ctx,
uint32_t size,
void *initial_value,
uint32_t struct_size);
void dal_vector_destruct(
struct vector *vector);
void dal_vector_destroy(
struct vector **vector);
uint32_t dal_vector_get_count(
const struct vector *vector);
/* dal_vector_insert_at
* reallocate container if necessary
* then shell items at right and insert
* return if the container modified
* do not check that index belongs to container
* since the function is private and index is going to be calculated
* either with by function or as get_count+1 */
bool dal_vector_insert_at(
struct vector *vector,
const void *what,
uint32_t position);
bool dal_vector_append(
struct vector *vector,
const void *item);
/* operator[] */
void *dal_vector_at_index(
const struct vector *vector,
uint32_t index);
void dal_vector_set_at_index(
const struct vector *vector,
const void *what,
uint32_t index);
/* create a clone (copy) of a vector */
struct vector *dal_vector_clone(
const struct vector *vector_other);
/* dal_vector_remove_at_index
* Shifts elements on the right from remove position to the left,
* removing an element at position by overwrite means*/
bool dal_vector_remove_at_index(
struct vector *vector,
uint32_t index);
uint32_t dal_vector_capacity(const struct vector *vector);
bool dal_vector_reserve(struct vector *vector, uint32_t capacity);
void dal_vector_clear(struct vector *vector);
/***************************************************************************
* Macro definitions of TYPE-SAFE versions of vector set/get functions.
***************************************************************************/
#define DAL_VECTOR_INSERT_AT(vector_type, type_t) \
static bool vector_type##_vector_insert_at( \
struct vector *vector, \
type_t what, \
uint32_t position) \
{ \
return dal_vector_insert_at(vector, what, position); \
}
#define DAL_VECTOR_APPEND(vector_type, type_t) \
static bool vector_type##_vector_append( \
struct vector *vector, \
type_t item) \
{ \
return dal_vector_append(vector, item); \
}
/* Note: "type_t" is the ONLY token accepted by "checkpatch.pl" and by
* "checkcommit" as *return type*.
* For uniformity reasons "type_t" is used for all type-safe macro
* definitions here. */
#define DAL_VECTOR_AT_INDEX(vector_type, type_t) \
static type_t vector_type##_vector_at_index( \
const struct vector *vector, \
uint32_t index) \
{ \
return dal_vector_at_index(vector, index); \
}
#define DAL_VECTOR_SET_AT_INDEX(vector_type, type_t) \
static void vector_type##_vector_set_at_index( \
const struct vector *vector, \
type_t what, \
uint32_t index) \
{ \
dal_vector_set_at_index(vector, what, index); \
}
#endif /* __DAL_VECTOR_H__ */