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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/amd_acpi.h
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/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef AMD_ACPI_H
#define AMD_ACPI_H
#include <linux/types.h>
struct atif_verify_interface {
u16 size; /* structure size in bytes (includes size field) */
u16 version; /* version */
u32 notification_mask; /* supported notifications mask */
u32 function_bits; /* supported functions bit vector */
} __packed;
struct atif_system_params {
u16 size; /* structure size in bytes (includes size field) */
u32 valid_mask; /* valid flags mask */
u32 flags; /* flags */
u8 command_code; /* notify command code */
} __packed;
struct atif_sbios_requests {
u16 size; /* structure size in bytes (includes size field) */
u32 pending; /* pending sbios requests */
u8 panel_exp_mode; /* panel expansion mode */
u8 thermal_gfx; /* thermal state: target gfx controller */
u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */
u8 forced_power_gfx; /* forced power state: target gfx controller */
u8 forced_power_state; /* forced power state: state id */
u8 system_power_src; /* system power source */
u8 backlight_level; /* panel backlight level (0-255) */
} __packed;
struct atif_qbtc_arguments {
u16 size; /* structure size in bytes (includes size field) */
u8 requested_display; /* which display is requested */
} __packed;
#define ATIF_QBTC_MAX_DATA_POINTS 99
struct atif_qbtc_data_point {
u8 luminance; /* luminance in percent */
u8 input_signal; /* input signal in range 0-255 */
} __packed;
struct atif_qbtc_output {
u16 size; /* structure size in bytes (includes size field) */
u16 flags; /* all zeroes */
u8 error_code; /* error code */
u8 ac_level; /* default brightness on AC power */
u8 dc_level; /* default brightness on DC power */
u8 min_input_signal; /* max input signal in range 0-255 */
u8 max_input_signal; /* min input signal in range 0-255 */
u8 number_of_points; /* number of data points */
struct atif_qbtc_data_point data_points[ATIF_QBTC_MAX_DATA_POINTS];
} __packed;
static_assert(ATIF_QBTC_MAX_DATA_POINTS == MAX_LUMINANCE_DATA_POINTS);
static_assert(sizeof(struct atif_qbtc_data_point) == sizeof(struct amdgpu_dm_luminance_data));
#define ATIF_NOTIFY_MASK 0x3
#define ATIF_NOTIFY_NONE 0
#define ATIF_NOTIFY_81 1
#define ATIF_NOTIFY_N 2
struct atcs_verify_interface {
u16 size; /* structure size in bytes (includes size field) */
u16 version; /* version */
u32 function_bits; /* supported functions bit vector */
} __packed;
#define ATCS_VALID_FLAGS_MASK 0x3
struct atcs_pref_req_input {
u16 size; /* structure size in bytes (includes size field) */
u16 client_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
u16 valid_flags_mask; /* valid flags mask */
u16 flags; /* flags */
u8 req_type; /* request type */
u8 perf_req; /* performance request */
} __packed;
struct atcs_pref_req_output {
u16 size; /* structure size in bytes (includes size field) */
u8 ret_val; /* return value */
} __packed;
struct atcs_pwr_shift_input {
u16 size; /* structure size in bytes (includes size field) */
u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */
u8 drv_state; /* 0 = operational, 1 = not operational */
} __packed;
struct atcs_get_uma_size_output {
u16 size; /* structure size in bytes (includes size field) */
u32 uma_size_mb; /* allocated UMA size in MB */
} __packed;
struct atcs_set_uma_allocation_size_input {
u16 size; /* structure size in bytes (includes size field) */
u8 uma_size_index; /* UMA size index */
u8 uma_size_type; /* UMA size type */
} __packed;
/* AMD hw uses four ACPI control methods:
* 1. ATIF
* ARG0: (ACPI_INTEGER) function code
* ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
* OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
* ATIF provides an entry point for the gfx driver to interact with the sbios.
* The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom
* notification. Which notification is used as indicated by the ATIF Control
* Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or
* a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS
* to identify pending System BIOS requests and associated parameters. For
* example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver
* will perform display device detection and invoke ATIF Control Method
* SELECT_ACTIVE_DISPLAYS.
*
* 2. ATPX
* ARG0: (ACPI_INTEGER) function code
* ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
* OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
* ATPX methods are used on PowerXpress systems to handle mux switching and
* discrete GPU power control.
*
* 3. ATRM
* ARG0: (ACPI_INTEGER) offset of vbios rom data
* ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K).
* OUTPUT: (ACPI_BUFFER) output buffer
* ATRM provides an interfacess to access the discrete GPU vbios image on
* PowerXpress systems with multiple GPUs.
*
* 4. ATCS
* ARG0: (ACPI_INTEGER) function code
* ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
* OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
* ATCS provides an interface to AMD chipset specific functionality.
*
*/
/* ATIF */
#define ATIF_FUNCTION_VERIFY_INTERFACE 0x0
/* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* WORD - version
* DWORD - supported notifications mask
* DWORD - supported functions bit vector
*/
/* Notifications mask */
# define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED (1 << 2)
# define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED (1 << 3)
# define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED (1 << 4)
# define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED (1 << 7)
# define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED (1 << 8)
# define ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED (1 << 12)
/* supported functions vector */
# define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED (1 << 0)
# define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED (1 << 1)
# define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED (1 << 12)
# define ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED (1 << 15)
# define ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED (1 << 16)
# define ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED (1 << 20)
#define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS 0x1
/* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* DWORD - valid flags mask
* DWORD - flags
*
* OR
*
* WORD - structure size in bytes (includes size field)
* DWORD - valid flags mask
* DWORD - flags
* BYTE - notify command code
*
* flags
* bits 1:0:
* 0 - Notify(VGA, 0x81) is not used for notification
* 1 - Notify(VGA, 0x81) is used for notification
* 2 - Notify(VGA, n) is used for notification where
* n (0xd0-0xd9) is specified in notify command code.
* bit 2:
* 1 - lid changes not reported though int10
* bit 3:
* 1 - system bios controls overclocking
* bit 4:
* 1 - enable overclocking
*/
#define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS 0x2
/* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* DWORD - pending sbios requests
* BYTE - reserved (all zeroes)
* BYTE - thermal state: target gfx controller
* BYTE - thermal state: state id (0: exit state, non-0: state)
* BYTE - forced power state: target gfx controller
* BYTE - forced power state: state id (0: forced state, non-0: state)
* BYTE - system power source
* BYTE - panel backlight level (0-255)
* BYTE - GPU package power limit: target gfx controller
* DWORD - GPU package power limit: value (24:8 fractional format, Watts)
*/
/* pending sbios requests */
# define ATIF_THERMAL_STATE_CHANGE_REQUEST (1 << 2)
# define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST (1 << 3)
# define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST (1 << 4)
# define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST (1 << 7)
# define ATIF_DGPU_DISPLAY_EVENT (1 << 8)
# define ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST (1 << 12)
/* target gfx controller */
# define ATIF_TARGET_GFX_SINGLE 0
# define ATIF_TARGET_GFX_PX_IGPU 1
# define ATIF_TARGET_GFX_PX_DGPU 2
/* system power source */
# define ATIF_POWER_SOURCE_AC 1
# define ATIF_POWER_SOURCE_DC 2
# define ATIF_POWER_SOURCE_RESTRICTED_AC_1 3
# define ATIF_POWER_SOURCE_RESTRICTED_AC_2 4
#define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION 0xD
/* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - gfx controller id
* BYTE - current temperature (degress Celsius)
* OUTPUT: none
*/
#define ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS 0x10
/* ARG0: ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
* ARG1:
* WORD - structure size in bytes (includes size field)
* BYTE - requested display
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* WORD - flags (currently all 16 bits are reserved)
* BYTE - error code (on failure, disregard all below fields)
* BYTE - AC level (default brightness in percent when machine has full power)
* BYTE - DC level (default brightness in percent when machine is on battery)
* BYTE - min input signal, in range 0-255, corresponding to 0% backlight
* BYTE - max input signal, in range 0-255, corresponding to 100% backlight
* BYTE - number of reported data points
* BYTE - luminance level in percent \ repeated structure
* BYTE - input signal in range 0-255 / does not have entries for 0% and 100%
*/
/* requested display */
# define ATIF_QBTC_REQUEST_LCD1 0
# define ATIF_QBTC_REQUEST_CRT1 1
# define ATIF_QBTC_REQUEST_DFP1 3
# define ATIF_QBTC_REQUEST_CRT2 4
# define ATIF_QBTC_REQUEST_LCD2 5
# define ATIF_QBTC_REQUEST_DFP2 7
# define ATIF_QBTC_REQUEST_DFP3 9
# define ATIF_QBTC_REQUEST_DFP4 10
# define ATIF_QBTC_REQUEST_DFP5 11
# define ATIF_QBTC_REQUEST_DFP6 12
/* error code */
# define ATIF_QBTC_ERROR_CODE_SUCCESS 0
# define ATIF_QBTC_ERROR_CODE_FAILURE 1
# define ATIF_QBTC_ERROR_CODE_DEVICE_NOT_SUPPORTED 2
#define ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION 0x11
/* ARG0: ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION
* ARG1: none
* OUTPUT: none
*/
#define ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION 0x15
/* ARG0: ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION
* ARG1: none
* OUTPUT:
* WORD - number of reported external gfx devices
* WORD - device structure size in bytes (excludes device size field)
* WORD - flags \
* WORD - bus number / repeated structure
*/
/* flags */
# define ATIF_EXTERNAL_GRAPHICS_PORT (1 << 0)
/* ATPX */
#define ATPX_FUNCTION_VERIFY_INTERFACE 0x0
/* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* WORD - version
* DWORD - supported functions bit vector
*/
/* supported functions vector */
# define ATPX_GET_PX_PARAMETERS_SUPPORTED (1 << 0)
# define ATPX_POWER_CONTROL_SUPPORTED (1 << 1)
# define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED (1 << 2)
# define ATPX_I2C_MUX_CONTROL_SUPPORTED (1 << 3)
# define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4)
# define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED (1 << 5)
# define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED (1 << 7)
# define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED (1 << 8)
#define ATPX_FUNCTION_GET_PX_PARAMETERS 0x1
/* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* DWORD - valid flags mask
* DWORD - flags
*/
/* flags */
# define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 0)
# define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 1)
# define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 2)
# define ATPX_CRT1_RGB_SIGNAL_MUXED (1 << 3)
# define ATPX_TV_SIGNAL_MUXED (1 << 4)
# define ATPX_DFP_SIGNAL_MUXED (1 << 5)
# define ATPX_SEPARATE_MUX_FOR_I2C (1 << 6)
# define ATPX_DYNAMIC_PX_SUPPORTED (1 << 7)
# define ATPX_ACF_NOT_SUPPORTED (1 << 8)
# define ATPX_FIXED_NOT_SUPPORTED (1 << 9)
# define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10)
# define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11)
# define ATPX_DGPU_CAN_DRIVE_DISPLAYS (1 << 12)
# define ATPX_MS_HYBRID_GFX_SUPPORTED (1 << 14)
#define ATPX_FUNCTION_POWER_CONTROL 0x2
/* ARG0: ATPX_FUNCTION_POWER_CONTROL
* ARG1:
* WORD - structure size in bytes (includes size field)
* BYTE - dGPU power state (0: power off, 1: power on)
* OUTPUT: none
*/
#define ATPX_FUNCTION_DISPLAY_MUX_CONTROL 0x3
/* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - display mux control (0: iGPU, 1: dGPU)
* OUTPUT: none
*/
# define ATPX_INTEGRATED_GPU 0
# define ATPX_DISCRETE_GPU 1
#define ATPX_FUNCTION_I2C_MUX_CONTROL 0x4
/* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - i2c/aux/hpd mux control (0: iGPU, 1: dGPU)
* OUTPUT: none
*/
#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION 0x5
/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - target gpu (0: iGPU, 1: dGPU)
* OUTPUT: none
*/
#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION 0x6
/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - target gpu (0: iGPU, 1: dGPU)
* OUTPUT: none
*/
#define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING 0x8
/* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING
* ARG1: none
* OUTPUT:
* WORD - number of display connectors
* WORD - connector structure size in bytes (excludes connector size field)
* BYTE - flags \
* BYTE - ATIF display vector bit position } repeated
* BYTE - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure
* WORD - connector ACPI id /
*/
/* flags */
# define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 0)
# define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 1)
# define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 2)
#define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS 0x9
/* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS
* ARG1: none
* OUTPUT:
* WORD - number of HPD/DDC ports
* WORD - port structure size in bytes (excludes port size field)
* BYTE - ATIF display vector bit position \
* BYTE - hpd id } reapeated structure
* BYTE - ddc id /
*
* available on A+A systems only
*/
/* hpd id */
# define ATPX_HPD_NONE 0
# define ATPX_HPD1 1
# define ATPX_HPD2 2
# define ATPX_HPD3 3
# define ATPX_HPD4 4
# define ATPX_HPD5 5
# define ATPX_HPD6 6
/* ddc id */
# define ATPX_DDC_NONE 0
# define ATPX_DDC1 1
# define ATPX_DDC2 2
# define ATPX_DDC3 3
# define ATPX_DDC4 4
# define ATPX_DDC5 5
# define ATPX_DDC6 6
# define ATPX_DDC7 7
# define ATPX_DDC8 8
/* ATCS */
#define ATCS_FUNCTION_VERIFY_INTERFACE 0x0
/* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* WORD - version
* DWORD - supported functions bit vector
*/
/* supported functions vector */
# define ATCS_GET_EXTERNAL_STATE_SUPPORTED (1 << 0)
# define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1)
# define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2)
# define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3)
# define ACPI_ATCS_GET_UMA_SIZE_SUPPORTED (1 << 5)
# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7)
# define ACPI_ATCS_SET_UMA_ALLOCATION_SIZE_SUPPORTED (1 << 9)
#define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1
/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* DWORD - valid flags mask
* DWORD - flags (0: undocked, 1: docked)
*/
/* flags */
# define ATCS_DOCKED (1 << 0)
#define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST 0x2
/* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
* WORD - valid flags mask
* WORD - flags
* BYTE - request type
* BYTE - performance request
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* BYTE - return value
*/
/* flags */
# define ATCS_ADVERTISE_CAPS (1 << 0)
# define ATCS_WAIT_FOR_COMPLETION (1 << 1)
/* request type */
# define ATCS_PCIE_LINK_SPEED 1
/* performance request */
# define ATCS_REMOVE 0
# define ATCS_FORCE_LOW_POWER 1
# define ATCS_PERF_LEVEL_1 2 /* PCIE Gen 1 */
# define ATCS_PERF_LEVEL_2 3 /* PCIE Gen 2 */
# define ATCS_PERF_LEVEL_3 4 /* PCIE Gen 3 */
/* return value */
# define ATCS_REQUEST_REFUSED 1
# define ATCS_REQUEST_COMPLETE 2
# define ATCS_REQUEST_IN_PROGRESS 3
#define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION 0x3
/* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION
* ARG1: none
* OUTPUT: none
*/
#define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH 0x4
/* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
* BYTE - number of active lanes
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* BYTE - number of active lanes
*/
#define ATCS_FUNCTION_POWER_SHIFT_CONTROL 0x8
/* ARG0: ATCS_FUNCTION_POWER_SHIFT_CONTROL
* ARG1:
* WORD - structure size in bytes (includes size field)
* WORD - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
* BYTE - Device ACPI state
* BYTE - Driver state
* OUTPUT: none
*/
#define ATCS_FUNCTION_GET_UMA_SIZE 0x6
/* ARG0: ATCS_FUNCTION_GET_UMA_SIZE
* ARG1: none
* OUTPUT:
* WORD - structure size in bytes (includes size field)
* DWORD - allocated UMA size in MB
*/
#define ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE 0xA
/* ARG0: ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE
* ARG1:
* WORD - structure size in bytes (includes size field)
* BYTE - UMA size index
* BYTE - UMA size type
* OUTPUT: none
*/
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/amd_cper.h
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/* SPDX-License-Identifier: MIT */
/*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMD_CPER_H__
#define __AMD_CPER_H__
#include <linux/uuid.h>
#define CPER_HDR_REV_1 (0x100)
#define CPER_SEC_MINOR_REV_1 (0x01)
#define CPER_SEC_MAJOR_REV_22 (0x22)
#define CPER_MAX_OAM_COUNT (8)
#define CPER_CTX_TYPE_CRASH (1)
#define CPER_CTX_TYPE_BOOT (9)
#define CPER_CREATOR_ID_AMDGPU "amdgpu"
#define CPER_NOTIFY_MCE \
GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
0xE1, 0x49, 0x13, 0xBB)
#define CPER_NOTIFY_CMC \
GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
0xEB, 0xD4, 0xF8, 0x90)
#define BOOT_TYPE \
GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
0xD4, 0x64, 0xB3, 0x8F)
#define AMD_CRASHDUMP \
GUID_INIT(0x32AC0C78, 0x2623, 0x48F6, 0xB0, 0xD0, 0x73, 0x65, \
0x72, 0x5F, 0xD6, 0xAE)
#define AMD_GPU_NONSTANDARD_ERROR \
GUID_INIT(0x32AC0C78, 0x2623, 0x48F6, 0x81, 0xA2, 0xAC, 0x69, \
0x17, 0x80, 0x55, 0x1D)
#define PROC_ERR_SECTION_TYPE \
GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
0x24, 0x2B, 0x6E, 0x1D)
enum cper_error_severity {
CPER_SEV_NON_FATAL_UNCORRECTED = 0,
CPER_SEV_FATAL_UNCORRECTED = 1,
CPER_SEV_NON_FATAL_CORRECTED = 2,
CPER_SEV_NUM = 3,
CPER_SEV_UNUSED = 10,
};
enum cper_aca_reg {
CPER_ACA_REG_CTL_LO = 0,
CPER_ACA_REG_CTL_HI = 1,
CPER_ACA_REG_STATUS_LO = 2,
CPER_ACA_REG_STATUS_HI = 3,
CPER_ACA_REG_ADDR_LO = 4,
CPER_ACA_REG_ADDR_HI = 5,
CPER_ACA_REG_MISC0_LO = 6,
CPER_ACA_REG_MISC0_HI = 7,
CPER_ACA_REG_CONFIG_LO = 8,
CPER_ACA_REG_CONFIG_HI = 9,
CPER_ACA_REG_IPID_LO = 10,
CPER_ACA_REG_IPID_HI = 11,
CPER_ACA_REG_SYND_LO = 12,
CPER_ACA_REG_SYND_HI = 13,
CPER_ACA_REG_COUNT = 32,
};
#pragma pack(push, 1)
struct cper_timestamp {
uint8_t seconds;
uint8_t minutes;
uint8_t hours;
uint8_t flag;
uint8_t day;
uint8_t month;
uint8_t year;
uint8_t century;
};
struct cper_hdr {
char signature[4]; /* "CPER" */
uint16_t revision;
uint32_t signature_end; /* 0xFFFFFFFF */
uint16_t sec_cnt;
enum cper_error_severity error_severity;
union {
struct {
uint32_t platform_id : 1;
uint32_t timestamp : 1;
uint32_t partition_id : 1;
uint32_t reserved : 29;
} valid_bits;
uint32_t valid_mask;
};
uint32_t record_length; /* Total size of CPER Entry */
struct cper_timestamp timestamp;
char platform_id[16];
guid_t partition_id; /* Reserved */
char creator_id[16];
guid_t notify_type; /* CMC, MCE */
char record_id[8]; /* Unique CPER Entry ID */
uint32_t flags; /* Reserved */
uint64_t persistence_info; /* Reserved */
uint8_t reserved[12]; /* Reserved */
};
struct cper_sec_desc {
uint32_t sec_offset; /* Offset from the start of CPER entry */
uint32_t sec_length;
uint8_t revision_minor; /* CPER_SEC_MINOR_REV_1 */
uint8_t revision_major; /* CPER_SEC_MAJOR_REV_22 */
union {
struct {
uint8_t fru_id : 1;
uint8_t fru_text : 1;
uint8_t reserved : 6;
} valid_bits;
uint8_t valid_mask;
};
uint8_t reserved;
union {
struct {
uint32_t primary : 1;
uint32_t reserved1 : 2;
uint32_t exceed_err_threshold : 1;
uint32_t latent_err : 1;
uint32_t reserved2 : 27;
} flag_bits;
uint32_t flag_mask;
};
guid_t sec_type;
char fru_id[16];
enum cper_error_severity severity;
char fru_text[20];
};
struct cper_sec_nonstd_err_hdr {
union {
struct {
uint64_t apic_id : 1;
uint64_t fw_id : 1;
uint64_t err_info_cnt : 6;
uint64_t err_context_cnt : 6;
} valid_bits;
uint64_t valid_mask;
};
uint64_t apic_id;
char fw_id[48];
};
struct cper_sec_nonstd_err_info {
guid_t error_type;
union {
struct {
uint64_t ms_chk : 1;
uint64_t target_addr_id : 1;
uint64_t req_id : 1;
uint64_t resp_id : 1;
uint64_t instr_ptr : 1;
uint64_t reserved : 59;
} valid_bits;
uint64_t valid_mask;
};
union {
struct {
uint64_t err_type_valid : 1;
uint64_t pcc_valid : 1;
uint64_t uncorr_valid : 1;
uint64_t precise_ip_valid : 1;
uint64_t restartable_ip_valid : 1;
uint64_t overflow_valid : 1;
uint64_t reserved1 : 10;
uint64_t err_type : 2;
uint64_t pcc : 1;
uint64_t uncorr : 1;
uint64_t precised_ip : 1;
uint64_t restartable_ip : 1;
uint64_t overflow : 1;
uint64_t reserved2 : 41;
} ms_chk_bits;
uint64_t ms_chk_mask;
};
uint64_t target_addr_id;
uint64_t req_id;
uint64_t resp_id;
uint64_t instr_ptr;
};
struct cper_sec_nonstd_err_ctx {
uint16_t reg_ctx_type;
uint16_t reg_arr_size;
uint32_t msr_addr;
uint64_t mm_reg_addr;
uint32_t reg_dump[CPER_ACA_REG_COUNT];
};
struct cper_sec_nonstd_err {
struct cper_sec_nonstd_err_hdr hdr;
struct cper_sec_nonstd_err_info info;
struct cper_sec_nonstd_err_ctx ctx;
};
struct cper_sec_crashdump_hdr {
uint64_t reserved1;
uint64_t reserved2;
char fw_id[48];
uint64_t reserved3[8];
};
struct cper_sec_crashdump_reg_data {
uint32_t status_lo;
uint32_t status_hi;
uint32_t addr_lo;
uint32_t addr_hi;
uint32_t ipid_lo;
uint32_t ipid_hi;
uint32_t synd_lo;
uint32_t synd_hi;
};
struct cper_sec_crashdump_body_fatal {
uint16_t reg_ctx_type;
uint16_t reg_arr_size;
uint32_t reserved1;
uint64_t reserved2;
struct cper_sec_crashdump_reg_data data;
};
struct cper_sec_crashdump_body_boot {
uint16_t reg_ctx_type;
uint16_t reg_arr_size;
uint32_t reserved1;
uint64_t reserved2;
uint64_t msg[CPER_MAX_OAM_COUNT];
};
struct cper_sec_crashdump_fatal {
struct cper_sec_crashdump_hdr hdr;
struct cper_sec_crashdump_body_fatal body;
};
struct cper_sec_crashdump_boot {
struct cper_sec_crashdump_hdr hdr;
struct cper_sec_crashdump_body_boot body;
};
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/amd_pcie.h
+86
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@@ -0,0 +1,86 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AMD_PCIE_H__
#define __AMD_PCIE_H__
/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00100000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
/* Following flags shows PCIe link speed supported by ASIC H/W.*/
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00000010
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
/* gen: chipset 1/2, asic 1/2/3 */
#define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
| CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 0x00000001
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 0x00000002
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 0x00000004
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 0x00000008
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 0x00000010
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 0x00000020
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 0x00000040
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_MASK 0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_SHIFT 0
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_MASK 0xFFFF0000
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16
/* 1/2/4/8/16 lanes */
#define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
| CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
| CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
| CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
| CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
#define AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 \
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 \
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 \
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 \
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16)
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
+141
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AMD_PCIE_HELPERS_H__
#define __AMD_PCIE_HELPERS_H__
#include "amd_pcie.h"
static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
{
if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
return true;
return false;
}
static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
{
if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
return true;
return false;
}
/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
uint16_t ns_pcie_gen)
{
uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &
CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
switch (asic_pcie_link_speed_cap) {
case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
return PP_PCIEGen1;
case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
return PP_PCIEGen2;
case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
return PP_PCIEGen3;
default:
if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
(ns_pcie_gen == PP_PCIEGen3)) {
return PP_PCIEGen3;
} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
return PP_PCIEGen2;
}
}
return PP_PCIEGen1;
}
static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
uint16_t ns_pcie_lanes)
{
int i, j;
uint16_t new_pcie_lanes = ns_pcie_lanes;
uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
switch (pcie_lane_width_cap) {
case 0:
pr_err("No valid PCIE lane width reported\n");
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
new_pcie_lanes = 1;
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
new_pcie_lanes = 2;
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
new_pcie_lanes = 4;
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
new_pcie_lanes = 8;
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
new_pcie_lanes = 12;
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
new_pcie_lanes = 16;
break;
case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
new_pcie_lanes = 32;
break;
default:
for (i = 0; i < 7; i++) {
if (ns_pcie_lanes == pcie_lanes[i]) {
if (pcie_lane_width_cap & (0x10000 << i)) {
break;
} else {
for (j = i - 1; j >= 0; j--) {
if (pcie_lane_width_cap & (0x10000 << j)) {
new_pcie_lanes = pcie_lanes[j];
break;
}
}
if (j < 0) {
for (j = i + 1; j < 7; j++) {
if (pcie_lane_width_cap & (0x10000 << j)) {
new_pcie_lanes = pcie_lanes[j];
break;
}
}
if (j > 7)
pr_err("Cannot find a valid PCIE lane width!\n");
}
}
break;
}
}
break;
}
return new_pcie_lanes;
}
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/amd_shared.h
+488
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@@ -0,0 +1,488 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AMD_SHARED_H__
#define __AMD_SHARED_H__
#include <drm/amd_asic_type.h>
#include <drm/drm_print.h>
#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
struct amdgpu_ip_block;
/*
* Chip flags
*/
enum amd_chip_flags {
AMD_ASIC_MASK = 0x0000ffffUL,
AMD_FLAGS_MASK = 0xffff0000UL,
AMD_IS_MOBILITY = 0x00010000UL,
AMD_IS_APU = 0x00020000UL,
AMD_IS_PX = 0x00040000UL,
AMD_EXP_HW_SUPPORT = 0x00080000UL,
};
enum amd_apu_flags {
AMD_APU_IS_RAVEN = 0x00000001UL,
AMD_APU_IS_RAVEN2 = 0x00000002UL,
AMD_APU_IS_PICASSO = 0x00000004UL,
AMD_APU_IS_RENOIR = 0x00000008UL,
AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
AMD_APU_IS_VANGOGH = 0x00000020UL,
AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,
};
/**
* DOC: IP Blocks
*
* GPUs are composed of IP (intellectual property) blocks. These
* IP blocks provide various functionalities: display, graphics,
* video decode, etc. The IP blocks that comprise a particular GPU
* are listed in the GPU's respective SoC file. amdgpu_device.c
* acquires the list of IP blocks for the GPU in use on initialization.
* It can then operate on this list to perform standard driver operations
* such as: init, fini, suspend, resume, etc.
*
*
* IP block implementations are named using the following convention:
* <functionality>_v<version> (E.g.: gfx_v6_0).
*/
/**
* enum amd_ip_block_type - Used to classify IP blocks by functionality.
*
* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
* @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia
* @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor
* @AMD_IP_BLOCK_TYPE_RAS: Reliability, Availability, Serviceability
* @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
*/
enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_COMMON,
AMD_IP_BLOCK_TYPE_GMC,
AMD_IP_BLOCK_TYPE_IH,
AMD_IP_BLOCK_TYPE_SMC,
AMD_IP_BLOCK_TYPE_PSP,
AMD_IP_BLOCK_TYPE_DCE,
AMD_IP_BLOCK_TYPE_GFX,
AMD_IP_BLOCK_TYPE_SDMA,
AMD_IP_BLOCK_TYPE_UVD,
AMD_IP_BLOCK_TYPE_VCE,
AMD_IP_BLOCK_TYPE_ACP,
AMD_IP_BLOCK_TYPE_VCN,
AMD_IP_BLOCK_TYPE_MES,
AMD_IP_BLOCK_TYPE_JPEG,
AMD_IP_BLOCK_TYPE_VPE,
AMD_IP_BLOCK_TYPE_UMSCH_MM,
AMD_IP_BLOCK_TYPE_ISP,
AMD_IP_BLOCK_TYPE_RAS,
AMD_IP_BLOCK_TYPE_NUM,
};
enum amd_clockgating_state {
AMD_CG_STATE_GATE = 0,
AMD_CG_STATE_UNGATE,
};
enum amd_powergating_state {
AMD_PG_STATE_GATE = 0,
AMD_PG_STATE_UNGATE,
};
/* CG flags */
#define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0)
#define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1)
#define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2)
#define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3)
#define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4)
#define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5)
#define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6)
#define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7)
#define AMD_CG_SUPPORT_MC_LS (1ULL << 8)
#define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9)
#define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10)
#define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11)
#define AMD_CG_SUPPORT_BIF_LS (1ULL << 12)
#define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13)
#define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14)
#define AMD_CG_SUPPORT_HDP_LS (1ULL << 15)
#define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16)
#define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17)
#define AMD_CG_SUPPORT_DRM_LS (1ULL << 18)
#define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19)
#define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20)
#define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21)
#define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22)
#define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23)
#define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24)
#define AMD_CG_SUPPORT_HDP_DS (1ULL << 25)
#define AMD_CG_SUPPORT_HDP_SD (1ULL << 26)
#define AMD_CG_SUPPORT_IH_CG (1ULL << 27)
#define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28)
#define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29)
#define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30)
#define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31)
#define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32)
#define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33)
/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
#define AMD_PG_SUPPORT_UVD (1 << 3)
#define AMD_PG_SUPPORT_VCE (1 << 4)
#define AMD_PG_SUPPORT_CP (1 << 5)
#define AMD_PG_SUPPORT_GDS (1 << 6)
#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
#define AMD_PG_SUPPORT_SDMA (1 << 8)
#define AMD_PG_SUPPORT_ACP (1 << 9)
#define AMD_PG_SUPPORT_SAMU (1 << 10)
#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
#define AMD_PG_SUPPORT_MMHUB (1 << 13)
#define AMD_PG_SUPPORT_VCN (1 << 14)
#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
#define AMD_PG_SUPPORT_ATHUB (1 << 16)
#define AMD_PG_SUPPORT_JPEG (1 << 17)
#define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18)
#define AMD_PG_SUPPORT_JPEG_DPG (1 << 19)
/**
* enum PP_FEATURE_MASK - Used to mask power play features.
*
* @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
* @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
* @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
* @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
* @PP_POWER_CONTAINMENT_MASK: Power containment.
* @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
* @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
* @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
* @PP_ULV_MASK: Ultra low voltage.
* @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
* @PP_CLOCK_STRETCH_MASK: Clock stretching.
* @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
* @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
* @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
* @PP_OVERDRIVE_MASK: Over- and under-clocking support.
* @PP_GFXOFF_MASK: Dynamic graphics engine power control.
* @PP_ACG_MASK: Adaptive clock generator.
* @PP_STUTTER_MODE: Stutter mode.
* @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
* @PP_GFX_DCS_MASK: GFX Async DCS.
*
* To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
* the kernel's command line parameters. This is usually done through a system's
* boot loader (E.g. GRUB). If manually loading the driver, pass
* ppfeaturemask=<mask> as a modprobe parameter.
*/
enum PP_FEATURE_MASK {
PP_SCLK_DPM_MASK = 0x1,
PP_MCLK_DPM_MASK = 0x2,
PP_PCIE_DPM_MASK = 0x4,
PP_SCLK_DEEP_SLEEP_MASK = 0x8,
PP_POWER_CONTAINMENT_MASK = 0x10,
PP_UVD_HANDSHAKE_MASK = 0x20,
PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
PP_VBI_TIME_SUPPORT_MASK = 0x80,
PP_ULV_MASK = 0x100,
PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
PP_CLOCK_STRETCH_MASK = 0x400,
PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
PP_SOCCLK_DPM_MASK = 0x1000,
PP_DCEFCLK_DPM_MASK = 0x2000,
PP_OVERDRIVE_MASK = 0x4000,
PP_GFXOFF_MASK = 0x8000,
PP_ACG_MASK = 0x10000,
PP_STUTTER_MODE = 0x20000,
PP_AVFS_MASK = 0x40000,
PP_GFX_DCS_MASK = 0x80000,
};
enum amd_harvest_ip_mask {
AMD_HARVEST_IP_VCN_MASK = 0x1,
AMD_HARVEST_IP_JPEG_MASK = 0x2,
AMD_HARVEST_IP_DMU_MASK = 0x4,
};
/**
* enum DC_FEATURE_MASK - Bits that control DC feature defaults
*/
enum DC_FEATURE_MASK {
//Default value can be found at "uint amdgpu_dc_feature_mask"
/**
* @DC_FBC_MASK: (0x1) disabled by default
*/
DC_FBC_MASK = (1 << 0),
/**
* @DC_MULTI_MON_PP_MCLK_SWITCH_MASK: (0x2) enabled by default
*/
DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1),
/**
* @DC_DISABLE_FRACTIONAL_PWM_MASK: (0x4) disabled by default
*/
DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2),
/**
* @DC_PSR_MASK: (0x8) disabled by default for DCN < 3.1
*/
DC_PSR_MASK = (1 << 3),
/**
* @DC_EDP_NO_POWER_SEQUENCING: (0x10) disabled by default
*/
DC_EDP_NO_POWER_SEQUENCING = (1 << 4),
/**
* @DC_DISABLE_LTTPR_DP1_4A: (0x20) disabled by default
*/
DC_DISABLE_LTTPR_DP1_4A = (1 << 5),
/**
* @DC_DISABLE_LTTPR_DP2_0: (0x40) disabled by default
*/
DC_DISABLE_LTTPR_DP2_0 = (1 << 6),
/**
* @DC_PSR_ALLOW_SMU_OPT: (0x80) disabled by default
*/
DC_PSR_ALLOW_SMU_OPT = (1 << 7),
/**
* @DC_PSR_ALLOW_MULTI_DISP_OPT: (0x100) disabled by default
*/
DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8),
/**
* @DC_REPLAY_MASK: (0x200) disabled by default for DCN < 3.1.4
*/
DC_REPLAY_MASK = (1 << 9),
/**
* @DC_FRL_MASK: (0x400) disabled by default
*/
DC_FRL_MASK = (1 << 10),
};
/**
* enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP
*/
enum DC_DEBUG_MASK {
/**
* @DC_DISABLE_PIPE_SPLIT: (0x1) If set, disable pipe-splitting
*/
DC_DISABLE_PIPE_SPLIT = 0x1,
/**
* @DC_DISABLE_STUTTER: (0x2) If set, disable memory stutter mode
*/
DC_DISABLE_STUTTER = 0x2,
/**
* @DC_DISABLE_DSC: (0x4) If set, disable display stream compression
*/
DC_DISABLE_DSC = 0x4,
/**
* @DC_DISABLE_CLOCK_GATING: (0x8) If set, disable clock gating optimizations
*/
DC_DISABLE_CLOCK_GATING = 0x8,
/**
* @DC_DISABLE_PSR: (0x10) If set, disable Panel self refresh v1 and PSR-SU
*/
DC_DISABLE_PSR = 0x10,
/**
* @DC_FORCE_SUBVP_MCLK_SWITCH: (0x20) If set, force mclk switch in subvp, even
* if mclk switch in vblank is possible
*/
DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
/**
* @DC_DISABLE_MPO: (0x40) If set, disable multi-plane offloading
*/
DC_DISABLE_MPO = 0x40,
/**
* @DC_ENABLE_DPIA_TRACE: (0x80) If set, enable trace logging for DPIA
*/
DC_ENABLE_DPIA_TRACE = 0x80,
/**
* @DC_ENABLE_DML2: (0x100) If set, force usage of DML2, even if the DCN version
* does not default to it.
*/
DC_ENABLE_DML2 = 0x100,
/**
* @DC_DISABLE_PSR_SU: (0x200) If set, disable PSR SU
*/
DC_DISABLE_PSR_SU = 0x200,
/**
* @DC_DISABLE_REPLAY: (0x400) If set, disable Panel Replay
*/
DC_DISABLE_REPLAY = 0x400,
/**
* @DC_DISABLE_IPS: (0x800) If set, disable all Idle Power States, all the time.
* If more than one IPS debug bit is set, the lowest bit takes
* precedence. For example, if DC_FORCE_IPS_ENABLE and
* DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes
* precedence.
*/
DC_DISABLE_IPS = 0x800,
/**
* @DC_DISABLE_IPS_DYNAMIC: (0x1000) If set, disable all IPS, all the time,
* *except* when driver goes into suspend.
*/
DC_DISABLE_IPS_DYNAMIC = 0x1000,
/**
* @DC_DISABLE_IPS2_DYNAMIC: (0x2000) If set, disable IPS2 (IPS1 allowed) if
* there is an enabled display. Otherwise, enable all IPS.
*/
DC_DISABLE_IPS2_DYNAMIC = 0x2000,
/**
* @DC_FORCE_IPS_ENABLE: (0x4000) If set, force enable all IPS, all the time.
*/
DC_FORCE_IPS_ENABLE = 0x4000,
/**
* @DC_DISABLE_ACPI_EDID: (0x8000) If set, don't attempt to fetch EDID for
* eDP display from ACPI _DDC method.
*/
DC_DISABLE_ACPI_EDID = 0x8000,
/**
* @DC_DISABLE_HDMI_CEC: (0x10000) If set, disable HDMI-CEC feature in amdgpu driver.
*/
DC_DISABLE_HDMI_CEC = 0x10000,
/**
* @DC_DISABLE_SUBVP_FAMS: (0x20000) If set, disable DCN Sub-Viewport & Firmware Assisted
* Memory Clock Switching (FAMS) feature in amdgpu driver.
*/
DC_DISABLE_SUBVP_FAMS = 0x20000,
/**
* @DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE: (0x40000) If set, disable support for custom
* brightness curves
*/
DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE = 0x40000,
/**
* @DC_HDCP_LC_FORCE_FW_ENABLE: (0x80000) If set, use HDCP Locality Check FW
* path regardless of reported HW capabilities.
*/
DC_HDCP_LC_FORCE_FW_ENABLE = 0x80000,
/**
* @DC_HDCP_LC_ENABLE_SW_FALLBACK: (0x100000) If set, upon HDCP Locality Check FW
* path failure, retry using legacy SW path.
*/
DC_HDCP_LC_ENABLE_SW_FALLBACK = 0x100000,
/**
* @DC_SKIP_DETECTION_LT: (0x200000) If set, skip detection link training
*/
DC_SKIP_DETECTION_LT = 0x200000,
};
enum amd_dpm_forced_level;
/**
* struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
* @name: Name of IP block
* @early_init: sets up early driver state (pre sw_init),
* does not configure hw - Optional
* @late_init: sets up late driver/hw state (post hw_init) - Optional
* @sw_init: sets up driver state, does not configure hw
* @sw_fini: tears down driver state, does not configure hw
* @early_fini: tears down stuff before dev detached from driver
* @hw_init: sets up the hw state
* @hw_fini: tears down the hw state
* @late_fini: final cleanup
* @prepare_suspend: handle IP specific changes to prepare for suspend
* (such as allocating any required memory)
* @suspend: handles IP specific hw/sw changes for suspend
* @resume: handles IP specific hw/sw changes for resume
* @complete: handles IP specific changes after resume
* @is_idle: returns current IP block idle status
* @wait_for_idle: poll for idle
* @check_soft_reset: check soft reset the IP block
* @pre_soft_reset: pre soft reset the IP block
* @soft_reset: soft reset the IP block
* @post_soft_reset: post soft reset the IP block
* @set_clockgating_state: enable/disable cg for the IP block
* @set_powergating_state: enable/disable pg for the IP block
* @get_clockgating_state: get current clockgating status
* @dump_ip_state: dump the IP state of the ASIC during a gpu hang
* @print_ip_state: print the IP state in devcoredump for each IP of the ASIC
*
* These hooks provide an interface for controlling the operational state
* of IP blocks. After acquiring a list of IP blocks for the GPU in use,
* the driver can make chip-wide state changes by walking this list and
* making calls to hooks from each IP block. This list is ordered to ensure
* that the driver initializes the IP blocks in a safe sequence.
*/
struct amd_ip_funcs {
char *name;
int (*early_init)(struct amdgpu_ip_block *ip_block);
int (*late_init)(struct amdgpu_ip_block *ip_block);
int (*sw_init)(struct amdgpu_ip_block *ip_block);
int (*sw_fini)(struct amdgpu_ip_block *ip_block);
int (*early_fini)(struct amdgpu_ip_block *ip_block);
int (*hw_init)(struct amdgpu_ip_block *ip_block);
int (*hw_fini)(struct amdgpu_ip_block *ip_block);
void (*late_fini)(struct amdgpu_ip_block *ip_block);
int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);
int (*suspend)(struct amdgpu_ip_block *ip_block);
int (*resume)(struct amdgpu_ip_block *ip_block);
void (*complete)(struct amdgpu_ip_block *ip_block);
bool (*is_idle)(struct amdgpu_ip_block *ip_block);
int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);
bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*soft_reset)(struct amdgpu_ip_block *ip_block);
int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
void (*get_clockgating_state)(struct amdgpu_ip_block *ip_block, u64 *flags);
void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p);
};
#endif /* __AMD_SHARED_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/amdgpu_ptl.h
+64
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/*
* Copyright 2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AMDGPU_PTL_H__
#define __AMDGPU_PTL_H__
enum amdgpu_ptl_fmt {
AMDGPU_PTL_FMT_I8 = 0,
AMDGPU_PTL_FMT_F16 = 1,
AMDGPU_PTL_FMT_BF16 = 2,
AMDGPU_PTL_FMT_F32 = 3,
AMDGPU_PTL_FMT_F64 = 4,
AMDGPU_PTL_FMT_F8 = 5,
AMDGPU_PTL_FMT_VECTOR = 6,
AMDGPU_PTL_FMT_INVALID = 7,
};
enum amdgpu_ptl_disable_source {
AMDGPU_PTL_DISABLE_SYSFS = 0,
AMDGPU_PTL_DISABLE_PROFILER,
AMDGPU_PTL_DISABLE_MAX,
};
struct amdgpu_ptl {
enum amdgpu_ptl_fmt fmt1;
enum amdgpu_ptl_fmt fmt2;
bool enabled;
bool hw_supported;
bool permanently_disabled;
/* PTL disable reference counting */
atomic_t disable_ref;
struct mutex mutex;
DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX);
bool ptl_sysfs_created;
};
int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code,
u32 *ptl_state,
enum amdgpu_ptl_fmt *fmt1,
enum amdgpu_ptl_fmt *fmt2);
int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev);
void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev);
extern const struct attribute_group amdgpu_ptl_attr_group;
#endif /* __AMDGPU_PTL_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/amdgpu_reg_state.h
+153
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@@ -0,0 +1,153 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMDGPU_REG_STATE_H__
#define __AMDGPU_REG_STATE_H__
enum amdgpu_reg_state {
AMDGPU_REG_STATE_TYPE_INVALID = 0,
AMDGPU_REG_STATE_TYPE_XGMI = 1,
AMDGPU_REG_STATE_TYPE_WAFL = 2,
AMDGPU_REG_STATE_TYPE_PCIE = 3,
AMDGPU_REG_STATE_TYPE_USR = 4,
AMDGPU_REG_STATE_TYPE_USR_1 = 5
};
enum amdgpu_sysfs_reg_offset {
AMDGPU_SYS_REG_STATE_XGMI = 0x0000,
AMDGPU_SYS_REG_STATE_WAFL = 0x1000,
AMDGPU_SYS_REG_STATE_PCIE = 0x2000,
AMDGPU_SYS_REG_STATE_USR = 0x3000,
AMDGPU_SYS_REG_STATE_USR_1 = 0x4000,
AMDGPU_SYS_REG_STATE_END = 0x5000,
};
struct amdgpu_reg_state_header {
uint16_t structure_size;
uint8_t format_revision;
uint8_t content_revision;
uint8_t state_type;
uint8_t num_instances;
uint16_t pad;
};
enum amdgpu_reg_inst_state {
AMDGPU_INST_S_OK,
AMDGPU_INST_S_EDISABLED,
AMDGPU_INST_S_EACCESS,
};
struct amdgpu_smn_reg_data {
uint64_t addr;
uint32_t value;
uint32_t pad;
};
struct amdgpu_reg_inst_header {
uint16_t instance;
uint16_t state;
uint16_t num_smn_regs;
uint16_t pad;
};
struct amdgpu_regs_xgmi_v1_0 {
struct amdgpu_reg_inst_header inst_header;
struct amdgpu_smn_reg_data smn_reg_values[];
};
struct amdgpu_reg_state_xgmi_v1_0 {
/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_XGMI */
struct amdgpu_reg_state_header common_header;
struct amdgpu_regs_xgmi_v1_0 xgmi_state_regs[];
};
struct amdgpu_regs_wafl_v1_0 {
struct amdgpu_reg_inst_header inst_header;
struct amdgpu_smn_reg_data smn_reg_values[];
};
struct amdgpu_reg_state_wafl_v1_0 {
/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_WAFL */
struct amdgpu_reg_state_header common_header;
struct amdgpu_regs_wafl_v1_0 wafl_state_regs[];
};
struct amdgpu_regs_pcie_v1_0 {
struct amdgpu_reg_inst_header inst_header;
uint16_t device_status;
uint16_t link_status;
uint32_t sub_bus_number_latency;
uint32_t pcie_corr_err_status;
uint32_t pcie_uncorr_err_status;
struct amdgpu_smn_reg_data smn_reg_values[];
};
struct amdgpu_reg_state_pcie_v1_0 {
/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_PCIE */
struct amdgpu_reg_state_header common_header;
struct amdgpu_regs_pcie_v1_0 pci_state_regs[];
};
struct amdgpu_regs_usr_v1_0 {
struct amdgpu_reg_inst_header inst_header;
struct amdgpu_smn_reg_data smn_reg_values[];
};
struct amdgpu_reg_state_usr_v1_0 {
/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_USR */
struct amdgpu_reg_state_header common_header;
struct amdgpu_regs_usr_v1_0 usr_state_regs[];
};
static inline size_t amdgpu_reginst_size(uint16_t num_inst, size_t inst_size,
uint16_t num_regs)
{
return num_inst *
(inst_size + num_regs * sizeof(struct amdgpu_smn_reg_data));
}
#define amdgpu_asic_get_reg_state_supported(adev) \
(((adev)->asic_funcs && (adev)->asic_funcs->get_reg_state) ? 1 : 0)
#define amdgpu_asic_get_reg_state(adev, state, buf, size) \
((adev)->asic_funcs->get_reg_state ? \
(adev)->asic_funcs->get_reg_state((adev), (state), (buf), \
(size)) : \
0)
int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev);
void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev);
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/arct_ip_offset.h
+1648
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h
+453
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@@ -0,0 +1,453 @@
/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _athub_1_0_OFFSET_HEADER
#define _athub_1_0_OFFSET_HEADER
// addressBlock: athub_atsdec
// base address: 0x3080
#define mmATC_ATS_CNTL 0x0000
#define mmATC_ATS_CNTL_BASE_IDX 0
#define mmATC_ATS_STATUS 0x0003
#define mmATC_ATS_STATUS_BASE_IDX 0
#define mmATC_ATS_FAULT_CNTL 0x0004
#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
#define mmATHUB_MISC_CNTL 0x000a
#define mmATHUB_MISC_CNTL_BASE_IDX 0
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
#define mmATC_VMID0_PASID_MAPPING 0x000c
#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID1_PASID_MAPPING 0x000d
#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID2_PASID_MAPPING 0x000e
#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID3_PASID_MAPPING 0x000f
#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID4_PASID_MAPPING 0x0010
#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID5_PASID_MAPPING 0x0011
#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID6_PASID_MAPPING 0x0012
#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID7_PASID_MAPPING 0x0013
#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID8_PASID_MAPPING 0x0014
#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID9_PASID_MAPPING 0x0015
#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID10_PASID_MAPPING 0x0016
#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID11_PASID_MAPPING 0x0017
#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID12_PASID_MAPPING 0x0018
#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID13_PASID_MAPPING 0x0019
#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID14_PASID_MAPPING 0x001a
#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID15_PASID_MAPPING 0x001b
#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
#define mmATC_ATS_VMID_STATUS 0x001c
#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
#define mmATC_PERFCOUNTER0_CFG 0x001e
#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER1_CFG 0x001f
#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER2_CFG 0x0020
#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER3_CFG 0x0021
#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmATC_PERFCOUNTER_LO 0x0023
#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
#define mmATC_PERFCOUNTER_HI 0x0024
#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL 0x0025
#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PASID_CNTL 0x0026
#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
#define mmATHUB_COMMAND 0x0029
#define mmATHUB_COMMAND_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
#define mmATHUB_MEM_POWER_LS 0x003a
#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
#define mmATS_IH_CREDIT 0x003b
#define mmATS_IH_CREDIT_BASE_IDX 0
#define mmATHUB_IH_CREDIT 0x003c
#define mmATHUB_IH_CREDIT_BASE_IDX 0
#define mmATC_VMID16_PASID_MAPPING 0x003d
#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID17_PASID_MAPPING 0x003e
#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID18_PASID_MAPPING 0x003f
#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID19_PASID_MAPPING 0x0040
#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID20_PASID_MAPPING 0x0041
#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID21_PASID_MAPPING 0x0042
#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID22_PASID_MAPPING 0x0043
#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID23_PASID_MAPPING 0x0044
#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID24_PASID_MAPPING 0x0045
#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID25_PASID_MAPPING 0x0046
#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID26_PASID_MAPPING 0x0047
#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID27_PASID_MAPPING 0x0048
#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID28_PASID_MAPPING 0x0049
#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID29_PASID_MAPPING 0x004a
#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID30_PASID_MAPPING 0x004b
#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID31_PASID_MAPPING 0x004c
#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d
#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e
#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f
#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define mmATC_ATS_SDPPORT_CNTL 0x0050
#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
// addressBlock: athub_xpbdec
// base address: 0x31f0
#define mmXPB_RTR_SRC_APRTR0 0x005c
#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR1 0x005d
#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR2 0x005e
#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR3 0x005f
#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR4 0x0060
#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR5 0x0061
#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR6 0x0062
#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR7 0x0063
#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR8 0x0064
#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR9 0x0065
#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066
#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067
#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068
#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069
#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP0 0x006a
#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP1 0x006b
#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP2 0x006c
#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP3 0x006d
#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP4 0x006e
#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP5 0x006f
#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP6 0x0070
#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP7 0x0071
#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP8 0x0072
#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP9 0x0073
#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074
#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075
#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076
#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077
#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
#define mmXPB_CLG_CFG0 0x0078
#define mmXPB_CLG_CFG0_BASE_IDX 0
#define mmXPB_CLG_CFG1 0x0079
#define mmXPB_CLG_CFG1_BASE_IDX 0
#define mmXPB_CLG_CFG2 0x007a
#define mmXPB_CLG_CFG2_BASE_IDX 0
#define mmXPB_CLG_CFG3 0x007b
#define mmXPB_CLG_CFG3_BASE_IDX 0
#define mmXPB_CLG_CFG4 0x007c
#define mmXPB_CLG_CFG4_BASE_IDX 0
#define mmXPB_CLG_CFG5 0x007d
#define mmXPB_CLG_CFG5_BASE_IDX 0
#define mmXPB_CLG_CFG6 0x007e
#define mmXPB_CLG_CFG6_BASE_IDX 0
#define mmXPB_CLG_CFG7 0x007f
#define mmXPB_CLG_CFG7_BASE_IDX 0
#define mmXPB_CLG_EXTRA 0x0080
#define mmXPB_CLG_EXTRA_BASE_IDX 0
#define mmXPB_CLG_EXTRA_MSK 0x0081
#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
#define mmXPB_LB_ADDR 0x0082
#define mmXPB_LB_ADDR_BASE_IDX 0
#define mmXPB_WCB_STS 0x0083
#define mmXPB_WCB_STS_BASE_IDX 0
#define mmXPB_HST_CFG 0x0084
#define mmXPB_HST_CFG_BASE_IDX 0
#define mmXPB_P2P_BAR_CFG 0x0085
#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
#define mmXPB_P2P_BAR0 0x0086
#define mmXPB_P2P_BAR0_BASE_IDX 0
#define mmXPB_P2P_BAR1 0x0087
#define mmXPB_P2P_BAR1_BASE_IDX 0
#define mmXPB_P2P_BAR2 0x0088
#define mmXPB_P2P_BAR2_BASE_IDX 0
#define mmXPB_P2P_BAR3 0x0089
#define mmXPB_P2P_BAR3_BASE_IDX 0
#define mmXPB_P2P_BAR4 0x008a
#define mmXPB_P2P_BAR4_BASE_IDX 0
#define mmXPB_P2P_BAR5 0x008b
#define mmXPB_P2P_BAR5_BASE_IDX 0
#define mmXPB_P2P_BAR6 0x008c
#define mmXPB_P2P_BAR6_BASE_IDX 0
#define mmXPB_P2P_BAR7 0x008d
#define mmXPB_P2P_BAR7_BASE_IDX 0
#define mmXPB_P2P_BAR_SETUP 0x008e
#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090
#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091
#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR0 0x0092
#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR1 0x0093
#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR2 0x0094
#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR3 0x0095
#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR4 0x0096
#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR5 0x0097
#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR6 0x0098
#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR7 0x0099
#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR8 0x009a
#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR9 0x009b
#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c
#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d
#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e
#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f
#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
#define mmXPB_CLK_GAT 0x00a0
#define mmXPB_CLK_GAT_BASE_IDX 0
#define mmXPB_INTF_CFG 0x00a1
#define mmXPB_INTF_CFG_BASE_IDX 0
#define mmXPB_INTF_STS 0x00a2
#define mmXPB_INTF_STS_BASE_IDX 0
#define mmXPB_PIPE_STS 0x00a3
#define mmXPB_PIPE_STS_BASE_IDX 0
#define mmXPB_SUB_CTRL 0x00a4
#define mmXPB_SUB_CTRL_BASE_IDX 0
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
#define mmXPB_PERF_KNOBS 0x00a6
#define mmXPB_PERF_KNOBS_BASE_IDX 0
#define mmXPB_STICKY 0x00a7
#define mmXPB_STICKY_BASE_IDX 0
#define mmXPB_STICKY_W1C 0x00a8
#define mmXPB_STICKY_W1C_BASE_IDX 0
#define mmXPB_MISC_CFG 0x00a9
#define mmXPB_MISC_CFG_BASE_IDX 0
#define mmXPB_INTF_CFG2 0x00aa
#define mmXPB_INTF_CFG2_BASE_IDX 0
#define mmXPB_CLG_EXTRA_RD 0x00ab
#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac
#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
#define mmXPB_CLG_GFX_MATCH 0x00ad
#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae
#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_MM_MATCH 0x00af
#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
#define mmXPB_CLG_MM_MATCH_MSK 0x00b0
#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1
#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2
#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3
#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4
#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5
#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6
#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7
#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8
#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9
#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba
#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb
#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc
#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
// addressBlock: athub_rpbdec
// base address: 0x33b0
#define mmRPB_PASSPW_CONF 0x00cc
#define mmRPB_PASSPW_CONF_BASE_IDX 0
#define mmRPB_BLOCKLEVEL_CONF 0x00cd
#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
#define mmRPB_TAG_CONF 0x00cf
#define mmRPB_TAG_CONF_BASE_IDX 0
#define mmRPB_EFF_CNTL 0x00d1
#define mmRPB_EFF_CNTL_BASE_IDX 0
#define mmRPB_ARB_CNTL 0x00d2
#define mmRPB_ARB_CNTL_BASE_IDX 0
#define mmRPB_ARB_CNTL2 0x00d3
#define mmRPB_ARB_CNTL2_BASE_IDX 0
#define mmRPB_BIF_CNTL 0x00d4
#define mmRPB_BIF_CNTL_BASE_IDX 0
#define mmRPB_WR_SWITCH_CNTL 0x00d5
#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
#define mmRPB_RD_SWITCH_CNTL 0x00d7
#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
#define mmRPB_CID_QUEUE_WR 0x00d8
#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
#define mmRPB_CID_QUEUE_RD 0x00d9
#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
#define mmRPB_CID_QUEUE_EX 0x00dc
#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
#define mmRPB_CID_QUEUE_EX_DATA 0x00dd
#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
#define mmRPB_SWITCH_CNTL2 0x00de
#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df
#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
#define mmRPB_VC_SWITCH_RDWR 0x00e0
#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
#define mmRPB_PERFCOUNTER_LO 0x00e1
#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
#define mmRPB_PERFCOUNTER_HI 0x00e2
#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
#define mmRPB_PERFCOUNTER0_CFG 0x00e3
#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER1_CFG 0x00e4
#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER2_CFG 0x00e5
#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER3_CFG 0x00e6
#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7
#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmRPB_RD_QUEUE_CNTL 0x00e9
#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
#define mmRPB_RD_QUEUE_CNTL2 0x00ea
#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
#define mmRPB_WR_QUEUE_CNTL 0x00eb
#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
#define mmRPB_WR_QUEUE_CNTL2 0x00ec
#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
#define mmRPB_EA_QUEUE_WR 0x00ed
#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
#define mmRPB_ATS_CNTL 0x00ee
#define mmRPB_ATS_CNTL_BASE_IDX 0
#define mmRPB_ATS_CNTL2 0x00ef
#define mmRPB_ATS_CNTL2_BASE_IDX 0
#define mmRPB_SDPPORT_CNTL 0x00f0
#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h
+2045
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_8_0_offset.h
+411
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@@ -0,0 +1,411 @@
/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _athub_1_8_0_OFFSET_HEADER
#define _athub_1_8_0_OFFSET_HEADER
// addressBlock: aid_athub_atsdec
// base address: 0x3080
#define regATC_ATS_CNTL 0x0000
#define regATC_ATS_CNTL_BASE_IDX 0
#define regATC_ATS_CNTL2 0x0001
#define regATC_ATS_CNTL2_BASE_IDX 0
#define regATC_ATS_CNTL3 0x0002
#define regATC_ATS_CNTL3_BASE_IDX 0
#define regATC_ATS_CNTL4 0x0003
#define regATC_ATS_CNTL4_BASE_IDX 0
#define regATC_ATS_MISC_CNTL 0x0005
#define regATC_ATS_MISC_CNTL_BASE_IDX 0
#define regATC_ATS_STATUS 0x0009
#define regATC_ATS_STATUS_BASE_IDX 0
#define regATC_PERFCOUNTER0_CFG 0x000a
#define regATC_PERFCOUNTER0_CFG_BASE_IDX 0
#define regATC_PERFCOUNTER1_CFG 0x000b
#define regATC_PERFCOUNTER1_CFG_BASE_IDX 0
#define regATC_PERFCOUNTER2_CFG 0x000c
#define regATC_PERFCOUNTER2_CFG_BASE_IDX 0
#define regATC_PERFCOUNTER3_CFG 0x000d
#define regATC_PERFCOUNTER3_CFG_BASE_IDX 0
#define regATC_PERFCOUNTER_RSLT_CNTL 0x000e
#define regATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regATC_PERFCOUNTER_LO 0x000f
#define regATC_PERFCOUNTER_LO_BASE_IDX 0
#define regATC_PERFCOUNTER_HI 0x0010
#define regATC_PERFCOUNTER_HI_BASE_IDX 0
#define regATC_ATS_FAULT_CNTL 0x0012
#define regATC_ATS_FAULT_CNTL_BASE_IDX 0
#define regATC_ATS_FAULT_STATUS_INFO 0x0013
#define regATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
#define regATC_ATS_FAULT_STATUS_INFO2 0x0014
#define regATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
#define regATC_ATS_FAULT_STATUS_INFO3 0x0015
#define regATC_ATS_FAULT_STATUS_INFO3_BASE_IDX 0
#define regATC_ATS_FAULT_STATUS_INFO4 0x0016
#define regATC_ATS_FAULT_STATUS_INFO4_BASE_IDX 0
#define regATC_ATS_FAULT_STATUS_ADDR 0x0017
#define regATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
#define regATC_ATS_DEFAULT_PAGE_LOW 0x0018
#define regATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL 0x001f
#define regATHUB_PCIE_ATS_CNTL_BASE_IDX 0
#define regATHUB_PCIE_PASID_CNTL 0x0020
#define regATHUB_PCIE_PASID_CNTL_BASE_IDX 0
#define regATHUB_PCIE_PAGE_REQ_CNTL 0x0021
#define regATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
#define regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0022
#define regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
#define regATHUB_COMMAND 0x0023
#define regATHUB_COMMAND_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_0 0x0024
#define regATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_1 0x0025
#define regATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_2 0x0026
#define regATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_3 0x0027
#define regATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_4 0x0028
#define regATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_5 0x0029
#define regATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_6 0x002a
#define regATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_7 0x002b
#define regATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_8 0x002c
#define regATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_9 0x002d
#define regATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_10 0x002e
#define regATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_11 0x002f
#define regATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_12 0x0030
#define regATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_13 0x0031
#define regATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_14 0x0032
#define regATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
#define regATHUB_PCIE_ATS_CNTL_VF_15 0x0033
#define regATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
#define regATHUB_SHARED_VIRT_RESET_REQ 0x0034
#define regATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define regATHUB_SHARED_ACTIVE_FCN_ID 0x0036
#define regATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define regATC_ATS_SDPPORT_CNTL 0x0038
#define regATC_ATS_SDPPORT_CNTL_BASE_IDX 0
#define regATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x003e
#define regATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
#define regATC_VMID0_PASID_MAPPING 0x003f
#define regATC_VMID0_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID1_PASID_MAPPING 0x0040
#define regATC_VMID1_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID2_PASID_MAPPING 0x0041
#define regATC_VMID2_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID3_PASID_MAPPING 0x0042
#define regATC_VMID3_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID4_PASID_MAPPING 0x0043
#define regATC_VMID4_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID5_PASID_MAPPING 0x0044
#define regATC_VMID5_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID6_PASID_MAPPING 0x0045
#define regATC_VMID6_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID7_PASID_MAPPING 0x0046
#define regATC_VMID7_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID8_PASID_MAPPING 0x0047
#define regATC_VMID8_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID9_PASID_MAPPING 0x0048
#define regATC_VMID9_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID10_PASID_MAPPING 0x0049
#define regATC_VMID10_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID11_PASID_MAPPING 0x004a
#define regATC_VMID11_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID12_PASID_MAPPING 0x004b
#define regATC_VMID12_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID13_PASID_MAPPING 0x004c
#define regATC_VMID13_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID14_PASID_MAPPING 0x004d
#define regATC_VMID14_PASID_MAPPING_BASE_IDX 0
#define regATC_VMID15_PASID_MAPPING 0x004e
#define regATC_VMID15_PASID_MAPPING_BASE_IDX 0
#define regATC_TRANS_FAULT_RSPCNTRL 0x0050
#define regATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
#define regATC_ATS_VMID_STATUS 0x0051
#define regATC_ATS_VMID_STATUS_BASE_IDX 0
#define regATHUB_MISC_CNTL 0x0055
#define regATHUB_MISC_CNTL_BASE_IDX 0
#define regATHUB_MEM_POWER_LS 0x0056
#define regATHUB_MEM_POWER_LS_BASE_IDX 0
#define regATHUB_IH_CREDIT 0x0057
#define regATHUB_IH_CREDIT_BASE_IDX 0
// addressBlock: aid_athub_xpbdec
// base address: 0x46000
#define regXPB_RTR_SRC_APRTR0 0x0000
#define regXPB_RTR_SRC_APRTR0_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR1 0x0001
#define regXPB_RTR_SRC_APRTR1_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR2 0x0002
#define regXPB_RTR_SRC_APRTR2_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR3 0x0003
#define regXPB_RTR_SRC_APRTR3_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR4 0x0004
#define regXPB_RTR_SRC_APRTR4_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR5 0x0005
#define regXPB_RTR_SRC_APRTR5_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR6 0x0006
#define regXPB_RTR_SRC_APRTR6_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR7 0x0007
#define regXPB_RTR_SRC_APRTR7_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR8 0x0008
#define regXPB_RTR_SRC_APRTR8_BASE_IDX 1
#define regXPB_RTR_SRC_APRTR9 0x0009
#define regXPB_RTR_SRC_APRTR9_BASE_IDX 1
#define regXPB_XDMA_RTR_SRC_APRTR0 0x000a
#define regXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 1
#define regXPB_XDMA_RTR_SRC_APRTR1 0x000b
#define regXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 1
#define regXPB_XDMA_RTR_SRC_APRTR2 0x000c
#define regXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 1
#define regXPB_XDMA_RTR_SRC_APRTR3 0x000d
#define regXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 1
#define regXPB_RTR_DEST_MAP0 0x000e
#define regXPB_RTR_DEST_MAP0_BASE_IDX 1
#define regXPB_RTR_DEST_MAP1 0x000f
#define regXPB_RTR_DEST_MAP1_BASE_IDX 1
#define regXPB_RTR_DEST_MAP2 0x0010
#define regXPB_RTR_DEST_MAP2_BASE_IDX 1
#define regXPB_RTR_DEST_MAP3 0x0011
#define regXPB_RTR_DEST_MAP3_BASE_IDX 1
#define regXPB_RTR_DEST_MAP4 0x0012
#define regXPB_RTR_DEST_MAP4_BASE_IDX 1
#define regXPB_RTR_DEST_MAP5 0x0013
#define regXPB_RTR_DEST_MAP5_BASE_IDX 1
#define regXPB_RTR_DEST_MAP6 0x0014
#define regXPB_RTR_DEST_MAP6_BASE_IDX 1
#define regXPB_RTR_DEST_MAP7 0x0015
#define regXPB_RTR_DEST_MAP7_BASE_IDX 1
#define regXPB_RTR_DEST_MAP8 0x0016
#define regXPB_RTR_DEST_MAP8_BASE_IDX 1
#define regXPB_RTR_DEST_MAP9 0x0017
#define regXPB_RTR_DEST_MAP9_BASE_IDX 1
#define regXPB_XDMA_RTR_DEST_MAP0 0x0018
#define regXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 1
#define regXPB_XDMA_RTR_DEST_MAP1 0x0019
#define regXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 1
#define regXPB_XDMA_RTR_DEST_MAP2 0x001a
#define regXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 1
#define regXPB_XDMA_RTR_DEST_MAP3 0x001b
#define regXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 1
#define regXPB_CLG_CFG0 0x001c
#define regXPB_CLG_CFG0_BASE_IDX 1
#define regXPB_CLG_CFG1 0x001d
#define regXPB_CLG_CFG1_BASE_IDX 1
#define regXPB_CLG_CFG2 0x001e
#define regXPB_CLG_CFG2_BASE_IDX 1
#define regXPB_CLG_CFG3 0x001f
#define regXPB_CLG_CFG3_BASE_IDX 1
#define regXPB_CLG_CFG4 0x0020
#define regXPB_CLG_CFG4_BASE_IDX 1
#define regXPB_CLG_CFG5 0x0021
#define regXPB_CLG_CFG5_BASE_IDX 1
#define regXPB_CLG_CFG6 0x0022
#define regXPB_CLG_CFG6_BASE_IDX 1
#define regXPB_CLG_CFG7 0x0023
#define regXPB_CLG_CFG7_BASE_IDX 1
#define regXPB_CLG_EXTRA0 0x0024
#define regXPB_CLG_EXTRA0_BASE_IDX 1
#define regXPB_CLG_EXTRA1 0x0025
#define regXPB_CLG_EXTRA1_BASE_IDX 1
#define regXPB_CLG_EXTRA_MSK 0x0026
#define regXPB_CLG_EXTRA_MSK_BASE_IDX 1
#define regXPB_LB_ADDR 0x0027
#define regXPB_LB_ADDR_BASE_IDX 1
#define regXPB_WCB_STS 0x0028
#define regXPB_WCB_STS_BASE_IDX 1
#define regXPB_HST_CFG 0x0029
#define regXPB_HST_CFG_BASE_IDX 1
#define regXPB_P2P_BAR_CFG 0x002a
#define regXPB_P2P_BAR_CFG_BASE_IDX 1
#define regXPB_P2P_BAR0 0x002b
#define regXPB_P2P_BAR0_BASE_IDX 1
#define regXPB_P2P_BAR1 0x002c
#define regXPB_P2P_BAR1_BASE_IDX 1
#define regXPB_P2P_BAR2 0x002d
#define regXPB_P2P_BAR2_BASE_IDX 1
#define regXPB_P2P_BAR3 0x002e
#define regXPB_P2P_BAR3_BASE_IDX 1
#define regXPB_P2P_BAR4 0x002f
#define regXPB_P2P_BAR4_BASE_IDX 1
#define regXPB_P2P_BAR5 0x0030
#define regXPB_P2P_BAR5_BASE_IDX 1
#define regXPB_P2P_BAR6 0x0031
#define regXPB_P2P_BAR6_BASE_IDX 1
#define regXPB_P2P_BAR7 0x0032
#define regXPB_P2P_BAR7_BASE_IDX 1
#define regXPB_P2P_BAR_SETUP 0x0033
#define regXPB_P2P_BAR_SETUP_BASE_IDX 1
#define regXPB_P2P_BAR_DELTA_ABOVE 0x0035
#define regXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 1
#define regXPB_P2P_BAR_DELTA_BELOW 0x0036
#define regXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 1
#define regXPB_PEER_SYS_BAR0 0x0037
#define regXPB_PEER_SYS_BAR0_BASE_IDX 1
#define regXPB_PEER_SYS_BAR1 0x0038
#define regXPB_PEER_SYS_BAR1_BASE_IDX 1
#define regXPB_PEER_SYS_BAR2 0x0039
#define regXPB_PEER_SYS_BAR2_BASE_IDX 1
#define regXPB_PEER_SYS_BAR3 0x003a
#define regXPB_PEER_SYS_BAR3_BASE_IDX 1
#define regXPB_PEER_SYS_BAR4 0x003b
#define regXPB_PEER_SYS_BAR4_BASE_IDX 1
#define regXPB_PEER_SYS_BAR5 0x003c
#define regXPB_PEER_SYS_BAR5_BASE_IDX 1
#define regXPB_PEER_SYS_BAR6 0x003d
#define regXPB_PEER_SYS_BAR6_BASE_IDX 1
#define regXPB_PEER_SYS_BAR7 0x003e
#define regXPB_PEER_SYS_BAR7_BASE_IDX 1
#define regXPB_PEER_SYS_BAR8 0x003f
#define regXPB_PEER_SYS_BAR8_BASE_IDX 1
#define regXPB_PEER_SYS_BAR9 0x0040
#define regXPB_PEER_SYS_BAR9_BASE_IDX 1
#define regXPB_XDMA_PEER_SYS_BAR0 0x0041
#define regXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 1
#define regXPB_XDMA_PEER_SYS_BAR1 0x0042
#define regXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 1
#define regXPB_XDMA_PEER_SYS_BAR2 0x0043
#define regXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 1
#define regXPB_XDMA_PEER_SYS_BAR3 0x0044
#define regXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 1
#define regXPB_CLK_GAT 0x0045
#define regXPB_CLK_GAT_BASE_IDX 1
#define regXPB_INTF_CFG 0x0046
#define regXPB_INTF_CFG_BASE_IDX 1
#define regXPB_INTF_STS 0x0047
#define regXPB_INTF_STS_BASE_IDX 1
#define regXPB_PIPE_STS 0x0048
#define regXPB_PIPE_STS_BASE_IDX 1
#define regXPB_SUB_CTRL 0x0049
#define regXPB_SUB_CTRL_BASE_IDX 1
#define regXPB_MAP_INVERT_FLUSH_NUM_LSB 0x004a
#define regXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 1
#define regXPB_PERF_KNOBS 0x004b
#define regXPB_PERF_KNOBS_BASE_IDX 1
#define regXPB_STICKY 0x004c
#define regXPB_STICKY_BASE_IDX 1
#define regXPB_STICKY_W1C 0x004d
#define regXPB_STICKY_W1C_BASE_IDX 1
#define regXPB_MISC_CFG 0x004e
#define regXPB_MISC_CFG_BASE_IDX 1
#define regXPB_INTF_CFG2 0x004f
#define regXPB_INTF_CFG2_BASE_IDX 1
#define regXPB_CLG_EXTRA_RD 0x0050
#define regXPB_CLG_EXTRA_RD_BASE_IDX 1
#define regXPB_CLG_EXTRA_MSK_RD 0x0051
#define regXPB_CLG_EXTRA_MSK_RD_BASE_IDX 1
#define regXPB_CLG_GFX_MATCH 0x0052
#define regXPB_CLG_GFX_MATCH_BASE_IDX 1
#define regXPB_CLG_GFX_MATCH_VLD 0x0053
#define regXPB_CLG_GFX_MATCH_VLD_BASE_IDX 1
#define regXPB_CLG_GFX_MATCH_MSK 0x0054
#define regXPB_CLG_GFX_MATCH_MSK_BASE_IDX 1
#define regXPB_CLG_MM_MATCH 0x0055
#define regXPB_CLG_MM_MATCH_BASE_IDX 1
#define regXPB_CLG_MM_MATCH_VLD 0x0056
#define regXPB_CLG_MM_MATCH_VLD_BASE_IDX 1
#define regXPB_CLG_MM_MATCH_MSK 0x0057
#define regXPB_CLG_MM_MATCH_MSK_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING0 0x0058
#define regXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING1 0x0059
#define regXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING2 0x005a
#define regXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING3 0x005b
#define regXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING4 0x005c
#define regXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING5 0x005d
#define regXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING6 0x005e
#define regXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 1
#define regXPB_CLG_GFX_UNITID_MAPPING7 0x005f
#define regXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 1
#define regXPB_CLG_MM_UNITID_MAPPING0 0x0060
#define regXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 1
#define regXPB_CLG_MM_UNITID_MAPPING1 0x0061
#define regXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 1
#define regXPB_CLG_MM_UNITID_MAPPING2 0x0062
#define regXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 1
#define regXPB_CLG_MM_UNITID_MAPPING3 0x0063
#define regXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 1
// addressBlock: aid_athub_rpbdec
// base address: 0x46200
#define regRPB_PASSPW_CONF 0x0080
#define regRPB_PASSPW_CONF_BASE_IDX 1
#define regRPB_BLOCKLEVEL_CONF 0x0081
#define regRPB_BLOCKLEVEL_CONF_BASE_IDX 1
#define regRPB_TAG_CONF 0x0082
#define regRPB_TAG_CONF_BASE_IDX 1
#define regRPB_TAG_CONF2 0x0083
#define regRPB_TAG_CONF2_BASE_IDX 1
#define regRPB_ARB_CNTL 0x0085
#define regRPB_ARB_CNTL_BASE_IDX 1
#define regRPB_ARB_CNTL2 0x0086
#define regRPB_ARB_CNTL2_BASE_IDX 1
#define regRPB_BIF_CNTL 0x0087
#define regRPB_BIF_CNTL_BASE_IDX 1
#define regRPB_BIF_CNTL2 0x0088
#define regRPB_BIF_CNTL2_BASE_IDX 1
#define regRPB_PERF_COUNTER_CNTL 0x008a
#define regRPB_PERF_COUNTER_CNTL_BASE_IDX 1
#define regRPB_DEINTRLV_COMBINE_CNTL 0x008c
#define regRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 1
#define regRPB_VC_SWITCH_RDWR 0x008d
#define regRPB_VC_SWITCH_RDWR_BASE_IDX 1
#define regRPB_PERFCOUNTER_LO 0x008e
#define regRPB_PERFCOUNTER_LO_BASE_IDX 1
#define regRPB_PERFCOUNTER_HI 0x008f
#define regRPB_PERFCOUNTER_HI_BASE_IDX 1
#define regRPB_PERFCOUNTER0_CFG 0x0090
#define regRPB_PERFCOUNTER0_CFG_BASE_IDX 1
#define regRPB_PERFCOUNTER1_CFG 0x0091
#define regRPB_PERFCOUNTER1_CFG_BASE_IDX 1
#define regRPB_PERFCOUNTER2_CFG 0x0092
#define regRPB_PERFCOUNTER2_CFG_BASE_IDX 1
#define regRPB_PERFCOUNTER3_CFG 0x0093
#define regRPB_PERFCOUNTER3_CFG_BASE_IDX 1
#define regRPB_PERFCOUNTER_RSLT_CNTL 0x0094
#define regRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define regRPB_ATS_CNTL 0x0096
#define regRPB_ATS_CNTL_BASE_IDX 1
#define regRPB_ATS_CNTL2 0x0097
#define regRPB_ATS_CNTL2_BASE_IDX 1
#define regRPB_SDPPORT_CNTL 0x0098
#define regRPB_SDPPORT_CNTL_BASE_IDX 1
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_8_0_sh_mask.h
+1807
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h
+272
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@@ -0,0 +1,272 @@
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _athub_2_0_0_DEFAULT_HEADER
#define _athub_2_0_0_DEFAULT_HEADER
// addressBlock: athub_atsdec
#define mmATC_ATS_CNTL_DEFAULT 0x009a0c00
#define mmATC_ATS_STATUS_DEFAULT 0x00000000
#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
#define mmATHUB_MISC_CNTL_DEFAULT 0x001c0200
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000
#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000
#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000
#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000
#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000
#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000
#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
#define mmATHUB_COMMAND_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000
#define mmATHUB_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000
#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208
#define mmATS_IH_CREDIT_DEFAULT 0x00150002
#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002
#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000
#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000
#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000
// addressBlock: athub_xpbdec
#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000
#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000
#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000
#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000
#define mmXPB_CLG_CFG0_DEFAULT 0x00000000
#define mmXPB_CLG_CFG1_DEFAULT 0x00000000
#define mmXPB_CLG_CFG2_DEFAULT 0x00000000
#define mmXPB_CLG_CFG3_DEFAULT 0x00000000
#define mmXPB_CLG_CFG4_DEFAULT 0x00000000
#define mmXPB_CLG_CFG5_DEFAULT 0x00000000
#define mmXPB_CLG_CFG6_DEFAULT 0x00000000
#define mmXPB_CLG_CFG7_DEFAULT 0x00000000
#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000
#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000
#define mmXPB_LB_ADDR_DEFAULT 0x00000000
#define mmXPB_WCB_STS_DEFAULT 0x00000000
#define mmXPB_HST_CFG_DEFAULT 0x00000000
#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f
#define mmXPB_P2P_BAR0_DEFAULT 0x00000000
#define mmXPB_P2P_BAR1_DEFAULT 0x00000000
#define mmXPB_P2P_BAR2_DEFAULT 0x00000000
#define mmXPB_P2P_BAR3_DEFAULT 0x00000000
#define mmXPB_P2P_BAR4_DEFAULT 0x00000000
#define mmXPB_P2P_BAR5_DEFAULT 0x00000000
#define mmXPB_P2P_BAR6_DEFAULT 0x00000000
#define mmXPB_P2P_BAR7_DEFAULT 0x00000000
#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000
#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000
#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000
#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000
#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000
#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000
#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000
#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000
#define mmXPB_CLK_GAT_DEFAULT 0x00040400
#define mmXPB_INTF_CFG_DEFAULT 0x000f1040
#define mmXPB_INTF_STS_DEFAULT 0x00000000
#define mmXPB_PIPE_STS_DEFAULT 0x00000000
#define mmXPB_SUB_CTRL_DEFAULT 0x00000000
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000
#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000
#define mmXPB_STICKY_DEFAULT 0x00000000
#define mmXPB_STICKY_W1C_DEFAULT 0x00000000
#define mmXPB_MISC_CFG_DEFAULT 0x4d585042
#define mmXPB_INTF_CFG2_DEFAULT 0x00000040
#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000
#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000
#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000
#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x003cf3cf
#define mmXPB_CLG_MM_MATCH_DEFAULT 0x00003000
#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000
#define mmXPB_CLG_GUS_MATCH_DEFAULT 0x00000040
#define mmXPB_CLG_GUS_MATCH_MSK_DEFAULT 0x00000000
#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000
#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040
#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080
#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0
#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100
#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140
#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000
#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0
#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000
#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040
#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080
#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0
#define mmXPB_CLG_GUS_UNITID_MAPPING0_DEFAULT 0x00000000
#define mmXPB_CLG_GUS_UNITID_MAPPING1_DEFAULT 0x00000040
#define mmXPB_CLG_GUS_UNITID_MAPPING2_DEFAULT 0x00000080
#define mmXPB_CLG_GUS_UNITID_MAPPING3_DEFAULT 0x000000c0
#define mmXPB_CLG_GUS_UNITID_MAPPING4_DEFAULT 0x00000100
#define mmXPB_CLG_GUS_UNITID_MAPPING5_DEFAULT 0x00000140
#define mmXPB_CLG_GUS_UNITID_MAPPING6_DEFAULT 0x00000180
#define mmXPB_CLG_GUS_UNITID_MAPPING7_DEFAULT 0x000001c0
// addressBlock: athub_rpbdec
#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230
#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0
#define mmRPB_TAG_CONF_DEFAULT 0x08040080
#define mmRPB_EFF_CNTL_DEFAULT 0x00001010
#define mmRPB_ARB_CNTL_DEFAULT 0x00040404
#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104
#define mmRPB_BIF_CNTL_DEFAULT 0x01000404
#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810
#define mmRPB_WR_COMBINE_CNTL_DEFAULT 0x00000013
#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810
#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000
#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000
#define mmRPB_PERF_COUNTER_CNTL_DEFAULT 0x00000010
#define mmRPB_PERF_COUNTER_STATUS_DEFAULT 0x00000000
#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000
#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000
#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810
#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000204
#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00204040
#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000
#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000
#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000
#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
#define mmRPB_BIF_CNTL2_DEFAULT 0x00000000
#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000
#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000
#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000
#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000
#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000
#define mmRPB_ATS_CNTL_DEFAULT 0x58088422
#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13
#define mmRPB_DF_SDPPORT_CNTL_DEFAULT 0x00003820
#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14010
#define mmRPB_NBIF_SDPPORT_CNTL_DEFAULT 0x08084020
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h
+514
View File
@@ -0,0 +1,514 @@
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _athub_2_0_0_OFFSET_HEADER
#define _athub_2_0_0_OFFSET_HEADER
// addressBlock: athub_atsdec
// base address: 0x3000
#define mmATC_ATS_CNTL 0x0000
#define mmATC_ATS_CNTL_BASE_IDX 0
#define mmATC_ATS_STATUS 0x0003
#define mmATC_ATS_STATUS_BASE_IDX 0
#define mmATC_ATS_FAULT_CNTL 0x0004
#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
#define mmATHUB_MISC_CNTL 0x000a
#define mmATHUB_MISC_CNTL_BASE_IDX 0
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
#define mmATC_VMID0_PASID_MAPPING 0x000c
#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID1_PASID_MAPPING 0x000d
#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID2_PASID_MAPPING 0x000e
#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID3_PASID_MAPPING 0x000f
#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID4_PASID_MAPPING 0x0010
#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID5_PASID_MAPPING 0x0011
#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID6_PASID_MAPPING 0x0012
#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID7_PASID_MAPPING 0x0013
#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID8_PASID_MAPPING 0x0014
#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID9_PASID_MAPPING 0x0015
#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID10_PASID_MAPPING 0x0016
#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID11_PASID_MAPPING 0x0017
#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID12_PASID_MAPPING 0x0018
#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID13_PASID_MAPPING 0x0019
#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID14_PASID_MAPPING 0x001a
#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID15_PASID_MAPPING 0x001b
#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
#define mmATC_ATS_VMID_STATUS 0x001c
#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
#define mmATC_PERFCOUNTER0_CFG 0x001e
#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER1_CFG 0x001f
#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER2_CFG 0x0020
#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER3_CFG 0x0021
#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmATC_PERFCOUNTER_LO 0x0023
#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
#define mmATC_PERFCOUNTER_HI 0x0024
#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL 0x0025
#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PASID_CNTL 0x0026
#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
#define mmATHUB_COMMAND 0x0029
#define mmATHUB_COMMAND_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_16 0x003a
#define mmATHUB_PCIE_ATS_CNTL_VF_16_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_17 0x003b
#define mmATHUB_PCIE_ATS_CNTL_VF_17_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_18 0x003c
#define mmATHUB_PCIE_ATS_CNTL_VF_18_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_19 0x003d
#define mmATHUB_PCIE_ATS_CNTL_VF_19_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_20 0x003e
#define mmATHUB_PCIE_ATS_CNTL_VF_20_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_21 0x003f
#define mmATHUB_PCIE_ATS_CNTL_VF_21_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_22 0x0040
#define mmATHUB_PCIE_ATS_CNTL_VF_22_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_23 0x0041
#define mmATHUB_PCIE_ATS_CNTL_VF_23_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_24 0x0042
#define mmATHUB_PCIE_ATS_CNTL_VF_24_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_25 0x0043
#define mmATHUB_PCIE_ATS_CNTL_VF_25_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_26 0x0044
#define mmATHUB_PCIE_ATS_CNTL_VF_26_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_27 0x0045
#define mmATHUB_PCIE_ATS_CNTL_VF_27_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_28 0x0046
#define mmATHUB_PCIE_ATS_CNTL_VF_28_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_29 0x0047
#define mmATHUB_PCIE_ATS_CNTL_VF_29_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_30 0x0048
#define mmATHUB_PCIE_ATS_CNTL_VF_30_BASE_IDX 0
#define mmATHUB_MEM_POWER_LS 0x0049
#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
#define mmATS_IH_CREDIT 0x004a
#define mmATS_IH_CREDIT_BASE_IDX 0
#define mmATHUB_IH_CREDIT 0x004b
#define mmATHUB_IH_CREDIT_BASE_IDX 0
#define mmATC_VMID16_PASID_MAPPING 0x004c
#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID17_PASID_MAPPING 0x004d
#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID18_PASID_MAPPING 0x004e
#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID19_PASID_MAPPING 0x004f
#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID20_PASID_MAPPING 0x0050
#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID21_PASID_MAPPING 0x0051
#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID22_PASID_MAPPING 0x0052
#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID23_PASID_MAPPING 0x0053
#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID24_PASID_MAPPING 0x0054
#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID25_PASID_MAPPING 0x0055
#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID26_PASID_MAPPING 0x0056
#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID27_PASID_MAPPING 0x0057
#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID28_PASID_MAPPING 0x0058
#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID29_PASID_MAPPING 0x0059
#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID30_PASID_MAPPING 0x005a
#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID31_PASID_MAPPING 0x005b
#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x005c
#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
#define mmATHUB_SHARED_VIRT_RESET_REQ 0x005d
#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x005e
#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define mmATC_ATS_SDPPORT_CNTL 0x005f
#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0061
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0062
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
// addressBlock: athub_xpbdec
// base address: 0x3190
#define mmXPB_RTR_SRC_APRTR0 0x0064
#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR1 0x0065
#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR2 0x0066
#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR3 0x0067
#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR4 0x0068
#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR5 0x0069
#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR6 0x006a
#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR7 0x006b
#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR8 0x006c
#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR9 0x006d
#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR0 0x006e
#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR1 0x006f
#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0070
#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0071
#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP0 0x0072
#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP1 0x0073
#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP2 0x0074
#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP3 0x0075
#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP4 0x0076
#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP5 0x0077
#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP6 0x0078
#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP7 0x0079
#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP8 0x007a
#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP9 0x007b
#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP0 0x007c
#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP1 0x007d
#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP2 0x007e
#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
#define mmXPB_XDMA_RTR_DEST_MAP3 0x007f
#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
#define mmXPB_CLG_CFG0 0x0080
#define mmXPB_CLG_CFG0_BASE_IDX 0
#define mmXPB_CLG_CFG1 0x0081
#define mmXPB_CLG_CFG1_BASE_IDX 0
#define mmXPB_CLG_CFG2 0x0082
#define mmXPB_CLG_CFG2_BASE_IDX 0
#define mmXPB_CLG_CFG3 0x0083
#define mmXPB_CLG_CFG3_BASE_IDX 0
#define mmXPB_CLG_CFG4 0x0084
#define mmXPB_CLG_CFG4_BASE_IDX 0
#define mmXPB_CLG_CFG5 0x0085
#define mmXPB_CLG_CFG5_BASE_IDX 0
#define mmXPB_CLG_CFG6 0x0086
#define mmXPB_CLG_CFG6_BASE_IDX 0
#define mmXPB_CLG_CFG7 0x0087
#define mmXPB_CLG_CFG7_BASE_IDX 0
#define mmXPB_CLG_EXTRA 0x0088
#define mmXPB_CLG_EXTRA_BASE_IDX 0
#define mmXPB_CLG_EXTRA_MSK 0x0089
#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
#define mmXPB_LB_ADDR 0x008a
#define mmXPB_LB_ADDR_BASE_IDX 0
#define mmXPB_WCB_STS 0x008b
#define mmXPB_WCB_STS_BASE_IDX 0
#define mmXPB_HST_CFG 0x008c
#define mmXPB_HST_CFG_BASE_IDX 0
#define mmXPB_P2P_BAR_CFG 0x008d
#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
#define mmXPB_P2P_BAR0 0x008e
#define mmXPB_P2P_BAR0_BASE_IDX 0
#define mmXPB_P2P_BAR1 0x008f
#define mmXPB_P2P_BAR1_BASE_IDX 0
#define mmXPB_P2P_BAR2 0x0090
#define mmXPB_P2P_BAR2_BASE_IDX 0
#define mmXPB_P2P_BAR3 0x0091
#define mmXPB_P2P_BAR3_BASE_IDX 0
#define mmXPB_P2P_BAR4 0x0092
#define mmXPB_P2P_BAR4_BASE_IDX 0
#define mmXPB_P2P_BAR5 0x0093
#define mmXPB_P2P_BAR5_BASE_IDX 0
#define mmXPB_P2P_BAR6 0x0094
#define mmXPB_P2P_BAR6_BASE_IDX 0
#define mmXPB_P2P_BAR7 0x0095
#define mmXPB_P2P_BAR7_BASE_IDX 0
#define mmXPB_P2P_BAR_SETUP 0x0096
#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0098
#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
#define mmXPB_P2P_BAR_DELTA_BELOW 0x0099
#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR0 0x009a
#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR1 0x009b
#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR2 0x009c
#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR3 0x009d
#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR4 0x009e
#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR5 0x009f
#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR6 0x00a0
#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR7 0x00a1
#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR8 0x00a2
#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR9 0x00a3
#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR0 0x00a4
#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR1 0x00a5
#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR2 0x00a6
#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
#define mmXPB_XDMA_PEER_SYS_BAR3 0x00a7
#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
#define mmXPB_CLK_GAT 0x00a8
#define mmXPB_CLK_GAT_BASE_IDX 0
#define mmXPB_INTF_CFG 0x00a9
#define mmXPB_INTF_CFG_BASE_IDX 0
#define mmXPB_INTF_STS 0x00aa
#define mmXPB_INTF_STS_BASE_IDX 0
#define mmXPB_PIPE_STS 0x00ab
#define mmXPB_PIPE_STS_BASE_IDX 0
#define mmXPB_SUB_CTRL 0x00ac
#define mmXPB_SUB_CTRL_BASE_IDX 0
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00ad
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
#define mmXPB_PERF_KNOBS 0x00ae
#define mmXPB_PERF_KNOBS_BASE_IDX 0
#define mmXPB_STICKY 0x00af
#define mmXPB_STICKY_BASE_IDX 0
#define mmXPB_STICKY_W1C 0x00b0
#define mmXPB_STICKY_W1C_BASE_IDX 0
#define mmXPB_MISC_CFG 0x00b1
#define mmXPB_MISC_CFG_BASE_IDX 0
#define mmXPB_INTF_CFG2 0x00b2
#define mmXPB_INTF_CFG2_BASE_IDX 0
#define mmXPB_CLG_EXTRA_RD 0x00b3
#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
#define mmXPB_CLG_EXTRA_MSK_RD 0x00b4
#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
#define mmXPB_CLG_GFX_MATCH 0x00b5
#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
#define mmXPB_CLG_GFX_MATCH_MSK 0x00b6
#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_MM_MATCH 0x00b7
#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
#define mmXPB_CLG_MM_MATCH_MSK 0x00b8
#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_GUS_MATCH 0x00b9
#define mmXPB_CLG_GUS_MATCH_BASE_IDX 0
#define mmXPB_CLG_GUS_MATCH_MSK 0x00ba
#define mmXPB_CLG_GUS_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00bb
#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00bc
#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00bd
#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00be
#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00bf
#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00c0
#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00c1
#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00c2
#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00c3
#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00c4
#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00c5
#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00c6
#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING0 0x00c7
#define mmXPB_CLG_GUS_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING1 0x00c8
#define mmXPB_CLG_GUS_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING2 0x00c9
#define mmXPB_CLG_GUS_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING3 0x00ca
#define mmXPB_CLG_GUS_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING4 0x00cb
#define mmXPB_CLG_GUS_UNITID_MAPPING4_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING5 0x00cc
#define mmXPB_CLG_GUS_UNITID_MAPPING5_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING6 0x00cd
#define mmXPB_CLG_GUS_UNITID_MAPPING6_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING7 0x00ce
#define mmXPB_CLG_GUS_UNITID_MAPPING7_BASE_IDX 0
// addressBlock: athub_rpbdec
// base address: 0x3350
#define mmRPB_PASSPW_CONF 0x00d4
#define mmRPB_PASSPW_CONF_BASE_IDX 0
#define mmRPB_BLOCKLEVEL_CONF 0x00d5
#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
#define mmRPB_TAG_CONF 0x00d7
#define mmRPB_TAG_CONF_BASE_IDX 0
#define mmRPB_EFF_CNTL 0x00d9
#define mmRPB_EFF_CNTL_BASE_IDX 0
#define mmRPB_ARB_CNTL 0x00da
#define mmRPB_ARB_CNTL_BASE_IDX 0
#define mmRPB_ARB_CNTL2 0x00db
#define mmRPB_ARB_CNTL2_BASE_IDX 0
#define mmRPB_BIF_CNTL 0x00dc
#define mmRPB_BIF_CNTL_BASE_IDX 0
#define mmRPB_WR_SWITCH_CNTL 0x00dd
#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
#define mmRPB_WR_COMBINE_CNTL 0x00de
#define mmRPB_WR_COMBINE_CNTL_BASE_IDX 0
#define mmRPB_RD_SWITCH_CNTL 0x00df
#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
#define mmRPB_CID_QUEUE_WR 0x00e0
#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
#define mmRPB_CID_QUEUE_RD 0x00e1
#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
#define mmRPB_PERF_COUNTER_CNTL 0x00e2
#define mmRPB_PERF_COUNTER_CNTL_BASE_IDX 0
#define mmRPB_PERF_COUNTER_STATUS 0x00e3
#define mmRPB_PERF_COUNTER_STATUS_BASE_IDX 0
#define mmRPB_CID_QUEUE_EX 0x00e4
#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
#define mmRPB_CID_QUEUE_EX_DATA 0x00e5
#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
#define mmRPB_SWITCH_CNTL2 0x00e6
#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00e7
#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
#define mmRPB_VC_SWITCH_RDWR 0x00e8
#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
#define mmRPB_PERFCOUNTER_LO 0x00e9
#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
#define mmRPB_PERFCOUNTER_HI 0x00ea
#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
#define mmRPB_PERFCOUNTER0_CFG 0x00eb
#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER1_CFG 0x00ec
#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER2_CFG 0x00ed
#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER3_CFG 0x00ee
#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00ef
#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmRPB_BIF_CNTL2 0x00f0
#define mmRPB_BIF_CNTL2_BASE_IDX 0
#define mmRPB_RD_QUEUE_CNTL 0x00f1
#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
#define mmRPB_RD_QUEUE_CNTL2 0x00f2
#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
#define mmRPB_WR_QUEUE_CNTL 0x00f3
#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
#define mmRPB_WR_QUEUE_CNTL2 0x00f4
#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
#define mmRPB_EA_QUEUE_WR 0x00f5
#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
#define mmRPB_ATS_CNTL 0x00f6
#define mmRPB_ATS_CNTL_BASE_IDX 0
#define mmRPB_ATS_CNTL2 0x00f7
#define mmRPB_ATS_CNTL2_BASE_IDX 0
#define mmRPB_DF_SDPPORT_CNTL 0x00f8
#define mmRPB_DF_SDPPORT_CNTL_BASE_IDX 0
#define mmRPB_SDPPORT_CNTL 0x00f9
#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
#define mmRPB_NBIF_SDPPORT_CNTL 0x00fa
#define mmRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h
+2264
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_offset.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _athub_2_1_0_OFFSET_HEADER
#define _athub_2_1_0_OFFSET_HEADER
// addressBlock: athub_atsdec
// base address: 0x3000
#define mmATHUB_ATS_MODE_CNTL 0x0000
#define mmATHUB_ATS_MODE_CNTL_BASE_IDX 0
#define mmATHUB_SHARED_VIRT_RESET_REQ 0x0001
#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x0002
#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define mmATC_ATS_CNTL 0x0003
#define mmATC_ATS_CNTL_BASE_IDX 0
#define mmATC_ATS_FAULT_CNTL 0x0006
#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
#define mmATHUB_MISC_CNTL 0x0009
#define mmATHUB_MISC_CNTL_BASE_IDX 0
#define mmATHUB_MEM_POWER_LS 0x000a
#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
#define mmATC_ATS_SDPPORT_CNTL 0x000b
#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
#define mmATC_ATS_CNTL2 0x000d
#define mmATC_ATS_CNTL2_BASE_IDX 0
#define mmATC_ATS_TR_QOS_CNTL 0x000e
#define mmATC_ATS_TR_QOS_CNTL_BASE_IDX 0
#define mmATC_ATS_MISC_CNTL 0x000f
#define mmATC_ATS_MISC_CNTL_BASE_IDX 0
#define mmATC_PERFCOUNTER0_CFG 0x0010
#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER1_CFG 0x0011
#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER2_CFG 0x0012
#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER3_CFG 0x0013
#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0014
#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmATC_PERFCOUNTER_LO 0x0015
#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
#define mmATC_PERFCOUNTER_HI 0x0016
#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
#define mmATS_IH_CREDIT 0x0017
#define mmATS_IH_CREDIT_BASE_IDX 0
#define mmATHUB_IH_CREDIT 0x0018
#define mmATHUB_IH_CREDIT_BASE_IDX 0
#define mmATC_ATS_GFX_ATCL2_STATUS 0x0019
#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x001a
#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO 0x001b
#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_ADDR 0x001c
#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
#define mmATC_ATS_FAULT_STATUS_INFO2 0x001d
#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL 0x001e
#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PASID_CNTL 0x001f
#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0020
#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0021
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
#define mmATHUB_COMMAND 0x0022
#define mmATHUB_COMMAND_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x0023
#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x0024
#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x0025
#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x0026
#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x0027
#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x0028
#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0029
#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x002a
#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x002b
#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x002c
#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x002d
#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x002e
#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x002f
#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0030
#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0031
#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0032
#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_16 0x0033
#define mmATHUB_PCIE_ATS_CNTL_VF_16_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_17 0x0034
#define mmATHUB_PCIE_ATS_CNTL_VF_17_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_18 0x0035
#define mmATHUB_PCIE_ATS_CNTL_VF_18_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_19 0x0036
#define mmATHUB_PCIE_ATS_CNTL_VF_19_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_20 0x0037
#define mmATHUB_PCIE_ATS_CNTL_VF_20_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_21 0x0038
#define mmATHUB_PCIE_ATS_CNTL_VF_21_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_22 0x0039
#define mmATHUB_PCIE_ATS_CNTL_VF_22_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_23 0x003a
#define mmATHUB_PCIE_ATS_CNTL_VF_23_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_24 0x003b
#define mmATHUB_PCIE_ATS_CNTL_VF_24_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_25 0x003c
#define mmATHUB_PCIE_ATS_CNTL_VF_25_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_26 0x003d
#define mmATHUB_PCIE_ATS_CNTL_VF_26_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_27 0x003e
#define mmATHUB_PCIE_ATS_CNTL_VF_27_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_28 0x003f
#define mmATHUB_PCIE_ATS_CNTL_VF_28_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_29 0x0040
#define mmATHUB_PCIE_ATS_CNTL_VF_29_BASE_IDX 0
#define mmATHUB_PCIE_ATS_CNTL_VF_30 0x0041
#define mmATHUB_PCIE_ATS_CNTL_VF_30_BASE_IDX 0
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0042
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
#define mmATC_ATS_VMID_STATUS 0x0043
#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
#define mmATC_ATS_STATUS 0x0044
#define mmATC_ATS_STATUS_BASE_IDX 0
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0045
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0046
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
#define mmATC_VMID0_PASID_MAPPING 0x0047
#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID1_PASID_MAPPING 0x0048
#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID2_PASID_MAPPING 0x0049
#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID3_PASID_MAPPING 0x004a
#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID4_PASID_MAPPING 0x004b
#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID5_PASID_MAPPING 0x004c
#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID6_PASID_MAPPING 0x004d
#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID7_PASID_MAPPING 0x004e
#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID8_PASID_MAPPING 0x004f
#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID9_PASID_MAPPING 0x0050
#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID10_PASID_MAPPING 0x0051
#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID11_PASID_MAPPING 0x0052
#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID12_PASID_MAPPING 0x0053
#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID13_PASID_MAPPING 0x0054
#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID14_PASID_MAPPING 0x0055
#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID15_PASID_MAPPING 0x0056
#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID16_PASID_MAPPING 0x0057
#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID17_PASID_MAPPING 0x0058
#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID18_PASID_MAPPING 0x0059
#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID19_PASID_MAPPING 0x005a
#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID20_PASID_MAPPING 0x005b
#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID21_PASID_MAPPING 0x005c
#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID22_PASID_MAPPING 0x005d
#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID23_PASID_MAPPING 0x005e
#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID24_PASID_MAPPING 0x005f
#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID25_PASID_MAPPING 0x0060
#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID26_PASID_MAPPING 0x0061
#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID27_PASID_MAPPING 0x0062
#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID28_PASID_MAPPING 0x0063
#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID29_PASID_MAPPING 0x0064
#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID30_PASID_MAPPING 0x0065
#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
#define mmATC_VMID31_PASID_MAPPING 0x0066
#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
// addressBlock: athub_xpbdec
// base address: 0x31a0
#define mmXPB_RTR_SRC_APRTR0 0x0068
#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR1 0x0069
#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR2 0x006a
#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR3 0x006b
#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR4 0x006c
#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR5 0x006d
#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR6 0x006e
#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR7 0x006f
#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR8 0x0070
#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR9 0x0071
#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR10 0x0072
#define mmXPB_RTR_SRC_APRTR10_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR11 0x0073
#define mmXPB_RTR_SRC_APRTR11_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR12 0x0074
#define mmXPB_RTR_SRC_APRTR12_BASE_IDX 0
#define mmXPB_RTR_SRC_APRTR13 0x0075
#define mmXPB_RTR_SRC_APRTR13_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP0 0x0076
#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP1 0x0077
#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP2 0x0078
#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP3 0x0079
#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP4 0x007a
#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP5 0x007b
#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP6 0x007c
#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP7 0x007d
#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP8 0x007e
#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP9 0x007f
#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP10 0x0080
#define mmXPB_RTR_DEST_MAP10_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP11 0x0081
#define mmXPB_RTR_DEST_MAP11_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP12 0x0082
#define mmXPB_RTR_DEST_MAP12_BASE_IDX 0
#define mmXPB_RTR_DEST_MAP13 0x0083
#define mmXPB_RTR_DEST_MAP13_BASE_IDX 0
#define mmXPB_CLG_CFG0 0x0084
#define mmXPB_CLG_CFG0_BASE_IDX 0
#define mmXPB_CLG_CFG1 0x0085
#define mmXPB_CLG_CFG1_BASE_IDX 0
#define mmXPB_CLG_CFG2 0x0086
#define mmXPB_CLG_CFG2_BASE_IDX 0
#define mmXPB_CLG_CFG3 0x0087
#define mmXPB_CLG_CFG3_BASE_IDX 0
#define mmXPB_CLG_CFG4 0x0088
#define mmXPB_CLG_CFG4_BASE_IDX 0
#define mmXPB_CLG_CFG5 0x0089
#define mmXPB_CLG_CFG5_BASE_IDX 0
#define mmXPB_CLG_CFG6 0x008a
#define mmXPB_CLG_CFG6_BASE_IDX 0
#define mmXPB_CLG_CFG7 0x008b
#define mmXPB_CLG_CFG7_BASE_IDX 0
#define mmXPB_CLG_EXTRA 0x008c
#define mmXPB_CLG_EXTRA_BASE_IDX 0
#define mmXPB_CLG_EXTRA_MSK 0x008d
#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
#define mmXPB_LB_ADDR 0x008e
#define mmXPB_LB_ADDR_BASE_IDX 0
#define mmXPB_WCB_STS 0x008f
#define mmXPB_WCB_STS_BASE_IDX 0
#define mmXPB_HST_CFG 0x0090
#define mmXPB_HST_CFG_BASE_IDX 0
#define mmXPB_P2P_BAR_CFG 0x0091
#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
#define mmXPB_P2P_BAR0 0x0092
#define mmXPB_P2P_BAR0_BASE_IDX 0
#define mmXPB_P2P_BAR1 0x0093
#define mmXPB_P2P_BAR1_BASE_IDX 0
#define mmXPB_P2P_BAR2 0x0094
#define mmXPB_P2P_BAR2_BASE_IDX 0
#define mmXPB_P2P_BAR3 0x0095
#define mmXPB_P2P_BAR3_BASE_IDX 0
#define mmXPB_P2P_BAR4 0x0096
#define mmXPB_P2P_BAR4_BASE_IDX 0
#define mmXPB_P2P_BAR5 0x0097
#define mmXPB_P2P_BAR5_BASE_IDX 0
#define mmXPB_P2P_BAR6 0x0098
#define mmXPB_P2P_BAR6_BASE_IDX 0
#define mmXPB_P2P_BAR7 0x0099
#define mmXPB_P2P_BAR7_BASE_IDX 0
#define mmXPB_P2P_BAR_SETUP 0x009a
#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
#define mmXPB_P2P_BAR_DELTA_ABOVE 0x009c
#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
#define mmXPB_P2P_BAR_DELTA_BELOW 0x009d
#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR0 0x009e
#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR1 0x009f
#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR2 0x00a0
#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR3 0x00a1
#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR4 0x00a2
#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR5 0x00a3
#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR6 0x00a4
#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR7 0x00a5
#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR8 0x00a6
#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR9 0x00a7
#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR10 0x00a8
#define mmXPB_PEER_SYS_BAR10_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR11 0x00a9
#define mmXPB_PEER_SYS_BAR11_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR12 0x00aa
#define mmXPB_PEER_SYS_BAR12_BASE_IDX 0
#define mmXPB_PEER_SYS_BAR13 0x00ab
#define mmXPB_PEER_SYS_BAR13_BASE_IDX 0
#define mmXPB_CLK_GAT 0x00ac
#define mmXPB_CLK_GAT_BASE_IDX 0
#define mmXPB_INTF_CFG 0x00ad
#define mmXPB_INTF_CFG_BASE_IDX 0
#define mmXPB_INTF_STS 0x00ae
#define mmXPB_INTF_STS_BASE_IDX 0
#define mmXPB_PIPE_STS 0x00af
#define mmXPB_PIPE_STS_BASE_IDX 0
#define mmXPB_SUB_CTRL 0x00b0
#define mmXPB_SUB_CTRL_BASE_IDX 0
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00b1
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
#define mmXPB_PERF_KNOBS 0x00b2
#define mmXPB_PERF_KNOBS_BASE_IDX 0
#define mmXPB_STICKY 0x00b3
#define mmXPB_STICKY_BASE_IDX 0
#define mmXPB_STICKY_W1C 0x00b4
#define mmXPB_STICKY_W1C_BASE_IDX 0
#define mmXPB_MISC_CFG 0x00b5
#define mmXPB_MISC_CFG_BASE_IDX 0
#define mmXPB_INTF_CFG2 0x00b6
#define mmXPB_INTF_CFG2_BASE_IDX 0
#define mmXPB_CLG_EXTRA_RD 0x00b7
#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
#define mmXPB_CLG_EXTRA_MSK_RD 0x00b8
#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
#define mmXPB_CLG_GFX_MATCH 0x00b9
#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
#define mmXPB_CLG_GFX_MATCH_MSK 0x00ba
#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_MM_MATCH 0x00bb
#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
#define mmXPB_CLG_MM_MATCH_MSK 0x00bc
#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_GUS_MATCH 0x00bd
#define mmXPB_CLG_GUS_MATCH_BASE_IDX 0
#define mmXPB_CLG_GUS_MATCH_MSK 0x00be
#define mmXPB_CLG_GUS_MATCH_MSK_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00bf
#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00c0
#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00c1
#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00c2
#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00c3
#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00c4
#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00c5
#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00c6
#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00c7
#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00c8
#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00c9
#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00ca
#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING0 0x00cb
#define mmXPB_CLG_GUS_UNITID_MAPPING0_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING1 0x00cc
#define mmXPB_CLG_GUS_UNITID_MAPPING1_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING2 0x00cd
#define mmXPB_CLG_GUS_UNITID_MAPPING2_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING3 0x00ce
#define mmXPB_CLG_GUS_UNITID_MAPPING3_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING4 0x00cf
#define mmXPB_CLG_GUS_UNITID_MAPPING4_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING5 0x00d0
#define mmXPB_CLG_GUS_UNITID_MAPPING5_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING6 0x00d1
#define mmXPB_CLG_GUS_UNITID_MAPPING6_BASE_IDX 0
#define mmXPB_CLG_GUS_UNITID_MAPPING7 0x00d2
#define mmXPB_CLG_GUS_UNITID_MAPPING7_BASE_IDX 0
// addressBlock: athub_rpbdec
// base address: 0x3350
#define mmRPB_PASSPW_CONF 0x00d4
#define mmRPB_PASSPW_CONF_BASE_IDX 0
#define mmRPB_BLOCKLEVEL_CONF 0x00d5
#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
#define mmRPB_TAG_CONF 0x00d6
#define mmRPB_TAG_CONF_BASE_IDX 0
#define mmRPB_EFF_CNTL 0x00d8
#define mmRPB_EFF_CNTL_BASE_IDX 0
#define mmRPB_ARB_CNTL 0x00d9
#define mmRPB_ARB_CNTL_BASE_IDX 0
#define mmRPB_ARB_CNTL2 0x00da
#define mmRPB_ARB_CNTL2_BASE_IDX 0
#define mmRPB_BIF_CNTL 0x00db
#define mmRPB_BIF_CNTL_BASE_IDX 0
#define mmRPB_BIF_CNTL2 0x00dc
#define mmRPB_BIF_CNTL2_BASE_IDX 0
#define mmRPB_WR_SWITCH_CNTL 0x00dd
#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
#define mmRPB_RD_SWITCH_CNTL 0x00de
#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
#define mmRPB_SWITCH_CNTL2 0x00df
#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
#define mmRPB_CID_QUEUE_WR 0x00e0
#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
#define mmRPB_EA_QUEUE_WR 0x00e1
#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
#define mmRPB_CID_QUEUE_RD 0x00e2
#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
#define mmRPB_CID_QUEUE_EX 0x00e3
#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
#define mmRPB_CID_QUEUE_EX_DATA 0x00e4
#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00e5
#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
#define mmRPB_VC_SWITCH_RDWR 0x00e6
#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
#define mmRPB_PERF_COUNTER_CNTL 0x00e7
#define mmRPB_PERF_COUNTER_CNTL_BASE_IDX 0
#define mmRPB_PERF_COUNTER_STATUS 0x00e8
#define mmRPB_PERF_COUNTER_STATUS_BASE_IDX 0
#define mmRPB_PERFCOUNTER_LO 0x00e9
#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
#define mmRPB_PERFCOUNTER_HI 0x00ea
#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
#define mmRPB_PERFCOUNTER0_CFG 0x00eb
#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER1_CFG 0x00ec
#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER2_CFG 0x00ed
#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER3_CFG 0x00ee
#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00ef
#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define mmRPB_RD_QUEUE_CNTL 0x00f0
#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
#define mmRPB_RD_QUEUE_CNTL2 0x00f1
#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
#define mmRPB_WR_QUEUE_CNTL 0x00f2
#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
#define mmRPB_WR_QUEUE_CNTL2 0x00f3
#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
#define mmRPB_ATS_CNTL 0x00f4
#define mmRPB_ATS_CNTL_BASE_IDX 0
#define mmRPB_ATS_CNTL2 0x00f5
#define mmRPB_ATS_CNTL2_BASE_IDX 0
#define mmRPB_ATS_CNTL3 0x00f6
#define mmRPB_ATS_CNTL3_BASE_IDX 0
#define mmRPB_DF_SDPPORT_CNTL 0x00f7
#define mmRPB_DF_SDPPORT_CNTL_BASE_IDX 0
#define mmRPB_SDPPORT_CNTL 0x00f8
#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
#define mmRPB_NBIF_SDPPORT_CNTL 0x00f9
#define mmRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h
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/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _athub_3_0_0_OFFSET_HEADER
#define _athub_3_0_0_OFFSET_HEADER
// addressBlock: athub_xpbdec
// base address: 0x3000
#define regXPB_RTR_SRC_APRTR0 0x0000
#define regXPB_RTR_SRC_APRTR0_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR1 0x0001
#define regXPB_RTR_SRC_APRTR1_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR2 0x0002
#define regXPB_RTR_SRC_APRTR2_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR3 0x0003
#define regXPB_RTR_SRC_APRTR3_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR4 0x0004
#define regXPB_RTR_SRC_APRTR4_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR5 0x0005
#define regXPB_RTR_SRC_APRTR5_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR6 0x0006
#define regXPB_RTR_SRC_APRTR6_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR7 0x0007
#define regXPB_RTR_SRC_APRTR7_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR8 0x0008
#define regXPB_RTR_SRC_APRTR8_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR9 0x0009
#define regXPB_RTR_SRC_APRTR9_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR10 0x000a
#define regXPB_RTR_SRC_APRTR10_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR11 0x000b
#define regXPB_RTR_SRC_APRTR11_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR12 0x000c
#define regXPB_RTR_SRC_APRTR12_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR13 0x000d
#define regXPB_RTR_SRC_APRTR13_BASE_IDX 0
#define regXPB_RTR_DEST_MAP0 0x000e
#define regXPB_RTR_DEST_MAP0_BASE_IDX 0
#define regXPB_RTR_DEST_MAP1 0x000f
#define regXPB_RTR_DEST_MAP1_BASE_IDX 0
#define regXPB_RTR_DEST_MAP2 0x0010
#define regXPB_RTR_DEST_MAP2_BASE_IDX 0
#define regXPB_RTR_DEST_MAP3 0x0011
#define regXPB_RTR_DEST_MAP3_BASE_IDX 0
#define regXPB_RTR_DEST_MAP4 0x0012
#define regXPB_RTR_DEST_MAP4_BASE_IDX 0
#define regXPB_RTR_DEST_MAP5 0x0013
#define regXPB_RTR_DEST_MAP5_BASE_IDX 0
#define regXPB_RTR_DEST_MAP6 0x0014
#define regXPB_RTR_DEST_MAP6_BASE_IDX 0
#define regXPB_RTR_DEST_MAP7 0x0015
#define regXPB_RTR_DEST_MAP7_BASE_IDX 0
#define regXPB_RTR_DEST_MAP8 0x0016
#define regXPB_RTR_DEST_MAP8_BASE_IDX 0
#define regXPB_RTR_DEST_MAP9 0x0017
#define regXPB_RTR_DEST_MAP9_BASE_IDX 0
#define regXPB_RTR_DEST_MAP10 0x0018
#define regXPB_RTR_DEST_MAP10_BASE_IDX 0
#define regXPB_RTR_DEST_MAP11 0x0019
#define regXPB_RTR_DEST_MAP11_BASE_IDX 0
#define regXPB_RTR_DEST_MAP12 0x001a
#define regXPB_RTR_DEST_MAP12_BASE_IDX 0
#define regXPB_RTR_DEST_MAP13 0x001b
#define regXPB_RTR_DEST_MAP13_BASE_IDX 0
#define regXPB_CLG_CFG0 0x001c
#define regXPB_CLG_CFG0_BASE_IDX 0
#define regXPB_CLG_CFG1 0x001d
#define regXPB_CLG_CFG1_BASE_IDX 0
#define regXPB_CLG_CFG2 0x001e
#define regXPB_CLG_CFG2_BASE_IDX 0
#define regXPB_CLG_CFG3 0x001f
#define regXPB_CLG_CFG3_BASE_IDX 0
#define regXPB_CLG_CFG4 0x0020
#define regXPB_CLG_CFG4_BASE_IDX 0
#define regXPB_CLG_CFG5 0x0021
#define regXPB_CLG_CFG5_BASE_IDX 0
#define regXPB_CLG_CFG6 0x0022
#define regXPB_CLG_CFG6_BASE_IDX 0
#define regXPB_CLG_CFG7 0x0023
#define regXPB_CLG_CFG7_BASE_IDX 0
#define regXPB_CLG_EXTRA 0x0024
#define regXPB_CLG_EXTRA_BASE_IDX 0
#define regXPB_CLG_EXTRA_MSK 0x0025
#define regXPB_CLG_EXTRA_MSK_BASE_IDX 0
#define regXPB_LB_ADDR 0x0026
#define regXPB_LB_ADDR_BASE_IDX 0
#define regXPB_WCB_STS 0x0027
#define regXPB_WCB_STS_BASE_IDX 0
#define regXPB_HST_CFG 0x0028
#define regXPB_HST_CFG_BASE_IDX 0
#define regXPB_P2P_BAR_CFG 0x0029
#define regXPB_P2P_BAR_CFG_BASE_IDX 0
#define regXPB_P2P_BAR0 0x002a
#define regXPB_P2P_BAR0_BASE_IDX 0
#define regXPB_P2P_BAR1 0x002b
#define regXPB_P2P_BAR1_BASE_IDX 0
#define regXPB_P2P_BAR2 0x002c
#define regXPB_P2P_BAR2_BASE_IDX 0
#define regXPB_P2P_BAR3 0x002d
#define regXPB_P2P_BAR3_BASE_IDX 0
#define regXPB_P2P_BAR4 0x002e
#define regXPB_P2P_BAR4_BASE_IDX 0
#define regXPB_P2P_BAR5 0x002f
#define regXPB_P2P_BAR5_BASE_IDX 0
#define regXPB_P2P_BAR6 0x0030
#define regXPB_P2P_BAR6_BASE_IDX 0
#define regXPB_P2P_BAR7 0x0031
#define regXPB_P2P_BAR7_BASE_IDX 0
#define regXPB_P2P_BAR_SETUP 0x0032
#define regXPB_P2P_BAR_SETUP_BASE_IDX 0
#define regXPB_P2P_BAR_DELTA_ABOVE 0x0034
#define regXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
#define regXPB_P2P_BAR_DELTA_BELOW 0x0035
#define regXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
#define regXPB_PEER_SYS_BAR0 0x0036
#define regXPB_PEER_SYS_BAR0_BASE_IDX 0
#define regXPB_PEER_SYS_BAR1 0x0037
#define regXPB_PEER_SYS_BAR1_BASE_IDX 0
#define regXPB_PEER_SYS_BAR2 0x0038
#define regXPB_PEER_SYS_BAR2_BASE_IDX 0
#define regXPB_PEER_SYS_BAR3 0x0039
#define regXPB_PEER_SYS_BAR3_BASE_IDX 0
#define regXPB_PEER_SYS_BAR4 0x003a
#define regXPB_PEER_SYS_BAR4_BASE_IDX 0
#define regXPB_PEER_SYS_BAR5 0x003b
#define regXPB_PEER_SYS_BAR5_BASE_IDX 0
#define regXPB_PEER_SYS_BAR6 0x003c
#define regXPB_PEER_SYS_BAR6_BASE_IDX 0
#define regXPB_PEER_SYS_BAR7 0x003d
#define regXPB_PEER_SYS_BAR7_BASE_IDX 0
#define regXPB_PEER_SYS_BAR8 0x003e
#define regXPB_PEER_SYS_BAR8_BASE_IDX 0
#define regXPB_PEER_SYS_BAR9 0x003f
#define regXPB_PEER_SYS_BAR9_BASE_IDX 0
#define regXPB_PEER_SYS_BAR10 0x0040
#define regXPB_PEER_SYS_BAR10_BASE_IDX 0
#define regXPB_PEER_SYS_BAR11 0x0041
#define regXPB_PEER_SYS_BAR11_BASE_IDX 0
#define regXPB_PEER_SYS_BAR12 0x0042
#define regXPB_PEER_SYS_BAR12_BASE_IDX 0
#define regXPB_PEER_SYS_BAR13 0x0043
#define regXPB_PEER_SYS_BAR13_BASE_IDX 0
#define regXPB_CLK_GAT 0x0044
#define regXPB_CLK_GAT_BASE_IDX 0
#define regXPB_INTF_CFG 0x0045
#define regXPB_INTF_CFG_BASE_IDX 0
#define regXPB_INTF_STS 0x0046
#define regXPB_INTF_STS_BASE_IDX 0
#define regXPB_PIPE_STS 0x0047
#define regXPB_PIPE_STS_BASE_IDX 0
#define regXPB_SUB_CTRL 0x0048
#define regXPB_SUB_CTRL_BASE_IDX 0
#define regXPB_MAP_INVERT_FLUSH_NUM_LSB 0x0049
#define regXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
#define regXPB_PERF_KNOBS 0x004a
#define regXPB_PERF_KNOBS_BASE_IDX 0
#define regXPB_STICKY 0x004b
#define regXPB_STICKY_BASE_IDX 0
#define regXPB_STICKY_W1C 0x004c
#define regXPB_STICKY_W1C_BASE_IDX 0
#define regXPB_MISC_CFG 0x004d
#define regXPB_MISC_CFG_BASE_IDX 0
#define regXPB_INTF_CFG2 0x004e
#define regXPB_INTF_CFG2_BASE_IDX 0
#define regXPB_CLG_EXTRA_RD 0x004f
#define regXPB_CLG_EXTRA_RD_BASE_IDX 0
#define regXPB_CLG_EXTRA_MSK_RD 0x0050
#define regXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
#define regXPB_CLG_GFX_MATCH 0x0051
#define regXPB_CLG_GFX_MATCH_BASE_IDX 0
#define regXPB_CLG_GFX_MATCH_MSK 0x0052
#define regXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
#define regXPB_CLG_MM_MATCH 0x0053
#define regXPB_CLG_MM_MATCH_BASE_IDX 0
#define regXPB_CLG_MM_MATCH_MSK 0x0054
#define regXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
#define regXPB_CLG_GUS_MATCH 0x0055
#define regXPB_CLG_GUS_MATCH_BASE_IDX 0
#define regXPB_CLG_GUS_MATCH_MSK 0x0056
#define regXPB_CLG_GUS_MATCH_MSK_BASE_IDX 0
// addressBlock: athub_rpbdec
// base address: 0x31b0
#define regRPB_PASSPW_CONF 0x006c
#define regRPB_PASSPW_CONF_BASE_IDX 0
#define regRPB_BLOCKLEVEL_CONF 0x006d
#define regRPB_BLOCKLEVEL_CONF_BASE_IDX 0
#define regRPB_TAG_CONF 0x006e
#define regRPB_TAG_CONF_BASE_IDX 0
#define regRPB_ARB_CNTL 0x0071
#define regRPB_ARB_CNTL_BASE_IDX 0
#define regRPB_ARB_CNTL2 0x0072
#define regRPB_ARB_CNTL2_BASE_IDX 0
#define regRPB_BIF_CNTL 0x0073
#define regRPB_BIF_CNTL_BASE_IDX 0
#define regRPB_BIF_CNTL2 0x0074
#define regRPB_BIF_CNTL2_BASE_IDX 0
#define regATHUB_MISC_CNTL 0x0075
#define regATHUB_MISC_CNTL_BASE_IDX 0
#define regATHUB_MEM_POWER_LS 0x0078
#define regATHUB_MEM_POWER_LS_BASE_IDX 0
#define regRPB_SDPPORT_CNTL 0x007a
#define regRPB_SDPPORT_CNTL_BASE_IDX 0
#define regRPB_NBIF_SDPPORT_CNTL 0x007b
#define regRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0
#define regRPB_DEINTRLV_COMBINE_CNTL 0x007c
#define regRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
#define regRPB_VC_SWITCH_RDWR 0x007d
#define regRPB_VC_SWITCH_RDWR_BASE_IDX 0
#define regRPB_PERF_COUNTER_CNTL 0x007e
#define regRPB_PERF_COUNTER_CNTL_BASE_IDX 0
#define regRPB_PERF_COUNTER_STATUS 0x007f
#define regRPB_PERF_COUNTER_STATUS_BASE_IDX 0
#define regRPB_PERFCOUNTER_LO 0x0080
#define regRPB_PERFCOUNTER_LO_BASE_IDX 0
#define regRPB_PERFCOUNTER_HI 0x0081
#define regRPB_PERFCOUNTER_HI_BASE_IDX 0
#define regRPB_PERFCOUNTER0_CFG 0x0082
#define regRPB_PERFCOUNTER0_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER1_CFG 0x0083
#define regRPB_PERFCOUNTER1_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER2_CFG 0x0084
#define regRPB_PERFCOUNTER2_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER3_CFG 0x0085
#define regRPB_PERFCOUNTER3_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER_RSLT_CNTL 0x0086
#define regRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regRPB_ATS_CNTL3 0x0087
#define regRPB_ATS_CNTL3_BASE_IDX 0
#define regRPB_DF_SDPPORT_CNTL 0x0088
#define regRPB_DF_SDPPORT_CNTL_BASE_IDX 0
#define regRPB_ATS_CNTL 0x0089
#define regRPB_ATS_CNTL_BASE_IDX 0
#define regRPB_ATS_CNTL2 0x008a
#define regRPB_ATS_CNTL2_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_4_1_0_offset.h
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/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _athub_4_1_0_OFFSET_HEADER
#define _athub_4_1_0_OFFSET_HEADER
// addressBlock: athub_xpbdec
// base address: 0x3000
#define regXPB_RTR_SRC_APRTR0 0x0000
#define regXPB_RTR_SRC_APRTR0_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR1 0x0001
#define regXPB_RTR_SRC_APRTR1_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR2 0x0002
#define regXPB_RTR_SRC_APRTR2_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR3 0x0003
#define regXPB_RTR_SRC_APRTR3_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR4 0x0004
#define regXPB_RTR_SRC_APRTR4_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR5 0x0005
#define regXPB_RTR_SRC_APRTR5_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR6 0x0006
#define regXPB_RTR_SRC_APRTR6_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR7 0x0007
#define regXPB_RTR_SRC_APRTR7_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR8 0x0008
#define regXPB_RTR_SRC_APRTR8_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR9 0x0009
#define regXPB_RTR_SRC_APRTR9_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR10 0x000a
#define regXPB_RTR_SRC_APRTR10_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR11 0x000b
#define regXPB_RTR_SRC_APRTR11_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR12 0x000c
#define regXPB_RTR_SRC_APRTR12_BASE_IDX 0
#define regXPB_RTR_SRC_APRTR13 0x000d
#define regXPB_RTR_SRC_APRTR13_BASE_IDX 0
#define regXPB_RTR_DEST_MAP0 0x000e
#define regXPB_RTR_DEST_MAP0_BASE_IDX 0
#define regXPB_RTR_DEST_MAP1 0x000f
#define regXPB_RTR_DEST_MAP1_BASE_IDX 0
#define regXPB_RTR_DEST_MAP2 0x0010
#define regXPB_RTR_DEST_MAP2_BASE_IDX 0
#define regXPB_RTR_DEST_MAP3 0x0011
#define regXPB_RTR_DEST_MAP3_BASE_IDX 0
#define regXPB_RTR_DEST_MAP4 0x0012
#define regXPB_RTR_DEST_MAP4_BASE_IDX 0
#define regXPB_RTR_DEST_MAP5 0x0013
#define regXPB_RTR_DEST_MAP5_BASE_IDX 0
#define regXPB_RTR_DEST_MAP6 0x0014
#define regXPB_RTR_DEST_MAP6_BASE_IDX 0
#define regXPB_RTR_DEST_MAP7 0x0015
#define regXPB_RTR_DEST_MAP7_BASE_IDX 0
#define regXPB_RTR_DEST_MAP8 0x0016
#define regXPB_RTR_DEST_MAP8_BASE_IDX 0
#define regXPB_RTR_DEST_MAP9 0x0017
#define regXPB_RTR_DEST_MAP9_BASE_IDX 0
#define regXPB_RTR_DEST_MAP10 0x0018
#define regXPB_RTR_DEST_MAP10_BASE_IDX 0
#define regXPB_RTR_DEST_MAP11 0x0019
#define regXPB_RTR_DEST_MAP11_BASE_IDX 0
#define regXPB_RTR_DEST_MAP12 0x001a
#define regXPB_RTR_DEST_MAP12_BASE_IDX 0
#define regXPB_RTR_DEST_MAP13 0x001b
#define regXPB_RTR_DEST_MAP13_BASE_IDX 0
#define regXPB_CLG_CFG0 0x001c
#define regXPB_CLG_CFG0_BASE_IDX 0
#define regXPB_CLG_CFG1 0x001d
#define regXPB_CLG_CFG1_BASE_IDX 0
#define regXPB_CLG_CFG2 0x001e
#define regXPB_CLG_CFG2_BASE_IDX 0
#define regXPB_CLG_CFG3 0x001f
#define regXPB_CLG_CFG3_BASE_IDX 0
#define regXPB_CLG_CFG4 0x0020
#define regXPB_CLG_CFG4_BASE_IDX 0
#define regXPB_CLG_CFG5 0x0021
#define regXPB_CLG_CFG5_BASE_IDX 0
#define regXPB_CLG_CFG6 0x0022
#define regXPB_CLG_CFG6_BASE_IDX 0
#define regXPB_CLG_CFG7 0x0023
#define regXPB_CLG_CFG7_BASE_IDX 0
#define regXPB_CLG_EXTRA0 0x0024
#define regXPB_CLG_EXTRA0_BASE_IDX 0
#define regXPB_CLG_EXTRA1 0x0025
#define regXPB_CLG_EXTRA1_BASE_IDX 0
#define regXPB_CLG_EXTRA_MSK 0x0026
#define regXPB_CLG_EXTRA_MSK_BASE_IDX 0
#define regXPB_LB_ADDR 0x0027
#define regXPB_LB_ADDR_BASE_IDX 0
#define regXPB_HST_CFG 0x0028
#define regXPB_HST_CFG_BASE_IDX 0
#define regXPB_P2P_BAR_CFG 0x0029
#define regXPB_P2P_BAR_CFG_BASE_IDX 0
#define regXPB_P2P_BAR0 0x002a
#define regXPB_P2P_BAR0_BASE_IDX 0
#define regXPB_P2P_BAR1 0x002b
#define regXPB_P2P_BAR1_BASE_IDX 0
#define regXPB_P2P_BAR2 0x002c
#define regXPB_P2P_BAR2_BASE_IDX 0
#define regXPB_P2P_BAR3 0x002d
#define regXPB_P2P_BAR3_BASE_IDX 0
#define regXPB_P2P_BAR4 0x002e
#define regXPB_P2P_BAR4_BASE_IDX 0
#define regXPB_P2P_BAR5 0x002f
#define regXPB_P2P_BAR5_BASE_IDX 0
#define regXPB_P2P_BAR6 0x0030
#define regXPB_P2P_BAR6_BASE_IDX 0
#define regXPB_P2P_BAR7 0x0031
#define regXPB_P2P_BAR7_BASE_IDX 0
#define regXPB_P2P_BAR_SETUP 0x0032
#define regXPB_P2P_BAR_SETUP_BASE_IDX 0
#define regXPB_P2P_BAR_DELTA_ABOVE 0x0034
#define regXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
#define regXPB_P2P_BAR_DELTA_BELOW 0x0035
#define regXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
#define regXPB_PEER_SYS_BAR0 0x0036
#define regXPB_PEER_SYS_BAR0_BASE_IDX 0
#define regXPB_PEER_SYS_BAR1 0x0037
#define regXPB_PEER_SYS_BAR1_BASE_IDX 0
#define regXPB_PEER_SYS_BAR2 0x0038
#define regXPB_PEER_SYS_BAR2_BASE_IDX 0
#define regXPB_PEER_SYS_BAR3 0x0039
#define regXPB_PEER_SYS_BAR3_BASE_IDX 0
#define regXPB_PEER_SYS_BAR4 0x003a
#define regXPB_PEER_SYS_BAR4_BASE_IDX 0
#define regXPB_PEER_SYS_BAR5 0x003b
#define regXPB_PEER_SYS_BAR5_BASE_IDX 0
#define regXPB_PEER_SYS_BAR6 0x003c
#define regXPB_PEER_SYS_BAR6_BASE_IDX 0
#define regXPB_PEER_SYS_BAR7 0x003d
#define regXPB_PEER_SYS_BAR7_BASE_IDX 0
#define regXPB_PEER_SYS_BAR8 0x003e
#define regXPB_PEER_SYS_BAR8_BASE_IDX 0
#define regXPB_PEER_SYS_BAR9 0x003f
#define regXPB_PEER_SYS_BAR9_BASE_IDX 0
#define regXPB_PEER_SYS_BAR10 0x0040
#define regXPB_PEER_SYS_BAR10_BASE_IDX 0
#define regXPB_PEER_SYS_BAR11 0x0041
#define regXPB_PEER_SYS_BAR11_BASE_IDX 0
#define regXPB_PEER_SYS_BAR12 0x0042
#define regXPB_PEER_SYS_BAR12_BASE_IDX 0
#define regXPB_PEER_SYS_BAR13 0x0043
#define regXPB_PEER_SYS_BAR13_BASE_IDX 0
#define regXPB_CLK_GAT 0x0044
#define regXPB_CLK_GAT_BASE_IDX 0
#define regXPB_INTF_CFG 0x0045
#define regXPB_INTF_CFG_BASE_IDX 0
#define regXPB_INTF_STS 0x0046
#define regXPB_INTF_STS_BASE_IDX 0
#define regXPB_PIPE_STS 0x0047
#define regXPB_PIPE_STS_BASE_IDX 0
#define regXPB_WCB_STS 0x0048
#define regXPB_WCB_STS_BASE_IDX 0
#define regXPB_MAP_INVERT_FLUSH_NUM_LSB 0x0049
#define regXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
#define regXPB_STICKY 0x004a
#define regXPB_STICKY_BASE_IDX 0
#define regXPB_STICKY_W1C 0x004b
#define regXPB_STICKY_W1C_BASE_IDX 0
#define regXPB_SUB_CTRL 0x004c
#define regXPB_SUB_CTRL_BASE_IDX 0
#define regXPB_PERF_KNOBS 0x004d
#define regXPB_PERF_KNOBS_BASE_IDX 0
#define regXPB_MISC_CFG 0x004e
#define regXPB_MISC_CFG_BASE_IDX 0
#define regXPB_INTF_CFG2 0x004f
#define regXPB_INTF_CFG2_BASE_IDX 0
#define regXPB_CLG_EXTRA_RD 0x0050
#define regXPB_CLG_EXTRA_RD_BASE_IDX 0
#define regXPB_CLG_EXTRA_MSK_RD 0x0051
#define regXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
#define regXPB_CLG_GFX_MATCH 0x0052
#define regXPB_CLG_GFX_MATCH_BASE_IDX 0
#define regXPB_CLG_GFX_MATCH_VLD 0x0053
#define regXPB_CLG_GFX_MATCH_VLD_BASE_IDX 0
#define regXPB_CLG_GFX_MATCH_MSK 0x0054
#define regXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
#define regXPB_CLG_MM_MATCH 0x0055
#define regXPB_CLG_MM_MATCH_BASE_IDX 0
#define regXPB_CLG_MM_MATCH_VLD 0x0056
#define regXPB_CLG_MM_MATCH_VLD_BASE_IDX 0
#define regXPB_CLG_MM_MATCH_MSK 0x0057
#define regXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING0 0x005a
#define regXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING1 0x005b
#define regXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING2 0x005c
#define regXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING3 0x005d
#define regXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING4 0x005e
#define regXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING5 0x005f
#define regXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING6 0x0060
#define regXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
#define regXPB_CLG_GFX_UNITID_MAPPING7 0x0061
#define regXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
#define regXPB_CLG_MM_UNITID_MAPPING0 0x0062
#define regXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
#define regXPB_CLG_MM_UNITID_MAPPING1 0x0063
#define regXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
#define regXPB_CLG_MM_UNITID_MAPPING2 0x0064
#define regXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
#define regXPB_CLG_MM_UNITID_MAPPING3 0x0065
#define regXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
// addressBlock: athub_rpbdec
// base address: 0x31d0
#define regATHUB_SHARED_VIRT_RESET_REQ 0x0074
#define regATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define regATHUB_MEM_POWER_LS 0x007f
#define regATHUB_MEM_POWER_LS_BASE_IDX 0
#define regATHUB_MISC_CNTL 0x0080
#define regATHUB_MISC_CNTL_BASE_IDX 0
#define regRPB_PASSPW_CONF 0x0081
#define regRPB_PASSPW_CONF_BASE_IDX 0
#define regRPB_BLOCKLEVEL_CONF 0x0082
#define regRPB_BLOCKLEVEL_CONF_BASE_IDX 0
#define regRPB_TAG_CONF 0x0083
#define regRPB_TAG_CONF_BASE_IDX 0
#define regRPB_ARB_CNTL 0x0085
#define regRPB_ARB_CNTL_BASE_IDX 0
#define regRPB_ARB_CNTL2 0x0086
#define regRPB_ARB_CNTL2_BASE_IDX 0
#define regRPB_BIF_CNTL 0x0087
#define regRPB_BIF_CNTL_BASE_IDX 0
#define regRPB_BIF_CNTL2 0x0088
#define regRPB_BIF_CNTL2_BASE_IDX 0
#define regRPB_SDPPORT_CNTL 0x0089
#define regRPB_SDPPORT_CNTL_BASE_IDX 0
#define regRPB_NBIF_SDPPORT_CNTL 0x008a
#define regRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0
#define regRPB_DEINTRLV_COMBINE_CNTL 0x008c
#define regRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
#define regRPB_VC_SWITCH_RDWR 0x008d
#define regRPB_VC_SWITCH_RDWR_BASE_IDX 0
#define regRPB_ATS_CNTL3 0x008e
#define regRPB_ATS_CNTL3_BASE_IDX 0
#define regRPB_DF_SDPPORT_CNTL 0x008f
#define regRPB_DF_SDPPORT_CNTL_BASE_IDX 0
#define regRPB_ATS_CNTL 0x0090
#define regRPB_ATS_CNTL_BASE_IDX 0
#define regRPB_ATS_CNTL2 0x0091
#define regRPB_ATS_CNTL2_BASE_IDX 0
#define regRPB_PERFCOUNTER0_CFG 0x0092
#define regRPB_PERFCOUNTER0_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER1_CFG 0x0093
#define regRPB_PERFCOUNTER1_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER2_CFG 0x0094
#define regRPB_PERFCOUNTER2_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER3_CFG 0x0095
#define regRPB_PERFCOUNTER3_CFG_BASE_IDX 0
#define regRPB_PERFCOUNTER_RSLT_CNTL 0x0096
#define regRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regRPB_PERF_COUNTER_CNTL 0x0097
#define regRPB_PERF_COUNTER_CNTL_BASE_IDX 0
#define regRPB_PERFCOUNTER_HI 0x0098
#define regRPB_PERFCOUNTER_HI_BASE_IDX 0
#define regRPB_PERFCOUNTER_LO 0x0099
#define regRPB_PERFCOUNTER_LO_BASE_IDX 0
#define regRPB_PERF_COUNTER_STATUS 0x009a
#define regRPB_PERF_COUNTER_STATUS_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/athub/athub_4_1_0_sh_mask.h
+1348
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h
+661
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@@ -0,0 +1,661 @@
/*
*
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BIF_3_0_D_H
#define BIF_3_0_D_H
#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C
#define ixPB0_DFT_JIT_INJ_REG0 0x13000
#define ixPB0_DFT_JIT_INJ_REG1 0x13004
#define ixPB0_DFT_JIT_INJ_REG2 0x13008
#define ixPB0_GLB_CTRL_REG0 0x10004
#define ixPB0_GLB_CTRL_REG1 0x10008
#define ixPB0_GLB_CTRL_REG2 0x1000C
#define ixPB0_GLB_CTRL_REG3 0x10010
#define ixPB0_GLB_CTRL_REG4 0x10014
#define ixPB0_GLB_CTRL_REG5 0x10018
#define ixPB0_GLB_OVRD_REG0 0x10030
#define ixPB0_GLB_OVRD_REG1 0x10034
#define ixPB0_GLB_OVRD_REG2 0x10038
#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C
#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020
#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024
#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028
#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C
#define ixPB0_HW_DEBUG 0x12004
#define ixPB0_PIF_CNTL 0x0010
#define ixPB0_PIF_CNTL2 0x0014
#define ixPB0_PIF_HW_DEBUG 0x0002
#define ixPB0_PIF_PAIRING 0x0011
#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020
#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032
#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021
#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033
#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034
#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035
#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036
#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037
#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022
#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023
#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024
#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025
#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026
#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027
#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030
#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031
#define ixPB0_PIF_PWRDOWN_0 0x0012
#define ixPB0_PIF_PWRDOWN_1 0x0013
#define ixPB0_PIF_PWRDOWN_2 0x0017
#define ixPB0_PIF_PWRDOWN_3 0x0018
#define ixPB0_PIF_SC_CTL 0x0016
#define ixPB0_PIF_SCRATCH 0x0001
#define ixPB0_PIF_SEQ_STATUS_0 0x0028
#define ixPB0_PIF_SEQ_STATUS_10 0x003A
#define ixPB0_PIF_SEQ_STATUS_1 0x0029
#define ixPB0_PIF_SEQ_STATUS_11 0x003B
#define ixPB0_PIF_SEQ_STATUS_12 0x003C
#define ixPB0_PIF_SEQ_STATUS_13 0x003D
#define ixPB0_PIF_SEQ_STATUS_14 0x003E
#define ixPB0_PIF_SEQ_STATUS_15 0x003F
#define ixPB0_PIF_SEQ_STATUS_2 0x002A
#define ixPB0_PIF_SEQ_STATUS_3 0x002B
#define ixPB0_PIF_SEQ_STATUS_4 0x002C
#define ixPB0_PIF_SEQ_STATUS_5 0x002D
#define ixPB0_PIF_SEQ_STATUS_6 0x002E
#define ixPB0_PIF_SEQ_STATUS_7 0x002F
#define ixPB0_PIF_SEQ_STATUS_8 0x0038
#define ixPB0_PIF_SEQ_STATUS_9 0x0039
#define ixPB0_PIF_TXPHYSTATUS 0x0015
#define ixPB0_PLL_LC0_CTRL_REG0 0x14480
#define ixPB0_PLL_LC0_OVRD_REG0 0x14490
#define ixPB0_PLL_LC0_OVRD_REG1 0x14494
#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
#define ixPB0_PLL_RO0_CTRL_REG0 0x14440
#define ixPB0_PLL_RO0_OVRD_REG0 0x14450
#define ixPB0_PLL_RO0_OVRD_REG1 0x14454
#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000
#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010
#define ixPB0_RX_GLB_CTRL_REG0 0x16000
#define ixPB0_RX_GLB_CTRL_REG1 0x16004
#define ixPB0_RX_GLB_CTRL_REG2 0x16008
#define ixPB0_RX_GLB_CTRL_REG3 0x1600C
#define ixPB0_RX_GLB_CTRL_REG4 0x16010
#define ixPB0_RX_GLB_CTRL_REG5 0x16014
#define ixPB0_RX_GLB_CTRL_REG6 0x16018
#define ixPB0_RX_GLB_CTRL_REG7 0x1601C
#define ixPB0_RX_GLB_CTRL_REG8 0x16020
#define ixPB0_RX_GLB_OVRD_REG0 0x16030
#define ixPB0_RX_GLB_OVRD_REG1 0x16034
#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028
#define ixPB0_RX_LANE0_CTRL_REG0 0x16440
#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448
#define ixPB0_RX_LANE10_CTRL_REG0 0x17500
#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508
#define ixPB0_RX_LANE11_CTRL_REG0 0x17600
#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608
#define ixPB0_RX_LANE12_CTRL_REG0 0x17840
#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848
#define ixPB0_RX_LANE13_CTRL_REG0 0x17880
#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888
#define ixPB0_RX_LANE14_CTRL_REG0 0x17900
#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908
#define ixPB0_RX_LANE15_CTRL_REG0 0x17A00
#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08
#define ixPB0_RX_LANE1_CTRL_REG0 0x16480
#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488
#define ixPB0_RX_LANE2_CTRL_REG0 0x16500
#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508
#define ixPB0_RX_LANE3_CTRL_REG0 0x16600
#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608
#define ixPB0_RX_LANE4_CTRL_REG0 0x16800
#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848
#define ixPB0_RX_LANE5_CTRL_REG0 0x16880
#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888
#define ixPB0_RX_LANE6_CTRL_REG0 0x16900
#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908
#define ixPB0_RX_LANE7_CTRL_REG0 0x16A00
#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08
#define ixPB0_RX_LANE8_CTRL_REG0 0x17440
#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448
#define ixPB0_RX_LANE9_CTRL_REG0 0x17480
#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488
#define ixPB0_STRAP_GLB_REG0 0x12020
#define ixPB0_STRAP_PLL_REG0 0x12030
#define ixPB0_STRAP_RX_REG0 0x12028
#define ixPB0_STRAP_RX_REG1 0x1202C
#define ixPB0_STRAP_TX_REG0 0x12024
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020
#define ixPB0_TX_GLB_CTRL_REG0 0x18000
#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004
#define ixPB0_TX_GLB_OVRD_REG0 0x18030
#define ixPB0_TX_GLB_OVRD_REG1 0x18034
#define ixPB0_TX_GLB_OVRD_REG2 0x18038
#define ixPB0_TX_GLB_OVRD_REG3 0x1803C
#define ixPB0_TX_GLB_OVRD_REG4 0x18040
#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010
#define ixPB0_TX_LANE0_CTRL_REG0 0x18440
#define ixPB0_TX_LANE0_OVRD_REG0 0x18444
#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448
#define ixPB0_TX_LANE10_CTRL_REG0 0x19500
#define ixPB0_TX_LANE10_OVRD_REG0 0x19504
#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508
#define ixPB0_TX_LANE11_CTRL_REG0 0x19600
#define ixPB0_TX_LANE11_OVRD_REG0 0x19604
#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608
#define ixPB0_TX_LANE12_CTRL_REG0 0x19840
#define ixPB0_TX_LANE12_OVRD_REG0 0x19844
#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848
#define ixPB0_TX_LANE13_CTRL_REG0 0x19880
#define ixPB0_TX_LANE13_OVRD_REG0 0x19884
#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888
#define ixPB0_TX_LANE14_CTRL_REG0 0x19900
#define ixPB0_TX_LANE14_OVRD_REG0 0x19904
#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908
#define ixPB0_TX_LANE15_CTRL_REG0 0x19A00
#define ixPB0_TX_LANE15_OVRD_REG0 0x19A04
#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08
#define ixPB0_TX_LANE1_CTRL_REG0 0x18480
#define ixPB0_TX_LANE1_OVRD_REG0 0x18484
#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488
#define ixPB0_TX_LANE2_CTRL_REG0 0x18500
#define ixPB0_TX_LANE2_OVRD_REG0 0x18504
#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508
#define ixPB0_TX_LANE3_CTRL_REG0 0x18600
#define ixPB0_TX_LANE3_OVRD_REG0 0x18604
#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608
#define ixPB0_TX_LANE4_CTRL_REG0 0x18840
#define ixPB0_TX_LANE4_OVRD_REG0 0x18844
#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848
#define ixPB0_TX_LANE5_CTRL_REG0 0x18880
#define ixPB0_TX_LANE5_OVRD_REG0 0x18884
#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888
#define ixPB0_TX_LANE6_CTRL_REG0 0x18900
#define ixPB0_TX_LANE6_OVRD_REG0 0x18904
#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908
#define ixPB0_TX_LANE7_CTRL_REG0 0x18A00
#define ixPB0_TX_LANE7_OVRD_REG0 0x18A04
#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08
#define ixPB0_TX_LANE8_CTRL_REG0 0x19440
#define ixPB0_TX_LANE8_OVRD_REG0 0x19444
#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448
#define ixPB0_TX_LANE9_CTRL_REG0 0x19480
#define ixPB0_TX_LANE9_OVRD_REG0 0x19484
#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488
#define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C
#define ixPB1_DFT_JIT_INJ_REG0 0x13000
#define ixPB1_DFT_JIT_INJ_REG1 0x13004
#define ixPB1_DFT_JIT_INJ_REG2 0x13008
#define ixPB1_GLB_CTRL_REG0 0x10004
#define ixPB1_GLB_CTRL_REG1 0x10008
#define ixPB1_GLB_CTRL_REG2 0x1000C
#define ixPB1_GLB_CTRL_REG3 0x10010
#define ixPB1_GLB_CTRL_REG4 0x10014
#define ixPB1_GLB_CTRL_REG5 0x10018
#define ixPB1_GLB_OVRD_REG0 0x10030
#define ixPB1_GLB_OVRD_REG1 0x10034
#define ixPB1_GLB_OVRD_REG2 0x10038
#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C
#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020
#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024
#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028
#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C
#define ixPB1_HW_DEBUG 0x12004
#define ixPB1_PIF_CNTL 0x0010
#define ixPB1_PIF_CNTL2 0x0014
#define ixPB1_PIF_HW_DEBUG 0x0002
#define ixPB1_PIF_PAIRING 0x0011
#define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020
#define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032
#define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021
#define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033
#define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034
#define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035
#define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036
#define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037
#define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022
#define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023
#define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024
#define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025
#define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026
#define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027
#define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030
#define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031
#define ixPB1_PIF_PWRDOWN_0 0x0012
#define ixPB1_PIF_PWRDOWN_1 0x0013
#define ixPB1_PIF_PWRDOWN_2 0x0017
#define ixPB1_PIF_PWRDOWN_3 0x0018
#define ixPB1_PIF_SC_CTL 0x0016
#define ixPB1_PIF_SCRATCH 0x0001
#define ixPB1_PIF_SEQ_STATUS_0 0x0028
#define ixPB1_PIF_SEQ_STATUS_10 0x003A
#define ixPB1_PIF_SEQ_STATUS_1 0x0029
#define ixPB1_PIF_SEQ_STATUS_11 0x003B
#define ixPB1_PIF_SEQ_STATUS_12 0x003C
#define ixPB1_PIF_SEQ_STATUS_13 0x003D
#define ixPB1_PIF_SEQ_STATUS_14 0x003E
#define ixPB1_PIF_SEQ_STATUS_15 0x003F
#define ixPB1_PIF_SEQ_STATUS_2 0x002A
#define ixPB1_PIF_SEQ_STATUS_3 0x002B
#define ixPB1_PIF_SEQ_STATUS_4 0x002C
#define ixPB1_PIF_SEQ_STATUS_5 0x002D
#define ixPB1_PIF_SEQ_STATUS_6 0x002E
#define ixPB1_PIF_SEQ_STATUS_7 0x002F
#define ixPB1_PIF_SEQ_STATUS_8 0x0038
#define ixPB1_PIF_SEQ_STATUS_9 0x0039
#define ixPB1_PIF_TXPHYSTATUS 0x0015
#define ixPB1_PLL_LC0_CTRL_REG0 0x14480
#define ixPB1_PLL_LC0_OVRD_REG0 0x14490
#define ixPB1_PLL_LC0_OVRD_REG1 0x14494
#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
#define ixPB1_PLL_RO0_CTRL_REG0 0x14440
#define ixPB1_PLL_RO0_OVRD_REG0 0x14450
#define ixPB1_PLL_RO0_OVRD_REG1 0x14454
#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000
#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010
#define ixPB1_RX_GLB_CTRL_REG0 0x16000
#define ixPB1_RX_GLB_CTRL_REG1 0x16004
#define ixPB1_RX_GLB_CTRL_REG2 0x16008
#define ixPB1_RX_GLB_CTRL_REG3 0x1600C
#define ixPB1_RX_GLB_CTRL_REG4 0x16010
#define ixPB1_RX_GLB_CTRL_REG5 0x16014
#define ixPB1_RX_GLB_CTRL_REG6 0x16018
#define ixPB1_RX_GLB_CTRL_REG7 0x1601C
#define ixPB1_RX_GLB_CTRL_REG8 0x16020
#define ixPB1_RX_GLB_OVRD_REG0 0x16030
#define ixPB1_RX_GLB_OVRD_REG1 0x16034
#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028
#define ixPB1_RX_LANE0_CTRL_REG0 0x16440
#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448
#define ixPB1_RX_LANE10_CTRL_REG0 0x17500
#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508
#define ixPB1_RX_LANE11_CTRL_REG0 0x17600
#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608
#define ixPB1_RX_LANE12_CTRL_REG0 0x17840
#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848
#define ixPB1_RX_LANE13_CTRL_REG0 0x17880
#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888
#define ixPB1_RX_LANE14_CTRL_REG0 0x17900
#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908
#define ixPB1_RX_LANE15_CTRL_REG0 0x17A00
#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08
#define ixPB1_RX_LANE1_CTRL_REG0 0x16480
#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488
#define ixPB1_RX_LANE2_CTRL_REG0 0x16500
#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508
#define ixPB1_RX_LANE3_CTRL_REG0 0x16600
#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608
#define ixPB1_RX_LANE4_CTRL_REG0 0x16800
#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848
#define ixPB1_RX_LANE5_CTRL_REG0 0x16880
#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888
#define ixPB1_RX_LANE6_CTRL_REG0 0x16900
#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908
#define ixPB1_RX_LANE7_CTRL_REG0 0x16A00
#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08
#define ixPB1_RX_LANE8_CTRL_REG0 0x17440
#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448
#define ixPB1_RX_LANE9_CTRL_REG0 0x17480
#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488
#define ixPB1_STRAP_GLB_REG0 0x12020
#define ixPB1_STRAP_PLL_REG0 0x12030
#define ixPB1_STRAP_RX_REG0 0x12028
#define ixPB1_STRAP_RX_REG1 0x1202C
#define ixPB1_STRAP_TX_REG0 0x12024
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020
#define ixPB1_TX_GLB_CTRL_REG0 0x18000
#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004
#define ixPB1_TX_GLB_OVRD_REG0 0x18030
#define ixPB1_TX_GLB_OVRD_REG1 0x18034
#define ixPB1_TX_GLB_OVRD_REG2 0x18038
#define ixPB1_TX_GLB_OVRD_REG3 0x1803C
#define ixPB1_TX_GLB_OVRD_REG4 0x18040
#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010
#define ixPB1_TX_LANE0_CTRL_REG0 0x18440
#define ixPB1_TX_LANE0_OVRD_REG0 0x18444
#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448
#define ixPB1_TX_LANE10_CTRL_REG0 0x19500
#define ixPB1_TX_LANE10_OVRD_REG0 0x19504
#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508
#define ixPB1_TX_LANE11_CTRL_REG0 0x19600
#define ixPB1_TX_LANE11_OVRD_REG0 0x19604
#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608
#define ixPB1_TX_LANE12_CTRL_REG0 0x19840
#define ixPB1_TX_LANE12_OVRD_REG0 0x19844
#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848
#define ixPB1_TX_LANE13_CTRL_REG0 0x19880
#define ixPB1_TX_LANE13_OVRD_REG0 0x19884
#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888
#define ixPB1_TX_LANE14_CTRL_REG0 0x19900
#define ixPB1_TX_LANE14_OVRD_REG0 0x19904
#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908
#define ixPB1_TX_LANE15_CTRL_REG0 0x19A00
#define ixPB1_TX_LANE15_OVRD_REG0 0x19A04
#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08
#define ixPB1_TX_LANE1_CTRL_REG0 0x18480
#define ixPB1_TX_LANE1_OVRD_REG0 0x18484
#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488
#define ixPB1_TX_LANE2_CTRL_REG0 0x18500
#define ixPB1_TX_LANE2_OVRD_REG0 0x18504
#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508
#define ixPB1_TX_LANE3_CTRL_REG0 0x18600
#define ixPB1_TX_LANE3_OVRD_REG0 0x18604
#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608
#define ixPB1_TX_LANE4_CTRL_REG0 0x18840
#define ixPB1_TX_LANE4_OVRD_REG0 0x18844
#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848
#define ixPB1_TX_LANE5_CTRL_REG0 0x18880
#define ixPB1_TX_LANE5_OVRD_REG0 0x18884
#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888
#define ixPB1_TX_LANE6_CTRL_REG0 0x18900
#define ixPB1_TX_LANE6_OVRD_REG0 0x18904
#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908
#define ixPB1_TX_LANE7_CTRL_REG0 0x18A00
#define ixPB1_TX_LANE7_OVRD_REG0 0x18A04
#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08
#define ixPB1_TX_LANE8_CTRL_REG0 0x19440
#define ixPB1_TX_LANE8_OVRD_REG0 0x19444
#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448
#define ixPB1_TX_LANE9_CTRL_REG0 0x19480
#define ixPB1_TX_LANE9_OVRD_REG0 0x19484
#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488
#define ixPCIE_BUS_CNTL 0x0021
#define ixPCIE_CFG_CNTL 0x003C
#define ixPCIE_CI_CNTL 0x0020
#define ixPCIE_CNTL 0x0010
#define ixPCIE_CNTL2 0x001C
#define ixPCIE_CONFIG_CNTL 0x0011
#define ixPCIE_DEBUG_CNTL 0x0012
#define ixPCIE_ERR_CNTL 0x006A
#define ixPCIE_F0_DPA_CAP 0x00E0
#define ixPCIE_F0_DPA_CNTL 0x00E5
#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE
#define ixPCIE_FC_CPL 0x0062
#define ixPCIE_FC_NP 0x0061
#define ixPCIE_FC_P 0x0060
#define ixPCIE_HW_DEBUG 0x0002
#define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A
#define ixPCIE_I2C_REG_DATA 0x003B
#define ixPCIE_INT_CNTL 0x001A
#define ixPCIE_INT_STATUS 0x001B
#define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9
#define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2
#define ixPCIE_LC_CDR_CNTL 0x00B3
#define ixPCIE_LC_CNTL 0x00A0
#define ixPCIE_LC_CNTL2 0x00B1
#define ixPCIE_LC_CNTL3 0x00B5
#define ixPCIE_LC_CNTL4 0x00B6
#define ixPCIE_LC_CNTL5 0x00B7
#define ixPCIE_LC_FORCE_COEFF 0x00B8
#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA
#define ixPCIE_LC_LANE_CNTL 0x00B4
#define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2
#define ixPCIE_LC_N_FTS_CNTL 0x00A3
#define ixPCIE_LC_SPEED_CNTL 0x00A4
#define ixPCIE_LC_STATE0 0x00A5
#define ixPCIE_LC_STATE10 0x0026
#define ixPCIE_LC_STATE1 0x00A6
#define ixPCIE_LC_STATE11 0x0027
#define ixPCIE_LC_STATE2 0x00A7
#define ixPCIE_LC_STATE3 0x00A8
#define ixPCIE_LC_STATE4 0x00A9
#define ixPCIE_LC_STATE5 0x00AA
#define ixPCIE_LC_STATE6 0x0022
#define ixPCIE_LC_STATE7 0x0023
#define ixPCIE_LC_STATE8 0x0024
#define ixPCIE_LC_STATE9 0x0025
#define ixPCIE_LC_STATUS1 0x0028
#define ixPCIE_LC_STATUS2 0x0029
#define ixPCIE_LC_TRAINING_CNTL 0x00A1
#define ixPCIE_P_BUF_STATUS 0x0041
#define ixPCIE_P_CNTL 0x0040
#define ixPCIE_P_DECODER_STATUS 0x0042
#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093
#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094
#define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087
#define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084
#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090
#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A
#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D
#define ixPCIE_PERF_CNTL_TXCLK 0x0081
#define ixPCIE_PERF_CNTL_TXCLK2 0x0095
#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088
#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085
#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091
#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B
#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E
#define ixPCIE_PERF_COUNT0_TXCLK 0x0082
#define ixPCIE_PERF_COUNT0_TXCLK2 0x0096
#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089
#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086
#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092
#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C
#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F
#define ixPCIE_PERF_COUNT1_TXCLK 0x0083
#define ixPCIE_PERF_COUNT1_TXCLK2 0x0097
#define ixPCIE_PERF_COUNT_CNTL 0x0080
#define ixPCIEP_HW_DEBUG 0x0002
#define ixPCIE_P_MISC_STATUS 0x0043
#define ixPCIEP_PORT_CNTL 0x0010
#define ixPCIE_P_PORT_LANE_STATUS 0x0050
#define ixPCIE_PRBS_CLR 0x00C8
#define ixPCIE_PRBS_ERRCNT_0 0x00D0
#define ixPCIE_PRBS_ERRCNT_10 0x00DA
#define ixPCIE_PRBS_ERRCNT_1 0x00D1
#define ixPCIE_PRBS_ERRCNT_11 0x00DB
#define ixPCIE_PRBS_ERRCNT_12 0x00DC
#define ixPCIE_PRBS_ERRCNT_13 0x00DD
#define ixPCIE_PRBS_ERRCNT_14 0x00DE
#define ixPCIE_PRBS_ERRCNT_15 0x00DF
#define ixPCIE_PRBS_ERRCNT_2 0x00D2
#define ixPCIE_PRBS_ERRCNT_3 0x00D3
#define ixPCIE_PRBS_ERRCNT_4 0x00D4
#define ixPCIE_PRBS_ERRCNT_5 0x00D5
#define ixPCIE_PRBS_ERRCNT_6 0x00D6
#define ixPCIE_PRBS_ERRCNT_7 0x00D7
#define ixPCIE_PRBS_ERRCNT_8 0x00D8
#define ixPCIE_PRBS_ERRCNT_9 0x00D9
#define ixPCIE_PRBS_FREERUN 0x00CB
#define ixPCIE_PRBS_HI_BITCNT 0x00CF
#define ixPCIE_PRBS_LO_BITCNT 0x00CE
#define ixPCIE_PRBS_MISC 0x00CC
#define ixPCIE_PRBS_STATUS1 0x00C9
#define ixPCIE_PRBS_STATUS2 0x00CA
#define ixPCIE_PRBS_USER_PATTERN 0x00CD
#define ixPCIE_P_RCV_L0S_FTS_DET 0x0050
#define ixPCIEP_RESERVED 0x0000
#define ixPCIEP_SCRATCH 0x0001
#define ixPCIEP_STRAP_LC 0x00C0
#define ixPCIEP_STRAP_MISC 0x00C1
#define ixPCIE_RESERVED 0x0000
#define ixPCIE_RX_CNTL 0x0070
#define ixPCIE_RX_CNTL2 0x001D
#define ixPCIE_RX_CNTL3 0x0074
#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082
#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081
#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080
#define ixPCIE_RX_EXPECTED_SEQNUM 0x0071
#define ixPCIE_RX_LAST_TLP0 0x0031
#define ixPCIE_RX_LAST_TLP1 0x0032
#define ixPCIE_RX_LAST_TLP2 0x0033
#define ixPCIE_RX_LAST_TLP3 0x0034
#define ixPCIE_RX_NUM_NAK 0x000E
#define ixPCIE_RX_NUM_NAK_GENERATED 0x000F
#define ixPCIE_RX_VENDOR_SPECIFIC 0x0072
#define ixPCIE_SCRATCH 0x0001
#define ixPCIE_STRAP_F0 0x00B0
#define ixPCIE_STRAP_F1 0x00B1
#define ixPCIE_STRAP_F2 0x00B2
#define ixPCIE_STRAP_F3 0x00B3
#define ixPCIE_STRAP_F4 0x00B4
#define ixPCIE_STRAP_F5 0x00B5
#define ixPCIE_STRAP_F6 0x00B6
#define ixPCIE_STRAP_F7 0x00B7
#define ixPCIE_STRAP_I2C_BD 0x00C4
#define ixPCIE_STRAP_MISC 0x00C0
#define ixPCIE_STRAP_MISC2 0x00C1
#define ixPCIE_STRAP_PI 0x00C2
#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026
#define ixPCIE_TX_CNTL 0x0020
#define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032
#define ixPCIE_TX_CREDITS_ADVT_NP 0x0031
#define ixPCIE_TX_CREDITS_ADVT_P 0x0030
#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037
#define ixPCIE_TX_CREDITS_INIT_CPL 0x0035
#define ixPCIE_TX_CREDITS_INIT_NP 0x0034
#define ixPCIE_TX_CREDITS_INIT_P 0x0033
#define ixPCIE_TX_CREDITS_STATUS 0x0036
#define ixPCIE_TX_LAST_TLP0 0x0035
#define ixPCIE_TX_LAST_TLP1 0x0036
#define ixPCIE_TX_LAST_TLP2 0x0037
#define ixPCIE_TX_LAST_TLP3 0x0038
#define ixPCIE_TX_REPLAY 0x0025
#define ixPCIE_TX_REQUESTER_ID 0x0021
#define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023
#define ixPCIE_TX_SEQ 0x0024
#define ixPCIE_TX_VENDOR_SPECIFIC 0x0022
#define ixPCIE_WPR_CNTL 0x0030
#define mmBACO_CNTL 0x14E5
#define mmBF_ANA_ISO_CNTL 0x14C7
#define mmBIF_BACO_DEBUG 0x14DF
#define mmBIF_BACO_DEBUG_LATCH 0x14DC
#define mmBIF_BACO_MSIC 0x14DE
#define mmBIF_BUSNUM_CNTL1 0x1525
#define mmBIF_BUSNUM_CNTL2 0x152B
#define mmBIF_BUSNUM_LIST0 0x1526
#define mmBIF_BUSNUM_LIST1 0x1527
#define mmBIF_BUSY_DELAY_CNTR 0x1529
#define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F
#define mmBIF_DEBUG_CNTL 0x151C
#define mmBIF_DEBUG_MUX 0x151D
#define mmBIF_DEBUG_OUT 0x151E
#define mmBIF_DEVFUNCNUM_LIST0 0x14E8
#define mmBIF_DEVFUNCNUM_LIST1 0x14E7
#define mmBIF_FB_EN 0x1524
#define mmBIF_FEATURES_CONTROL_MISC 0x14C2
#define mmBIF_PERFCOUNTER0_RESULT 0x152D
#define mmBIF_PERFCOUNTER1_RESULT 0x152E
#define mmBIF_PERFMON_CNTL 0x152C
#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F
#define mmBIF_RESET_EN 0x1511
#define mmBIF_SCRATCH0 0x150E
#define mmBIF_SCRATCH1 0x150F
#define mmBIF_SSA_DISP_LOWER 0x14D2
#define mmBIF_SSA_DISP_UPPER 0x14D3
#define mmBIF_SSA_GFX0_LOWER 0x14CA
#define mmBIF_SSA_GFX0_UPPER 0x14CB
#define mmBIF_SSA_GFX1_LOWER 0x14CC
#define mmBIF_SSA_GFX1_UPPER 0x14CD
#define mmBIF_SSA_GFX2_LOWER 0x14CE
#define mmBIF_SSA_GFX2_UPPER 0x14CF
#define mmBIF_SSA_GFX3_LOWER 0x14D0
#define mmBIF_SSA_GFX3_UPPER 0x14D1
#define mmBIF_SSA_MC_LOWER 0x14D4
#define mmBIF_SSA_MC_UPPER 0x14D5
#define mmBIF_SSA_PWR_STATUS 0x14C8
#define mmBIF_XDMA_HI 0x14C1
#define mmBIF_XDMA_LO 0x14C0
#define mmBIOS_SCRATCH_0 0x05C9
#define mmBIOS_SCRATCH_10 0x05D3
#define mmBIOS_SCRATCH_1 0x05CA
#define mmBIOS_SCRATCH_11 0x05D4
#define mmBIOS_SCRATCH_12 0x05D5
#define mmBIOS_SCRATCH_13 0x05D6
#define mmBIOS_SCRATCH_14 0x05D7
#define mmBIOS_SCRATCH_15 0x05D8
#define mmBIOS_SCRATCH_2 0x05CB
#define mmBIOS_SCRATCH_3 0x05CC
#define mmBIOS_SCRATCH_4 0x05CD
#define mmBIOS_SCRATCH_5 0x05CE
#define mmBIOS_SCRATCH_6 0x05CF
#define mmBIOS_SCRATCH_7 0x05D0
#define mmBIOS_SCRATCH_8 0x05D1
#define mmBIOS_SCRATCH_9 0x05D2
#define mmBUS_CNTL 0x1508
#define mmCAPTURE_HOST_BUSNUM 0x153C
#define mmCLKREQB_PAD_CNTL 0x1521
#define mmCONFIG_APER_SIZE 0x150C
#define mmCONFIG_CNTL 0x1509
#define mmCONFIG_F0_BASE 0x150B
#define mmCONFIG_MEMSIZE 0x150A
#define mmCONFIG_REG_APER_SIZE 0x150D
#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
#define mmHOST_BUSNUM 0x153D
#define mmHW_DEBUG 0x1515
#define mmIMPCTL_RESET 0x14F5
#define mmINTERRUPT_CNTL 0x151A
#define mmINTERRUPT_CNTL2 0x151B
#define mmMASTER_CREDIT_CNTL 0x1516
#define mmMM_CFGREGS_CNTL 0x1513
#define mmMM_DATA 0x0001
#define mmMM_INDEX 0x0000
#define mmMM_INDEX_HI 0x0006
#define mmNEW_REFCLKB_TIMER 0x14EA
#define mmNEW_REFCLKB_TIMER_1 0x14E9
#define mmPCIE_DATA 0x000D
#define mmPCIE_INDEX 0x000C
#define mmPEER0_FB_OFFSET_HI 0x14F3
#define mmPEER0_FB_OFFSET_LO 0x14F2
#define mmPEER1_FB_OFFSET_HI 0x14F1
#define mmPEER1_FB_OFFSET_LO 0x14F0
#define mmPEER2_FB_OFFSET_HI 0x14EF
#define mmPEER2_FB_OFFSET_LO 0x14EE
#define mmPEER3_FB_OFFSET_HI 0x14ED
#define mmPEER3_FB_OFFSET_LO 0x14EC
#define mmPEER_REG_RANGE0 0x153E
#define mmPEER_REG_RANGE1 0x153F
#define mmSLAVE_HANG_ERROR 0x153B
#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
#define mmSMBCLK_PAD_CNTL 0x1523
#define mmSMBDAT_PAD_CNTL 0x1522
#define mmSMBUS_BACO_DUMMY 0x14C6
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
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/*
* BIF_4_1 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BIF_4_1_D_H
#define BIF_4_1_D_H
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
#define mmCC_BIF_BX_FUSESTRAP0 0x14D7
#define mmBUS_CNTL 0x1508
#define mmCONFIG_CNTL 0x1509
#define mmCONFIG_MEMSIZE 0x150a
#define mmCONFIG_F0_BASE 0x150b
#define mmCONFIG_APER_SIZE 0x150c
#define mmCONFIG_REG_APER_SIZE 0x150d
#define mmBIF_SCRATCH0 0x150e
#define mmBIF_SCRATCH1 0x150f
#define mmBX_RESET_EN 0x1514
#define mmMM_CFGREGS_CNTL 0x1513
#define mmHW_DEBUG 0x1515
#define mmMASTER_CREDIT_CNTL 0x1516
#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
#define mmBX_RESET_CNTL 0x1518
#define mmINTERRUPT_CNTL 0x151a
#define mmINTERRUPT_CNTL2 0x151b
#define mmBIF_DEBUG_CNTL 0x151c
#define mmBIF_DEBUG_MUX 0x151d
#define mmBIF_DEBUG_OUT 0x151e
#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
#define mmCLKREQB_PAD_CNTL 0x1521
#define mmSMBUS_SLV_CNTL 0x14fd
#define mmSMBUS_SLV_CNTL1 0x14fe
#define mmSMBDAT_PAD_CNTL 0x1522
#define mmSMBCLK_PAD_CNTL 0x1523
#define mmBIF_XDMA_LO 0x14c0
#define mmBIF_XDMA_HI 0x14c1
#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
#define mmBIF_DOORBELL_CNTL 0x14c3
#define mmBIF_SLVARB_MODE 0x14c4
#define mmBIF_FB_EN 0x1524
#define mmBIF_BUSNUM_CNTL1 0x1525
#define mmBIF_BUSNUM_LIST0 0x1526
#define mmBIF_BUSNUM_LIST1 0x1527
#define mmBIF_BUSNUM_CNTL2 0x152b
#define mmBIF_BUSY_DELAY_CNTR 0x1529
#define mmBIF_PERFMON_CNTL 0x152c
#define mmBIF_PERFCOUNTER0_RESULT 0x152d
#define mmBIF_PERFCOUNTER1_RESULT 0x152e
#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
#define mmGPU_HDP_FLUSH_REQ 0x1537
#define mmGPU_HDP_FLUSH_DONE 0x1538
#define mmSLAVE_HANG_ERROR 0x153b
#define mmCAPTURE_HOST_BUSNUM 0x153c
#define mmHOST_BUSNUM 0x153d
#define mmPEER_REG_RANGE0 0x153e
#define mmPEER_REG_RANGE1 0x153f
#define mmPEER0_FB_OFFSET_HI 0x14f3
#define mmPEER0_FB_OFFSET_LO 0x14f2
#define mmPEER1_FB_OFFSET_HI 0x14f1
#define mmPEER1_FB_OFFSET_LO 0x14f0
#define mmPEER2_FB_OFFSET_HI 0x14ef
#define mmPEER2_FB_OFFSET_LO 0x14ee
#define mmPEER3_FB_OFFSET_HI 0x14ed
#define mmPEER3_FB_OFFSET_LO 0x14ec
#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb
#define mmSMBUS_BACO_DUMMY 0x14c6
#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
#define mmBACO_CNTL 0x14e5
#define mmBF_ANA_ISO_CNTL 0x14c7
#define mmMEM_TYPE_CNTL 0x14e4
#define mmBIF_BACO_DEBUG 0x14df
#define mmBIF_BACO_DEBUG_LATCH 0x14dc
#define mmBACO_CNTL_MISC 0x14db
#define mmBIF_SSA_PWR_STATUS 0x14c8
#define mmBIF_SSA_GFX0_LOWER 0x14ca
#define mmBIF_SSA_GFX0_UPPER 0x14cb
#define mmBIF_SSA_GFX1_LOWER 0x14cc
#define mmBIF_SSA_GFX1_UPPER 0x14cd
#define mmBIF_SSA_GFX2_LOWER 0x14ce
#define mmBIF_SSA_GFX2_UPPER 0x14cf
#define mmBIF_SSA_GFX3_LOWER 0x14d0
#define mmBIF_SSA_GFX3_UPPER 0x14d1
#define mmBIF_SSA_DISP_LOWER 0x14d2
#define mmBIF_SSA_DISP_UPPER 0x14d3
#define mmBIF_SSA_MC_LOWER 0x14d4
#define mmBIF_SSA_MC_UPPER 0x14d5
#define mmIMPCTL_RESET 0x14f5
#define mmGARLIC_FLUSH_CNTL 0x1401
#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
#define mmGARLIC_FLUSH_REQ 0x1412
#define mmGPU_GARLIC_FLUSH_REQ 0x1413
#define mmGPU_GARLIC_FLUSH_DONE 0x1414
#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415
#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416
#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417
#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418
#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419
#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a
#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b
#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c
#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d
#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e
#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f
#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420
#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421
#define mmBIOS_SCRATCH_0 0x5c9
#define mmBIOS_SCRATCH_1 0x5ca
#define mmBIOS_SCRATCH_2 0x5cb
#define mmBIOS_SCRATCH_3 0x5cc
#define mmBIOS_SCRATCH_4 0x5cd
#define mmBIOS_SCRATCH_5 0x5ce
#define mmBIOS_SCRATCH_6 0x5cf
#define mmBIOS_SCRATCH_7 0x5d0
#define mmBIOS_SCRATCH_8 0x5d1
#define mmBIOS_SCRATCH_9 0x5d2
#define mmBIOS_SCRATCH_10 0x5d3
#define mmBIOS_SCRATCH_11 0x5d4
#define mmBIOS_SCRATCH_12 0x5d5
#define mmBIOS_SCRATCH_13 0x5d6
#define mmBIOS_SCRATCH_14 0x5d7
#define mmBIOS_SCRATCH_15 0x5d8
#define mmVENDOR_ID 0x0
#define mmDEVICE_ID 0x0
#define mmCOMMAND 0x1
#define mmSTATUS 0x1
#define mmREVISION_ID 0x2
#define mmPROG_INTERFACE 0x2
#define mmSUB_CLASS 0x2
#define mmBASE_CLASS 0x2
#define mmCACHE_LINE 0x3
#define mmLATENCY 0x3
#define mmHEADER 0x3
#define mmBIST 0x3
#define mmBASE_ADDR_1 0x4
#define mmBASE_ADDR_2 0x5
#define mmBASE_ADDR_3 0x6
#define mmBASE_ADDR_4 0x7
#define mmBASE_ADDR_5 0x8
#define mmBASE_ADDR_6 0x9
#define mmROM_BASE_ADDR 0xc
#define mmCAP_PTR 0xd
#define mmINTERRUPT_LINE 0xf
#define mmINTERRUPT_PIN 0xf
#define mmADAPTER_ID 0xb
#define mmMIN_GRANT 0xf
#define mmMAX_LATENCY 0xf
#define mmVENDOR_CAP_LIST 0x12
#define mmADAPTER_ID_W 0x13
#define mmPMI_CAP_LIST 0x14
#define mmPMI_CAP 0x14
#define mmPMI_STATUS_CNTL 0x15
#define mmPCIE_CAP_LIST 0x16
#define mmPCIE_CAP 0x16
#define mmDEVICE_CAP 0x17
#define mmDEVICE_CNTL 0x18
#define mmDEVICE_STATUS 0x18
#define mmLINK_CAP 0x19
#define mmLINK_CNTL 0x1a
#define mmLINK_STATUS 0x1a
#define mmDEVICE_CAP2 0x1f
#define mmDEVICE_CNTL2 0x20
#define mmDEVICE_STATUS2 0x20
#define mmLINK_CAP2 0x21
#define mmLINK_CNTL2 0x22
#define mmLINK_STATUS2 0x22
#define mmMSI_CAP_LIST 0x28
#define mmMSI_MSG_CNTL 0x28
#define mmMSI_MSG_ADDR_LO 0x29
#define mmMSI_MSG_ADDR_HI 0x2a
#define mmMSI_MSG_DATA_64 0x2b
#define mmMSI_MSG_DATA 0x2a
#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
#define mmPCIE_VENDOR_SPECIFIC1 0x42
#define mmPCIE_VENDOR_SPECIFIC2 0x43
#define mmPCIE_VC_ENH_CAP_LIST 0x44
#define mmPCIE_PORT_VC_CAP_REG1 0x45
#define mmPCIE_PORT_VC_CAP_REG2 0x46
#define mmPCIE_PORT_VC_CNTL 0x47
#define mmPCIE_PORT_VC_STATUS 0x47
#define mmPCIE_VC0_RESOURCE_CAP 0x48
#define mmPCIE_VC0_RESOURCE_CNTL 0x49
#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
#define mmPCIE_VC1_RESOURCE_CAP 0x4b
#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
#define mmPCIE_UNCORR_ERR_STATUS 0x55
#define mmPCIE_UNCORR_ERR_MASK 0x56
#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
#define mmPCIE_CORR_ERR_STATUS 0x58
#define mmPCIE_CORR_ERR_MASK 0x59
#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
#define mmPCIE_HDR_LOG0 0x5b
#define mmPCIE_HDR_LOG1 0x5c
#define mmPCIE_HDR_LOG2 0x5d
#define mmPCIE_HDR_LOG3 0x5e
#define mmPCIE_TLP_PREFIX_LOG0 0x62
#define mmPCIE_TLP_PREFIX_LOG1 0x63
#define mmPCIE_TLP_PREFIX_LOG2 0x64
#define mmPCIE_TLP_PREFIX_LOG3 0x65
#define mmPCIE_BAR_ENH_CAP_LIST 0x80
#define mmPCIE_BAR1_CAP 0x81
#define mmPCIE_BAR1_CNTL 0x82
#define mmPCIE_BAR2_CAP 0x83
#define mmPCIE_BAR2_CNTL 0x84
#define mmPCIE_BAR3_CAP 0x85
#define mmPCIE_BAR3_CNTL 0x86
#define mmPCIE_BAR4_CAP 0x87
#define mmPCIE_BAR4_CNTL 0x88
#define mmPCIE_BAR5_CAP 0x89
#define mmPCIE_BAR5_CNTL 0x8a
#define mmPCIE_BAR6_CAP 0x8b
#define mmPCIE_BAR6_CNTL 0x8c
#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
#define mmPCIE_PWR_BUDGET_DATA 0x92
#define mmPCIE_PWR_BUDGET_CAP 0x93
#define mmPCIE_DPA_ENH_CAP_LIST 0x94
#define mmPCIE_DPA_CAP 0x95
#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
#define mmPCIE_DPA_STATUS 0x97
#define mmPCIE_DPA_CNTL 0x97
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
#define mmPCIE_LINK_CNTL3 0x9d
#define mmPCIE_LANE_ERROR_STATUS 0x9e
#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
#define mmPCIE_ACS_CAP 0xa9
#define mmPCIE_ACS_CNTL 0xa9
#define mmPCIE_ATS_ENH_CAP_LIST 0xac
#define mmPCIE_ATS_CAP 0xad
#define mmPCIE_ATS_CNTL 0xad
#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
#define mmPCIE_PAGE_REQ_CNTL 0xb1
#define mmPCIE_PAGE_REQ_STATUS 0xb1
#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
#define mmPCIE_PASID_CAP 0xb5
#define mmPCIE_PASID_CNTL 0xb5
#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
#define mmPCIE_TPH_REQR_CAP 0xb9
#define mmPCIE_TPH_REQR_CNTL 0xba
#define mmPCIE_MC_ENH_CAP_LIST 0xbc
#define mmPCIE_MC_CAP 0xbd
#define mmPCIE_MC_CNTL 0xbd
#define mmPCIE_MC_ADDR0 0xbe
#define mmPCIE_MC_ADDR1 0xbf
#define mmPCIE_MC_RCV0 0xc0
#define mmPCIE_MC_RCV1 0xc1
#define mmPCIE_MC_BLOCK_ALL0 0xc2
#define mmPCIE_MC_BLOCK_ALL1 0xc3
#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
#define mmPCIE_LTR_CAP 0xc9
#define mmPCIE_INDEX 0xe
#define mmPCIE_DATA 0xf
#define mmPCIE_INDEX_2 0xc
#define mmPCIE_DATA_2 0xd
#define ixPCIE_RESERVED 0x1400000
#define ixPCIE_SCRATCH 0x1400001
#define ixPCIE_HW_DEBUG 0x1400002
#define ixPCIE_RX_NUM_NAK 0x140000e
#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
#define ixPCIE_CNTL 0x1400010
#define ixPCIE_CONFIG_CNTL 0x1400011
#define ixPCIE_DEBUG_CNTL 0x1400012
#define ixPCIE_INT_CNTL 0x140001a
#define ixPCIE_INT_STATUS 0x140001b
#define ixPCIE_CNTL2 0x140001c
#define ixPCIE_RX_CNTL2 0x140001d
#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
#define ixPCIE_CI_CNTL 0x1400020
#define ixPCIE_BUS_CNTL 0x1400021
#define ixPCIE_LC_STATE6 0x1400022
#define ixPCIE_LC_STATE7 0x1400023
#define ixPCIE_LC_STATE8 0x1400024
#define ixPCIE_LC_STATE9 0x1400025
#define ixPCIE_LC_STATE10 0x1400026
#define ixPCIE_LC_STATE11 0x1400027
#define ixPCIE_LC_STATUS1 0x1400028
#define ixPCIE_LC_STATUS2 0x1400029
#define ixPCIE_WPR_CNTL 0x1400030
#define ixPCIE_RX_LAST_TLP0 0x1400031
#define ixPCIE_RX_LAST_TLP1 0x1400032
#define ixPCIE_RX_LAST_TLP2 0x1400033
#define ixPCIE_RX_LAST_TLP3 0x1400034
#define ixPCIE_TX_LAST_TLP0 0x1400035
#define ixPCIE_TX_LAST_TLP1 0x1400036
#define ixPCIE_TX_LAST_TLP2 0x1400037
#define ixPCIE_TX_LAST_TLP3 0x1400038
#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
#define ixPCIE_I2C_REG_DATA 0x140003b
#define ixPCIE_CFG_CNTL 0x140003c
#define ixPCIE_P_CNTL 0x1400040
#define ixPCIE_P_BUF_STATUS 0x1400041
#define ixPCIE_P_DECODER_STATUS 0x1400042
#define ixPCIE_P_MISC_STATUS 0x1400043
#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
#define ixPCIE_OBFF_CNTL 0x1400061
#define ixPCIE_TX_LTR_CNTL 0x1400060
#define ixPCIE_PERF_COUNT_CNTL 0x1400080
#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
#define ixPCIE_STRAP_F0 0x14000b0
#define ixPCIE_STRAP_F1 0x14000b1
#define ixPCIE_STRAP_F2 0x14000b2
#define ixPCIE_STRAP_F3 0x14000b3
#define ixPCIE_STRAP_F4 0x14000b4
#define ixPCIE_STRAP_F5 0x14000b5
#define ixPCIE_STRAP_F6 0x14000b6
#define ixPCIE_STRAP_F7 0x14000b7
#define ixPCIE_STRAP_MISC 0x14000c0
#define ixPCIE_STRAP_MISC2 0x14000c1
#define ixPCIE_STRAP_PI 0x14000c2
#define ixPCIE_STRAP_I2C_BD 0x14000c4
#define ixPCIE_PRBS_CLR 0x14000c8
#define ixPCIE_PRBS_STATUS1 0x14000c9
#define ixPCIE_PRBS_STATUS2 0x14000ca
#define ixPCIE_PRBS_FREERUN 0x14000cb
#define ixPCIE_PRBS_MISC 0x14000cc
#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
#define ixPCIE_PRBS_ERRCNT_10 0x14000da
#define ixPCIE_PRBS_ERRCNT_11 0x14000db
#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
#define ixPCIE_PRBS_ERRCNT_14 0x14000de
#define ixPCIE_PRBS_ERRCNT_15 0x14000df
#define ixPCIE_F0_DPA_CAP 0x14000e0
#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
#define ixPCIE_F0_DPA_CNTL 0x14000e5
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
#define ixPCIEP_RESERVED 0x10010000
#define ixPCIEP_SCRATCH 0x10010001
#define ixPCIEP_HW_DEBUG 0x10010002
#define ixPCIEP_PORT_CNTL 0x10010010
#define ixPCIE_TX_CNTL 0x10010020
#define ixPCIE_TX_REQUESTER_ID 0x10010021
#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
#define ixPCIE_TX_SEQ 0x10010024
#define ixPCIE_TX_REPLAY 0x10010025
#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
#define ixPCIE_TX_CREDITS_STATUS 0x10010036
#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
#define ixPCIE_FC_P 0x10010060
#define ixPCIE_FC_NP 0x10010061
#define ixPCIE_FC_CPL 0x10010062
#define ixPCIE_ERR_CNTL 0x1001006a
#define ixPCIE_RX_CNTL 0x10010070
#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
#define ixPCIE_RX_CNTL3 0x10010074
#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
#define ixPCIE_LC_CNTL 0x100100a0
#define ixPCIE_LC_CNTL2 0x100100b1
#define ixPCIE_LC_CNTL3 0x100100b5
#define ixPCIE_LC_CNTL4 0x100100b6
#define ixPCIE_LC_CNTL5 0x100100b7
#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
#define ixPCIE_LC_SPEED_CNTL 0x100100a4
#define ixPCIE_LC_CDR_CNTL 0x100100b3
#define ixPCIE_LC_LANE_CNTL 0x100100b4
#define ixPCIE_LC_FORCE_COEFF 0x100100b8
#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
#define ixPCIE_LC_STATE0 0x100100a5
#define ixPCIE_LC_STATE1 0x100100a6
#define ixPCIE_LC_STATE2 0x100100a7
#define ixPCIE_LC_STATE3 0x100100a8
#define ixPCIE_LC_STATE4 0x100100a9
#define ixPCIE_LC_STATE5 0x100100aa
#define ixPCIEP_STRAP_LC 0x100100c0
#define ixPCIEP_STRAP_MISC 0x100100c1
#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
#define ixPB0_GLB_CTRL_REG0 0x1200004
#define ixPB0_GLB_CTRL_REG1 0x1200008
#define ixPB0_GLB_CTRL_REG2 0x120000c
#define ixPB0_GLB_CTRL_REG3 0x1200010
#define ixPB0_GLB_CTRL_REG4 0x1200014
#define ixPB0_GLB_CTRL_REG5 0x1200018
#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
#define ixPB0_GLB_OVRD_REG0 0x1200030
#define ixPB0_GLB_OVRD_REG1 0x1200034
#define ixPB0_GLB_OVRD_REG2 0x1200038
#define ixPB0_HW_DEBUG 0x1202004
#define ixPB0_STRAP_GLB_REG0 0x1202020
#define ixPB0_STRAP_TX_REG0 0x1202024
#define ixPB0_STRAP_RX_REG0 0x1202028
#define ixPB0_STRAP_RX_REG1 0x120202c
#define ixPB0_STRAP_PLL_REG0 0x1202030
#define ixPB0_STRAP_PIN_REG0 0x1202034
#define ixPB0_DFT_JIT_INJ_REG0 0x1203000
#define ixPB0_DFT_JIT_INJ_REG1 0x1203004
#define ixPB0_DFT_JIT_INJ_REG2 0x1203008
#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
#define ixPB0_RX_GLB_CTRL_REG0 0x1206000
#define ixPB0_RX_GLB_CTRL_REG1 0x1206004
#define ixPB0_RX_GLB_CTRL_REG2 0x1206008
#define ixPB0_RX_GLB_CTRL_REG3 0x120600c
#define ixPB0_RX_GLB_CTRL_REG4 0x1206010
#define ixPB0_RX_GLB_CTRL_REG5 0x1206014
#define ixPB0_RX_GLB_CTRL_REG6 0x1206018
#define ixPB0_RX_GLB_CTRL_REG7 0x120601c
#define ixPB0_RX_GLB_CTRL_REG8 0x1206020
#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
#define ixPB0_RX_GLB_OVRD_REG0 0x1206030
#define ixPB0_RX_GLB_OVRD_REG1 0x1206034
#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
#define ixPB0_TX_GLB_CTRL_REG0 0x1208000
#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
#define ixPB0_TX_GLB_OVRD_REG0 0x1208030
#define ixPB0_TX_GLB_OVRD_REG1 0x1208034
#define ixPB0_TX_GLB_OVRD_REG2 0x1208038
#define ixPB0_TX_GLB_OVRD_REG3 0x120803c
#define ixPB0_TX_GLB_OVRD_REG4 0x1208040
#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
#define ixPB1_GLB_CTRL_REG0 0x2200004
#define ixPB1_GLB_CTRL_REG1 0x2200008
#define ixPB1_GLB_CTRL_REG2 0x220000c
#define ixPB1_GLB_CTRL_REG3 0x2200010
#define ixPB1_GLB_CTRL_REG4 0x2200014
#define ixPB1_GLB_CTRL_REG5 0x2200018
#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
#define ixPB1_GLB_OVRD_REG0 0x2200030
#define ixPB1_GLB_OVRD_REG1 0x2200034
#define ixPB1_GLB_OVRD_REG2 0x2200038
#define ixPB1_HW_DEBUG 0x2202004
#define ixPB1_STRAP_GLB_REG0 0x2202020
#define ixPB1_STRAP_TX_REG0 0x2202024
#define ixPB1_STRAP_RX_REG0 0x2202028
#define ixPB1_STRAP_RX_REG1 0x220202c
#define ixPB1_STRAP_PLL_REG0 0x2202030
#define ixPB1_STRAP_PIN_REG0 0x2202034
#define ixPB1_DFT_JIT_INJ_REG0 0x2203000
#define ixPB1_DFT_JIT_INJ_REG1 0x2203004
#define ixPB1_DFT_JIT_INJ_REG2 0x2203008
#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
#define ixPB1_RX_GLB_CTRL_REG0 0x2206000
#define ixPB1_RX_GLB_CTRL_REG1 0x2206004
#define ixPB1_RX_GLB_CTRL_REG2 0x2206008
#define ixPB1_RX_GLB_CTRL_REG3 0x220600c
#define ixPB1_RX_GLB_CTRL_REG4 0x2206010
#define ixPB1_RX_GLB_CTRL_REG5 0x2206014
#define ixPB1_RX_GLB_CTRL_REG6 0x2206018
#define ixPB1_RX_GLB_CTRL_REG7 0x220601c
#define ixPB1_RX_GLB_CTRL_REG8 0x2206020
#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
#define ixPB1_RX_GLB_OVRD_REG0 0x2206030
#define ixPB1_RX_GLB_OVRD_REG1 0x2206034
#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
#define ixPB1_TX_GLB_CTRL_REG0 0x2208000
#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
#define ixPB1_TX_GLB_OVRD_REG0 0x2208030
#define ixPB1_TX_GLB_OVRD_REG1 0x2208034
#define ixPB1_TX_GLB_OVRD_REG2 0x2208038
#define ixPB1_TX_GLB_OVRD_REG3 0x220803c
#define ixPB1_TX_GLB_OVRD_REG4 0x2208040
#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
#define ixPB0_PIF_SCRATCH 0x1100001
#define ixPB0_PIF_HW_DEBUG 0x1100002
#define ixPB0_PIF_PRG6 0x1100003
#define ixPB0_PIF_PRG7 0x1100004
#define ixPB0_PIF_CNTL 0x1100010
#define ixPB0_PIF_PAIRING 0x1100011
#define ixPB0_PIF_PWRDOWN_0 0x1100012
#define ixPB0_PIF_PWRDOWN_1 0x1100013
#define ixPB0_PIF_CNTL2 0x1100014
#define ixPB0_PIF_TXPHYSTATUS 0x1100015
#define ixPB0_PIF_SC_CTL 0x1100016
#define ixPB0_PIF_PWRDOWN_2 0x1100017
#define ixPB0_PIF_PWRDOWN_3 0x1100018
#define ixPB0_PIF_SC_CTL2 0x1100019
#define ixPB0_PIF_PRG0 0x110001a
#define ixPB0_PIF_PRG1 0x110001b
#define ixPB0_PIF_PRG2 0x110001c
#define ixPB0_PIF_PRG3 0x110001d
#define ixPB0_PIF_PRG4 0x110001e
#define ixPB0_PIF_PRG5 0x110001f
#define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020
#define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021
#define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022
#define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023
#define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024
#define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025
#define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026
#define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027
#define ixPB0_PIF_SEQ_STATUS_0 0x1100028
#define ixPB0_PIF_SEQ_STATUS_1 0x1100029
#define ixPB0_PIF_SEQ_STATUS_2 0x110002a
#define ixPB0_PIF_SEQ_STATUS_3 0x110002b
#define ixPB0_PIF_SEQ_STATUS_4 0x110002c
#define ixPB0_PIF_SEQ_STATUS_5 0x110002d
#define ixPB0_PIF_SEQ_STATUS_6 0x110002e
#define ixPB0_PIF_SEQ_STATUS_7 0x110002f
#define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030
#define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031
#define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032
#define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033
#define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034
#define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035
#define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036
#define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037
#define ixPB0_PIF_SEQ_STATUS_8 0x1100038
#define ixPB0_PIF_SEQ_STATUS_9 0x1100039
#define ixPB0_PIF_SEQ_STATUS_10 0x110003a
#define ixPB0_PIF_SEQ_STATUS_11 0x110003b
#define ixPB0_PIF_SEQ_STATUS_12 0x110003c
#define ixPB0_PIF_SEQ_STATUS_13 0x110003d
#define ixPB0_PIF_SEQ_STATUS_14 0x110003e
#define ixPB0_PIF_SEQ_STATUS_15 0x110003f
#define ixPB1_PIF_SCRATCH 0x2100001
#define ixPB1_PIF_HW_DEBUG 0x2100002
#define ixPB1_PIF_PRG6 0x2100003
#define ixPB1_PIF_PRG7 0x2100004
#define ixPB1_PIF_CNTL 0x2100010
#define ixPB1_PIF_PAIRING 0x2100011
#define ixPB1_PIF_PWRDOWN_0 0x2100012
#define ixPB1_PIF_PWRDOWN_1 0x2100013
#define ixPB1_PIF_CNTL2 0x2100014
#define ixPB1_PIF_TXPHYSTATUS 0x2100015
#define ixPB1_PIF_SC_CTL 0x2100016
#define ixPB1_PIF_PWRDOWN_2 0x2100017
#define ixPB1_PIF_PWRDOWN_3 0x2100018
#define ixPB1_PIF_SC_CTL2 0x2100019
#define ixPB1_PIF_PRG0 0x210001a
#define ixPB1_PIF_PRG1 0x210001b
#define ixPB1_PIF_PRG2 0x210001c
#define ixPB1_PIF_PRG3 0x210001d
#define ixPB1_PIF_PRG4 0x210001e
#define ixPB1_PIF_PRG5 0x210001f
#define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020
#define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021
#define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022
#define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023
#define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024
#define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025
#define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026
#define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027
#define ixPB1_PIF_SEQ_STATUS_0 0x2100028
#define ixPB1_PIF_SEQ_STATUS_1 0x2100029
#define ixPB1_PIF_SEQ_STATUS_2 0x210002a
#define ixPB1_PIF_SEQ_STATUS_3 0x210002b
#define ixPB1_PIF_SEQ_STATUS_4 0x210002c
#define ixPB1_PIF_SEQ_STATUS_5 0x210002d
#define ixPB1_PIF_SEQ_STATUS_6 0x210002e
#define ixPB1_PIF_SEQ_STATUS_7 0x210002f
#define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030
#define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031
#define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032
#define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033
#define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034
#define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035
#define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036
#define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037
#define ixPB1_PIF_SEQ_STATUS_8 0x2100038
#define ixPB1_PIF_SEQ_STATUS_9 0x2100039
#define ixPB1_PIF_SEQ_STATUS_10 0x210003a
#define ixPB1_PIF_SEQ_STATUS_11 0x210003b
#define ixPB1_PIF_SEQ_STATUS_12 0x210003c
#define ixPB1_PIF_SEQ_STATUS_13 0x210003d
#define ixPB1_PIF_SEQ_STATUS_14 0x210003e
#define ixPB1_PIF_SEQ_STATUS_15 0x210003f
#define mmBIF_RFE_SNOOP_REG 0x27
#define mmBIF_RFE_WARMRST_CNTL 0x1459
#define mmBIF_RFE_SOFTRST_CNTL 0x1441
#define mmBIF_RFE_IMPRST_CNTL 0x1458
#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
#define mmBIF_PWDN_COMMAND 0x1444
#define mmBIF_PWDN_STATUS 0x1445
#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448
#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
#define mmBIF_RFE_MMCFG_CNTL 0x144c
#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
#define mmBIF_IMPCTL_SMPLCNTL 0x1450
#define mmBIF_IMPCTL_RXCNTL 0x1451
#define mmBIF_IMPCTL_TXCNTL_pd 0x1452
#define mmBIF_IMPCTL_TXCNTL_pu 0x1453
#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
#define mmBIF_CLOCKS_BITS 0x1489
#define mmBIF_LNCNT_RESET 0x1488
#define mmLNCNT_CONTROL 0x1487
#define mmNEW_REFCLKB_TIMER 0x1485
#define mmNEW_REFCLKB_TIMER_1 0x1484
#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483
#define mmBIF_RESET_EN 0x1482
#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481
#define mmBIF_BACO_MSIC 0x1480
#define mmBIF_RESET_CNTL 0x1486
#define mmBIF_RFE_CNTL_MISC 0x148c
#endif /* BIF_4_1_D_H */
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_10_0_2_OFFSET_HEADER
#define _clk_10_0_2_OFFSET_HEADER
// addressBlock: clk_clk1_0_SmuClkDec
// base address: 0x5b800
#define mmCLK1_CLK_PLL_REQ 0x000f
#define mmCLK1_CLK_PLL_REQ_BASE_IDX 1
#define mmCLK1_CLK0_BYPASS_CNTL 0x0049
#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK1_BYPASS_CNTL 0x0053
#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK2_BYPASS_CNTL 0x005d
#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK2_STATUS 0x005e
#define mmCLK1_CLK2_STATUS_BASE_IDX 1
#define mmCLK1_CLK3_DFS_CNTL 0x005f
#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX 1
#define mmCLK1_CLK3_DS_CNTL 0x0060
#define mmCLK1_CLK3_DS_CNTL_BASE_IDX 1
#define mmCLK1_CLK3_ALLOW_DS 0x0061
#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX 1
#define mmCLK1_CLK3_BYPASS_CNTL 0x0067
#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK0_CURRENT_CNT 0x008a
#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX 1
#define mmCLK1_CLK1_CURRENT_CNT 0x008b
#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX 1
#define mmCLK1_CLK2_CURRENT_CNT 0x008c
#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX 1
#define mmCLK1_CLK3_CURRENT_CNT 0x008d
#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX 1
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_10_0_2_SH_MASK_HEADER
#define _clk_10_0_2_SH_MASK_HEADER
// addressBlock: clk_clk1_0_SmuClkDec
//CLK1_CLK_PLL_REQ
#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
//CLK1_CLK0_BYPASS_CNTL
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L
//CLK1_CLK1_BYPASS_CNTL
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L
//CLK1_CLK2_BYPASS_CNTL
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
//CLK1_CLK3_DS_CNTL
#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0
#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L
//CLK1_CLK3_ALLOW_DS
#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0
#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L
//CLK1_CLK3_BYPASS_CNTL
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L
//CLK1_CLK0_CURRENT_CNT
#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
//CLK1_CLK1_CURRENT_CNT
#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
//CLK1_CLK2_CURRENT_CNT
#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
//CLK1_CLK3_CURRENT_CNT
#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_11_0_0_OFFSET_HEADER
#define _clk_11_0_0_OFFSET_HEADER
// addressBlock: clk_clk3_0_SmuClkDec
// base address: 0x5c800
#define mmCLK3_0_CLK3_CLK_PLL_REQ 0x000e
#define mmCLK3_0_CLK3_CLK_PLL_REQ_BASE_IDX 3
#define mmCLK3_0_CLK3_CLK2_DFS_CNTL 0x0054
#define mmCLK3_0_CLK3_CLK2_DFS_CNTL_BASE_IDX 3
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_11_0_0_SH_MASK_HEADER
#define _clk_11_0_0_SH_MASK_HEADER
// addressBlock: clk_clk3_0_SmuClkDec
//CLK3_0_CLK3_CLK_PLL_REQ
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
//CLK3_0_CLK3_CLK2_DFS_CNTL
#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER__SHIFT 0x0
#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER_MASK 0x0000007FL
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_offset.h
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/*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_11_0_1_OFFSET_HEADER
#define _clk_11_0_1_OFFSET_HEADER
#define mmCLK4_0_CLK4_CLK_PLL_REQ 0x460e
#define mmCLK4_0_CLK4_CLK_PLL_REQ_BASE_IDX 0
#define mmCLK4_0_CLK4_CLK2_CURRENT_CNT 0x467f
#define mmCLK4_0_CLK4_CLK2_CURRENT_CNT_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_sh_mask.h
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/*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_11_0_1_SH_MASK_HEADER
#define _clk_11_0_1_SH_MASK_HEADER
//CLK4_0_CLK4_CLK_PLL_REQ
#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK4_0_CLK4_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK4_0_CLK4_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
//CLK4_0_CLK4_CLK2_CURRENT_CNT
#define CLK4_0_CLK4_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK4_0_CLK4_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h
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/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_11_5_0_OFFSET_HEADER
#define _clk_11_5_0_OFFSET_HEADER
// addressBlock: clk_clk1_0_SmuClkDec
// base address: 0x5c000
#define mmCLK1_0_CLK1_CLK_PLL_REQ 0x0410
#define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL 0x044a
#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL 0x0454
#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL 0x045e
#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK3_DS_CNTL 0x0461
#define mmCLK1_0_CLK1_CLK3_DS_CNTL_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK3_ALLOW_DS 0x0462
#define mmCLK1_0_CLK1_CLK3_ALLOW_DS_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL 0x0468
#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT 0x04a7
#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT 0x04a8
#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT 0x04a9
#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT_BASE_IDX 0
#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT 0x04aa
#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h
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/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _clk_11_5_0_SH_MASK_HEADER
#define _clk_11_5_0_SH_MASK_HEADER
// addressBlock: clk_clk1_0_SmuClkDec
//CLK1_0_CLK1_CLK_PLL_REQ
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
//CLK1_0_CLK1_CLK0_BYPASS_CNTL
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L
//CLK1_0_CLK1_CLK1_BYPASS_CNTL
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L
//CLK1_0_CLK1_CLK2_BYPASS_CNTL
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
//CLK1_0_CLK1_CLK3_DS_CNTL
#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0
#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L
//CLK1_0_CLK1_CLK3_ALLOW_DS
#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0
#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L
//CLK1_0_CLK1_CLK3_BYPASS_CNTL
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L
//CLK1_0_CLK1_CLK0_CURRENT_CNT
#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
//CLK1_0_CLK1_CLK1_CURRENT_CNT
#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
//CLK1_0_CLK1_CLK2_CURRENT_CNT
#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
//CLK1_0_CLK1_CLK3_CURRENT_CNT
#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0
#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h
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/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */
#ifndef _clk_15_0_0_OFFSET_HEADER
#define _clk_15_0_0_OFFSET_HEADER
// addressBlock: clk_clk8_0_SmuClkDec
// base address: 0x6e000
#define regCLK8_CLK0_DS_CNTL 0x4c14
#define regCLK8_CLK0_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK1_DS_CNTL 0x4c1c
#define regCLK8_CLK1_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK2_DS_CNTL 0x4c24
#define regCLK8_CLK2_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK3_DS_CNTL 0x4c2c
#define regCLK8_CLK3_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK4_DS_CNTL 0x4c34
#define regCLK8_CLK4_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK0_BYPASS_CNTL 0x4c1a
#define regCLK8_CLK0_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK1_BYPASS_CNTL 0x4c22
#define regCLK8_CLK1_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK2_BYPASS_CNTL 0x4c2a
#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK3_BYPASS_CNTL 0x4c32
#define regCLK8_CLK3_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK4_BYPASS_CNTL 0x4c3a
#define regCLK8_CLK4_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK_TICK_CNT_CONFIG_REG 0x4c51
#define regCLK8_CLK_TICK_CNT_CONFIG_REG_BASE_IDX 0
#define regCLK8_CLK_TICK_CNT_STATUS 0x4c52
#define regCLK8_CLK_TICK_CNT_STATUS_BASE_IDX 0
#define regCLK8_CLK0_CURRENT_CNT 0x4c53
#define regCLK8_CLK0_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK1_CURRENT_CNT 0x4c54
#define regCLK8_CLK1_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK2_CURRENT_CNT 0x4c55
#define regCLK8_CLK2_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK3_CURRENT_CNT 0x4c56
#define regCLK8_CLK3_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK4_CURRENT_CNT 0x4c57
#define regCLK8_CLK4_CURRENT_CNT_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h
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/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */
#ifndef _clk_15_0_0_SH_MASK_HEADER
#define _clk_15_0_0_SH_MASK_HEADER
// addressBlock: clk_clk8_0_SmuClkDec
//CLK8_CLK_TICK_CNT_CONFIG_REG
#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT 0x0
#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK 0xFFFFL
//CLK8_CLK0_BYPASS_CNTL
#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0
#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L
//CLK8_CLK1_BYPASS_CNTL
#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0
#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L
//CLK8_CLK2_BYPASS_CNTL
#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
//CLK8_CLK3_BYPASS_CNTL
#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0
#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L
//CLK8_CLK4_BYPASS_CNTL
#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL__SHIFT 0x0
#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL_MASK 0x00000007L
//CLK8_CLK0_DS_CNTL
#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT 0x0
#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK 0x0000000FL
#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT 0x4
#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK 0x00000010L
//CLK8_CLK1_DS_CNTL
#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT 0x0
#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK 0x0000000FL
#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT 0x4
#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK 0x00000010L
//CLK8_CLK2_DS_CNTL
#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT 0x0
#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK 0x0000000FL
#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT 0x4
#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK 0x00000010L
//CLK8_CLK3_DS_CNTL
#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0
#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x0000000FL
#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT 0x4
#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK 0x00000010L
//CLK8_CLK4_DS_CNTL
#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID__SHIFT 0x0
#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID_MASK 0x0000000FL
#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS__SHIFT 0x4
#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS_MASK 0x00000010L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_offset.h
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _clk_15_0_5_OFFSET_HEADER
#define _clk_15_0_5_OFFSET_HEADER
// addressBlock: clk_clk5_0_SmuClkDec
// base address: 0x6c800
#define regCLK5_CLK0_DS_CNTL 0x4604
#define regCLK5_CLK0_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK0_BYPASS_CNTL 0x460a
#define regCLK5_CLK0_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK1_DS_CNTL 0x460c
#define regCLK5_CLK1_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK1_BYPASS_CNTL 0x4612
#define regCLK5_CLK1_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK2_DS_CNTL 0x4614
#define regCLK5_CLK2_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK2_BYPASS_CNTL 0x461a
#define regCLK5_CLK2_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK3_DS_CNTL 0x461c
#define regCLK5_CLK3_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK3_BYPASS_CNTL 0x4622
#define regCLK5_CLK3_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK_TICK_CNT_CONFIG_REG 0x4629
#define regCLK5_CLK_TICK_CNT_CONFIG_REG_BASE_IDX 0
#define regCLK5_CLK_TICK_CNT_STATUS 0x462a
#define regCLK5_CLK_TICK_CNT_STATUS_BASE_IDX 0
#define regCLK5_CLK0_CURRENT_CNT 0x462b
#define regCLK5_CLK0_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK1_CURRENT_CNT 0x462c
#define regCLK5_CLK1_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK2_CURRENT_CNT 0x462d
#define regCLK5_CLK2_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK3_CURRENT_CNT 0x462e
#define regCLK5_CLK3_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK4_CURRENT_CNT 0x462f
#define regCLK5_CLK4_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK5_CURRENT_CNT 0x4630
#define regCLK5_CLK5_CURRENT_CNT_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _clk_15_0_5_SH_MASK_HEADER
#define _clk_15_0_5_SH_MASK_HEADER
// addressBlock: clk_clk5_0_SmuClkDec
//CLK5_CLK_TICK_CNT_CONFIG_REG
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT 0x0
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK 0x00FFFFFFL
//CLK5_CLK0_BYPASS_CNTL
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK1_BYPASS_CNTL
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK2_BYPASS_CNTL
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK3_BYPASS_CNTL
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK0_DS_CNTL
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK 0x00000010L
//CLK5_CLK1_DS_CNTL
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK 0x00000010L
//CLK5_CLK2_DS_CNTL
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK 0x00000010L
//CLK5_CLK3_DS_CNTL
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK 0x00000010L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_1_sh_mask.h
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