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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_10_0_2_OFFSET_HEADER
+#define _clk_10_0_2_OFFSET_HEADER
+
+
+
+// addressBlock: clk_clk1_0_SmuClkDec
+// base address: 0x5b800
+#define mmCLK1_CLK_PLL_REQ                                                                             0x000f
+#define mmCLK1_CLK_PLL_REQ_BASE_IDX                                                                    1
+#define mmCLK1_CLK0_BYPASS_CNTL                                                                        0x0049
+#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                               1
+#define mmCLK1_CLK1_BYPASS_CNTL                                                                        0x0053
+#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                               1
+#define mmCLK1_CLK2_BYPASS_CNTL                                                                        0x005d
+#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                               1
+#define mmCLK1_CLK2_STATUS                                                                             0x005e
+#define mmCLK1_CLK2_STATUS_BASE_IDX                                                                    1
+#define mmCLK1_CLK3_DFS_CNTL                                                                           0x005f
+#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX                                                                  1
+#define mmCLK1_CLK3_DS_CNTL                                                                            0x0060
+#define mmCLK1_CLK3_DS_CNTL_BASE_IDX                                                                   1
+#define mmCLK1_CLK3_ALLOW_DS                                                                           0x0061
+#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX                                                                  1
+#define mmCLK1_CLK3_BYPASS_CNTL                                                                        0x0067
+#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                               1
+#define mmCLK1_CLK0_CURRENT_CNT                                                                        0x008a
+#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX                                                               1
+#define mmCLK1_CLK1_CURRENT_CNT                                                                        0x008b
+#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX                                                               1
+#define mmCLK1_CLK2_CURRENT_CNT                                                                        0x008c
+#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX                                                               1
+#define mmCLK1_CLK3_CURRENT_CNT                                                                        0x008d
+#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX                                                               1
+
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_10_0_2_SH_MASK_HEADER
+#define _clk_10_0_2_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk1_0_SmuClkDec
+//CLK1_CLK_PLL_REQ
+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
+//CLK1_CLK0_BYPASS_CNTL
+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                         0x10
+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                           0x000F0000L
+//CLK1_CLK1_BYPASS_CNTL
+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                         0x10
+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                           0x000F0000L
+//CLK1_CLK2_BYPASS_CNTL
+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                         0x10
+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                           0x000F0000L
+//CLK1_CLK3_DS_CNTL
+#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x00000007L
+//CLK1_CLK3_ALLOW_DS
+#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                              0x0
+#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                                0x00000001L
+//CLK1_CLK3_BYPASS_CNTL
+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                         0x10
+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                           0x000F0000L
+//CLK1_CLK0_CURRENT_CNT
+#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
+#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
+//CLK1_CLK1_CURRENT_CNT
+#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
+#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
+//CLK1_CLK2_CURRENT_CNT
+#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
+#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
+//CLK1_CLK3_CURRENT_CNT
+#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
+#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
+
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_0_0_OFFSET_HEADER
+#define _clk_11_0_0_OFFSET_HEADER
+
+
+// addressBlock: clk_clk3_0_SmuClkDec
+// base address: 0x5c800
+#define mmCLK3_0_CLK3_CLK_PLL_REQ                                                                      0x000e
+#define mmCLK3_0_CLK3_CLK_PLL_REQ_BASE_IDX                                                             3
+#define mmCLK3_0_CLK3_CLK2_DFS_CNTL                                                                    0x0054
+#define mmCLK3_0_CLK3_CLK2_DFS_CNTL_BASE_IDX                                                           3
+
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_0_0_SH_MASK_HEADER
+#define _clk_11_0_0_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk3_0_SmuClkDec
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+//CLK3_0_CLK3_CLK2_DFS_CNTL
+#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER__SHIFT                                                        0x0
+#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER_MASK                                                          0x0000007FL
+
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_offset.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _clk_11_0_1_OFFSET_HEADER
+#define _clk_11_0_1_OFFSET_HEADER
+
+#define mmCLK4_0_CLK4_CLK_PLL_REQ                                                                      0x460e
+#define mmCLK4_0_CLK4_CLK_PLL_REQ_BASE_IDX                                                             0
+
+#define mmCLK4_0_CLK4_CLK2_CURRENT_CNT                                                                 0x467f
+#define mmCLK4_0_CLK4_CLK2_CURRENT_CNT_BASE_IDX                                                        0
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_sh_mask.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _clk_11_0_1_SH_MASK_HEADER
+#define _clk_11_0_1_SH_MASK_HEADER
+
+//CLK4_0_CLK4_CLK_PLL_REQ
+#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK4_0_CLK4_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc
+#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK4_0_CLK4_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L
+#define CLK4_0_CLK4_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+
+//CLK4_0_CLK4_CLK2_CURRENT_CNT
+#define CLK4_0_CLK4_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK4_0_CLK4_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_5_0_OFFSET_HEADER
+#define _clk_11_5_0_OFFSET_HEADER
+
+
+// addressBlock: clk_clk1_0_SmuClkDec
+// base address: 0x5c000
+#define mmCLK1_0_CLK1_CLK_PLL_REQ                                                                      0x0410
+#define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX                                                             0
+#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL                                                                 0x044a
+#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL                                                                 0x0454
+#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL                                                                 0x045e
+#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK3_DS_CNTL                                                                     0x0461
+#define mmCLK1_0_CLK1_CLK3_DS_CNTL_BASE_IDX                                                            0
+#define mmCLK1_0_CLK1_CLK3_ALLOW_DS                                                                    0x0462
+#define mmCLK1_0_CLK1_CLK3_ALLOW_DS_BASE_IDX                                                           0
+#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL                                                                 0x0468
+#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT                                                                 0x04a7
+#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT                                                                 0x04a8
+#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT                                                                 0x04a9
+#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT                                                                 0x04aa
+#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT_BASE_IDX                                                        0
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_5_0_SH_MASK_HEADER
+#define _clk_11_5_0_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk1_0_SmuClkDec
+//CLK1_0_CLK1_CLK_PLL_REQ
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+//CLK1_0_CLK1_CLK0_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK1_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK2_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK3_DS_CNTL
+#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                       0x0
+#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                         0x00000007L
+//CLK1_0_CLK1_CLK3_ALLOW_DS
+#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                       0x0
+#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                         0x00000001L
+//CLK1_0_CLK1_CLK3_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK0_CURRENT_CNT
+#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+//CLK1_0_CLK1_CLK1_CURRENT_CNT
+#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+//CLK1_0_CLK1_CLK2_CURRENT_CNT
+#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+//CLK1_0_CLK1_CLK3_CURRENT_CNT
+#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2026 Advanced Micro Devices, Inc. */
+
+#ifndef _clk_15_0_0_OFFSET_HEADER
+#define _clk_15_0_0_OFFSET_HEADER
+
+// addressBlock: clk_clk8_0_SmuClkDec
+// base address: 0x6e000
+#define regCLK8_CLK0_DS_CNTL                                                                            0x4c14
+#define regCLK8_CLK0_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK8_CLK1_DS_CNTL                                                                            0x4c1c
+#define regCLK8_CLK1_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK8_CLK2_DS_CNTL                                                                            0x4c24
+#define regCLK8_CLK2_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK8_CLK3_DS_CNTL                                                                            0x4c2c
+#define regCLK8_CLK3_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK8_CLK4_DS_CNTL                                                                            0x4c34
+#define regCLK8_CLK4_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK8_CLK0_BYPASS_CNTL                                                                        0x4c1a
+#define regCLK8_CLK0_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK8_CLK1_BYPASS_CNTL                                                                        0x4c22
+#define regCLK8_CLK1_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK8_CLK2_BYPASS_CNTL                                                                        0x4c2a
+#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK8_CLK3_BYPASS_CNTL                                                                        0x4c32
+#define regCLK8_CLK3_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK8_CLK4_BYPASS_CNTL                                                                        0x4c3a
+#define regCLK8_CLK4_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK8_CLK_TICK_CNT_CONFIG_REG                                                                 0x4c51
+#define regCLK8_CLK_TICK_CNT_CONFIG_REG_BASE_IDX                                                        0
+#define regCLK8_CLK_TICK_CNT_STATUS                                                                     0x4c52
+#define regCLK8_CLK_TICK_CNT_STATUS_BASE_IDX                                                            0
+#define regCLK8_CLK0_CURRENT_CNT                                                                        0x4c53
+#define regCLK8_CLK0_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK8_CLK1_CURRENT_CNT                                                                        0x4c54
+#define regCLK8_CLK1_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK8_CLK2_CURRENT_CNT                                                                        0x4c55
+#define regCLK8_CLK2_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK8_CLK3_CURRENT_CNT                                                                        0x4c56
+#define regCLK8_CLK3_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK8_CLK4_CURRENT_CNT                                                                        0x4c57
+#define regCLK8_CLK4_CURRENT_CNT_BASE_IDX                                                               0
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2026 Advanced Micro Devices, Inc. */
+
+#ifndef _clk_15_0_0_SH_MASK_HEADER
+#define _clk_15_0_0_SH_MASK_HEADER
+
+// addressBlock: clk_clk8_0_SmuClkDec
+//CLK8_CLK_TICK_CNT_CONFIG_REG
+#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT                                                   0x0
+#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK                                                     0xFFFFL
+//CLK8_CLK0_BYPASS_CNTL
+#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK8_CLK1_BYPASS_CNTL
+#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK8_CLK2_BYPASS_CNTL
+#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK8_CLK3_BYPASS_CNTL
+#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK8_CLK4_BYPASS_CNTL
+#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK8_CLK0_DS_CNTL
+#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT                                                              0x4
+#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK                                                                0x00000010L
+//CLK8_CLK1_DS_CNTL
+#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT                                                              0x4
+#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK                                                                0x00000010L
+//CLK8_CLK2_DS_CNTL
+#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT                                                              0x4
+#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK                                                                0x00000010L
+//CLK8_CLK3_DS_CNTL
+#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT                                                              0x4
+#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK                                                                0x00000010L
+//CLK8_CLK4_DS_CNTL
+#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS__SHIFT                                                              0x4
+#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS_MASK                                                                0x00000010L
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_offset.h

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: MIT
+// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
+
+#ifndef _clk_15_0_5_OFFSET_HEADER
+#define _clk_15_0_5_OFFSET_HEADER
+
+// addressBlock: clk_clk5_0_SmuClkDec
+// base address: 0x6c800
+#define regCLK5_CLK0_DS_CNTL                                                                            0x4604
+#define regCLK5_CLK0_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK5_CLK0_BYPASS_CNTL                                                                        0x460a
+#define regCLK5_CLK0_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK5_CLK1_DS_CNTL                                                                            0x460c
+#define regCLK5_CLK1_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK5_CLK1_BYPASS_CNTL                                                                        0x4612
+#define regCLK5_CLK1_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK5_CLK2_DS_CNTL                                                                            0x4614
+#define regCLK5_CLK2_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK5_CLK2_BYPASS_CNTL                                                                        0x461a
+#define regCLK5_CLK2_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK5_CLK3_DS_CNTL                                                                            0x461c
+#define regCLK5_CLK3_DS_CNTL_BASE_IDX                                                                   0
+#define regCLK5_CLK3_BYPASS_CNTL                                                                        0x4622
+#define regCLK5_CLK3_BYPASS_CNTL_BASE_IDX                                                               0
+#define regCLK5_CLK_TICK_CNT_CONFIG_REG                                                                 0x4629
+#define regCLK5_CLK_TICK_CNT_CONFIG_REG_BASE_IDX                                                        0
+#define regCLK5_CLK_TICK_CNT_STATUS                                                                     0x462a
+#define regCLK5_CLK_TICK_CNT_STATUS_BASE_IDX                                                            0
+#define regCLK5_CLK0_CURRENT_CNT                                                                        0x462b
+#define regCLK5_CLK0_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK5_CLK1_CURRENT_CNT                                                                        0x462c
+#define regCLK5_CLK1_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK5_CLK2_CURRENT_CNT                                                                        0x462d
+#define regCLK5_CLK2_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK5_CLK3_CURRENT_CNT                                                                        0x462e
+#define regCLK5_CLK3_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK5_CLK4_CURRENT_CNT                                                                        0x462f
+#define regCLK5_CLK4_CURRENT_CNT_BASE_IDX                                                               0
+#define regCLK5_CLK5_CURRENT_CNT                                                                        0x4630
+#define regCLK5_CLK5_CURRENT_CNT_BASE_IDX                                                               0
+
+#endif

linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
+
+#ifndef _clk_15_0_5_SH_MASK_HEADER
+#define _clk_15_0_5_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk5_0_SmuClkDec
+//CLK5_CLK_TICK_CNT_CONFIG_REG
+#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT                                                  0x0
+#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK                                                    0x00FFFFFFL
+//CLK5_CLK0_BYPASS_CNTL
+#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK5_CLK1_BYPASS_CNTL
+#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK5_CLK2_BYPASS_CNTL
+#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK5_CLK3_BYPASS_CNTL
+#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
+#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
+//CLK5_CLK0_DS_CNTL
+#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT                                                               0x4
+#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK                                                                 0x00000010L
+//CLK5_CLK1_DS_CNTL
+#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT                                                               0x4
+#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK                                                                 0x00000010L
+//CLK5_CLK2_DS_CNTL
+#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT                                                               0x4
+#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK                                                                 0x00000010L
+//CLK5_CLK3_DS_CNTL
+#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
+#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x0000000FL
+#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT                                                               0x4
+#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK                                                                 0x00000010L
+
+#endif