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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_0_offset.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dpcs_2_0_0_OFFSET_HEADER
#define _dpcs_2_0_0_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL 0x2937
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2 0x2938
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2939
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06
#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL 0x2a0f
#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL2 0x2a10
#define mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a11
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
// base address: 0x6c0
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9
#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada
#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade
#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
// base address: 0x6c0
#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0
#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5
#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL 0x2ae7
#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL2 0x2ae8
#define mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae9
#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr2_dispdec
// base address: 0x6c0
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
// base address: 0xa20
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1
#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6
#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
// base address: 0xa20
#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8
#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd
#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL 0x2bbf
#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL2 0x2bc0
#define mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bc1
#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr3_dispdec
// base address: 0xa20
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcsrx_dispdec
// base address: 0x0
#define mmDPCSRX_PHY_CNTL 0x2c76
#define mmDPCSRX_PHY_CNTL_BASE_IDX 2
#define mmDPCSRX_RX_CLOCK_CNTL 0x2c78
#define mmDPCSRX_RX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSRX_RX_CNTL 0x2c7a
#define mmDPCSRX_RX_CNTL_BASE_IDX 2
#define mmDPCSRX_CBUS_CNTL 0x2c7b
#define mmDPCSRX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSRX_REG_ERROR_STATUS 0x2c7c
#define mmDPCSRX_REG_ERROR_STATUS_BASE_IDX 2
#define mmDPCSRX_RX_ERROR_STATUS 0x2c7d
#define mmDPCSRX_RX_ERROR_STATUS_BASE_IDX 2
#define mmDPCSRX_INDEX_MODE_ADDR 0x2c80
#define mmDPCSRX_INDEX_MODE_ADDR_BASE_IDX 2
#define mmDPCSRX_INDEX_MODE_DATA 0x2c81
#define mmDPCSRX_INDEX_MODE_DATA_BASE_IDX 2
#define mmDPCSRX_DEBUG_CONFIG 0x2c82
#define mmDPCSRX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
// base address: 0xd80
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89
#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a
#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e
#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
// base address: 0xd80
#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90
#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95
#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL 0x2c97
#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL2 0x2c98
#define mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c99
#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr4_dispdec
// base address: 0xd80
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx5_dispdec
// base address: 0x10e0
#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0x2d60
#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_TX_CNTL 0x2d61
#define mmDPCSTX5_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_CBUS_CNTL 0x2d62
#define mmDPCSTX5_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL 0x2d63
#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0x2d64
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x2d65
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0x2d66
#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec
// base address: 0x10e0
#define mmRDPCSTX5_RDPCSTX_CNTL 0x2d68
#define mmRDPCSTX5_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL 0x2d69
#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL 0x2d6a
#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA 0x2d6b
#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_CR_ADDR 0x2d6c
#define mmRDPCSTX5_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_CR_DATA 0x2d6d
#define mmRDPCSTX5_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL 0x2d6e
#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL 0x2d6f
#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL2 0x2d70
#define mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_SCRATCH 0x2d71
#define mmRDPCSTX5_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2d74
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG 0x2d75
#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0 0x2d78
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1 0x2d79
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2 0x2d7a
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3 0x2d7b
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4 0x2d7c
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5 0x2d7d
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6 0x2d7e
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7 0x2d7f
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8 0x2d80
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9 0x2d81
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10 0x2d82
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11 0x2d83
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12 0x2d84
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13 0x2d85
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14 0x2d86
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0 0x2d87
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1 0x2d88
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2 0x2d89
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3 0x2d8a
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL 0x2d8b
#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2d8c
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2d8d
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG 0x2d8e
#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr5_dispdec
// base address: 0x10e0
#define mmDPCSSYS_CR5_DPCSSYS_CR_ADDR 0x2d6c
#define mmDPCSSYS_CR5_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR5_DPCSSYS_CR_DATA 0x2d6d
#define mmDPCSSYS_CR5_DPCSSYS_CR_DATA_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_0_sh_mask.h
+3912
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_offset.h
+151
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@@ -0,0 +1,151 @@
/*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dpcs_2_0_3_OFFSET_HEADER
#define _dpcs_2_0_3_OFFSET_HEADER
// addressBlock: dpcssysa_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssysa_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2939
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
// addressBlock: dpcssysa_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssysa_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a11
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_sh_mask.h
+952
View File
@@ -0,0 +1,952 @@
/*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dpcs_2_0_3_SH_MASK_HEADER
#define _dpcs_2_0_3_SH_MASK_HEADER
// addressBlock: dpcssysa_dpcs0_dpcstx0_dispdec
//DPCSTX0_DPCSTX_TX_CLOCK_CNTL
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
//DPCSTX0_DPCSTX_TX_CNTL
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L
//DPCSTX0_DPCSTX_CBUS_CNTL
#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0
#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f
#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL
#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L
//DPCSTX0_DPCSTX_INTERRUPT_CNTL
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L
#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L
//DPCSTX0_DPCSTX_PLL_UPDATE_ADDR
#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0
#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL
//DPCSTX0_DPCSTX_PLL_UPDATE_DATA
#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0
#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL
//DPCSTX0_DPCSTX_DEBUG_CONFIG
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x4
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x8
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x00000001L
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x0000000EL
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x00000070L
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0x00000700L
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x00010000L
#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xFF000000L
//DPCSTX0_DPCSTX_TEST_DEBUG_DATA
#define DPCSTX0_DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA__SHIFT 0x0
#define DPCSTX0_DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
// addressBlock: dpcssysa_dpcs0_rdpcstx0_dispdec
//RDPCSTX0_RDPCSTX_CNTL
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L
//RDPCSTX0_RDPCSTX_CLOCK_CNTL
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L
//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L
//RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA
#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L
//RDPCSTX0_RDPCS_TX_CR_ADDR
#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
//RDPCSTX0_RDPCS_TX_CR_DATA
#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
//RDPCSTX0_RDPCSTX_SCRATCH
#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL
//RDPCSTX0_RDPCSTX_PHY_CNTL0
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0xe
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x0001C000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL1
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L
//RDPCSTX0_RDPCSTX_PHY_CNTL2
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DP4__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DP4_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE_MASK 0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L
//RDPCSTX0_RDPCSTX_PHY_CNTL3
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL4
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL5
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0xb
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x15
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x1a
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0x1b
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x0000000CL
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x000000E0L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000300L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000800L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x000C0000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00E00000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x03000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x04000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x08000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x10000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL6
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0xb
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x15
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0x1a
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1b
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x0000000CL
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_LPD_MASK 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_RATE_MASK 0x000000E0L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00000300L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00000800L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00001000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x000C0000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_LPD_MASK 0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_RATE_MASK 0x00E00000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x03000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x04000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x08000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x10000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL7
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L
//RDPCSTX0_RDPCSTX_PHY_CNTL8
#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL
//RDPCSTX0_RDPCSTX_PHY_CNTL9
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL10
#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL
//RDPCSTX0_RDPCSTX_PHY_CNTL11
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL12
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L
//RDPCSTX0_RDPCSTX_PHY_CNTL13
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL14
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L
//RDPCSTX0_RDPCSTX_PHY_FUSE0
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L
//RDPCSTX0_RDPCSTX_PHY_FUSE1
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L
//RDPCSTX0_RDPCSTX_PHY_FUSE2
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L
//RDPCSTX0_RDPCSTX_PHY_FUSE3
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L
//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L
// addressBlock: dpcssysa_dpcssys_cr0_dispdec
//DPCSSYS_CR0_DPCSSYS_CR_ADDR
#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
//DPCSSYS_CR0_DPCSSYS_CR_DATA
#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
// addressBlock: dpcssysa_dpcs0_dpcstx1_dispdec
//DPCSTX1_DPCSTX_TX_CLOCK_CNTL
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
//DPCSTX1_DPCSTX_TX_CNTL
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L
#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L
//DPCSTX1_DPCSTX_CBUS_CNTL
#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0
#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f
#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL
#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L
//DPCSTX1_DPCSTX_INTERRUPT_CNTL
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L
#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L
//DPCSTX1_DPCSTX_PLL_UPDATE_ADDR
#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0
#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL
//DPCSTX1_DPCSTX_PLL_UPDATE_DATA
#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0
#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL
// addressBlock: dpcssysa_dpcs0_rdpcstx1_dispdec
//RDPCSTX1_RDPCSTX_CNTL
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L
//RDPCSTX1_RDPCSTX_CLOCK_CNTL
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L
//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L
//RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA
#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L
//RDPCSTX1_RDPCS_TX_CR_ADDR
#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
//RDPCSTX1_RDPCS_TX_CR_DATA
#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
//RDPCSTX1_RDPCS_TX_SRAM_CNTL
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L
//RDPCSTX1_RDPCSTX_SCRATCH
#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL
//RDPCSTX1_RDPCSTX_PHY_CNTL0
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0xe
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x0001C000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL1
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L
//RDPCSTX1_RDPCSTX_PHY_CNTL2
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DP4__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DP4_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE_MASK 0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L
//RDPCSTX1_RDPCSTX_PHY_CNTL3
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL4
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL5
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0xb
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x15
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x1a
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0x1b
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x0000000CL
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x000000E0L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000300L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000800L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x000C0000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00E00000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x03000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x04000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x08000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x10000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL6
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0xb
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x15
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0x1a
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1b
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x0000000CL
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_LPD_MASK 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_RATE_MASK 0x000000E0L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00000300L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00000800L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00001000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x000C0000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_LPD_MASK 0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_RATE_MASK 0x00E00000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x03000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x04000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x08000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x10000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL7
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L
//RDPCSTX1_RDPCSTX_PHY_CNTL8
#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL
//RDPCSTX1_RDPCSTX_PHY_CNTL9
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL10
#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL
//RDPCSTX1_RDPCSTX_PHY_CNTL11
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL12
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L
//RDPCSTX1_RDPCSTX_PHY_CNTL13
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL14
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_1_0_offset.h
+565
View File
@@ -0,0 +1,565 @@
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dpcs_2_1_0_OFFSET_HEADER
#define _dpcs_2_1_0_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938
#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939
#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06
#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10
#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11
#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
// base address: 0x6c0
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9
#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada
#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade
#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
// base address: 0x6c0
#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0
#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5
#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7
#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SPARE 0x2ae8
#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CNTL2 0x2ae9
#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr2_dispdec
// base address: 0x6c0
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
// base address: 0xa20
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1
#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6
#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
// base address: 0xa20
#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8
#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd
#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf
#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SPARE 0x2bc0
#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CNTL2 0x2bc1
#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr3_dispdec
// base address: 0xa20
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
// base address: 0xd80
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89
#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a
#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e
#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
// base address: 0xd80
#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90
#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95
#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c97
#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SPARE 0x2c98
#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CNTL2 0x2c99
#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2 0x2cbb
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr4_dispdec
// base address: 0xd80
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_1_0_sh_mask.h
+3430
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h
+604
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@@ -0,0 +1,604 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Authors: AMD
*/
#ifndef _dpcs_3_0_0_OFFSET_HEADER
#define _dpcs_3_0_0_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938
#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939
#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06
#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10
#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11
#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15
#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
// base address: 0x6c0
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9
#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada
#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade
#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
// base address: 0x6c0
#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0
#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5
#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7
#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SPARE 0x2ae8
#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CNTL2 0x2ae9
#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed
#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr2_dispdec
// base address: 0x6c0
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
// base address: 0xa20
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1
#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6
#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
// base address: 0xa20
#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8
#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd
#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf
#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SPARE 0x2bc0
#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CNTL2 0x2bc1
#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5
#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr3_dispdec
// base address: 0xa20
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
// base address: 0xd80
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89
#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a
#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e
#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
// base address: 0xd80
#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90
#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95
#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c97
#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SPARE 0x2c98
#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CNTL2 0x2c99
#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d
#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr4_dispdec
// base address: 0xd80
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx5_dispdec
// base address: 0x10e0
#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0x2d60
#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_TX_CNTL 0x2d61
#define mmDPCSTX5_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_CBUS_CNTL 0x2d62
#define mmDPCSTX5_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL 0x2d63
#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0x2d64
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x2d65
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0x2d66
#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec
// base address: 0x10e0
#define mmRDPCSTX5_RDPCSTX_CNTL 0x2d68
#define mmRDPCSTX5_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL 0x2d69
#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL 0x2d6a
#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA 0x2d6b
#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_CR_ADDR 0x2d6c
#define mmRDPCSTX5_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_CR_DATA 0x2d6d
#define mmRDPCSTX5_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL 0x2d6e
#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_SCRATCH 0x2d6f
#define mmRDPCSTX5_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_SPARE 0x2d70
#define mmRDPCSTX5_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_CNTL2 0x2d71
#define mmRDPCSTX5_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2d74
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG 0x2d75
#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0 0x2d78
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1 0x2d79
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2 0x2d7a
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3 0x2d7b
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4 0x2d7c
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5 0x2d7d
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6 0x2d7e
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7 0x2d7f
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8 0x2d80
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9 0x2d81
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10 0x2d82
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11 0x2d83
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12 0x2d84
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13 0x2d85
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14 0x2d86
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0 0x2d87
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1 0x2d88
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2 0x2d89
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3 0x2d8a
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL 0x2d8b
#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2d8c
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2d8d
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG 0x2d8e
#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_3_offset.h
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// SPDX-License-Identifier: MIT
/*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Authors: AMD
*/
#ifndef _dpcs_3_0_3_OFFSET_HEADER
#define _dpcs_3_0_3_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938
#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939
#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10
#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11
#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_3_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h
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/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */
#ifndef _dpcs_4_0_0_OFFSET_HEADER
#define _dpcs_4_0_0_OFFSET_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
// base address: 0x0
#define regDC_GENERICA 0x2868
#define regDC_GENERICA_BASE_IDX 2
#define regDC_GENERICB 0x2869
#define regDC_GENERICB_BASE_IDX 2
#define regDCIO_CLOCK_CNTL 0x286a
#define regDCIO_CLOCK_CNTL_BASE_IDX 2
#define regDC_REF_CLK_CNTL 0x286b
#define regDC_REF_CLK_CNTL_BASE_IDX 2
#define regUNIPHYA_LINK_CNTL 0x286d
#define regUNIPHYA_LINK_CNTL_BASE_IDX 2
#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYB_LINK_CNTL 0x286f
#define regUNIPHYB_LINK_CNTL_BASE_IDX 2
#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYC_LINK_CNTL 0x2871
#define regUNIPHYC_LINK_CNTL_BASE_IDX 2
#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYD_LINK_CNTL 0x2873
#define regUNIPHYD_LINK_CNTL_BASE_IDX 2
#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYE_LINK_CNTL 0x2875
#define regUNIPHYE_LINK_CNTL_BASE_IDX 2
#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regDCIO_WRCMD_DELAY 0x287e
#define regDCIO_WRCMD_DELAY_BASE_IDX 2
#define regDC_PINSTRAPS 0x2880
#define regDC_PINSTRAPS_BASE_IDX 2
#define regDCIO_SPARE 0x2882
#define regDCIO_SPARE_BASE_IDX 2
#define regINTERCEPT_STATE 0x2884
#define regINTERCEPT_STATE_BASE_IDX 2
#define regDCIO_PATTERN_GEN_PAT 0x2886
#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2
#define regDCIO_PATTERN_GEN_EN 0x2887
#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2
#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define regDPCS_DCIO_TEST_CLK_SRC 0x2890
#define regDPCS_DCIO_TEST_CLK_SRC_BASE_IDX 2
#define regDCIO_DEBUG 0x2897
#define regDCIO_DEBUG_BASE_IDX 2
#define regDCIO_TEST_DEBUG_INDEX 0x2899
#define regDCIO_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDCIO_TEST_DEBUG_DATA 0x289a
#define regDCIO_TEST_DEBUG_DATA_BASE_IDX 2
#define regDBG_OUT_CNTL 0x289c
#define regDBG_OUT_CNTL_BASE_IDX 2
#define regDCIO_DEBUG_CONFIG 0x289d
#define regDCIO_DEBUG_CONFIG_BASE_IDX 2
#define regDCIO_SOFT_RESET 0x289e
#define regDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_DDC1_MASK 0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX 2
#define regDC_GPIO_DDC1_A 0x28d1
#define regDC_GPIO_DDC1_A_BASE_IDX 2
#define regDC_GPIO_DDC1_EN 0x28d2
#define regDC_GPIO_DDC1_EN_BASE_IDX 2
#define regDC_GPIO_DDC1_Y 0x28d3
#define regDC_GPIO_DDC1_Y_BASE_IDX 2
#define regDC_GPIO_DDC2_MASK 0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX 2
#define regDC_GPIO_DDC2_A 0x28d5
#define regDC_GPIO_DDC2_A_BASE_IDX 2
#define regDC_GPIO_DDC2_EN 0x28d6
#define regDC_GPIO_DDC2_EN_BASE_IDX 2
#define regDC_GPIO_DDC2_Y 0x28d7
#define regDC_GPIO_DDC2_Y_BASE_IDX 2
#define regDC_GPIO_DDC3_MASK 0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX 2
#define regDC_GPIO_DDC3_A 0x28d9
#define regDC_GPIO_DDC3_A_BASE_IDX 2
#define regDC_GPIO_DDC3_EN 0x28da
#define regDC_GPIO_DDC3_EN_BASE_IDX 2
#define regDC_GPIO_DDC3_Y 0x28db
#define regDC_GPIO_DDC3_Y_BASE_IDX 2
#define regDC_GPIO_DDC4_MASK 0x28dc
#define regDC_GPIO_DDC4_MASK_BASE_IDX 2
#define regDC_GPIO_DDC4_A 0x28dd
#define regDC_GPIO_DDC4_A_BASE_IDX 2
#define regDC_GPIO_DDC4_EN 0x28de
#define regDC_GPIO_DDC4_EN_BASE_IDX 2
#define regDC_GPIO_DDC4_Y 0x28df
#define regDC_GPIO_DDC4_Y_BASE_IDX 2
#define regDC_GPIO_DDC5_MASK 0x28e0
#define regDC_GPIO_DDC5_MASK_BASE_IDX 2
#define regDC_GPIO_DDC5_A 0x28e1
#define regDC_GPIO_DDC5_A_BASE_IDX 2
#define regDC_GPIO_DDC5_EN 0x28e2
#define regDC_GPIO_DDC5_EN_BASE_IDX 2
#define regDC_GPIO_DDC5_Y 0x28e3
#define regDC_GPIO_DDC5_Y_BASE_IDX 2
#define regDC_GPIO_DDCVGA_MASK 0x28e8
#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_A 0x28e9
#define regDC_GPIO_DDCVGA_A_BASE_IDX 2
#define regDC_GPIO_DDCVGA_EN 0x28ea
#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define regDC_GPIO_DDCVGA_Y 0x28eb
#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define regDC_GPIO_PWRSEQ0_EN 0x28fa
#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2
#define regDC_GPIO_PAD_STRENGTH_1 0x28fc
#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define regPHY_AUX_CNTL 0x28ff
#define regPHY_AUX_CNTL_BASE_IDX 2
#define regDC_GPIO_PWRSEQ1_EN 0x2902
#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_0 0x2916
#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_1 0x2917
#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_3 0x291b
#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_4 0x291c
#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_5 0x291d
#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define regAUXI2C_PAD_ALL_PWR_OK 0x291e
#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h
+688
View File
@@ -0,0 +1,688 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */
#ifndef _dpcs_4_0_0_SH_MASK_HEADER
#define _dpcs_4_0_0_SH_MASK_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
//DC_GENERICA
#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
//DC_GENERICB
#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
//DCIO_CLOCK_CNTL
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
//DC_REF_CLK_CNTL
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
//UNIPHYA_LINK_CNTL
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYA_CHANNEL_XBAR_CNTL
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYB_LINK_CNTL
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYB_CHANNEL_XBAR_CNTL
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYC_LINK_CNTL
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYC_CHANNEL_XBAR_CNTL
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYD_LINK_CNTL
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYD_CHANNEL_XBAR_CNTL
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYE_LINK_CNTL
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYE_CHANNEL_XBAR_CNTL
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//DCIO_WRCMD_DELAY
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L
//DC_PINSTRAPS
#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L
#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L
//DCIO_SPARE
#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0
#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL
//INTERCEPT_STATE
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0
#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1
#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT 0x2
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8
#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT 0x9
#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT 0xa
#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE__SHIFT 0x10
#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE__SHIFT 0x11
#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE__SHIFT 0x12
#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE__SHIFT 0x13
#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE__SHIFT 0x14
#define INTERCEPT_STATE__DPCS5_DC_INTERCEPTB_STATE__SHIFT 0x15
#define INTERCEPT_STATE__DPCS6_DC_INTERCEPTB_STATE__SHIFT 0x16
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L
#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L
#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK 0x00000004L
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L
#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK 0x00000200L
#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK 0x00000400L
#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE_MASK 0x00010000L
#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE_MASK 0x00020000L
#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE_MASK 0x00040000L
#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE_MASK 0x00080000L
#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE_MASK 0x00100000L
#define INTERCEPT_STATE__DPCS5_DC_INTERCEPTB_STATE_MASK 0x00200000L
#define INTERCEPT_STATE__DPCS6_DC_INTERCEPTB_STATE_MASK 0x00400000L
//DCIO_PATTERN_GEN_PAT
#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0
#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL
//DCIO_PATTERN_GEN_EN
#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0
#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L
//DCIO_BL_PWM_FRAME_START_DISP_SEL
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L
//DCIO_GSL_GENLK_PAD_CNTL
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
//DCIO_GSL_SWAPLOCK_PAD_CNTL
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
//DPCS_DCIO_TEST_CLK_SRC
#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL__SHIFT 0x0
#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL_MASK 0x00000007L
//DCIO_DEBUG
#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xFFFFFFFFL
//DCIO_TEST_DEBUG_INDEX
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000FFL
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
//DCIO_TEST_DEBUG_DATA
#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
//DBG_OUT_CNTL
#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL__SHIFT 0x0
#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL__SHIFT 0x5
#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA__SHIFT 0xc
#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL_MASK 0x00000003L
#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL_MASK 0x000000E0L
#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA_MASK 0x00FFF000L
//DCIO_DEBUG_CONFIG
#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x00000001L
//DCIO_SOFT_RESET
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4
#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0x5
#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0x6
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10
#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11
#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT 0x14
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L
#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000020L
#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00000040L
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L
#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L
#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK 0x00100000L
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
//DC_GPIO_DDC1_MASK
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
#define DC_GPIO_DDC1_MASK__DC_GPIO_AUX1_PD_HP_EN__SHIFT 0x18
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDC1_MASK__DC_GPIO_AUX1_PD_HP_EN_MASK 0x01000000L
//DC_GPIO_DDC1_A
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L
//DC_GPIO_DDC1_EN
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L
//DC_GPIO_DDC1_Y
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L
//DC_GPIO_DDC2_MASK
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
#define DC_GPIO_DDC2_MASK__DC_GPIO_AUX2_PD_HP_EN__SHIFT 0x18
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDC2_MASK__DC_GPIO_AUX2_PD_HP_EN_MASK 0x01000000L
//DC_GPIO_DDC2_A
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L
//DC_GPIO_DDC2_EN
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L
//DC_GPIO_DDC2_Y
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L
//DC_GPIO_DDC3_MASK
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
#define DC_GPIO_DDC3_MASK__DC_GPIO_AUX3_PD_HP_EN__SHIFT 0x18
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDC3_MASK__DC_GPIO_AUX3_PD_HP_EN_MASK 0x01000000L
//DC_GPIO_DDC3_A
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L
//DC_GPIO_DDC3_EN
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L
//DC_GPIO_DDC3_Y
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L
//DC_GPIO_DDC4_MASK
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
#define DC_GPIO_DDC4_MASK__DC_GPIO_AUX4_PD_HP_EN__SHIFT 0x18
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L
#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L
#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDC4_MASK__DC_GPIO_AUX4_PD_HP_EN_MASK 0x01000000L
//DC_GPIO_DDC4_A
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L
//DC_GPIO_DDC4_EN
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L
//DC_GPIO_DDC4_Y
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L
//DC_GPIO_DDC5_MASK
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
#define DC_GPIO_DDC5_MASK__DC_GPIO_AUX5_PD_HP_EN__SHIFT 0x18
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L
#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L
#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDC5_MASK__DC_GPIO_AUX5_PD_HP_EN_MASK 0x01000000L
//DC_GPIO_DDC5_A
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L
//DC_GPIO_DDC5_EN
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L
//DC_GPIO_DDC5_Y
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L
//DC_GPIO_DDCVGA_MASK
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
//DC_GPIO_DDCVGA_A
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
//DC_GPIO_DDCVGA_EN
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
//DC_GPIO_DDCVGA_Y
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
//DC_GPIO_PWRSEQ0_EN
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L
//DC_GPIO_PAD_STRENGTH_1
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
//PHY_AUX_CNTL
#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe
#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10
#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12
#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14
#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L
#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L
#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L
#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L
//DC_GPIO_PWRSEQ1_EN
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L
//DC_GPIO_AUX_CTRL_0
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L
//DC_GPIO_AUX_CTRL_1
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L
//DC_GPIO_AUX_CTRL_3
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2
#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3
#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa
#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb
#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16
#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18
#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L
#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L
#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L
#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L
#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L
#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L
#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L
#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L
#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L
#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L
//DC_GPIO_AUX_CTRL_4
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L
#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L
#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L
#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L
//DC_GPIO_AUX_CTRL_5
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6
#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe
#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf
#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11
#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13
#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15
#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16
#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b
#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c
#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L
#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L
#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L
#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L
#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L
#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L
#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L
#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L
#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L
#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L
#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L
#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L
#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L
//AUXI2C_PAD_ALL_PWR_OK
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_offset.h
+109
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _dpcs_4_0_1_OFFSET_HEADER
#define _dpcs_4_0_1_OFFSET_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
// base address: 0x0
#define regDC_GENERICA 0x2868
#define regDC_GENERICA_BASE_IDX 2
#define regDC_GENERICB 0x2869
#define regDC_GENERICB_BASE_IDX 2
#define regDCIO_CLOCK_CNTL 0x286a
#define regDCIO_CLOCK_CNTL_BASE_IDX 2
#define regDC_REF_CLK_CNTL 0x286b
#define regDC_REF_CLK_CNTL_BASE_IDX 2
#define regUNIPHYA_LINK_CNTL 0x286d
#define regUNIPHYA_LINK_CNTL_BASE_IDX 2
#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYB_LINK_CNTL 0x286f
#define regUNIPHYB_LINK_CNTL_BASE_IDX 2
#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYC_LINK_CNTL 0x2871
#define regUNIPHYC_LINK_CNTL_BASE_IDX 2
#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYD_LINK_CNTL 0x2873
#define regUNIPHYD_LINK_CNTL_BASE_IDX 2
#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYE_LINK_CNTL 0x2875
#define regUNIPHYE_LINK_CNTL_BASE_IDX 2
#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regDCIO_WRCMD_DELAY 0x287e
#define regDCIO_WRCMD_DELAY_BASE_IDX 2
#define regDC_PINSTRAPS 0x2880
#define regDC_PINSTRAPS_BASE_IDX 2
#define regDCIO_SPARE 0x2882
#define regDCIO_SPARE_BASE_IDX 2
#define regINTERCEPT_STATE 0x2884
#define regINTERCEPT_STATE_BASE_IDX 2
#define regDCIO_PATTERN_GEN_PAT 0x2886
#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2
#define regDCIO_PATTERN_GEN_EN 0x2887
#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2
#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define regDPCS_DCIO_TEST_CLK_SRC 0x2890
#define regDPCS_DCIO_TEST_CLK_SRC_BASE_IDX 2
#define regDCIO_DEBUG 0x2897
#define regDCIO_DEBUG_BASE_IDX 2
#define regDCIO_TEST_DEBUG_INDEX 0x2899
#define regDCIO_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDCIO_TEST_DEBUG_DATA 0x289a
#define regDCIO_TEST_DEBUG_DATA_BASE_IDX 2
#define regDBG_OUT_CNTL 0x289c
#define regDBG_OUT_CNTL_BASE_IDX 2
#define regDCIO_DEBUG_CONFIG 0x289d
#define regDCIO_DEBUG_CONFIG_BASE_IDX 2
#define regDCIO_SOFT_RESET 0x289e
#define regDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_DDC1_MASK 0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX 2
#define regDC_GPIO_DDC2_MASK 0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX 2
#define regDC_GPIO_DDC3_MASK 0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_MASK 0x28e8
#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_A 0x28e9
#define regDC_GPIO_DDCVGA_A_BASE_IDX 2
#define regDC_GPIO_DDCVGA_EN 0x28ea
#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define regDC_GPIO_DDCVGA_Y 0x28eb
#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define regDC_GPIO_PWRSEQ0_EN 0x28fa
#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2
#define regDC_GPIO_PAD_STRENGTH_1 0x28fc
#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define regPHY_AUX_CNTL 0x28ff
#define regPHY_AUX_CNTL_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_0 0x2916
#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_1 0x2917
#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_3 0x291b
#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_4 0x291c
#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_5 0x291d
#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define regAUXI2C_PAD_ALL_PWR_OK 0x291e
#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_sh_mask.h
+413
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _dpcs_4_0_1_SH_MASK_HEADER
#define _dpcs_4_0_1_SH_MASK_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
//DC_GENERICA
#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
//DC_GENERICB
#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
//DCIO_CLOCK_CNTL
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
//DC_REF_CLK_CNTL
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
//UNIPHYA_LINK_CNTL
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYA_CHANNEL_XBAR_CNTL
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYB_LINK_CNTL
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYB_CHANNEL_XBAR_CNTL
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYC_LINK_CNTL
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYC_CHANNEL_XBAR_CNTL
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYD_LINK_CNTL
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYD_CHANNEL_XBAR_CNTL
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYE_LINK_CNTL
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYE_CHANNEL_XBAR_CNTL
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//DCIO_WRCMD_DELAY
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L
//DC_PINSTRAPS
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L
//DCIO_SPARE
#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0
#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL
//INTERCEPT_STATE
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0
#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT 0x2
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8
#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE__SHIFT 0x10
#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE__SHIFT 0x11
#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE__SHIFT 0x12
#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE__SHIFT 0x13
#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE__SHIFT 0x14
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L
#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK 0x00000004L
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L
#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE_MASK 0x00010000L
#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE_MASK 0x00020000L
#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE_MASK 0x00040000L
#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE_MASK 0x00080000L
#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE_MASK 0x00100000L
//DCIO_PATTERN_GEN_PAT
#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0
#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL
//DCIO_PATTERN_GEN_EN
#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0
#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L
//DCIO_BL_PWM_FRAME_START_DISP_SEL
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L
//DCIO_GSL_GENLK_PAD_CNTL
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
//DCIO_GSL_SWAPLOCK_PAD_CNTL
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
//DPCS_DCIO_TEST_CLK_SRC
#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL__SHIFT 0x0
#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL_MASK 0x00000007L
//DCIO_TEST_DEBUG_INDEX
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000FFL
//DCIO_TEST_DEBUG_DATA
#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
//DBG_OUT_CNTL
#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL__SHIFT 0x0
#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL__SHIFT 0x5
#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA__SHIFT 0xc
#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL_MASK 0x00000003L
#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL_MASK 0x000000E0L
#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA_MASK 0x00FFF000L
//DCIO_DEBUG_CONFIG
#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x00000001L
//DCIO_SOFT_RESET
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10
#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT 0x14
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L
#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK 0x00100000L
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
//DC_GPIO_DDC1_MASK
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
//DC_GPIO_DDC2_MASK
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
//DC_GPIO_DDC3_MASK
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
//DC_GPIO_DDCVGA_MASK
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
//DC_GPIO_DDCVGA_A
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
//DC_GPIO_DDCVGA_EN
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
//DC_GPIO_DDCVGA_Y
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
//DC_GPIO_PWRSEQ0_EN
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L
//DC_GPIO_PAD_STRENGTH_1
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
//PHY_AUX_CNTL
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L
//DC_GPIO_AUX_CTRL_0
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L
//DC_GPIO_AUX_CTRL_1
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L
//DC_GPIO_AUX_CTRL_3
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L
//DC_GPIO_AUX_CTRL_4
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L
//DC_GPIO_AUX_CTRL_5
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L
//AUXI2C_PAD_ALL_PWR_OK
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_3_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_3_sh_mask.h
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