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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _mmhub_2_0_0_DEFAULT_HEADER
#define _mmhub_2_0_0_DEFAULT_HEADER
// addressBlock: mmhub_dagbdec
#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8
#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003046
#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039
#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111
#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a0e408
#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7
#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8
#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003046
#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039
#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000
#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a0e408
#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7
#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070
#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88
#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_DEFAULT 0x00000000
#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_DEFAULT 0x00000000
#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000
#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa
#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000
#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff
#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000
#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff
#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff
#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000
#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000
#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
#define mmDAGB0_RESERVE0_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE1_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE2_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE3_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE4_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE5_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE6_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE7_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE8_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE9_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE10_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE11_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE12_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE13_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE14_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE15_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE16_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE17_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE18_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE19_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE20_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE21_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE22_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE23_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE24_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE25_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE26_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE27_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE28_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE29_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE30_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE31_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE32_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE33_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE34_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE35_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE36_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE37_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE38_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE39_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE40_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE41_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE42_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE43_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE44_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE45_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE46_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE47_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE48_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE49_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE50_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE51_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE52_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE53_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE54_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE55_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE56_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE57_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE58_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE59_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE60_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE61_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE62_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE63_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE64_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE65_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE66_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE67_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE68_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE69_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE70_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE71_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE72_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE73_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE74_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE75_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE76_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE77_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE78_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE79_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE80_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE81_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE82_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE83_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE84_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE85_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE86_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE87_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE88_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE89_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE90_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE91_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE92_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE93_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE94_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE95_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE96_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE97_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE98_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE99_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE100_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE101_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE102_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE103_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE104_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE105_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE106_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE107_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE108_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE109_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE110_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE111_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE112_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE113_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE114_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE115_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE116_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE117_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE118_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE119_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE120_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE121_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE122_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE123_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE124_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE125_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE126_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE127_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE128_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE129_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE130_DEFAULT 0xffffffff
#define mmDAGB0_RESERVE131_DEFAULT 0xffffffff
// addressBlock: mmhub_mmea_mmeadec
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555
#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25
#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25
#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924
#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924
#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444
#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444
#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000
#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000
#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03
#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249
#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249
#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924
#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924
#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff
#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff
#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40
#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff
#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000
#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf
#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000
#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000
#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000
#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000
#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000
#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000
#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f
#define mmMMEA0_MISC_DEFAULT 0x0c00a070
#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000
#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000
#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000
#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000
#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000
#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000
#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000
#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000
#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000
#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000
#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000
#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300
#define mmMMEA0_MISC2_DEFAULT 0x00000000
#define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000
// addressBlock: mmhub_pctldec
#define mmPCTL_MISC_DEFAULT 0x00000889
#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000
#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000
#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000
#define mmPCTL_PG_DAGB_DEFAULT 0x00000000
#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000
#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000
#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000
#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000
#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000
#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000
#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000
#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000
#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000
#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000
#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000
#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000
#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000
#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0
#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800
#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000
#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000
#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620
#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a
#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000
#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000
#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
#define mmPCTL0_MISC_DEFAULT 0x00011000
#define mmPCTL1_MISC_DEFAULT 0x00000800
#define mmPCTL2_MISC_DEFAULT 0x00000800
#define mmPCTL_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmPCTL_PERFCOUNTER_HI_DEFAULT 0x00000000
#define mmPCTL_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmPCTL_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmPCTL_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
// addressBlock: mmhub_l1tlb_mmvml1pfdec
#define mmMMMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000
// addressBlock: mmhub_l1tlb_mmvml1pldec
#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
// addressBlock: mmhub_l1tlb_mmvml1prdec
#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmatcl2dec
#define mmMM_ATC_L2_CNTL_DEFAULT 0x000001c0
#define mmMM_ATC_L2_CNTL2_DEFAULT 0x00000100
#define mmMM_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000
#define mmMM_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000
#define mmMM_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000
#define mmMM_ATC_L2_CNTL3_DEFAULT 0x000001f8
#define mmMM_ATC_L2_STATUS_DEFAULT 0x00000000
#define mmMM_ATC_L2_STATUS2_DEFAULT 0x00000000
#define mmMM_ATC_L2_MISC_CG_DEFAULT 0x00000200
#define mmMM_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
#define mmMM_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
#define mmMM_ATC_L2_SDPPORT_CTRL_DEFAULT 0x000003ff
// addressBlock: mmhub_mmutcl2_mmvml2pfdec
#define mmMMVM_L2_CNTL_DEFAULT 0x00080602
#define mmMMVM_L2_CNTL2_DEFAULT 0x00000000
#define mmMMVM_L2_CNTL3_DEFAULT 0x80100007
#define mmMMVM_L2_STATUS_DEFAULT 0x00000000
#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_CNTL_DEFAULT 0x0000010f
#define mmMMVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
#define mmMMVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
#define mmMMVM_L2_CNTL4_DEFAULT 0x000000c1
#define mmMMVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
#define mmMMVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
#define mmMMVM_L2_IH_LOG_CNTL_DEFAULT 0x00000002
#define mmMMVM_L2_IH_LOG_BUSY_DEFAULT 0x00000000
#define mmMMVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
#define mmMMVM_L2_CNTL5_DEFAULT 0x00003fe0
#define mmMMVM_L2_GCR_CNTL_DEFAULT 0x00000000
#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT 0x00000000
#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000
#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT 0x00000000
#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmvml2vcdec
#define mmMMVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
#define mmMMVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG0_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG1_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG2_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG3_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG4_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG5_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG6_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG7_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG8_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG9_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG10_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG11_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG12_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG13_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG14_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG15_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG16_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG17_REQ_DEFAULT 0x02f80000
#define mmMMVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmvml2pldec
#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
// addressBlock: mmhub_mmutcl2_mmvml2prdec
#define mmMMMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmMMMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_DEFAULT 0x00000000
#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_DEFAULT 0x00000000
#define mmMMVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
#define mmMMMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
#define mmMMMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
#define mmMMVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000
#define mmMMVM_PCIE_ATS_CNTL_VF_31_DEFAULT 0x00000000
#define mmMMUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
#define mmMMMC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
#define mmMMMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
#define mmMMMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
#define mmMMMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
#define mmMMMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
#define mmMMMC_VM_FB_OFFSET_DEFAULT 0x00000000
#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
#define mmMMMC_VM_STEERING_DEFAULT 0x00000001
#define mmMMMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
#define mmMMMC_MEM_POWER_LS_DEFAULT 0x00000208
#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
#define mmMMMC_VM_APT_CNTL_DEFAULT 0x00000000
#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
#define mmMMMC_SHARED_VIRT_RESET_REQ2_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
#define mmMMMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
#define mmMMMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
#define mmMMMC_VM_AGP_TOP_DEFAULT 0x00000000
#define mmMMMC_VM_AGP_BOT_DEFAULT 0x00000000
#define mmMMMC_VM_AGP_BASE_DEFAULT 0x00000000
#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
#define mmMMMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000501
// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
#define mmMM_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
#define mmMM_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
#define mmMM_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
#define mmMM_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_default.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_2_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_2_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_3_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_3_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h
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@@ -0,0 +1,802 @@
/*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mmhub_4_2_0_OFFSET_HEADER
#define _mmhub_4_2_0_OFFSET_HEADER
// addressBlock: mmhub_dagb_dagbdec
// base address: 0x60000
#define regDAGB0_CNTL_MISC2 0x00a7
#define regDAGB0_CNTL_MISC2_BASE_IDX 1
#define regDAGB1_CNTL_MISC2 0x01a7
#define regDAGB1_CNTL_MISC2_BASE_IDX 1
// addressBlock: mmhub_mm_cane_mmcanedec
// base address: 0x60c20
#define regMM_CANE_ICG_CTRL 0x0313
#define regMM_CANE_ICG_CTRL_BASE_IDX 1
// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
// base address: 0x66000
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0000
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0001
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
#define regMMUTCL2_CGTT_CLK_CTRL 0x0002
#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 2
#define regMMMC_SHARED_ACTIVE_FCN_ID 0x0003
#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 2
#define regMMUTCL2_CGTT_BUSY_CTRL 0x0004
#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 2
#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x0005
#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvml2pfdec
// base address: 0x66090
#define regMMVM_L2_CNTL 0x0024
#define regMMVM_L2_CNTL_BASE_IDX 2
#define regMMVM_L2_CNTL2 0x0025
#define regMMVM_L2_CNTL2_BASE_IDX 2
#define regMMVM_L2_CNTL3 0x0026
#define regMMVM_L2_CNTL3_BASE_IDX 2
#define regMMVM_L2_STATUS 0x0027
#define regMMVM_L2_STATUS_BASE_IDX 2
#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0028
#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 2
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0029
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 2
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x002a
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_CNTL 0x002b
#define regMMVM_INVALIDATE_CNTL_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32 0x002c
#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32 0x002d
#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x002e
#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x002f
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0030
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32 0x0031
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32 0x0032
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0033
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0034
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0035
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0036
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0038
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0039
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x003a
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x003b
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x003c
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 2
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x003d
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 2
#define regMMVM_L2_CNTL4 0x003e
#define regMMVM_L2_CNTL4_BASE_IDX 2
#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x003f
#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 2
#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x0040
#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 2
#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x0041
#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 2
#define regMMVM_L2_CACHE_PARITY_CNTL 0x0042
#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 2
#define regMMVM_L2_CGTT_CLK_CTRL 0x0043
#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 2
#define regMMVM_L2_CNTL5 0x0044
#define regMMVM_L2_CNTL5_BASE_IDX 2
#define regMMVM_L2_GCR_CNTL 0x0045
#define regMMVM_L2_GCR_CNTL_BASE_IDX 2
#define regMMVM_L2_CGTT_BUSY_CTRL 0x0046
#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 2
#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0047
#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 2
#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0048
#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 2
#define regMMVM_L2_BANK_SELECT_MASKS 0x0051
#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 2
#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0052
#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 2
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0053
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 2
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0054
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 2
#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0055
#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 2
#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x0056
#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 2
#define regMMVML2_IH_FAULT_INTERRUPT_CNTL 0x0057
#define regMMVML2_IH_FAULT_INTERRUPT_CNTL_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvml2prdec
// base address: 0x66210
#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0084
#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0085
#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER_LO 0x0086
#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER_HI 0x0087
#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmatcl2prdec
// base address: 0x66250
#define regMM_ATC_L2_PERFCOUNTER_LO 0x0094
#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 2
#define regMM_ATC_L2_PERFCOUNTER_HI 0x0095
#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvml2pldec
// base address: 0x66290
#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x00a4
#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x00a5
#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x00a6
#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x00a7
#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x00a8
#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x00a9
#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x00aa
#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x00ab
#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER8_CFG 0x00ac
#define regMMMC_VM_L2_PERFCOUNTER8_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER9_CFG 0x00ad
#define regMMMC_VM_L2_PERFCOUNTER9_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER10_CFG 0x00ae
#define regMMMC_VM_L2_PERFCOUNTER10_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER11_CFG 0x00af
#define regMMMC_VM_L2_PERFCOUNTER11_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER12_CFG 0x00b0
#define regMMMC_VM_L2_PERFCOUNTER12_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER13_CFG 0x00b1
#define regMMMC_VM_L2_PERFCOUNTER13_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER14_CFG 0x00b2
#define regMMMC_VM_L2_PERFCOUNTER14_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER15_CFG 0x00b3
#define regMMMC_VM_L2_PERFCOUNTER15_CFG_BASE_IDX 2
#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x00b4
#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER0_CFG 0x00b5
#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER1_CFG 0x00b6
#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER2_CFG 0x00b7
#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER3_CFG 0x00b8
#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 2
#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x00b9
#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmatcl2pldec
// base address: 0x662f0
#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x00bc
#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 2
#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x00bd
#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 2
#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x00cc
#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
// base address: 0x66400
#define regMMMC_VM_FB_LOCATION_BASE_LO32 0x0100
#define regMMMC_VM_FB_LOCATION_BASE_LO32_BASE_IDX 2
#define regMMMC_VM_FB_LOCATION_BASE_HI32 0x0101
#define regMMMC_VM_FB_LOCATION_BASE_HI32_BASE_IDX 2
#define regMMMC_VM_FB_LOCATION_TOP_LO32 0x0102
#define regMMMC_VM_FB_LOCATION_TOP_LO32_BASE_IDX 2
#define regMMMC_VM_FB_LOCATION_TOP_HI32 0x0103
#define regMMMC_VM_FB_LOCATION_TOP_HI32_BASE_IDX 2
#define regMMMC_VM_AGP_TOP_LO32 0x0104
#define regMMMC_VM_AGP_TOP_LO32_BASE_IDX 2
#define regMMMC_VM_AGP_TOP_HI32 0x0105
#define regMMMC_VM_AGP_TOP_HI32_BASE_IDX 2
#define regMMMC_VM_AGP_BOT_LO32 0x0106
#define regMMMC_VM_AGP_BOT_LO32_BASE_IDX 2
#define regMMMC_VM_AGP_BOT_HI32 0x0107
#define regMMMC_VM_AGP_BOT_HI32_BASE_IDX 2
#define regMMMC_VM_AGP_BASE_LO32 0x0108
#define regMMMC_VM_AGP_BASE_LO32_BASE_IDX 2
#define regMMMC_VM_AGP_BASE_HI32 0x0109
#define regMMMC_VM_AGP_BASE_HI32_BASE_IDX 2
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 0x010a
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32_BASE_IDX 2
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 0x010b
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32_BASE_IDX 2
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 0x010c
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32_BASE_IDX 2
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 0x010d
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32_BASE_IDX 2
#define regMMMC_VM_MX_L1_TLB_CNTL 0x010e
#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvml2vcdec
// base address: 0x66440
#define regMMVM_CONTEXT0_CNTL 0x0110
#define regMMVM_CONTEXT0_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT1_CNTL 0x0111
#define regMMVM_CONTEXT1_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT2_CNTL 0x0112
#define regMMVM_CONTEXT2_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT3_CNTL 0x0113
#define regMMVM_CONTEXT3_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT4_CNTL 0x0114
#define regMMVM_CONTEXT4_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT5_CNTL 0x0115
#define regMMVM_CONTEXT5_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT6_CNTL 0x0116
#define regMMVM_CONTEXT6_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT7_CNTL 0x0117
#define regMMVM_CONTEXT7_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT8_CNTL 0x0118
#define regMMVM_CONTEXT8_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT9_CNTL 0x0119
#define regMMVM_CONTEXT9_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT10_CNTL 0x011a
#define regMMVM_CONTEXT10_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT11_CNTL 0x011b
#define regMMVM_CONTEXT11_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT12_CNTL 0x011c
#define regMMVM_CONTEXT12_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT13_CNTL 0x011d
#define regMMVM_CONTEXT13_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT14_CNTL 0x011e
#define regMMVM_CONTEXT14_CNTL_BASE_IDX 2
#define regMMVM_CONTEXT15_CNTL 0x011f
#define regMMVM_CONTEXT15_CNTL_BASE_IDX 2
#define regMMVM_CONTEXTS_DISABLE 0x0120
#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG0_SEM 0x0121
#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG1_SEM 0x0122
#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG2_SEM 0x0123
#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG3_SEM 0x0124
#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG4_SEM 0x0125
#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG5_SEM 0x0126
#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG6_SEM 0x0127
#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG7_SEM 0x0128
#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG8_SEM 0x0129
#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG9_SEM 0x012a
#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG10_SEM 0x012b
#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG11_SEM 0x012c
#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG12_SEM 0x012d
#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG13_SEM 0x012e
#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG14_SEM 0x012f
#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG15_SEM 0x0130
#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG16_SEM 0x0131
#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG17_SEM 0x0132
#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG0_REQ 0x0133
#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG1_REQ 0x0134
#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG2_REQ 0x0135
#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG3_REQ 0x0136
#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG4_REQ 0x0137
#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG5_REQ 0x0138
#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG6_REQ 0x0139
#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG7_REQ 0x013a
#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG8_REQ 0x013b
#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG9_REQ 0x013c
#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG10_REQ 0x013d
#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG11_REQ 0x013e
#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG12_REQ 0x013f
#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG13_REQ 0x0140
#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG14_REQ 0x0141
#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG15_REQ 0x0142
#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG16_REQ 0x0143
#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG17_REQ 0x0144
#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG0_ACK 0x0145
#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG1_ACK 0x0146
#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG2_ACK 0x0147
#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG3_ACK 0x0148
#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG4_ACK 0x0149
#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG5_ACK 0x014a
#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG6_ACK 0x014b
#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG7_ACK 0x014c
#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG8_ACK 0x014d
#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG9_ACK 0x014e
#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG10_ACK 0x014f
#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG11_ACK 0x0150
#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG12_ACK 0x0151
#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG13_ACK 0x0152
#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG14_ACK 0x0153
#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG15_ACK 0x0154
#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG16_ACK 0x0155
#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG17_ACK 0x0156
#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0157
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0158
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0159
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x015a
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x015b
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x015c
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x015d
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x015e
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x015f
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0160
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0161
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0162
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0163
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0164
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0165
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0166
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0167
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0168
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0169
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x016a
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x016b
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x016c
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x016d
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x016e
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x016f
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0170
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0171
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0172
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0173
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0174
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0175
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0176
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0177
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0178
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0179
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 2
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x017a
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 2
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x017b
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x017c
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x017d
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x017e
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x017f
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0180
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0181
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0182
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0183
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0184
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0185
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0186
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0187
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0188
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0189
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x018a
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x018b
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x018c
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x018d
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x018e
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x018f
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0190
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0191
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0192
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0193
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0194
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0195
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0196
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0197
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0198
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0199
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x019a
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x019b
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x019c
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x019d
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x019e
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x019f
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x01a0
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x01a1
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x01a2
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x01a3
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x01a4
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x01a5
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x01a6
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x01a7
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x01a8
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x01a9
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x01aa
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x01ab
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x01ac
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x01ad
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x01ae
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x01af
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x01b0
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x01b1
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x01b2
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x01b3
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x01b4
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x01b5
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x01b6
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x01b7
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x01b8
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x01b9
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x01ba
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x01bb
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x01bc
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x01bd
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x01be
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x01bf
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x01c0
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x01c1
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x01c2
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x01c3
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x01c4
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x01c5
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x01c6
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x01c7
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x01c8
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x01c9
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x01ca
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x01cb
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x01cc
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x01cd
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x01ce
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x01cf
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x01d0
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x01d1
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x01d2
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x01d3
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x01d4
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x01d5
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x01d6
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x01d7
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x01d8
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x01d9
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x01da
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01db
#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01dc
#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01dd
#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01de
#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01df
#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e0
#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e1
#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e2
#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e3
#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e4
#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e5
#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e6
#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e7
#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e8
#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e9
#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01ea
#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01eb
#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvmsharedvfdec
// base address: 0x667c0
#define regMMMC_VM_PCIE_ATOMIC_SUPPORTED 0x01f0
#define regMMMC_VM_PCIE_ATOMIC_SUPPORTED_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
// base address: 0x667e0
#define regMMVM_PCIE_ATS_CNTL 0x01f8
#define regMMVM_PCIE_ATS_CNTL_BASE_IDX 2
#define regMMMC_VM_NB_MMIOBASE 0x01f9
#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 2
#define regMMMC_VM_NB_MMIOLIMIT 0x01fa
#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 2
#define regMMMC_VM_NB_PCI_CTRL 0x01fb
#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 2
#define regMMMC_VM_NB_PCI_ARB 0x01fc
#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 2
#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x01fd
#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 2
#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x01fe
#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 2
#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x01ff
#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 2
#define regMMMC_VM_STEERING 0x0200
#define regMMMC_VM_STEERING_BASE_IDX 2
#define regMMMC_SHARED_VIRT_RESET_REQ 0x0201
#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 2
#define regMMMC_VM_XGMI_LFB_CNTL 0x0202
#define regMMMC_VM_XGMI_LFB_CNTL_BASE_IDX 2
#define regMMMC_VM_XGMI_LFB_SIZE 0x0203
#define regMMMC_VM_XGMI_LFB_SIZE_BASE_IDX 2
#define regMMMC_VM_HOST_MAPPING 0x0204
#define regMMMC_VM_HOST_MAPPING_BASE_IDX 2
#define regMMMC_VM_XGMI_GPUIOV_ENABLE 0x0205
#define regMMMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 2
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0206
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 2
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0207
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 2
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x0208
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 2
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x0209
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 2
#define regMMMC_VM_LPDDR_ADDRESS_START 0x020a
#define regMMMC_VM_LPDDR_ADDRESS_START_BASE_IDX 2
#define regMMMC_VM_LPDDR_ADDRESS_END 0x020b
#define regMMMC_VM_LPDDR_ADDRESS_END_BASE_IDX 2
#define regMMMC_VM_APT_CNTL 0x020c
#define regMMMC_VM_APT_CNTL_BASE_IDX 2
#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x020d
#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmatcl2dec
// base address: 0x669d0
#define regMM_ATC_L2_CNTL 0x0274
#define regMM_ATC_L2_CNTL_BASE_IDX 2
#define regMM_ATC_L2_CNTL2 0x0275
#define regMM_ATC_L2_CNTL2_BASE_IDX 2
#define regMM_ATC_L2_CACHE_DATA0 0x0278
#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 2
#define regMM_ATC_L2_CACHE_DATA1 0x0279
#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 2
#define regMM_ATC_L2_CACHE_DATA2 0x027a
#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 2
#define regMM_ATC_L2_CNTL3 0x027d
#define regMM_ATC_L2_CNTL3_BASE_IDX 2
#define regMM_ATC_L2_CNTL4 0x027e
#define regMM_ATC_L2_CNTL4_BASE_IDX 2
#define regMM_ATC_L2_CNTL5 0x027f
#define regMM_ATC_L2_CNTL5_BASE_IDX 2
#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x0280
#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 2
#define regMM_ATC_L2_STATUS 0x0281
#define regMM_ATC_L2_STATUS_BASE_IDX 2
#define regMM_ATC_L2_MISC_CG 0x0282
#define regMM_ATC_L2_MISC_CG_BASE_IDX 2
#define regMM_ATC_L2_CGTT_CLK_CTRL 0x0283
#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 2
#define regMM_ATC_L2_SDPPORT_CTRL 0x0287
#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvml2pspdec
// base address: 0x66b40
#define regMMVM_IOMMU_CONTROL_REGISTER 0x02d4
#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 2
#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x02d5
#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvmsharedpspdec
// base address: 0x66b90
#define regMMMC_VM_FB_OFFSET 0x02ec
#define regMMMC_VM_FB_OFFSET_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h
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