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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h
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/*
*
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_6_0_D_H
#define SMU_6_0_D_H
#define ixLCAC_MC0_CNTL 0x011C
#define ixLCAC_MC0_OVR_SEL 0x011D
#define ixLCAC_MC0_OVR_VAL 0x011E
#define ixLCAC_MC1_CNTL 0x011F
#define ixLCAC_MC1_OVR_SEL 0x0120
#define ixLCAC_MC1_OVR_VAL 0x0121
#define ixLCAC_MC2_CNTL 0x0122
#define ixLCAC_MC2_OVR_SEL 0x0123
#define ixLCAC_MC2_OVR_VAL 0x0124
#define ixLCAC_MC3_CNTL 0x0125
#define ixLCAC_MC3_OVR_SEL 0x0126
#define ixLCAC_MC3_OVR_VAL 0x0127
#define ixLCAC_MC4_CNTL 0x0128
#define ixLCAC_MC4_OVR_SEL 0x0129
#define ixLCAC_MC4_OVR_VAL 0x012A
#define ixLCAC_MC5_CNTL 0x012B
#define ixLCAC_MC5_OVR_SEL 0x012C
#define ixLCAC_MC5_OVR_VAL 0x012D
#define mmCG_SPLL_FUNC_CNTL 0x0180
#define mmCG_SPLL_FUNC_CNTL_2 0x0181
#define mmCG_SPLL_FUNC_CNTL_3 0x0182
#define mmCG_SPLL_FUNC_CNTL_4 0x0183
#define mmCG_SPLL_STATUS 0x0185
#define mmSPLL_CNTL_MODE 0x0186
#define mmCG_SPLL_SPREAD_SPECTRUM 0x0188
#define mmCG_SPLL_SPREAD_SPECTRUM_2 0x0189
#define mmCG_SPLL_AUTOSCALE_CNTL 0x018B
#define mmMPLL_BYPASSCLK_SEL 0x0197
#define mmCG_CLKPIN_CNTL 0x0198
#define mmCG_CLKPIN_CNTL_2 0x0199
#define mmTHM_CLK_CNTL 0x019B
#define mmMISC_CLK_CNTL 0x019C
#define mmCG_THERMAL_CTRL 0x01C0
#define mmCG_THERMAL_STATUS 0x01C1
#define mmCG_THERMAL_INT 0x01C2
#define mmCG_MULT_THERMAL_CTRL 0x01C4
#define mmCG_MULT_THERMAL_STATUS 0x01C5
#define mmCG_FDO_CTRL0 0x01D5
#define mmCG_FDO_CTRL1 0x01D6
#define mmCG_FDO_CTRL2 0x01D7
#define mmCG_TACH_CTRL 0x01DC
#define mmCG_TACH_STATUS 0x01DD
#define mmGENERAL_PWRMGT 0x1E0
#define mmCG_TPC 0x1E1
#define mmSCLK_PWRMGT_CNTL 0x1E2
#define mmTARGET_AND_CURRENT_PROFILE_INDEX 0x01E6
#define mmCG_FTV 0x01EF
#define mmCG_FFCT_0 0x01F0
#define mmCG_BSP 0x01FF
#define mmCG_AT 0x0200
#define mmCG_GIT 0x0201
#define mmCG_SSP 0x0203
#define mmCG_DISPLAY_GAP_CNTL 0x020A
#define mmCG_ULV_CONTROL 0x021E
#define mmCG_ULV_PARAMETER 0x021F
#define mmSMC_SCRATCH0 0x0221
#define mmCG_CAC_CTRL 0x022E
#define ixSMC_PC_C 0x80000370
#define ixTHM_TMON0_DEBUG 0x03F0
#define ixTHM_TMON0_INT_DATA 0x0380
#define ixTHM_TMON0_RDIL0_DATA 0x0300
#define ixTHM_TMON0_RDIL10_DATA 0x030A
#define ixTHM_TMON0_RDIL11_DATA 0x030B
#define ixTHM_TMON0_RDIL12_DATA 0x030C
#define ixTHM_TMON0_RDIL13_DATA 0x030D
#define ixTHM_TMON0_RDIL14_DATA 0x030E
#define ixTHM_TMON0_RDIL15_DATA 0x030F
#define ixTHM_TMON0_RDIL1_DATA 0x0301
#define ixTHM_TMON0_RDIL2_DATA 0x0302
#define ixTHM_TMON0_RDIL3_DATA 0x0303
#define ixTHM_TMON0_RDIL4_DATA 0x0304
#define ixTHM_TMON0_RDIL5_DATA 0x0305
#define ixTHM_TMON0_RDIL6_DATA 0x0306
#define ixTHM_TMON0_RDIL7_DATA 0x0307
#define ixTHM_TMON0_RDIL8_DATA 0x0308
#define ixTHM_TMON0_RDIL9_DATA 0x0309
#define ixTHM_TMON0_RDIR0_DATA 0x0310
#define ixTHM_TMON0_RDIR10_DATA 0x031A
#define ixTHM_TMON0_RDIR11_DATA 0x031B
#define ixTHM_TMON0_RDIR12_DATA 0x031C
#define ixTHM_TMON0_RDIR13_DATA 0x031D
#define ixTHM_TMON0_RDIR14_DATA 0x031E
#define ixTHM_TMON0_RDIR15_DATA 0x031F
#define ixTHM_TMON0_RDIR1_DATA 0x0311
#define ixTHM_TMON0_RDIR2_DATA 0x0312
#define ixTHM_TMON0_RDIR3_DATA 0x0313
#define ixTHM_TMON0_RDIR4_DATA 0x0314
#define ixTHM_TMON0_RDIR5_DATA 0x0315
#define ixTHM_TMON0_RDIR6_DATA 0x0316
#define ixTHM_TMON0_RDIR7_DATA 0x0317
#define ixTHM_TMON0_RDIR8_DATA 0x0318
#define ixTHM_TMON0_RDIR9_DATA 0x0319
#define ixTHM_TMON1_DEBUG 0x03F1
#define ixTHM_TMON1_INT_DATA 0x0381
#define ixTHM_TMON1_RDIL0_DATA 0x0320
#define ixTHM_TMON1_RDIL10_DATA 0x032A
#define ixTHM_TMON1_RDIL11_DATA 0x032B
#define ixTHM_TMON1_RDIL12_DATA 0x032C
#define ixTHM_TMON1_RDIL13_DATA 0x032D
#define ixTHM_TMON1_RDIL14_DATA 0x032E
#define ixTHM_TMON1_RDIL15_DATA 0x032F
#define ixTHM_TMON1_RDIL1_DATA 0x0321
#define ixTHM_TMON1_RDIL2_DATA 0x0322
#define ixTHM_TMON1_RDIL3_DATA 0x0323
#define ixTHM_TMON1_RDIL4_DATA 0x0324
#define ixTHM_TMON1_RDIL5_DATA 0x0325
#define ixTHM_TMON1_RDIL6_DATA 0x0326
#define ixTHM_TMON1_RDIL7_DATA 0x0327
#define ixTHM_TMON1_RDIL8_DATA 0x0328
#define ixTHM_TMON1_RDIL9_DATA 0x0329
#define ixTHM_TMON1_RDIR0_DATA 0x0330
#define ixTHM_TMON1_RDIR10_DATA 0x033A
#define ixTHM_TMON1_RDIR11_DATA 0x033B
#define ixTHM_TMON1_RDIR12_DATA 0x033C
#define ixTHM_TMON1_RDIR13_DATA 0x033D
#define ixTHM_TMON1_RDIR14_DATA 0x033E
#define ixTHM_TMON1_RDIR15_DATA 0x033F
#define ixTHM_TMON1_RDIR1_DATA 0x0331
#define ixTHM_TMON1_RDIR2_DATA 0x0332
#define ixTHM_TMON1_RDIR3_DATA 0x0333
#define ixTHM_TMON1_RDIR4_DATA 0x0334
#define ixTHM_TMON1_RDIR5_DATA 0x0335
#define ixTHM_TMON1_RDIR6_DATA 0x0336
#define ixTHM_TMON1_RDIR7_DATA 0x0337
#define ixTHM_TMON1_RDIR8_DATA 0x0338
#define ixTHM_TMON1_RDIR9_DATA 0x0339
#define mmGPIOPAD_A 0x05E7
#define mmGPIOPAD_EN 0x05E8
#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x05F1
#define mmGPIOPAD_INT_EN 0x05EE
#define mmGPIOPAD_INT_POLARITY 0x05F0
#define mmGPIOPAD_INT_STAT 0x05EC
#define mmGPIOPAD_INT_STAT_AK 0x05ED
#define mmGPIOPAD_INT_STAT_EN 0x05EB
#define mmGPIOPAD_INT_TYPE 0x05EF
#define mmGPIOPAD_MASK 0x05E6
#define mmGPIOPAD_PD_EN 0x05F4
#define mmGPIOPAD_PINSTRAPS 0x05EA
#define mmGPIOPAD_PU_EN 0x05F3
#define mmGPIOPAD_RCVR_SEL 0x05F2
#define mmGPIOPAD_STRENGTH 0x05E5
#define mmGPIOPAD_SW_INT_STAT 0x05E4
#define mmGPIOPAD_Y 0x05E9
#define mmSMC_IND_ACCESS_CNTL 0x008A
#define mmSMC_IND_DATA_0 0x0081
#define mmSMC_IND_DATA 0x0081
#define mmSMC_IND_DATA_1 0x0083
#define mmSMC_IND_DATA_2 0x0085
#define mmSMC_IND_DATA_3 0x0087
#define mmSMC_IND_INDEX_0 0x0080
#define mmSMC_IND_INDEX 0x0080
#define mmSMC_IND_INDEX_1 0x0082
#define mmSMC_IND_INDEX_2 0x0084
#define mmSMC_IND_INDEX_3 0x0086
#define mmSMC_MESSAGE_0 0x008B
#define mmSMC_MESSAGE_1 0x008D
#define mmSMC_MESSAGE_2 0x008F
#define mmSMC_RESP_0 0x008C
#define mmSMC_RESP_1 0x008E
#define mmSMC_RESP_2 0x0090
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h
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/*
*
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_6_0_SH_MASK_H
#define SMU_6_0_SH_MASK_H
#define CG_AT__CG_R_MASK 0x0000FFFFL
#define CG_AT__CG_R__SHIFT 0x00000000
#define CG_AT__CG_L_MASK 0xFFFF0000L
#define CG_AT__CG_L__SHIFT 0x00000010
#define CG_BSP__BSP_MASK 0x0000FFFFL
#define CG_BSP__BSP__SHIFT 0x00000000
#define CG_BSP__BSU_MASK 0x000F0000L
#define CG_BSP__BSU__SHIFT 0x00000010
#define CG_CAC_CTRL__CAC_WINDOW_MASK 0x00FFFFFFL
#define CG_CAC_CTRL__CAC_WINDOW__SHIFT 0x00000000
#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x00000002L
#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x00000001
#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x00000004L
#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x00000002
#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x00000008L
#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x00000003
#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x00000100L
#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x00000008
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK 0x00000003L
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT 0x00000000
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK 0x0000000CL
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT 0x00000002
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x0003FFF0L
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x00000004
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x00700000
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x00000014
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK 0x03000000L
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT 0x00000018
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK 0x0C000000L
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT 0x0000001A
#define CG_FFCT_0__UTC_0_MASK 0x000003FFL
#define CG_FFCT_0__UTC_0__SHIFT 0x00000000
#define CG_FFCT_0__DTC_0_MASK 0x000FFC00L
#define CG_FFCT_0__DTC_0__SHIFT 0x0000000A
#define CG_GIT__CG_GICST_MASK 0x0000FFFFL
#define CG_GIT__CG_GICST__SHIFT 0x00000000
#define CG_GIT__CG_GIPOT_MASK 0xFFFF0000L
#define CG_GIT__CG_GIPOT__SHIFT 0x00000010
#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x00000001L
#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x00000000
#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK 0x00000002L
#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP__SHIFT 0x00000001
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x00000008L
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x00000003
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003F0L
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x007F00000
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x00000014
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x0000001FF
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x00000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x00800000
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x00000017
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x04000000
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x0000001A
#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03FFFFFFL
#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000L
#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x0000001C
#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x00000002L
#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x00000001
#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x00000001L
#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x00000000
#define CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK 0x0000FFF0L
#define CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT 0x00000004
#define CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK 0x00000200L
#define CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT 0x00000000
#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK 0x03FFFFFFL
#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR__SHIFT 0x00000009
#define CG_SSP__SST_MASK 0x0000FFFFL
#define CG_SSP__SST__SHIFT 0x00000000
#define CG_SSP__SSTU_MASK 0x000F0000L
#define CG_SSP__SSTU__SHIFT 0x00000010
#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x00000007L
#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x00000000
#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x003FC000
#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0x0000000E
#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L
#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x00000009
#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0x0000FF00L
#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x00000008
#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0x00FF0000L
#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x00000010
#define CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK 0x01000000L
#define CG_THERMAL_INT__THERM_INT_MASK_HIGH__SHIFT 0x00000018
#define CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK 0x02000000
#define CG_THERMAL_INT__THERM_INT_MASK_LOW__SHIFT 0x00000019
#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L
#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x00000014
#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL
#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x00000000
#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003fe00L
#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x00000009
#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL
#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x00000000
#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL
#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x00000000
#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL
#define CG_FDO_CTRL2__TMIN__SHIFT 0x00000000
#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L
#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0x0000000B
#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L
#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x00000019
#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L
#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x00000000
#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x00000003
#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL
#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x00000000
#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x00000001L
#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x00000000
#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x00000002L
#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x00000001
#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x00000004L
#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x00000002
#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x00000008L
#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x00000003
#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x00000040L
#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x00000006
#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x00000400L
#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0x0000000A
#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x00800000L
#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x00000017
#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000
#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL
#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000
#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f
#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL
#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000
#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009
#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f
#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL
#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000
#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f
#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL
#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000
#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f
#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL
#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000
#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f
#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL
#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000
#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL
#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009
#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL
#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000
#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL
#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004
#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000
#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL
#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000
#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x00000001L
#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x00000000
#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x0001fffeL
#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x00000001
#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffffL
#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x00000000
#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffffL
#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x00000000
#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x00000001L
#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x00000000
#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x0001fffeL
#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x00000001
#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffffL
#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x00000000
#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffffL
#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x00000000
#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x00000001L
#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x00000000
#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x0001fffeL
#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x00000001
#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffffL
#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x00000000
#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffffL
#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x00000000
#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x00000001L
#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x00000000
#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x0001fffeL
#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x00000001
#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffffL
#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x00000000
#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffffL
#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x00000000
#define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x00000001L
#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x00000000
#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x0001fffeL
#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x00000001
#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffffL
#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x00000000
#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffffL
#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x00000000
#define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x00000001L
#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x00000000
#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x0001fffeL
#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x00000001
#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffffL
#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x00000000
#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffffL
#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x00000000
#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0x0000FF00L
#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x00000008
#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x00000001L
#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x00000000
#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x00000002L
#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x00000001
#define SCLK_PWRMGT_CNTL__FIR_RESET_MASK 0x00000010L
#define SCLK_PWRMGT_CNTL__FIR_RESET__SHIFT 0x00000004
#define SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK 0x00000020L
#define SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL__SHIFT 0x00000005
#define SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK 0x00000040L
#define SCLK_PWRMGT_CNTL__FIR_TREND_MODE__SHIFT 0x00000006
#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x00000080L
#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x00000007
#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x00000100L
#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x00000008
#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x00000200L
#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x00000009
#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x00000400L
#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0x0000000A
#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x00000800L
#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0x0000000B
#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x00001000L
#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0x0000000C
#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x00002000L
#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0x0000000D
#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x00004000L
#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0x0000000E
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x00000100L
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x00000008
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x00010000L
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x00000010
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x01000000L
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018
#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffffL
#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x00000000
#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffffL
#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x00000000
#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffffL
#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x00000000
#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffffL
#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x00000000
#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL
#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000
#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffffL
#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x00000000
#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffffL
#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x00000000
#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffffL
#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x00000000
#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffffL
#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x00000000
#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL
#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000
#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffffffffL
#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000
#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffffffffL
#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000
#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffffffffL
#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x00000000
#define SMC_PC_C__smc_pc_c_MASK 0xffffffffL
#define SMC_PC_C__smc_pc_c__SHIFT 0x00000000
#define SMC_RESP_0__SMC_RESP_MASK 0xffffffffL
#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000
#define SMC_RESP_1__SMC_RESP_MASK 0xffffffffL
#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000
#define SMC_RESP_2__SMC_RESP_MASK 0xffffffffL
#define SMC_RESP_2__SMC_RESP__SHIFT 0x00000000
#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L
#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c
#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L
#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004
#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L
#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003
#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L
#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001
#define SPLL_CNTL_MODE__SPLL_REFCLK_SEL_MASK 0x0C000000L
#define SPLL_CNTL_MODE__SPLL_REFCLK_SEL__SHIFT 0x0000001A
#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L
#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c
#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L
#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000
#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L
#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a
#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L
#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002
#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L
#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d
#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L
#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018
#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L
#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c
#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK 0x000000F0L
#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT 0x00000004
#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0x000000FFL
#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x00000000
#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0x0000FF00L
#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x00000008
#define MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK 0x000000FFL
#define MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT 0x00000000
#define MISC_CLK_CNTL__ZCLK_SEL_MASK 0x0000FF00L
#define MISC_CLK_CNTL__ZCLK_SEL__SHIFT 0x00000008
#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001fL
#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x00000000
#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000ffe0L
#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x00000005
#define THM_TMON0_INT_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_INT_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_INT_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_INT_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_INT_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x00000000
#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L
#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007ffL
#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001fL
#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x00000000
#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000ffe0L
#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x00000005
#define THM_TMON1_INT_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_INT_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_INT_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_INT_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_INT_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x00000000
#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00fff000L
#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0x0000000c
#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L
#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0x0000000b
#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007ffL
#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x00000000
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h
+741
View File
@@ -0,0 +1,741 @@
/*
* SMU_7_0_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_7_0_0_D_H
#define SMU_7_0_0_D_H
#define mmGCK_SMC_IND_INDEX 0x80
#define mmGCK0_GCK_SMC_IND_INDEX 0x80
#define mmGCK1_GCK_SMC_IND_INDEX 0x82
#define mmGCK2_GCK_SMC_IND_INDEX 0x84
#define mmGCK3_GCK_SMC_IND_INDEX 0x86
#define mmGCK_SMC_IND_DATA 0x81
#define mmGCK0_GCK_SMC_IND_DATA 0x81
#define mmGCK1_GCK_SMC_IND_DATA 0x83
#define mmGCK2_GCK_SMC_IND_DATA 0x85
#define mmGCK3_GCK_SMC_IND_DATA 0x87
#define ixCG_DCLK_CNTL 0xc050009c
#define ixCG_DCLK_STATUS 0xc05000a0
#define ixCG_VCLK_CNTL 0xc05000a4
#define ixCG_VCLK_STATUS 0xc05000a8
#define ixCG_ECLK_CNTL 0xc05000ac
#define ixCG_ECLK_STATUS 0xc05000b0
#define ixCG_ACLK_CNTL 0xc05000dc
#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
#define ixCG_SPLL_FUNC_CNTL 0xc0500140
#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
#define ixSPLL_CNTL_MODE 0xc0500160
#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
#define ixMPLL_BYPASSCLK_SEL 0xc050019c
#define ixCG_CLKPIN_CNTL 0xc05001a0
#define ixCG_CLKPIN_CNTL_2 0xc05001a4
#define ixTHM_CLK_CNTL 0xc05001a8
#define ixMISC_CLK_CTRL 0xc05001ac
#define ixGCK_PLL_TEST_CNTL 0xc05001c0
#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
#define mmSMC_IND_INDEX 0x80
#define mmSMC0_SMC_IND_INDEX 0x80
#define mmSMC1_SMC_IND_INDEX 0x82
#define mmSMC2_SMC_IND_INDEX 0x84
#define mmSMC3_SMC_IND_INDEX 0x86
#define mmSMC_IND_DATA 0x81
#define mmSMC0_SMC_IND_DATA 0x81
#define mmSMC1_SMC_IND_DATA 0x83
#define mmSMC2_SMC_IND_DATA 0x85
#define mmSMC3_SMC_IND_DATA 0x87
#define mmSMC_IND_INDEX_0 0x80
#define mmSMC_IND_DATA_0 0x81
#define mmSMC_IND_INDEX_1 0x82
#define mmSMC_IND_DATA_1 0x83
#define mmSMC_IND_INDEX_2 0x84
#define mmSMC_IND_DATA_2 0x85
#define mmSMC_IND_INDEX_3 0x86
#define mmSMC_IND_DATA_3 0x87
#define mmSMC_IND_INDEX_4 0x88
#define mmSMC_IND_DATA_4 0x89
#define mmSMC_IND_INDEX_5 0x8a
#define mmSMC_IND_DATA_5 0x8b
#define mmSMC_IND_INDEX_6 0x8c
#define mmSMC_IND_DATA_6 0x8d
#define mmSMC_IND_INDEX_7 0x8e
#define mmSMC_IND_DATA_7 0x8f
#define mmSMC_IND_ACCESS_CNTL 0x90
#define mmSMC_MESSAGE_0 0x94
#define mmSMC_RESP_0 0x95
#define mmSMC_MESSAGE_1 0x96
#define mmSMC_RESP_1 0x97
#define mmSMC_MESSAGE_2 0x98
#define mmSMC_RESP_2 0x99
#define mmSMC_MESSAGE_3 0x9a
#define mmSMC_RESP_3 0x9b
#define mmSMC_MESSAGE_4 0x9c
#define mmSMC_RESP_4 0x9d
#define mmSMC_MESSAGE_5 0x9e
#define mmSMC_RESP_5 0x9f
#define mmSMC_MESSAGE_6 0xa0
#define mmSMC_RESP_6 0xa1
#define mmSMC_MESSAGE_7 0xa2
#define mmSMC_RESP_7 0xa3
#define mmSMC_MSG_ARG_0 0xa4
#define mmSMC_MSG_ARG_1 0xa5
#define mmSMC_MSG_ARG_2 0xa6
#define mmSMC_MSG_ARG_3 0xa7
#define mmSMC_MSG_ARG_4 0xa8
#define mmSMC_MSG_ARG_5 0xa9
#define mmSMC_MSG_ARG_6 0xaa
#define mmSMC_MSG_ARG_7 0xab
#define mmSMC_MESSAGE_8 0xb5
#define mmSMC_RESP_8 0xb6
#define mmSMC_MESSAGE_9 0xb7
#define mmSMC_RESP_9 0xb8
#define mmSMC_MESSAGE_10 0xb9
#define mmSMC_RESP_10 0xba
#define mmSMC_MESSAGE_11 0xbb
#define mmSMC_RESP_11 0xbc
#define mmSMC_MSG_ARG_8 0xbd
#define mmSMC_MSG_ARG_9 0xbe
#define mmSMC_MSG_ARG_10 0xbf
#define mmSMC_MSG_ARG_11 0x91
#define ixSMC_SYSCON_RESET_CNTL 0x80000000
#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
#define ixSMC_SYSCON_MISC_CNTL 0x80000010
#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
#define ixSMC_PC_C 0x80000370
#define ixSMC_SCRATCH9 0x80000424
#define mmCG_FPS_CNT 0x1a4
#define mmSMU_SMC_IND_INDEX 0x80
#define mmSMU0_SMU_SMC_IND_INDEX 0x80
#define mmSMU1_SMU_SMC_IND_INDEX 0x82
#define mmSMU2_SMU_SMC_IND_INDEX 0x84
#define mmSMU3_SMU_SMC_IND_INDEX 0x86
#define mmSMU_SMC_IND_DATA 0x81
#define mmSMU0_SMU_SMC_IND_DATA 0x81
#define mmSMU1_SMU_SMC_IND_DATA 0x83
#define mmSMU2_SMU_SMC_IND_DATA 0x85
#define mmSMU3_SMU_SMC_IND_DATA 0x87
#define ixRCU_UC_EVENTS 0xc0000004
#define ixRCU_MISC_CTRL 0xc0000010
#define ixCC_RCU_FUSES 0xc00c0000
#define ixCC_SMU_MISC_FUSES 0xc00c0004
#define ixCC_SCLK_VID_FUSES 0xc00c0008
#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
#define ixCC_GIO_IOC_FUSES 0xc00c0010
#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
#define ixCC_TST_ID_STRAPS 0xc00c0020
#define ixCC_FCTRL_FUSES 0xc00c0024
#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
#define ixSMU_STATUS 0xe0003088
#define ixSMU_FIRMWARE 0xe00030a4
#define ixSMU_INPUT_DATA 0xe00030b8
#define ixSMU_EFUSE_0 0xc0100000
#define ixDPM_TABLE_1 0x3f000
#define ixDPM_TABLE_2 0x3f004
#define ixDPM_TABLE_3 0x3f008
#define ixDPM_TABLE_4 0x3f00c
#define ixDPM_TABLE_5 0x3f010
#define ixDPM_TABLE_6 0x3f014
#define ixDPM_TABLE_7 0x3f018
#define ixDPM_TABLE_8 0x3f01c
#define ixDPM_TABLE_9 0x3f020
#define ixDPM_TABLE_10 0x3f024
#define ixDPM_TABLE_11 0x3f028
#define ixDPM_TABLE_12 0x3f02c
#define ixDPM_TABLE_13 0x3f030
#define ixDPM_TABLE_14 0x3f034
#define ixDPM_TABLE_15 0x3f038
#define ixDPM_TABLE_16 0x3f03c
#define ixDPM_TABLE_17 0x3f040
#define ixDPM_TABLE_18 0x3f044
#define ixDPM_TABLE_19 0x3f048
#define ixDPM_TABLE_20 0x3f04c
#define ixDPM_TABLE_21 0x3f050
#define ixDPM_TABLE_22 0x3f054
#define ixDPM_TABLE_23 0x3f058
#define ixDPM_TABLE_24 0x3f05c
#define ixDPM_TABLE_25 0x3f060
#define ixDPM_TABLE_26 0x3f064
#define ixDPM_TABLE_27 0x3f068
#define ixDPM_TABLE_28 0x3f06c
#define ixDPM_TABLE_29 0x3f070
#define ixDPM_TABLE_30 0x3f074
#define ixDPM_TABLE_31 0x3f078
#define ixDPM_TABLE_32 0x3f07c
#define ixDPM_TABLE_33 0x3f080
#define ixDPM_TABLE_34 0x3f084
#define ixDPM_TABLE_35 0x3f088
#define ixDPM_TABLE_36 0x3f08c
#define ixDPM_TABLE_37 0x3f090
#define ixDPM_TABLE_38 0x3f094
#define ixDPM_TABLE_39 0x3f098
#define ixDPM_TABLE_40 0x3f09c
#define ixDPM_TABLE_41 0x3f0a0
#define ixDPM_TABLE_42 0x3f0a4
#define ixDPM_TABLE_43 0x3f0a8
#define ixDPM_TABLE_44 0x3f0ac
#define ixDPM_TABLE_45 0x3f0b0
#define ixDPM_TABLE_46 0x3f0b4
#define ixDPM_TABLE_47 0x3f0b8
#define ixDPM_TABLE_48 0x3f0bc
#define ixDPM_TABLE_49 0x3f0c0
#define ixDPM_TABLE_50 0x3f0c4
#define ixDPM_TABLE_51 0x3f0c8
#define ixDPM_TABLE_52 0x3f0cc
#define ixDPM_TABLE_53 0x3f0d0
#define ixDPM_TABLE_54 0x3f0d4
#define ixDPM_TABLE_55 0x3f0d8
#define ixDPM_TABLE_56 0x3f0dc
#define ixDPM_TABLE_57 0x3f0e0
#define ixDPM_TABLE_58 0x3f0e4
#define ixDPM_TABLE_59 0x3f0e8
#define ixDPM_TABLE_60 0x3f0ec
#define ixDPM_TABLE_61 0x3f0f0
#define ixDPM_TABLE_62 0x3f0f4
#define ixDPM_TABLE_63 0x3f0f8
#define ixDPM_TABLE_64 0x3f0fc
#define ixDPM_TABLE_65 0x3f100
#define ixDPM_TABLE_66 0x3f104
#define ixDPM_TABLE_67 0x3f108
#define ixDPM_TABLE_68 0x3f10c
#define ixDPM_TABLE_69 0x3f110
#define ixDPM_TABLE_70 0x3f114
#define ixDPM_TABLE_71 0x3f118
#define ixDPM_TABLE_72 0x3f11c
#define ixDPM_TABLE_73 0x3f120
#define ixDPM_TABLE_74 0x3f124
#define ixDPM_TABLE_75 0x3f128
#define ixDPM_TABLE_76 0x3f12c
#define ixDPM_TABLE_77 0x3f130
#define ixDPM_TABLE_78 0x3f134
#define ixDPM_TABLE_79 0x3f138
#define ixDPM_TABLE_80 0x3f13c
#define ixDPM_TABLE_81 0x3f140
#define ixDPM_TABLE_82 0x3f144
#define ixDPM_TABLE_83 0x3f148
#define ixDPM_TABLE_84 0x3f14c
#define ixDPM_TABLE_85 0x3f150
#define ixDPM_TABLE_86 0x3f154
#define ixDPM_TABLE_87 0x3f158
#define ixDPM_TABLE_88 0x3f15c
#define ixDPM_TABLE_89 0x3f160
#define ixDPM_TABLE_90 0x3f164
#define ixDPM_TABLE_91 0x3f168
#define ixDPM_TABLE_92 0x3f16c
#define ixDPM_TABLE_93 0x3f170
#define ixDPM_TABLE_94 0x3f174
#define ixDPM_TABLE_95 0x3f178
#define ixDPM_TABLE_96 0x3f17c
#define ixDPM_TABLE_97 0x3f180
#define ixDPM_TABLE_98 0x3f184
#define ixDPM_TABLE_99 0x3f188
#define ixDPM_TABLE_100 0x3f18c
#define ixDPM_TABLE_101 0x3f190
#define ixDPM_TABLE_102 0x3f194
#define ixDPM_TABLE_103 0x3f198
#define ixDPM_TABLE_104 0x3f19c
#define ixDPM_TABLE_105 0x3f1a0
#define ixDPM_TABLE_106 0x3f1a4
#define ixDPM_TABLE_107 0x3f1a8
#define ixDPM_TABLE_108 0x3f1ac
#define ixDPM_TABLE_109 0x3f1b0
#define ixDPM_TABLE_110 0x3f1b4
#define ixDPM_TABLE_111 0x3f1b8
#define ixDPM_TABLE_112 0x3f1bc
#define ixDPM_TABLE_113 0x3f1c0
#define ixDPM_TABLE_114 0x3f1c4
#define ixDPM_TABLE_115 0x3f1c8
#define ixDPM_TABLE_116 0x3f1cc
#define ixDPM_TABLE_117 0x3f1d0
#define ixDPM_TABLE_118 0x3f1d4
#define ixDPM_TABLE_119 0x3f1d8
#define ixDPM_TABLE_120 0x3f1dc
#define ixDPM_TABLE_121 0x3f1e0
#define ixDPM_TABLE_122 0x3f1e4
#define ixDPM_TABLE_123 0x3f1e8
#define ixDPM_TABLE_124 0x3f1ec
#define ixDPM_TABLE_125 0x3f1f0
#define ixDPM_TABLE_126 0x3f1f4
#define ixDPM_TABLE_127 0x3f1f8
#define ixDPM_TABLE_128 0x3f1fc
#define ixDPM_TABLE_129 0x3f200
#define ixDPM_TABLE_130 0x3f204
#define ixDPM_TABLE_131 0x3f208
#define ixDPM_TABLE_132 0x3f20c
#define ixDPM_TABLE_133 0x3f210
#define ixDPM_TABLE_134 0x3f214
#define ixDPM_TABLE_135 0x3f218
#define ixDPM_TABLE_136 0x3f21c
#define ixDPM_TABLE_137 0x3f220
#define ixDPM_TABLE_138 0x3f224
#define ixDPM_TABLE_139 0x3f228
#define ixDPM_TABLE_140 0x3f22c
#define ixDPM_TABLE_141 0x3f230
#define ixDPM_TABLE_142 0x3f234
#define ixDPM_TABLE_143 0x3f238
#define ixDPM_TABLE_144 0x3f23c
#define ixDPM_TABLE_145 0x3f240
#define ixDPM_TABLE_146 0x3f244
#define ixDPM_TABLE_147 0x3f248
#define ixDPM_TABLE_148 0x3f24c
#define ixDPM_TABLE_149 0x3f250
#define ixDPM_TABLE_150 0x3f254
#define ixDPM_TABLE_151 0x3f258
#define ixDPM_TABLE_152 0x3f25c
#define ixDPM_TABLE_153 0x3f260
#define ixDPM_TABLE_154 0x3f264
#define ixDPM_TABLE_155 0x3f268
#define ixDPM_TABLE_156 0x3f26c
#define ixDPM_TABLE_157 0x3f270
#define ixDPM_TABLE_158 0x3f274
#define ixDPM_TABLE_159 0x3f278
#define ixDPM_TABLE_160 0x3f27c
#define ixDPM_TABLE_161 0x3f280
#define ixDPM_TABLE_162 0x3f284
#define ixDPM_TABLE_163 0x3f288
#define ixDPM_TABLE_164 0x3f28c
#define ixDPM_TABLE_165 0x3f290
#define ixDPM_TABLE_166 0x3f294
#define ixDPM_TABLE_167 0x3f298
#define ixDPM_TABLE_168 0x3f29c
#define ixDPM_TABLE_169 0x3f2a0
#define ixDPM_TABLE_170 0x3f2a4
#define ixDPM_TABLE_171 0x3f2a8
#define ixDPM_TABLE_172 0x3f2ac
#define ixDPM_TABLE_173 0x3f2b0
#define ixDPM_TABLE_174 0x3f2b4
#define ixDPM_TABLE_175 0x3f2b8
#define ixDPM_TABLE_176 0x3f2bc
#define ixDPM_TABLE_177 0x3f2c0
#define ixDPM_TABLE_178 0x3f2c4
#define ixDPM_TABLE_179 0x3f2c8
#define ixDPM_TABLE_180 0x3f2cc
#define ixDPM_TABLE_181 0x3f2d0
#define ixDPM_TABLE_182 0x3f2d4
#define ixDPM_TABLE_183 0x3f2d8
#define ixDPM_TABLE_184 0x3f2dc
#define ixDPM_TABLE_185 0x3f2e0
#define ixDPM_TABLE_186 0x3f2e4
#define ixDPM_TABLE_187 0x3f2e8
#define ixDPM_TABLE_188 0x3f2ec
#define ixDPM_TABLE_189 0x3f2f0
#define ixDPM_TABLE_190 0x3f2f4
#define ixDPM_TABLE_191 0x3f2f8
#define ixSOFT_REGISTERS_TABLE_1 0x3f900
#define ixSOFT_REGISTERS_TABLE_2 0x3f904
#define ixSOFT_REGISTERS_TABLE_3 0x3f908
#define ixSOFT_REGISTERS_TABLE_4 0x3f90c
#define ixSOFT_REGISTERS_TABLE_5 0x3f910
#define ixSOFT_REGISTERS_TABLE_6 0x3f914
#define ixSOFT_REGISTERS_TABLE_7 0x3f918
#define ixSOFT_REGISTERS_TABLE_8 0x3f91c
#define ixSOFT_REGISTERS_TABLE_9 0x3f920
#define ixSOFT_REGISTERS_TABLE_10 0x3f924
#define ixSOFT_REGISTERS_TABLE_11 0x3f928
#define ixSOFT_REGISTERS_TABLE_12 0x3f92c
#define ixSOFT_REGISTERS_TABLE_13 0x3f930
#define ixSOFT_REGISTERS_TABLE_14 0x3f934
#define ixSOFT_REGISTERS_TABLE_15 0x3f938
#define ixSOFT_REGISTERS_TABLE_16 0x3f93c
#define ixSOFT_REGISTERS_TABLE_17 0x3f940
#define ixSOFT_REGISTERS_TABLE_18 0x3f944
#define ixSOFT_REGISTERS_TABLE_19 0x3f948
#define ixSOFT_REGISTERS_TABLE_20 0x3f94c
#define ixSOFT_REGISTERS_TABLE_21 0x3f950
#define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00
#define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14
#define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28
#define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c
#define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50
#define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64
#define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78
#define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c
#define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04
#define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18
#define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c
#define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40
#define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54
#define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68
#define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c
#define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90
#define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08
#define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c
#define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30
#define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44
#define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58
#define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c
#define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80
#define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94
#define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c
#define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20
#define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34
#define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48
#define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c
#define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70
#define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84
#define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98
#define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10
#define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24
#define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38
#define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c
#define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60
#define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74
#define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88
#define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c
#define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0
#define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4
#define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8
#define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac
#define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0
#define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4
#define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8
#define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc
#define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0
#define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4
#define ixSMU_LCLK_DPM_CNTL 0x3fdc8
#define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc
#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0
#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4
#define ixPM_FUSES_1 0x3fa80
#define ixPM_FUSES_2 0x3fa84
#define ixPM_FUSES_3 0x3fa88
#define ixPM_FUSES_4 0x3fa8c
#define ixPM_FUSES_5 0x3fa90
#define ixPM_FUSES_6 0x3fa94
#define ixPM_FUSES_7 0x3fa98
#define ixPM_FUSES_8 0x3fa9c
#define ixPM_FUSES_9 0x3faa0
#define ixPM_FUSES_10 0x3faa4
#define ixPM_FUSES_11 0x3faa8
#define ixPM_FUSES_12 0x3faac
#define ixPM_FUSES_13 0x3fab0
#define ixPM_FUSES_14 0x3fab4
#define ixPM_FUSES_15 0x3fab8
#define ixPM_FUSES_16 0x3fabc
#define ixPM_FUSES_17 0x3fac0
#define ixPM_FUSES_18 0x3fac4
#define ixPM_FUSES_19 0x3fac8
#define ixPM_FUSES_20 0x3facc
#define ixPM_FUSES_21 0x3fad0
#define ixPM_FUSES_22 0x3fad4
#define ixPM_FUSES_23 0x3fad8
#define ixPM_FUSES_24 0x3fadc
#define ixPM_FUSES_25 0x3fae0
#define ixPM_FUSES_26 0x3fae4
#define ixPM_FUSES_27 0x3fae8
#define ixPM_FUSES_28 0x3faec
#define ixPM_FUSES_29 0x3faf0
#define ixPM_FUSES_30 0x3faf4
#define ixPM_FUSES_31 0x3faf8
#define ixPM_FUSES_32 0x3fafc
#define ixPM_FUSES_33 0x3fb00
#define ixPM_FUSES_34 0x3fb04
#define ixPM_FUSES_35 0x3fb08
#define ixPM_FUSES_36 0x3fb0c
#define ixPM_FUSES_37 0x3fb10
#define ixPM_FUSES_38 0x3fb14
#define ixPM_FUSES_39 0x3fb18
#define ixPM_FUSES_40 0x3fb1c
#define ixPM_FUSES_41 0x3fb20
#define ixPM_FUSES_42 0x3fb24
#define ixPM_FUSES_43 0x3fb28
#define ixPM_FUSES_44 0x3fb2c
#define ixPM_FUSES_45 0x3fb30
#define ixPM_FUSES_46 0x3fb34
#define ixPM_FUSES_47 0x3fb38
#define ixPM_FUSES_48 0x3fb3c
#define ixPM_FUSES_49 0x3fb40
#define ixPM_FUSES_50 0x3fb44
#define ixPM_FUSES_51 0x3fb48
#define ixPM_FUSES_52 0x3fb4c
#define ixPM_FUSES_53 0x3fb50
#define ixPM_FUSES_54 0x3fb54
#define ixPM_FUSES_55 0x3fb58
#define ixPM_FUSES_56 0x3fb5c
#define ixPM_FUSES_57 0x3fb60
#define ixPM_FUSES_58 0x3fb64
#define ixPM_FUSES_59 0x3fb68
#define ixPM_FUSES_60 0x3fb6c
#define ixPM_FUSES_61 0x3fb70
#define ixPM_FUSES_62 0x3fb74
#define ixPM_FUSES_63 0x3fb78
#define ixPM_FUSES_64 0x3fb7c
#define ixPM_FUSES_65 0x3fb80
#define ixFIRMWARE_FLAGS 0x3f800
#define ixTEMPERATURE_READ_ADDR 0x3f808
#define ixCURRENT_GNB_TEMP 0x3f810
#define ixCURRENT_GLOBAL_TEMP 0x3f814
#define ixFEATURE_STATUS 0x3f818
#define ixPCIE_PLL_RECONF 0x3f81c
#define ixPM_INTERVAL_CNTL_0 0x3f820
#define ixPM_INTERVAL_CNTL_1 0x3f824
#define ixPM_INTERVAL_CNTL_2 0x3f82c
#define ixVPC_INTERVAL_CNTL 0x3f830
#define ixDISP_PHY_TDP_LIMIT 0x3f834
#define ixFCH_PWR_CREDIT 0x3f838
#define ixPKGPWR_MV_AVG 0x3f83c
#define ixPACKAGE_POWER 0x3f840
#define ixPKG_PWR_CNTL 0x3f844
#define ixPKG_PWR_STATUS 0x3f848
#define ixDISP_PHY_CONFIG 0x3f84c
#define ixGPU_TDP_LIMIT 0x3f850
#define ixEXT_API_IN_DATA_0_0 0x3f858
#define ixEXT_API_IN_DATA_0_1 0x3f85c
#define ixEXT_API_IN_DATA_0_2 0x3f860
#define ixEXT_API_IN_DATA_0_3 0x3f864
#define ixEXT_API_OUT_DATA_0_0 0x3f868
#define ixEXT_API_OUT_DATA_0_1 0x3f86c
#define ixEXT_API_OUT_DATA_0_2 0x3f870
#define ixEXT_API_OUT_DATA_0_3 0x3f874
#define ixBAPM_PARAMETERS 0x3f984
#define ixBAPM_PARAMETERS_2 0x3f988
#define ixBAPM_PARAMETERS_3 0x3f98c
#define ixBAPM_PARAMETERS_4 0x3f990
#define ixSMU_SVI_TELEMETRY 0x3f994
#define ixBAPM_STATUS 0x3f998
#define ixSMU_HTC_STATUS 0x3f99c
#define ixSMU_VPC_STATUS 0x3f9a0
#define ixENTITY_TEMPERATURES_1 0x3f9a4
#define ixENTITY_TEMPERATURES_2 0x3f9a8
#define ixENTITY_TEMPERATURES_3 0x3f9ac
#define ixCU_POWER 0x3f9b0
#define ixGPU_POWER 0x3f9b4
#define ixNTE_POWER 0x3f9b8
#define ixTDC_STATUS 0x3f9d0
#define ixTDC_MV_AVERAGE 0x3f9d4
#define ixPM_CONFIG 0x3f9d8
#define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc
#define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0
#define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4
#define ixNB_DPM_CONFIG_1 0x3f9e8
#define ixNB_DPM_CONFIG_2 0x3f9ec
#define ixNB_DPM_CONFIG_3 0x3f9f0
#define ixSMU_IDD_OVERRIDE 0x3f9fc
#define ixAVS_CONFIG 0x3fa00
#define ixTDC_VRM_LIMIT 0x3fa04
#define ixCU0_PSM_CONFIG 0x3fa08
#define ixCU1_PSM_CONFIG 0x3fa0c
#define ixSPMI_CONFIG 0x3fa10
#define ixSPMI_SMC_CHAIN_ADDR 0x3fa14
#define ixSPMI_STATUS 0x3fa30
#define ixAVSNB_CONFIG 0x3fa34
#define ixHTC_CONFIG 0x3fa38
#define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c
#define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40
#define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44
#define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48
#define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c
#define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50
#define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54
#define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58
#define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c
#define ixSMU_TCEN_ALIVE 0x3fa60
#define ixPDM_STATUS 0x3fa64
#define ixPDM_CNTL_1 0x3fa68
#define ixPDM_CNTL_2 0x3fa6c
#define ixPDM_CNTL_3 0x3fa70
#define ixSMU_PM_STATUS_0 0x3fe00
#define ixSMU_PM_STATUS_1 0x3fe04
#define ixSMU_PM_STATUS_2 0x3fe08
#define ixSMU_PM_STATUS_3 0x3fe0c
#define ixSMU_PM_STATUS_4 0x3fe10
#define ixSMU_PM_STATUS_5 0x3fe14
#define ixSMU_PM_STATUS_6 0x3fe18
#define ixSMU_PM_STATUS_7 0x3fe1c
#define ixSMU_PM_STATUS_8 0x3fe20
#define ixSMU_PM_STATUS_9 0x3fe24
#define ixSMU_PM_STATUS_10 0x3fe28
#define ixSMU_PM_STATUS_11 0x3fe2c
#define ixSMU_PM_STATUS_12 0x3fe30
#define ixSMU_PM_STATUS_13 0x3fe34
#define ixSMU_PM_STATUS_14 0x3fe38
#define ixSMU_PM_STATUS_15 0x3fe3c
#define ixSMU_PM_STATUS_16 0x3fe40
#define ixSMU_PM_STATUS_17 0x3fe44
#define ixSMU_PM_STATUS_18 0x3fe48
#define ixSMU_PM_STATUS_19 0x3fe4c
#define ixSMU_PM_STATUS_20 0x3fe50
#define ixSMU_PM_STATUS_21 0x3fe54
#define ixSMU_PM_STATUS_22 0x3fe58
#define ixSMU_PM_STATUS_23 0x3fe5c
#define ixSMU_PM_STATUS_24 0x3fe60
#define ixSMU_PM_STATUS_25 0x3fe64
#define ixSMU_PM_STATUS_26 0x3fe68
#define ixSMU_PM_STATUS_27 0x3fe6c
#define ixSMU_PM_STATUS_28 0x3fe70
#define ixSMU_PM_STATUS_29 0x3fe74
#define ixSMU_PM_STATUS_30 0x3fe78
#define ixSMU_PM_STATUS_31 0x3fe7c
#define ixSMU_PM_STATUS_32 0x3fe80
#define ixSMU_PM_STATUS_33 0x3fe84
#define ixSMU_PM_STATUS_34 0x3fe88
#define ixSMU_PM_STATUS_35 0x3fe8c
#define ixSMU_PM_STATUS_36 0x3fe90
#define ixSMU_PM_STATUS_37 0x3fe94
#define ixSMU_PM_STATUS_38 0x3fe98
#define ixSMU_PM_STATUS_39 0x3fe9c
#define ixSMU_PM_STATUS_40 0x3fea0
#define ixSMU_PM_STATUS_41 0x3fea4
#define ixSMU_PM_STATUS_42 0x3fea8
#define ixSMU_PM_STATUS_43 0x3feac
#define ixSMU_PM_STATUS_44 0x3feb0
#define ixSMU_PM_STATUS_45 0x3feb4
#define ixSMU_PM_STATUS_46 0x3feb8
#define ixSMU_PM_STATUS_47 0x3febc
#define ixSMU_PM_STATUS_48 0x3fec0
#define ixSMU_PM_STATUS_49 0x3fec4
#define ixSMU_PM_STATUS_50 0x3fec8
#define ixSMU_PM_STATUS_51 0x3fecc
#define ixSMU_PM_STATUS_52 0x3fed0
#define ixSMU_PM_STATUS_53 0x3fed4
#define ixSMU_PM_STATUS_54 0x3fed8
#define ixSMU_PM_STATUS_55 0x3fedc
#define ixSMU_PM_STATUS_56 0x3fee0
#define ixSMU_PM_STATUS_57 0x3fee4
#define ixSMU_PM_STATUS_58 0x3fee8
#define ixSMU_PM_STATUS_59 0x3feec
#define ixSMU_PM_STATUS_60 0x3fef0
#define ixSMU_PM_STATUS_61 0x3fef4
#define ixSMU_PM_STATUS_62 0x3fef8
#define ixSMU_PM_STATUS_63 0x3fefc
#define ixSMU_PM_STATUS_64 0x3ff00
#define ixSMU_PM_STATUS_65 0x3ff04
#define ixSMU_PM_STATUS_66 0x3ff08
#define ixSMU_PM_STATUS_67 0x3ff0c
#define ixSMU_PM_STATUS_68 0x3ff10
#define ixSMU_PM_STATUS_69 0x3ff14
#define ixSMU_PM_STATUS_70 0x3ff18
#define ixSMU_PM_STATUS_71 0x3ff1c
#define ixSMU_PM_STATUS_72 0x3ff20
#define ixSMU_PM_STATUS_73 0x3ff24
#define ixSMU_PM_STATUS_74 0x3ff28
#define ixSMU_PM_STATUS_75 0x3ff2c
#define ixSMU_PM_STATUS_76 0x3ff30
#define ixSMU_PM_STATUS_77 0x3ff34
#define ixSMU_PM_STATUS_78 0x3ff38
#define ixSMU_PM_STATUS_79 0x3ff3c
#define ixSMU_PM_STATUS_80 0x3ff40
#define ixSMU_PM_STATUS_81 0x3ff44
#define ixSMU_PM_STATUS_82 0x3ff48
#define ixSMU_PM_STATUS_83 0x3ff4c
#define ixSMU_PM_STATUS_84 0x3ff50
#define ixSMU_PM_STATUS_85 0x3ff54
#define ixSMU_PM_STATUS_86 0x3ff58
#define ixSMU_PM_STATUS_87 0x3ff5c
#define ixSMU_PM_STATUS_88 0x3ff60
#define ixSMU_PM_STATUS_89 0x3ff64
#define ixSMU_PM_STATUS_90 0x3ff68
#define ixSMU_PM_STATUS_91 0x3ff6c
#define ixSMU_PM_STATUS_92 0x3ff70
#define ixSMU_PM_STATUS_93 0x3ff74
#define ixSMU_PM_STATUS_94 0x3ff78
#define ixSMU_PM_STATUS_95 0x3ff7c
#define ixSMU_PM_STATUS_96 0x3ff80
#define ixSMU_PM_STATUS_97 0x3ff84
#define ixSMU_PM_STATUS_98 0x3ff88
#define ixSMU_PM_STATUS_99 0x3ff8c
#define ixSMU_PM_STATUS_100 0x3ff90
#define ixSMU_PM_STATUS_101 0x3ff94
#define ixSMU_PM_STATUS_102 0x3ff98
#define ixSMU_PM_STATUS_103 0x3ff9c
#define ixSMU_PM_STATUS_104 0x3ffa0
#define ixSMU_PM_STATUS_105 0x3ffa4
#define ixSMU_PM_STATUS_106 0x3ffa8
#define ixSMU_PM_STATUS_107 0x3ffac
#define ixSMU_PM_STATUS_108 0x3ffb0
#define ixSMU_PM_STATUS_109 0x3ffb4
#define ixSMU_PM_STATUS_110 0x3ffb8
#define ixSMU_PM_STATUS_111 0x3ffbc
#define ixSMU_PM_STATUS_112 0x3ffc0
#define ixSMU_PM_STATUS_113 0x3ffc4
#define ixSMU_PM_STATUS_114 0x3ffc8
#define ixSMU_PM_STATUS_115 0x3ffcc
#define ixSMU_PM_STATUS_116 0x3ffd0
#define ixSMU_PM_STATUS_117 0x3ffd4
#define ixSMU_PM_STATUS_118 0x3ffd8
#define ixSMU_PM_STATUS_119 0x3ffdc
#define ixSMU_PM_STATUS_120 0x3ffe0
#define ixSMU_PM_STATUS_121 0x3ffe4
#define ixSMU_PM_STATUS_122 0x3ffe8
#define ixSMU_PM_STATUS_123 0x3ffec
#define ixSMU_PM_STATUS_124 0x3fff0
#define ixSMU_PM_STATUS_125 0x3fff4
#define ixSMU_PM_STATUS_126 0x3fff8
#define ixSMU_PM_STATUS_127 0x3fffc
#define ixCG_THERMAL_INT_ENA 0xc2100024
#define ixCG_THERMAL_INT_CTRL 0xc2100028
#define ixCG_THERMAL_INT_STATUS 0xc210002c
#define ixGENERAL_PWRMGT 0xc0200000
#define ixCNB_PWRMGT_CNTL 0xc0200004
#define ixSCLK_PWRMGT_CNTL 0xc0200008
#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
#define ixPLL_TEST_CNTL 0xc020003c
#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
#define ixCG_ACPI_CNTL 0xc0200064
#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
#define ixSMU_VOLTAGE_STATUS 0xc0200094
#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
#define ixCG_ULV_PARAMETER 0xc020015c
#define ixSCLK_MIN_DIV 0xc0200308
#define ixLCAC_SX0_CNTL 0xc0400d00
#define ixLCAC_SX0_OVR_SEL 0xc0400d04
#define ixLCAC_SX0_OVR_VAL 0xc0400d08
#define ixLCAC_MC0_CNTL 0xc0400d30
#define ixLCAC_MC0_OVR_SEL 0xc0400d34
#define ixLCAC_MC0_OVR_VAL 0xc0400d38
#define ixLCAC_MC1_CNTL 0xc0400d3c
#define ixLCAC_MC1_OVR_SEL 0xc0400d40
#define ixLCAC_MC1_OVR_VAL 0xc0400d44
#define ixLCAC_MC2_CNTL 0xc0400d48
#define ixLCAC_MC2_OVR_SEL 0xc0400d4c
#define ixLCAC_MC2_OVR_VAL 0xc0400d50
#define ixLCAC_MC3_CNTL 0xc0400d54
#define ixLCAC_MC3_OVR_SEL 0xc0400d58
#define ixLCAC_MC3_OVR_VAL 0xc0400d5c
#define ixLCAC_CPL_CNTL 0xc0400d80
#define ixLCAC_CPL_OVR_SEL 0xc0400d84
#define ixLCAC_CPL_OVR_VAL 0xc0400d88
#endif /* SMU_7_0_0_D_H */
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@@ -0,0 +1,671 @@
/*
* SMU_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_8_0_D_H
#define SMU_8_0_D_H
#define ixTHM_TCON_CSR_CONFIG 0xd82014a4
#define ixTHM_TCON_CSR_DATA 0xd82014a8
#define ixTHM_TCON_HTC 0xd8200c64
#define ixTHM_TCON_CUR_TMP 0xd8200ca4
#define ixTHM_TCON_THERM_TRIP 0xd8200ce4
#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
#define ixTHM_THERMAL_INT_ENA 0xd8200d10
#define ixTHM_THERMAL_INT_CTRL 0xd8200d14
#define ixTHM_THERMAL_INT_STATUS 0xd8200d18
#define ixTMON0_RDIL0_DATA 0xd8202000
#define ixTMON0_RDIL1_DATA 0xd8202004
#define ixTMON0_RDIL2_DATA 0xd8202008
#define ixTMON0_RDIL3_DATA 0xd820200c
#define ixTMON0_RDIL4_DATA 0xd8202010
#define ixTMON0_RDIL5_DATA 0xd8202014
#define ixTMON0_RDIL6_DATA 0xd8202018
#define ixTMON0_RDIL7_DATA 0xd820201c
#define ixTMON0_RDIL8_DATA 0xd8202020
#define ixTMON0_RDIL9_DATA 0xd8202024
#define ixTMON0_RDIL10_DATA 0xd8202028
#define ixTMON0_RDIL11_DATA 0xd820202c
#define ixTMON0_RDIL12_DATA 0xd8202030
#define ixTMON0_RDIL13_DATA 0xd8202034
#define ixTMON0_RDIL14_DATA 0xd8202038
#define ixTMON0_RDIL15_DATA 0xd820203c
#define ixTMON0_RDIR0_DATA 0xd8202040
#define ixTMON0_RDIR1_DATA 0xd8202044
#define ixTMON0_RDIR2_DATA 0xd8202048
#define ixTMON0_RDIR3_DATA 0xd820204c
#define ixTMON0_RDIR4_DATA 0xd8202050
#define ixTMON0_RDIR5_DATA 0xd8202054
#define ixTMON0_RDIR6_DATA 0xd8202058
#define ixTMON0_RDIR7_DATA 0xd820205c
#define ixTMON0_RDIR8_DATA 0xd8202060
#define ixTMON0_RDIR9_DATA 0xd8202064
#define ixTMON0_RDIR10_DATA 0xd8202068
#define ixTMON0_RDIR11_DATA 0xd820206c
#define ixTMON0_RDIR12_DATA 0xd8202070
#define ixTMON0_RDIR13_DATA 0xd8202074
#define ixTMON0_RDIR14_DATA 0xd8202078
#define ixTMON0_RDIR15_DATA 0xd820207c
#define ixTMON0_INT_DATA 0xd8202080
#define ixTMON0_RDIL_PRESENT0 0xd8202084
#define ixTMON0_RDIL_PRESENT1 0xd8202088
#define ixTMON0_RDIR_PRESENT0 0xd820208c
#define ixTMON0_RDIR_PRESENT1 0xd8202090
#define ixTMON0_CONFIG 0xd8202098
#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0
#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4
#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8
#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac
#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0
#define ixTMON0_DEBUG0 0xd82020b4
#define ixTMON0_DEBUG1 0xd82020b8
#define ixTMON1_RDIL0_DATA 0xd8202100
#define ixTMON1_RDIL1_DATA 0xd8202104
#define ixTMON1_RDIL2_DATA 0xd8202108
#define ixTMON1_RDIL3_DATA 0xd820210c
#define ixTMON1_RDIL4_DATA 0xd8202110
#define ixTMON1_RDIL5_DATA 0xd8202114
#define ixTMON1_RDIL6_DATA 0xd8202118
#define ixTMON1_RDIL7_DATA 0xd820211c
#define ixTMON1_RDIL8_DATA 0xd8202120
#define ixTMON1_RDIL9_DATA 0xd8202124
#define ixTMON1_RDIL10_DATA 0xd8202128
#define ixTMON1_RDIL11_DATA 0xd820212c
#define ixTMON1_RDIL12_DATA 0xd8202130
#define ixTMON1_RDIL13_DATA 0xd8202134
#define ixTMON1_RDIL14_DATA 0xd8202138
#define ixTMON1_RDIL15_DATA 0xd820213c
#define ixTMON1_RDIR0_DATA 0xd8202140
#define ixTMON1_RDIR1_DATA 0xd8202144
#define ixTMON1_RDIR2_DATA 0xd8202148
#define ixTMON1_RDIR3_DATA 0xd820214c
#define ixTMON1_RDIR4_DATA 0xd8202150
#define ixTMON1_RDIR5_DATA 0xd8202154
#define ixTMON1_RDIR6_DATA 0xd8202158
#define ixTMON1_RDIR7_DATA 0xd820215c
#define ixTMON1_RDIR8_DATA 0xd8202160
#define ixTMON1_RDIR9_DATA 0xd8202164
#define ixTMON1_RDIR10_DATA 0xd8202168
#define ixTMON1_RDIR11_DATA 0xd820216c
#define ixTMON1_RDIR12_DATA 0xd8202170
#define ixTMON1_RDIR13_DATA 0xd8202174
#define ixTMON1_RDIR14_DATA 0xd8202178
#define ixTMON1_RDIR15_DATA 0xd820217c
#define ixTMON1_INT_DATA 0xd8202180
#define ixTMON1_RDIL_PRESENT0 0xd8202184
#define ixTMON1_RDIL_PRESENT1 0xd8202188
#define ixTMON1_RDIR_PRESENT0 0xd820218c
#define ixTMON1_RDIR_PRESENT1 0xd8202190
#define ixTMON1_CONFIG 0xd8202198
#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0
#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4
#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8
#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac
#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0
#define ixTMON1_DEBUG0 0xd82021b4
#define ixTMON1_DEBUG1 0xd82021b8
#define ixTHM_TMON0_REMOTE_START 0xd8202800
#define ixTHM_TMON0_REMOTE_END 0xd82028fc
#define ixTHM_TMON1_REMOTE_START 0xd8202900
#define ixTHM_TMON1_REMOTE_END 0xd82029fc
#define ixTHM_TCON_LOCAL0 0xd8202e00
#define ixTHM_TCON_LOCAL1 0xd8202e04
#define ixTHM_TCON_LOCAL2 0xd8202e08
#define ixTHM_TCON_LOCAL3 0xd8202e0c
#define ixTHM_TCON_LOCAL4 0xd8202e10
#define ixTHM_TCON_LOCAL5 0xd8202e14
#define ixTHM_TCON_LOCAL6 0xd8202e18
#define ixTHM_TCON_LOCAL7 0xd8202e1c
#define ixTHM_TCON_LOCAL8 0xd8202e20
#define ixTHM_TCON_LOCAL9 0xd8202e24
#define ixTHM_TCON_LOCAL10 0xd8202e28
#define ixTHM_TCON_LOCAL11 0xd8202e2c
#define ixTHM_TCON_LOCAL12 0xd8202e30
#define ixTHM_TCON_LOCAL13 0xd8202ef8
#define ixTHM_TCON_LOCAL14 0xd8202efc
#define ixTHM_FUSE0 0xd8210000
#define ixTHM_FUSE1 0xd8210004
#define ixTHM_FUSE2 0xd8210008
#define ixTHM_FUSE3 0xd821000c
#define ixTHM_FUSE4 0xd8210010
#define ixTHM_FUSE5 0xd8210014
#define ixTHM_FUSE6 0xd8210018
#define ixTHM_FUSE7 0xd821001c
#define ixTHM_FUSE8 0xd8210020
#define ixTHM_FUSE9 0xd8210024
#define ixTHM_FUSE10 0xd8210028
#define ixTHM_FUSE11 0xd821002c
#define ixTHM_FUSE12 0xd8210030
#define mmMP0PUB_IND_INDEX 0x180
#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180
#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182
#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184
#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186
#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188
#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a
#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c
#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e
#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190
#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192
#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194
#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196
#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198
#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a
#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c
#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e
#define mmMP0PUB_IND_DATA 0x181
#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181
#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183
#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185
#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187
#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189
#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b
#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d
#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f
#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191
#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193
#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195
#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197
#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199
#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b
#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d
#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f
#define mmMP0PUB_IND_INDEX_0 0x180
#define mmMP0PUB_IND_DATA_0 0x181
#define mmMP0PUB_IND_INDEX_1 0x182
#define mmMP0PUB_IND_DATA_1 0x183
#define mmMP0PUB_IND_INDEX_2 0x184
#define mmMP0PUB_IND_DATA_2 0x185
#define mmMP0PUB_IND_INDEX_3 0x186
#define mmMP0PUB_IND_DATA_3 0x187
#define mmMP0PUB_IND_INDEX_4 0x188
#define mmMP0PUB_IND_DATA_4 0x189
#define mmMP0PUB_IND_INDEX_5 0x18a
#define mmMP0PUB_IND_DATA_5 0x18b
#define mmMP0PUB_IND_INDEX_6 0x18c
#define mmMP0PUB_IND_DATA_6 0x18d
#define mmMP0PUB_IND_INDEX_7 0x18e
#define mmMP0PUB_IND_DATA_7 0x18f
#define mmMP0PUB_IND_INDEX_8 0x190
#define mmMP0PUB_IND_DATA_8 0x191
#define mmMP0PUB_IND_INDEX_9 0x192
#define mmMP0PUB_IND_DATA_9 0x193
#define mmMP0PUB_IND_INDEX_10 0x194
#define mmMP0PUB_IND_DATA_10 0x195
#define mmMP0PUB_IND_INDEX_11 0x196
#define mmMP0PUB_IND_DATA_11 0x197
#define mmMP0PUB_IND_INDEX_12 0x198
#define mmMP0PUB_IND_DATA_12 0x199
#define mmMP0PUB_IND_INDEX_13 0x19a
#define mmMP0PUB_IND_DATA_13 0x19b
#define mmMP0PUB_IND_INDEX_14 0x19c
#define mmMP0PUB_IND_DATA_14 0x19d
#define mmMP0PUB_IND_INDEX_15 0x19e
#define mmMP0PUB_IND_DATA_15 0x19f
#define mmMP0_IND_ACCESS_CNTL 0x1a0
#define mmMP0_MSP_MESSAGE_0 0x1a1
#define mmMP0_MSP_MESSAGE_1 0x1a2
#define mmMP0_MSP_MESSAGE_2 0x1a3
#define mmMP0_MSP_MESSAGE_3 0x1a4
#define mmMP0_MSP_MESSAGE_4 0x1a5
#define mmMP0_MSP_MESSAGE_5 0x1a6
#define mmMP0_MSP_MESSAGE_6 0x1a7
#define mmMP0_MSP_MESSAGE_7 0x1a8
#define mmSAM_IH_EXT_ERR_INTR 0x1a9
#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa
#define mmMP0_DISP_TIMER0_CTRL0 0x1ab
#define mmMP0_DISP_TIMER0_CTRL1 0x1ac
#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad
#define mmMP0_DISP_TIMER0_INTEN 0x1ae
#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af
#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0
#define mmMP0_DISP_TIMER0_CNT 0x1b1
#define mmMP0_DISP_TIMER1_CTRL0 0x1b2
#define mmMP0_DISP_TIMER1_CTRL1 0x1b3
#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4
#define mmMP0_DISP_TIMER1_INTEN 0x1b5
#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6
#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7
#define mmMP0_DISP_TIMER1_CNT 0x1b8
#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0
#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1
#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2
#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3
#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4
#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5
#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6
#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7
#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8
#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9
#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca
#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb
#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc
#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd
#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce
#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf
#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0
#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1
#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2
#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3
#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4
#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5
#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6
#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7
#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8
#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9
#define mmSMU_MP1_SRBM2P_RESP_10 0x1da
#define mmSMU_MP1_SRBM2P_RESP_11 0x1db
#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc
#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd
#define mmSMU_MP1_SRBM2P_RESP_14 0x1de
#define mmSMU_MP1_SRBM2P_RESP_15 0x1df
#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0
#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1
#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2
#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3
#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4
#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5
#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6
#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7
#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8
#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9
#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea
#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb
#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec
#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed
#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee
#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef
#define mmSMU_MP1_ACP2MP_RESP 0x1f0
#define mmSMU_MP1_DC2MP_RESP 0x1f1
#define mmSMU_MP1_UVD2MP_RESP 0x1f2
#define mmSMU_MP1_VCE2MP_RESP 0x1f3
#define mmSMU_MP1_RLC2MP_RESP 0x1f4
#define mmMP_FPS_CNT 0x1f5
#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6
#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7
#define mmSMU_SRBM_CONFIG 0x1f8
#define ixMP_FPS_CNT_XBAR 0xcf200800
#define ixMP_SRBM_CONFIG_XBAR 0xcf200804
#define ixMP_SRBM_CONTROL 0xcf200c00
#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04
#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08
#define ixMP_CRBBM_CONTROL 0xcf200c0c
#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10
#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14
#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000
#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004
#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008
#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c
#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010
#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014
#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018
#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c
#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020
#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024
#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028
#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c
#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030
#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038
#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c
#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040
#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044
#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048
#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c
#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050
#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054
#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058
#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c
#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060
#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064
#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068
#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c
#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070
#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074
#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078
#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c
#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080
#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084
#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088
#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c
#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090
#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094
#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098
#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c
#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0
#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4
#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8
#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac
#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0
#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4
#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8
#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc
#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0
#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4
#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8
#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc
#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0
#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4
#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8
#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc
#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0
#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4
#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8
#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec
#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0
#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4
#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8
#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc
#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100
#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104
#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108
#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c
#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110
#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114
#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118
#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c
#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120
#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124
#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128
#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c
#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130
#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134
#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138
#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c
#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140
#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144
#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148
#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c
#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150
#define ixMP_IOC_CTRL 0xcf100000
#define ixMP_IOC_RDDATA 0xcf100004
#define ixMP_IOC_PHASE1 0xcf100008
#define ixMP_IOC_PHASE2 0xcf10000c
#define ixMP_IOC_PHASE3 0xcf100010
#define ixMP_IOC_READ_0 0xcf100024
#define ixMP_IOC_READ_1 0xcf100028
#define ixMP_IOC_READ_2 0xcf10002c
#define ixMP_IOC_READ_3 0xcf100030
#define ixMP_IOC_READ_4 0xcf100034
#define ixMP_IOC_READ_5 0xcf100038
#define ixMP_IOC_READ_6 0xcf10003c
#define ixMP_IOC_READ_7 0xcf100040
#define ixMP_IOC_READ_8 0xcf100044
#define ixMP_IOC_READ_9 0xcf100048
#define ixMP_IOC_READ_10 0xcf10004c
#define ixMP_IOC_READ_11 0xcf100050
#define ixMP_IOC_READ_12 0xcf100054
#define ixMP_IOC_READ_13 0xcf100058
#define ixMP_IOC_READ_14 0xcf10005c
#define ixMP_IOC_READ_15 0xcf100060
#define ixMP_IOC_WRITE_0 0xcf100064
#define ixMP_IOC_WRITE_1 0xcf100068
#define ixMP_IOC_WRITE_2 0xcf10006c
#define ixMP_IOC_WRITE_3 0xcf100070
#define ixMP_IOC_WRITE_4 0xcf100074
#define ixMP_IOC_WRITE_5 0xcf100078
#define ixMP_IOC_WRITE_6 0xcf10007c
#define ixMP_IOC_WRITE_7 0xcf100080
#define ixMP_IOC_WRITE_8 0xcf100084
#define ixMP_IOC_WRITE_9 0xcf100088
#define ixMP_IOC_WRITE_10 0xcf10008c
#define ixMP_IOC_WRITE_11 0xcf100090
#define ixMP_IOC_WRITE_12 0xcf100094
#define ixMP_IOC_WRITE_13 0xcf100098
#define ixMP_IOC_WRITE_14 0xcf10009c
#define ixMP_IOC_WRITE_15 0xcf1000a0
#define ixMP_INTERRUPT_CONTROL 0xcf200400
#define ixMP0_SW_INT 0xcf200404
#define ixMP0_SW_INT_CTXID 0xcf200408
#define ixMP1_SW_INT 0xcf20040c
#define ixMP1_SW_INT_CTXID 0xcf200410
#define ixDISP_TIMER_ID 0xcf200414
#define mmPWRHW_SMC_IND_INDEX 0x180
#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180
#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182
#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184
#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186
#define mmPWRHW_SMC_IND_DATA 0x181
#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181
#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183
#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185
#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187
#define ixCURRENT_STATE_CPU0 0xd0210000
#define ixCURRENT_STATE_CPU1 0xd0210010
#define ixCPU_REDUN_DONE0 0xd0210004
#define ixCPU_REDUN_DONE1 0xd0210014
#define ixCURRENT_VID_CPU0 0xd0210008
#define ixCURRENT_VID_CPU1 0xd0210018
#define ixUNBPM_PWRMGT_ACK 0xd0211000
#define ixCURRENT_FREQ_STATE_NB 0xd0211004
#define ixCURRENT_PSTATE_NB 0xd0211008
#define ixUNBPM_MSG_INT_CONFIG 0xd021100c
#define ixUNBPM_NBPWRMGT_CMD 0xd0211010
#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014
#define ixDDR0_FUSE_SSB_XFER 0xd0211018
#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c
#define ixDDR1_FUSE_SSB_XFER 0xd0211020
#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024
#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028
#define ixSYNFIFO_CLK_RATIO 0xd021102c
#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030
#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034
#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038
#define ixMISC_GNB_PWRMGT_DATA 0xd021103c
#define ixGN_GNB_SLOW 0xd0211040
#define ixGN_FORCE_NBPS1 0xd0211044
#define ixMISC_SMU_PWRMGT_DATA 0xd0211048
#define ixNB_COF 0xd021104c
#define ixUNBPM_CK_IRESET 0xd0211050
#define ixCURRENT_VID_NB 0xd0211054
#define ixSPR_FUSE_PSTATEPWR1 0xd0211058
#define ixSPR_FUSE_PSTATEPWR2 0xd021105c
#define ixSPR_FUSE_PSTATEPWR3 0xd0211060
#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064
#define ixSPR_PRODUCT_INFO0 0xd0211068
#define ixSPR_SERIALNUM_REG1 0xd021106c
#define ixSPR_SERIALNUM_REG2 0xd0211070
#define ixSPR_PRODUCT_INFO1 0xd0211074
#define ixSPR_EXT_PRODUCT_INFO 0xd021107c
#define ixSPR_MSIDFUSE 0xd0211080
#define ixSPR_LINK_PRODUCT_INFO 0xd0211084
#define ixSPR_BRAND_NAME_ADDR 0xd0211088
#define ixSPR_BRAND_NAME_DATA 0xd021108c
#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090
#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094
#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098
#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c
#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0
#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4
#define ixNUM_BOOST_STATES 0xd02110a8
#define ixWARM_RESET_NB_CONTROL 0xd02110ac
#define ixONION_NO_STREAMS_PEND 0xd02110b0
#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4
#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8
#define ixUNBPM_PWRCTRL_MISC 0xd02110bc
#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0
#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4
#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8
#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc
#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0
#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4
#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8
#define ixUNBPM_SCRATCH_0 0xd021e000
#define ixUNBPM_SCRATCH_1 0xd021e004
#define ixPOWERON_CPU_0 0xd0220000
#define ixPOWERREADY_CPU_0 0xd0220004
#define ixPGRUNFEEDBACK_CPU_0 0xd0220008
#define ixRCC3ON_CPU_0 0xd022000c
#define ixRCC3EXITDONE_CPU_0 0xd0220010
#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014
#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018
#define ixCORE_REDUN_SSB_XFER_0 0xd022001c
#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020
#define ixCORE_APM_SSB_XFER_0 0xd0220024
#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028
#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c
#define ixLDOIVRON_CPU_0 0xd0220030
#define ixLDOIVREXITDONE_CPU_0 0xd0220034
#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038
#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c
#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044
#define ixCK_DISABLECORE_CPU_0 0xd0220048
#define ixCOREPM_ID_0 0xd022004c
#define ixCOREPM_SCRATCH_0 0xd0220050
#define ixRCC3_WAKEMIN_CPU_0 0xd0220054
#define ixSPMI_CONFIG0_0 0xd0221000
#define ixSPMI_CONFIG1_0 0xd0221004
#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008
#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c
#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010
#define ixSPMI_FSM_BUSY_0 0xd0221014
#define ixSPMI_PATH_0 0xd0221018
#define ixSPMI_C6_STATE_0 0xd022101c
#define ixSPMI_JTAG_OVER_0 0xd0221020
#define ixSPMI_SRAM_ADDRESS_0 0xd0221024
#define ixSPMI_SRAM_DATA_0 0xd0221028
#define ixSPMI_RESET_0 0xd022102c
#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030
#define ixSPMI_SPARE_0 0xd0221034
#define ixSPMI_SPARE_EX_0 0xd0221038
#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c
#define ixPOWERON_CPU_1 0xd0230000
#define ixPOWERREADY_CPU_1 0xd0230004
#define ixPGRUNFEEDBACK_CPU_1 0xd0230008
#define ixRCC3ON_CPU_1 0xd023000c
#define ixRCC3EXITDONE_CPU_1 0xd0230010
#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014
#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018
#define ixCORE_REDUN_SSB_XFER_1 0xd023001c
#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020
#define ixCORE_APM_SSB_XFER_1 0xd0230024
#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028
#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c
#define ixLDOIVRON_CPU_1 0xd0230030
#define ixLDOIVREXITDONE_CPU_1 0xd0230034
#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038
#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c
#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044
#define ixCK_DISABLECORE_CPU_1 0xd0230048
#define ixCOREPM_ID_1 0xd023004c
#define ixCOREPM_SCRATCH_1 0xd0230050
#define ixRCC3_WAKEMIN_CPU_1 0xd0230054
#define ixSPMI_CONFIG0_1 0xd0231000
#define ixSPMI_CONFIG1_1 0xd0231004
#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008
#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c
#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010
#define ixSPMI_FSM_BUSY_1 0xd0231014
#define ixSPMI_PATH_1 0xd0231018
#define ixSPMI_C6_STATE_1 0xd023101c
#define ixSPMI_JTAG_OVER_1 0xd0231020
#define ixSPMI_SRAM_ADDRESS_1 0xd0231024
#define ixSPMI_SRAM_DATA_1 0xd0231028
#define ixSPMI_RESET_1 0xd023102c
#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030
#define ixSPMI_SPARE_1 0xd0231034
#define ixSPMI_SPARE_EX_1 0xd0231038
#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c
#define ixGENERAL_PWRMGT 0xd0200000
#define ixCNB_PWRMGT_CNTL 0xd0200004
#define ixSCLK_PWRMGT_CNTL 0xd0200008
#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014
#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0
#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4
#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8
#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac
#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0
#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4
#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8
#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc
#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0
#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4
#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044
#define ixCG_ACPI_CNTL 0xd0200064
#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080
#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084
#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c
#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088
#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c
#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310
#define ixSMU_VOLTAGE_STATUS 0xd0200094
#define ixCG_ULV_PARAMETER 0xd020015c
#define ixPWR_DC_RESP 0xd0200300
#define ixPWR_VCE_RESP 0xd0200304
#define ixPWR_UVD_RESP 0xd0200308
#define ixPWR_ACP_RESP 0xd020030c
#define ixPWR_DC_REQ 0xd020031c
#define ixSCLK_MIN_DIV 0xd02003ac
#define ixPCIE_PGFSM_CONFIG 0xd02002d0
#define ixPCIE_PGFSM_WRITE 0xd02002d4
#define ixSERDES_BUSY 0xd02002d8
#define ixPCIE_PGFSM2_CONFIG 0xd02002dc
#define ixPCIE_PGFSM2_WRITE 0xd02002e0
#define ixSERDES2_BUSY 0xd02002e4
#define ixPCIE_PGFSM_0_READ 0xd02002e8
#define ixPCIE_PGFSM_1_READ 0xd02002ec
#define ixPWR_ACPI_INTERRUPT 0xd0200318
#define ixVDDGFX_IDLE_PARAMETER 0xd020036c
#define ixVDDGFX_IDLE_CONTROL 0xd0200370
#define ixVDDGFX_IDLE_EXIT 0xd0200374
#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378
#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c
#define ixLCAC_MC0_CNTL 0xd0208130
#define ixLCAC_MC0_OVR_SEL 0xd0208134
#define ixLCAC_MC0_OVR_VAL 0xd0208138
#define ixLCAC_MC1_CNTL 0xd020813c
#define ixLCAC_MC1_OVR_SEL 0xd0208140
#define ixLCAC_MC1_OVR_VAL 0xd0208144
#define ixLCAC_MC2_CNTL 0xd0208148
#define ixLCAC_MC2_OVR_SEL 0xd020814c
#define ixLCAC_MC2_OVR_VAL 0xd0208150
#define ixLCAC_MC3_CNTL 0xd0208154
#define ixLCAC_MC3_OVR_SEL 0xd0208158
#define ixLCAC_MC3_OVR_VAL 0xd020815c
#define ixLCAC_CPL_CNTL 0xd0208160
#define ixLCAC_CPL_OVR_SEL 0xd0208164
#define ixLCAC_CPL_OVR_VAL 0xd0208168
#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000
#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004
#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c
#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010
#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014
#define ixSOUTHBRIDGE_TYPE 0xd020c01c
#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020
#define ixALLOW_SR_INTR_CTRL 0xd020c024
#define mmGC_CAC_LKG_AGGR_LOWER 0x3294
#define mmGC_CAC_LKG_AGGR_UPPER 0x3295
#define ixGC_CAC_WEIGHT_CU_0 0x32
#define ixGC_CAC_WEIGHT_CU_1 0x33
#define ixGC_CAC_WEIGHT_CU_2 0x34
#define ixGC_CAC_WEIGHT_CU_3 0x35
#define ixGC_CAC_ACC_CU0 0xba
#define ixGC_CAC_ACC_CU1 0xbb
#define ixGC_CAC_ACC_CU2 0xbc
#define ixGC_CAC_ACC_CU3 0xbd
#define ixGC_CAC_ACC_CU4 0xbe
#define ixGC_CAC_ACC_CU5 0xbf
#define ixGC_CAC_ACC_CU6 0xc0
#define ixGC_CAC_ACC_CU7 0xc1
#define ixGC_CAC_OVRD_CU 0xe7
#endif /* SMU_8_0_D_H */
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h
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