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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_12_0_0_offset.h
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/*
* Copyright (C) 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_12_0_0_OFFSET_HEADER
#define _umc_12_0_0_OFFSET_HEADER
#define regUMCCH0_OdEccCntSel 0x032c
#define regUMCCH0_OdEccCntSel_BASE_IDX 0
#define regUMCCH0_OdEccErrCnt 0x032d
#define regUMCCH0_OdEccErrCnt_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_12_0_0_sh_mask.h
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/*
* Copyright (C) 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_12_0_0_SH_MASK_HEADER
#define _umc_12_0_0_SH_MASK_HEADER
//UMCCH0_OdEccCntSel
#define UMCCH0_OdEccCntSel__OdEccCntSel__SHIFT 0x0
#define UMCCH0_OdEccCntSel__OdEccErrInt__SHIFT 0x4
#define UMCCH0_OdEccCntSel__OdEccCntSel_MASK 0x00000007L
#define UMCCH0_OdEccCntSel__OdEccErrInt_MASK 0x00000030L
//UMCCH0_OdEccErrCnt
#define UMCCH0_OdEccErrCnt__Cnt__SHIFT 0x0
#define UMCCH0_OdEccErrCnt__CntOvr__SHIFT 0x10
#define UMCCH0_OdEccErrCnt__OvrClr__SHIFT 0x11
#define UMCCH0_OdEccErrCnt__Cnt_MASK 0x0000FFFFL
#define UMCCH0_OdEccErrCnt__CntOvr_MASK 0x00010000L
#define UMCCH0_OdEccErrCnt__OvrClr_MASK 0x00020000L
//MCA_UMC_UMC0_MCUMC_STATUST0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT 0x2f
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT 0x36
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK 0x0000000000C00000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK 0x000000003F000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK 0x00000000C0000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK 0x000000C000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK 0x0000060000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK 0x000F800000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK 0x0040000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
//MCA_UMC_UMC0_MCUMC_ADDRT0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xFF00000000000000L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h
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/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_0_DEFAULT_HEADER
#define _umc_6_0_DEFAULT_HEADER
#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000
#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203
#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h
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/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_0_OFFSET_H_
#define _umc_6_0_OFFSET_H_
#define mmUMCCH0_0_EccCtrl 0x0053
#define mmUMCCH0_0_EccCtrl_BASE_IDX 0
#define mmUMCCH1_0_EccCtrl 0x0853
#define mmUMCCH1_0_EccCtrl_BASE_IDX 0
#define mmUMCCH2_0_EccCtrl 0x1053
#define mmUMCCH2_0_EccCtrl_BASE_IDX 0
#define mmUMCCH3_0_EccCtrl 0x1853
#define mmUMCCH3_0_EccCtrl_BASE_IDX 0
#define mmUMCCH0_0_UMC_CONFIG 0x0040
#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0
#define mmUMCCH1_0_UMC_CONFIG 0x0840
#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0
#define mmUMCCH2_0_UMC_CONFIG 0x1040
#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0
#define mmUMCCH3_0_UMC_CONFIG 0x1840
#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0
#define mmUMCCH0_0_UmcLocalCap 0x0306
#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0
#define mmUMCCH1_0_UmcLocalCap 0x0b06
#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0
#define mmUMCCH2_0_UmcLocalCap 0x1306
#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0
#define mmUMCCH3_0_UmcLocalCap 0x1b06
#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h
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/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_0_SH_MASK_HEADER
#define _umc_6_0_SH_MASK_HEADER
#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L
#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa
#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L
#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0
#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L
#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f
#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L
#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_1_1_OFFSET_HEADER
#define _umc_6_1_1_OFFSET_HEADER
#define mmUMCCH0_0_EccErrCntSel 0x0360
#define mmUMCCH0_0_EccErrCntSel_BASE_IDX 0
#define mmUMCCH0_0_EccErrCnt 0x0361
#define mmUMCCH0_0_EccErrCnt_BASE_IDX 0
#define mmMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
#define mmMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_1_1_SH_MASK_HEADER
#define _umc_6_1_1_SH_MASK_HEADER
//UMCCH0_0_EccErrCntSel
#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT 0xc
#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
//UMCCH0_0_EccErrCnt
#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT 0x0
#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
//MCA_UMC_UMC0_MCUMC_STATUST0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0__SHIFT 0x16
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1__SHIFT 0x26
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2__SHIFT 0x29
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3__SHIFT 0x2f
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4__SHIFT 0x36
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0_MASK 0x00000000FFC00000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1_MASK 0x000000C000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2_MASK 0x0000060000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3_MASK 0x000F800000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4_MASK 0x0040000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
//MCA_UMC_UMC0_MCUMC_ADDRT0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK 0x3F00000000000000L
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xC000000000000000L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_1_2_OFFSET_HEADER
#define _umc_6_1_2_OFFSET_HEADER
#define mmUMCCH0_0_EccErrCntSel_ARCT 0x0360
#define mmUMCCH0_0_EccErrCntSel_ARCT_BASE_IDX 1
#define mmUMCCH0_0_EccErrCnt_ARCT 0x0361
#define mmUMCCH0_0_EccErrCnt_ARCT_BASE_IDX 1
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT 0x03c2
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT_BASE_IDX 1
#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_ARCT 0x03c4
#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_ARCT_BASE_IDX 1
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
+91
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@@ -0,0 +1,91 @@
/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_6_1_2_SH_MASK_HEADER
#define _umc_6_1_2_SH_MASK_HEADER
//UMCCH0_0_EccErrCntSel_ARCT
#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel__SHIFT 0x0
#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt__SHIFT 0xc
#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn__SHIFT 0xf
#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel_MASK 0x0000000FL
#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt_MASK 0x00003000L
#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn_MASK 0x00008000L
//UMCCH0_0_EccErrCnt_ARCT
#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt__SHIFT 0x0
#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt_MASK 0x0000FFFFL
//MCA_UMC_UMC0_MCUMC_STATUST0_ARCT
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCode__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCodeExt__SHIFT 0x10
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV0__SHIFT 0x16
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreId__SHIFT 0x20
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV1__SHIFT 0x26
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Scrub__SHIFT 0x28
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV2__SHIFT 0x29
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Poison__SHIFT 0x2b
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Deferred__SHIFT 0x2c
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UECC__SHIFT 0x2d
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__CECC__SHIFT 0x2e
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV3__SHIFT 0x2f
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Transparent__SHIFT 0x34
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__SyndV__SHIFT 0x35
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV4__SHIFT 0x36
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__TCC__SHIFT 0x37
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreIdVal__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__PCC__SHIFT 0x39
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__AddrV__SHIFT 0x3a
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__MiscV__SHIFT 0x3b
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__En__SHIFT 0x3c
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UC__SHIFT 0x3d
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Overflow__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Val__SHIFT 0x3f
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCode_MASK 0x000000000000FFFFL
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV0_MASK 0x00000000FFC00000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreId_MASK 0x0000003F00000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV1_MASK 0x000000C000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Scrub_MASK 0x0000010000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV2_MASK 0x0000060000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Poison_MASK 0x0000080000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Deferred_MASK 0x0000100000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UECC_MASK 0x0000200000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__CECC_MASK 0x0000400000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV3_MASK 0x000F800000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Transparent_MASK 0x0010000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__SyndV_MASK 0x0020000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV4_MASK 0x0040000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__TCC_MASK 0x0080000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreIdVal_MASK 0x0100000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__PCC_MASK 0x0200000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__AddrV_MASK 0x0400000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__MiscV_MASK 0x0800000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__En_MASK 0x1000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UC_MASK 0x2000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Overflow_MASK 0x4000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Val_MASK 0x8000000000000000L
//MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT
#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__LSB__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__Reserved__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__LSB_MASK 0x3F00000000000000L
#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__Reserved_MASK 0xC000000000000000L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h
+2626
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h
+10796
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_10_0_offset.h
+35
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@@ -0,0 +1,35 @@
/*
* Copyright (C) 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_8_10_0_OFFSET_HEADER
#define _umc_8_10_0_OFFSET_HEADER
#define regUMCCH0_0_GeccErrCntSel 0x0328
#define regUMCCH0_0_GeccErrCntSel_BASE_IDX 2
#define regUMCCH0_0_GeccErrCnt 0x0329
#define regUMCCH0_0_GeccErrCnt_BASE_IDX 2
#define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 2
#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 2
#define regUMCCH0_0_GeccCtrl 0x0053
#define regUMCCH0_0_GeccCtrl_BASE_IDX 2
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_10_0_sh_mask.h
+97
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@@ -0,0 +1,97 @@
/*
* Copyright (C) 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_8_10_0_SH_MASK_HEADER
#define _umc_8_10_0_SH_MASK_HEADER
//UMCCH0_0_GeccErrCntSel
#define UMCCH0_0_GeccErrCntSel__GeccErrInt__SHIFT 0xc
#define UMCCH0_0_GeccErrCntSel__GeccErrCntEn__SHIFT 0xf
#define UMCCH0_0_GeccErrCntSel__PoisonCntEn__SHIFT 0x10
#define UMCCH0_0_GeccErrCntSel__GeccErrInt_MASK 0x00003000L
#define UMCCH0_0_GeccErrCntSel__GeccErrCntEn_MASK 0x00008000L
#define UMCCH0_0_GeccErrCntSel__PoisonCntEn_MASK 0x00030000L
//UMCCH0_0_GeccErrCnt
#define UMCCH0_0_GeccErrCnt__GeccErrCnt__SHIFT 0x0
#define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt__SHIFT 0x10
#define UMCCH0_0_GeccErrCnt__GeccErrCnt_MASK 0x0000FFFFL
#define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt_MASK 0xFFFF0000L
//MCA_UMC_UMC0_MCUMC_STATUST0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT 0x2f
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT 0x36
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK 0x0000000000C00000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK 0x000000003F000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK 0x00000000C0000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK 0x000000C000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK 0x0000060000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK 0x000F800000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK 0x0040000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
//MCA_UMC_UMC0_MCUMC_ADDRT0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
//UMCCH0_0_GeccCtrl
#define UMCCH0_0_GeccCtrl__UCFatalEn__SHIFT 0xd
#define UMCCH0_0_GeccCtrl__UCFatalEn_MASK 0x00002000L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_14_0_offset.h
+29
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@@ -0,0 +1,29 @@
/*
* Copyright (C) 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_8_14_0_OFFSET_HEADER
#define _umc_8_14_0_OFFSET_HEADER
#define regUMCCH0_GeccErrCntSel 0x0328
#define regUMCCH0_GeccErrCntSel_BASE_IDX 0
#define regUMCCH0_GeccErrCnt 0x0329
#define regUMCCH0_GeccErrCnt_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_14_0_sh_mask.h
+37
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@@ -0,0 +1,37 @@
/*
* Copyright (C) 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_8_14_0_SH_MASK_HEADER
#define _umc_8_14_0_SH_MASK_HEADER
//UMCCH0_GeccErrCntSel
#define UMCCH0_GeccErrCntSel__GeccErrInt__SHIFT 0xc
#define UMCCH0_GeccErrCntSel__GeccErrCntEn__SHIFT 0xf
#define UMCCH0_GeccErrCntSel__PoisonCntEn__SHIFT 0x10
#define UMCCH0_GeccErrCntSel__GeccErrInt_MASK 0x00003000L
#define UMCCH0_GeccErrCntSel__GeccErrCntEn_MASK 0x00008000L
#define UMCCH0_GeccErrCntSel__PoisonCntEn_MASK 0x00030000L
//UMCCH0_GeccErrCnt
#define UMCCH0_GeccErrCnt__GeccErrCnt__SHIFT 0x0
#define UMCCH0_GeccErrCnt__GeccUnCorrErrCnt__SHIFT 0x10
#define UMCCH0_GeccErrCnt__GeccErrCnt_MASK 0x0000FFFFL
#define UMCCH0_GeccErrCnt__GeccUnCorrErrCnt_MASK 0xFFFF0000L
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_7_0_offset.h
+33
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@@ -0,0 +1,33 @@
/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_8_7_0_OFFSET_HEADER
#define _umc_8_7_0_OFFSET_HEADER
#define mmUMCCH0_0_GeccErrCntSel 0x0328
#define mmUMCCH0_0_GeccErrCntSel_BASE_IDX 0
#define mmUMCCH0_0_GeccErrCnt 0x0329
#define mmUMCCH0_0_GeccErrCnt_BASE_IDX 0
#define mmMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
#define mmMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_7_0_sh_mask.h
+100
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@@ -0,0 +1,100 @@
/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_8_7_0_SH_MASK_HEADER
#define _umc_8_7_0_SH_MASK_HEADER
//UMCCH0_0_GeccErrCntSel
#define UMCCH0_0_GeccErrCntSel__GeccErrCntCsSel__SHIFT 0x0
#define UMCCH0_0_GeccErrCntSel__GeccErrInt__SHIFT 0xc
#define UMCCH0_0_GeccErrCntSel__GeccErrCntEn__SHIFT 0xf
#define UMCCH0_0_GeccErrCntSel__PoisonCntEn__SHIFT 0x10
#define UMCCH0_0_GeccErrCntSel__GeccErrCntCsSel_MASK 0x0000000FL
#define UMCCH0_0_GeccErrCntSel__GeccErrInt_MASK 0x00003000L
#define UMCCH0_0_GeccErrCntSel__GeccErrCntEn_MASK 0x00008000L
#define UMCCH0_0_GeccErrCntSel__PoisonCntEn_MASK 0x00030000L
//UMCCH0_0_GeccErrCnt
#define UMCCH0_0_GeccErrCnt__GeccErrCnt__SHIFT 0x0
#define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt__SHIFT 0x10
#define UMCCH0_0_GeccErrCnt__GeccErrCnt_MASK 0x0000FFFFL
#define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt_MASK 0xFFFF0000L
//MCA_UMC_UMC0_MCUMC_STATUST0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT 0x2f
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT 0x36
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK 0x0000000000C00000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK 0x000000003F000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK 0x00000000C0000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK 0x000000C000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK 0x0000060000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK 0x000F800000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK 0x0040000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
//MCA_UMC_UMC0_MCUMC_ADDRT0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK 0x3F00000000000000L
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xC000000000000000L
#endif