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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
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linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IRQSRCS_GFX_10_1_H__
#define __IRQSRCS_GFX_10_1_H__
#define GFX_10_1__SRCID__CP_RB_INTERRUPT_PKT 176 // B0 CP_INTERRUPT pkt in RB
#define GFX_10_1__SRCID__CP_GENERIC_INT 177 // B1 MES GENERIC INT
#define GFX_10_1__SRCID__CP_IB1_INTERRUPT_PKT 177 // B1 CP_INTERRUPT pkt in IB1
#define GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT 178 // B2 CP_INTERRUPT pkt in IB2
#define GFX_10_1__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 // B4 PM4 Pkt Rsvd Bits Error
#define GFX_10_1__SRCID__CP_EOP_INTERRUPT 181 // B5 End-of-Pipe Interrupt
#define GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR 183 // B7 Bad Opcode Error
#define GFX_10_1__SRCID__CP_PRIV_REG_FAULT 184 // B8 Privileged Register Fault
#define GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT 185 // B9 Privileged Instr Fault
#define GFX_10_1__SRCID__CP_WAIT_MEM_SEM_FAULT 186 // BA Wait Memory Semaphore Fault (Synchronization Object Fault)
#define GFX_10_1__SRCID__CP_CTX_EMPTY_INTERRUPT 187 // BB Context Empty Interrupt
#define GFX_10_1__SRCID__CP_CTX_BUSY_INTERRUPT 188 // BC Context Busy Interrupt
#define GFX_10_1__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 // C0 CP.ME Wait_Reg_Mem Poll Timeout
#define GFX_10_1__SRCID__CP_SIG_INCOMPLETE 193 // C1 "Surface Probe Fault Signal Incomplete"
#define GFX_10_1__SRCID__CP_PREEMPT_ACK 194 // C2 Preemption Ack-wledge
#define GFX_10_1__SRCID__CP_GPF 195 // C3 General Protection Fault (GPF)
#define GFX_10_1__SRCID__CP_GDS_ALLOC_ERROR 196 // C4 GDS Alloc Error
#define GFX_10_1__SRCID__CP_ECC_ERROR 197 // C5 ECC Error
#define GFX_10_1__SRCID__CP_COMPUTE_QUERY_STATUS 199 // C7 Compute query status
#define GFX_10_1__SRCID__CP_VM_DOORBELL 200 // C8 Unattached VM Doorbell Received
#define GFX_10_1__SRCID__CP_FUE_ERROR 201 // C9 ECC FUE Error
#define GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 // CA Streaming Perf Monitor Interrupt
#define GFX_10_1__SRCID__GRBM_RD_TIMEOUT_ERROR 232 // E8 CRead timeout error
#define GFX_10_1__SRCID__GRBM_REG_GUI_IDLE 233 // E9 Register GUI Idle
#define GFX_10_1__SRCID__SQ_INTERRUPT_ID 239 // EF SQ Interrupt (ttrace wrap, errors)
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h
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/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IRQSRCS_GFX_11_0_0_H__
#define __IRQSRCS_GFX_11_0_0_H__
#define GFX_11_0_0__SRCID__UTCL2_FAULT 0 // UTCL2 has encountered a fault or retry scenario
#define GFX_11_0_0__SRCID__UTCL2_DATA_POISONING 1 // UTCL2 for data poisoning
#define GFX_11_0_0__SRCID__MEM_ACCES_MON 10 // 0x0A EA memory access monitor interrupt
#define GFX_11_0_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 // 0x30 SDMA atomic*_rtn ops complete
#define GFX_11_0_0__SRCID__SDMA_TRAP 49 // 0x31 Trap
#define GFX_11_0_0__SRCID__SDMA_SRBMWRITE 50 // 0x32 SRBM write Protection
#define GFX_11_0_0__SRCID__SDMA_CTXEMPTY 51 // 0x33 Context Empty
#define GFX_11_0_0__SRCID__SDMA_PREEMPT 52 // 0x34 SDMA New Run List
#define GFX_11_0_0__SRCID__SDMA_IB_PREEMPT 53 // 0x35 sdma mid - command buffer preempt interrupt
#define GFX_11_0_0__SRCID__SDMA_DOORBELL_INVALID 54 // 0x36 Doorbell BE invalid
#define GFX_11_0_0__SRCID__SDMA_QUEUE_HANG 55 // 0x37 Queue hang or Command timeout
#define GFX_11_0_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 // 0x38 SDMA atomic CMPSWAP loop timeout
#define GFX_11_0_0__SRCID__SDMA_POLL_TIMEOUT 57 // 0x39 SRBM read poll timeout
#define GFX_11_0_0__SRCID__SDMA_PAGE_TIMEOUT 58 // 0x3A Page retry timeout after UTCL2 return nack = 1
#define GFX_11_0_0__SRCID__SDMA_PAGE_NULL 59 // 0x3B Page Null from UTCL2 when nack = 2
#define GFX_11_0_0__SRCID__SDMA_PAGE_FAULT 60 // 0x3C Page Fault Error from UTCL2 when nack = 3
#define GFX_11_0_0__SRCID__SDMA_VM_HOLE 61 // 0x3D MC or SEM address in VM hole
#define GFX_11_0_0__SRCID__SDMA_ECC 62 // 0x3E ECC Error
#define GFX_11_0_0__SRCID__SDMA_FROZEN 63 // 0x3F SDMA Frozen
#define GFX_11_0_0__SRCID__SDMA_SRAM_ECC 64 // 0x40 SRAM ECC Error
#define GFX_11_0_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 65 // 0x41 GPF(Sem incomplete timeout)
#define GFX_11_0_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 66 // 0x42 Semaphore wait fail timeout
#define GFX_11_0_0__SRCID__SDMA_FENCE 67 // 0x43 User fence
#define GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT 128 // 0x80 FED Interrupt (for data poisoning)
#define GFX_11_0_0__SRCID__CP_GENERIC_INT 177 // 0xB1 CP_GENERIC int
#define GFX_11_0_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 // 0xB4 PM4 Pkt Rsvd Bits Error
#define GFX_11_0_0__SRCID__CP_EOP_INTERRUPT 181 // 0xB5 End-of-Pipe Interrupt
#define GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR 183 // 0xB7 Bad Opcode Error
#define GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT 184 // 0xB8 Privileged Register Fault
#define GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT 185 // 0xB9 Privileged Instr Fault
#define GFX_11_0_0__SRCID__CP_WAIT_MEM_SEM_FAULT 186 // 0xBA Wait Memory Semaphore Fault (Synchronization Object Fault)
#define GFX_11_0_0__SRCID__CP_CTX_EMPTY_INTERRUPT 187 // 0xBB Context Empty Interrupt
#define GFX_11_0_0__SRCID__CP_CTX_BUSY_INTERRUPT 188 // 0xBC Context Busy Interrupt
#define GFX_11_0_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 // 0xC0 CP.ME Wait_Reg_Mem Poll Timeout
#define GFX_11_0_0__SRCID__CP_SIG_INCOMPLETE 193 // 0xC1 "Surface Probe Fault Signal Incomplete"
#define GFX_11_0_0__SRCID__CP_PREEMPT_ACK 194 // 0xC2 Preemption Ack-wledge
#define GFX_11_0_0__SRCID__CP_GPF 195 // 0xC3 General Protection Fault (GPF)
#define GFX_11_0_0__SRCID__CP_GDS_ALLOC_ERROR 196 // 0xC4 GDS Alloc Error
#define GFX_11_0_0__SRCID__CP_ECC_ERROR 197 // 0xC5 ECC Error
#define GFX_11_0_0__SRCID__CP_COMPUTE_QUERY_STATUS 199 // 0xC7 Compute query status
#define GFX_11_0_0__SRCID__CP_VM_DOORBELL 200 // 0xC8 Unattached VM Doorbell Received
#define GFX_11_0_0__SRCID__CP_FUE_ERROR 201 // 0xC9 ECC FUE Error
#define GFX_11_0_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 // 0xCA Streaming Perf Monitor Interrupt
#define GFX_11_0_0__SRCID__GRBM_RD_TIMEOUT_ERROR 232 // 0xE8 CRead timeout error
#define GFX_11_0_0__SRCID__GRBM_REG_GUI_IDLE 233 // 0xE9 Register GUI Idle
#define GFX_11_0_0__SRCID__SQ_INTERRUPT_ID 239 // 0xEF SQ Interrupt (ttrace wrap, errors)
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_0_0.h
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/* SPDX-License-Identifier: MIT */
/*
* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IRQSRCS_GFX_12_0_0_H__
#define __IRQSRCS_GFX_12_0_0_H__
#define GFX_12_0_0__SRCID__UTCL2_FAULT 0 // UTCL2 has encountered a fault or retry scenario
#define GFX_12_0_0__SRCID__UTCL2_DATA_POISONING 1 // UTCL2 for data poisoning
#define GFX_12_0_0__SRCID__MEM_ACCES_MON 10 // 0x0A EA memory access monitor interrupt
#define GFX_12_0_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 // 0x30 SDMA atomic*_rtn ops complete
#define GFX_12_0_0__SRCID__SDMA_TRAP 49 // 0x31 Trap
#define GFX_12_0_0__SRCID__SDMA_SRBMWRITE 50 // 0x32 SRBM write Protection
#define GFX_12_0_0__SRCID__SDMA_CTXEMPTY 51 // 0x33 Context Empty
#define GFX_12_0_0__SRCID__SDMA_PREEMPT 52 // 0x34 SDMA New Run List
#define GFX_12_0_0__SRCID__SDMA_IB_PREEMPT 53 // 0x35 sdma mid - command buffer preempt interrupt
#define GFX_12_0_0__SRCID__SDMA_DOORBELL_INVALID 54 // 0x36 Doorbell BE invalid
#define GFX_12_0_0__SRCID__SDMA_QUEUE_HANG 55 // 0x37 Queue hang or Command timeout
#define GFX_12_0_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 // 0x38 SDMA atomic CMPSWAP loop timeout
#define GFX_12_0_0__SRCID__SDMA_POLL_TIMEOUT 57 // 0x39 SRBM read poll timeout
#define GFX_12_0_0__SRCID__SDMA_PAGE_TIMEOUT 58 // 0x3A Page retry timeout after UTCL2 return nack = 1
#define GFX_12_0_0__SRCID__SDMA_PAGE_NULL 59 // 0x3B Page Null from UTCL2 when nack = 2
#define GFX_12_0_0__SRCID__SDMA_PAGE_FAULT 60 // 0x3C Page Fault Error from UTCL2 when nack = 3
#define GFX_12_0_0__SRCID__SDMA_VM_HOLE 61 // 0x3D MC or SEM address in VM hole
#define GFX_12_0_0__SRCID__SDMA_ECC 62 // 0x3E ECC Error
#define GFX_12_0_0__SRCID__SDMA_FROZEN 63 // 0x3F SDMA Frozen
#define GFX_12_0_0__SRCID__SDMA_SRAM_ECC 64 // 0x40 SRAM ECC Error
#define GFX_12_0_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 65 // 0x41 GPF(Sem incomplete timeout)
#define GFX_12_0_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 66 // 0x42 Semaphore wait fail timeout
#define GFX_12_0_0__SRCID__SDMA_FENCE 70 // 0x46 User fence
#define GFX_12_0_0__SRCID__RLC_GC_FED_INTERRUPT 128 // 0x80 FED Interrupt (for data poisoning)
#define GFX_12_0_0__SRCID__CP_GENERIC_INT 177 // 0xB1 CP_GENERIC int
#define GFX_12_0_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 // 0xB4 PM4 Pkt Rsvd Bits Error
#define GFX_12_0_0__SRCID__CP_EOP_INTERRUPT 181 // 0xB5 End-of-Pipe Interrupt
#define GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR 183 // 0xB7 Bad Opcode Error
#define GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT 184 // 0xB8 Privileged Register Fault
#define GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT 185 // 0xB9 Privileged Instr Fault
#define GFX_12_0_0__SRCID__CP_WAIT_MEM_SEM_FAULT 186 // 0xBA Wait Memory Semaphore Fault (Sync Object Fault)
#define GFX_12_0_0__SRCID__CP_CTX_EMPTY_INTERRUPT 187 // 0xBB Context Empty Interrupt
#define GFX_12_0_0__SRCID__CP_CTX_BUSY_INTERRUPT 188 // 0xBC Context Busy Interrupt
#define GFX_12_0_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 // 0xC0 CP.ME Wait_Reg_Mem Poll Timeout
#define GFX_12_0_0__SRCID__CP_SIG_INCOMPLETE 193 // 0xC1 "Surface Probe Fault Signal Incomplete"
#define GFX_12_0_0__SRCID__CP_PREEMPT_ACK 194 // 0xC2 Preemption Ack-wledge
#define GFX_12_0_0__SRCID__CP_GPF 195 // 0xC3 General Protection Fault (GPF)
#define GFX_12_0_0__SRCID__CP_GDS_ALLOC_ERROR 196 // 0xC4 GDS Alloc Error
#define GFX_12_0_0__SRCID__CP_ECC_ERROR 197 // 0xC5 ECC Error
#define GFX_12_0_0__SRCID__CP_COMPUTE_QUERY_STATUS 199 // 0xC7 Compute query status
#define GFX_12_0_0__SRCID__CP_VM_DOORBELL 200 // 0xC8 Unattached VM Doorbell Received
#define GFX_12_0_0__SRCID__CP_FUE_ERROR 201 // 0xC9 ECC FUE Error
#define GFX_12_0_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 // 0xCA Streaming Perf Monitor Interrupt
#define GFX_12_0_0__SRCID__GRBM_RD_TIMEOUT_ERROR 232 // 0xE8 CRead timeout error
#define GFX_12_0_0__SRCID__GRBM_REG_GUI_IDLE 233 // 0xE9 Register GUI Idle
#define GFX_12_0_0__SRCID__SQ_INTERRUPT_ID 239 // 0xEF SQ Interrupt (ttrace wrap, errors)
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h
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/*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IRQSRCS_GFX_12_1_0_H__
#define __IRQSRCS_GFX_12_1_0_H__
/* 0x0 UTCL2 has encountered a fault scenario */
#define GFX_12_1_0__SRCID__UTCL2_FAULT 0
/* 0x1 UTCL2 has encountered a retry scenario */
#define GFX_12_1_0__SRCID__UTCL2_RETRY 1
/* 0x2 UTCL2 for data poisoning */
#define GFX_12_1_0__SRCID__UTCL2_DATA_POISONING 2
/* 0x30 SDMA atomic*_rtn ops complete */
#define GFX_12_1_0__SRCID__SDMA_ATOMIC_RTN_DONE 48
/* 0x31 Trap */
#define GFX_12_1_0__SRCID__SDMA_TRAP 49
/* 0x32 SRBM write Protection */
#define GFX_12_1_0__SRCID__SDMA_SRBMWRITE 50
/* 0x33 Context Empty */
#define GFX_12_1_0__SRCID__SDMA_CTXEMPTY 51
/* 0x34 SDMA New Run List */
#define GFX_12_1_0__SRCID__SDMA_PREEMPT 52
/* 0x35 sdma mid - command buffer preempt interrupt */
#define GFX_12_1_0__SRCID__SDMA_IB_PREEMPT 53
/* 0x36 Doorbell BE invalid */
#define GFX_12_1_0__SRCID__SDMA_DOORBELL_INVALID 54
/* 0x37 Queue hang or Command timeout */
#define GFX_12_1_0__SRCID__SDMA_QUEUE_HANG 55
/* 0x38 SDMA atomic CMPSWAP loop timeout */
#define GFX_12_1_0__SRCID__SDMA_ATOMIC_TIMEOUT 56
/* 0x39 SRBM read poll timeout */
#define GFX_12_1_0__SRCID__SDMA_POLL_TIMEOUT 57
/* 0x3A Page retry timeout after UTCL2 return nack = 1 */
#define GFX_12_1_0__SRCID__SDMA_PAGE_TIMEOUT 58
/* 0x3B Page Null from UTCL2 when nack = 2 */
#define GFX_12_1_0__SRCID__SDMA_PAGE_NULL 59
/* 0x3C Page Fault Error from UTCL2 when nack = 3 */
#define GFX_12_1_0__SRCID__SDMA_PAGE_FAULT 60
/* 0x3D MC or SEM address in VM hole */
#define GFX_12_1_0__SRCID__SDMA_INVALID_ADDR 61
/* 0x3E ECC Error */
#define GFX_12_1_0__SRCID__SDMA_ECC 62
/* 0x3F SDMA Frozen */
#define GFX_12_1_0__SRCID__SDMA_FROZEN 63
/* 0x40 SRAM ECC Error */
#define GFX_12_1_0__SRCID__SDMA_SRAM_ECC 64
/* 0x41 GPF(Sem incomplete timeout) */
#define GFX_12_1_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 65
/* 0x42 Semaphore wait fail timeout */
#define GFX_12_1_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 66
/* 0x43 Wptr less than Rptr in active queue */
#define GFX_12_1_0__SRCID__SDMA_INVALID_RB_PTR 67
/* 0x44 BE command exception */
#define GFX_12_1_0__SRCID__SDMA_BE_EXCEPTION 68
/* 0x46 User fence. inherit from gfx v12_0 for gfx user queue */
#define GFX_12_1_0__SRCID__SDMA_FENCE 70
/* 0xB0 CP_INTERRUPT pkt in RB */
#define GFX_12_1_0__SRCID__CP_RB_INT_PKT 176
/* 0xB1 CP_INTERRUPT pkt in IB1 */
#define GFX_12_1_0__SRCID__CP_IB1_INT_PKT 177
/* 0xB2 CP_INTERRUPT pkt in IB2 */
#define GFX_12_1_0__SRCID__CP_IB2_INT_PKT 178
/* 0xB3 DMA Watch Interrupt */
#define GFX_12_1_0__SRCID__CP_DMA_WATCH_INTERRUPT 179
/* 0xB4 PM4 Pkt Rsvd Bits Error */
#define GFX_12_1_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180
/* 0xB5 End-of-Pipe Interrupt */
#define GFX_12_1_0__SRCID__CP_EOP_INTERRUPT 181
/* 0xB7 Bad Opcode Error */
#define GFX_12_1_0__SRCID__CP_BAD_OPCODE_ERROR 183
/* 0xB8 Privileged Register Fault */
#define GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT 184
/* 0xB9 Privileged Instr Fault */
#define GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT 185
/* 0xBA Wait Memory Semaphore Fault (Sync Object Fault) */
#define GFX_12_1_0__SRCID__CP_WAIT_MEM_SEM_FAULT 186
/* 0xBB Context Empty Interrupt */
#define GFX_12_1_0__SRCID__CP_CTX_EMPTY_INTERRUPT 187
/* 0xBC Context Busy Interrupt */
#define GFX_12_1_0__SRCID__CP_CTX_BUSY_INTERRUPT 188
/* 0xC0 CP.ME Wait_Reg_Mem Poll Timeout */
#define GFX_12_1_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192
/* 0xC1 Surface Probe Fault Signal Incomplete */
#define GFX_12_1_0__SRCID__CP_SIG_INCOMPLETE 193
/* 0xC2 Preemption Ack-wledge */
#define GFX_12_1_0__SRCID__CP_PREEMPT_ACK 194
/* 0xC3 General Protection Fault (GPF) */
#define GFX_12_1_0__SRCID__CP_GPF 195
/* 0xC4 GDS Alloc Error */
#define GFX_12_1_0__SRCID__CP_GDS_ALLOC_ERROR 196
/* 0xC5 ECC Error */
#define GFX_12_1_0__SRCID__CP_ECC_ERROR 197
/* 0xC8 Unattached VM Doorbell Received */
#define GFX_12_1_0__SRCID__CP_VM_DOORBELL 200
/* 0xC9 ECC FUE Error */
#define GFX_12_1_0__SRCID__CP_FUE_ERROR 201
/* 0xCA Suspend Completion Interrupt */
#define GFX_12_1_0__SRCID__CP_SUSPEAND_REQ_INTERRUPT 202
/* 0xCB Resume Completion Interrupt */
#define GFX_12_1_0__SRCID__CP_RESUME_REQ_INTERRUPT 203
/* 0xCA RLC Streaming Perf Monitor Interrupt
* ContextID[15:0] each bit indicates poison is seen on respecive indexed VMID
* Ex: ContextID[3] == 1 means VMID-3 encountered poison consumption
* ContextID[16] == 1 indicates that complete VF need to reset with FLR */
#define GFX_12_1_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202
/* 0xCB RLC Poison Interrupt */
#define GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT 203
/* 0xE7 High on ContextID[0] - nHT Error; ContextID[1] - illegal Opcode Error */
#define GFX_12_1_0__SRCID__PMR_EA_ERROR_INTERRUPT 231
/* 0xE8 CRead timeout error */
#define GFX_12_1_0__SRCID__GRBM_RD_TIMEOUT_ERROR 232
/* 0xE9 Register GUI Idle */
#define GFX_12_1_0__SRCID__GRBM_REG_GUI_IDLE 233
/* 0xEF SQ Interrupt (ttrace wrap, errors) */
#define GFX_12_1_0__SRCID__SQ_INTERRUPT_ID 239
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_9_0.h
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_GFX_9_0_H__
#define __IRQSRCS_GFX_9_0_H__
#define GFX_9_0__SRCID__CP_RB_INTERRUPT_PKT 176 /* B0 CP_INTERRUPT pkt in RB */
#define GFX_9_0__SRCID__CP_IB1_INTERRUPT_PKT 177 /* B1 CP_INTERRUPT pkt in IB1 */
#define GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT 178 /* B2 CP_INTERRUPT pkt in IB2 */
#define GFX_9_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 /* B4 PM4 Pkt Rsvd Bits Error */
#define GFX_9_0__SRCID__CP_EOP_INTERRUPT 181 /* B5 End-of-Pipe Interrupt */
#define GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR 183 /* B7 Bad Opcode Error */
#define GFX_9_0__SRCID__CP_PRIV_REG_FAULT 184 /* B8 Privileged Register Fault */
#define GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT 185 /* B9 Privileged Instr Fault */
#define GFX_9_0__SRCID__CP_WAIT_MEM_SEM_FAULT 186 /* BA Wait Memory Semaphore Fault (Synchronization Object Fault) */
#define GFX_9_0__SRCID__CP_CTX_EMPTY_INTERRUPT 187 /* BB Context Empty Interrupt */
#define GFX_9_0__SRCID__CP_CTX_BUSY_INTERRUPT 188 /* BC Context Busy Interrupt */
#define GFX_9_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 /* C0 CP.ME Wait_Reg_Mem Poll Timeout */
#define GFX_9_0__SRCID__CP_SIG_INCOMPLETE 193 /* C1 "Surface Probe Fault Signal Incomplete" */
#define GFX_9_0__SRCID__CP_PREEMPT_ACK 194 /* C2 Preemption Ack-wledge */
#define GFX_9_0__SRCID__CP_GPF 195 /* C3 General Protection Fault (GPF) */
#define GFX_9_0__SRCID__CP_GDS_ALLOC_ERROR 196 /* C4 GDS Alloc Error */
#define GFX_9_0__SRCID__CP_ECC_ERROR 197 /* C5 ECC Error */
#define GFX_9_0__SRCID__CP_COMPUTE_QUERY_STATUS 199 /* C7 Compute query status */
#define GFX_9_0__SRCID__CP_VM_DOORBELL 200 /* C8 Unattached VM Doorbell Received */
#define GFX_9_0__SRCID__CP_FUE_ERROR 201 /* C9 ECC FUE Error */
#define GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 /* CA Streaming Perf Monitor Interrupt */
#define GFX_9_0__SRCID__GRBM_RD_TIMEOUT_ERROR 232 /* E8 CRead timeout error */
#define GFX_9_0__SRCID__GRBM_REG_GUI_IDLE 233 /* E9 Register GUI Idle */
#define GFX_9_0__SRCID__SQ_INTERRUPT_ID 239 /* EF SQ Interrupt (ttrace wrap, errors) */
#endif /* __IRQSRCS_GFX_9_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h
+62
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@@ -0,0 +1,62 @@
/*
* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IRQSRCS_ISP_4_1_H__
#define __IRQSRCS_ISP_4_1_H__
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_FAIL_TIMEOUT 0x12 // Semaphore wait fail timeout
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_INCOMPLETE_TIMEOUT 0x13 // Semaphore wait incomplete timeout
#define ISP_4_1__SRCID__ISP_SEMA_SIGNAL_INCOMPLETE_TIMEOUT 0x14 // Semaphore signal incomplete timeout
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE5_CHANGED 0x15 // Ringbuffer base5 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT5 0x16 // Ringbuffer write point 5 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE6_CHANGED 0x17 // Ringbuffer base6 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT6 0x18 // Ringbuffer write point 6 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE7_CHANGED 0x19 // Ringbuffer base7 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT7 0x1A // Ringbuffer write point 7 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE8_CHANGED 0x1B // Ringbuffer base8 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT8 0x1C // Ringbuffer write point 8 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE9_CHANGED 0x00 // Ringbuffer base9 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9 0x01 // Ringbuffer write point 9 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE10_CHANGED 0x02 // Ringbuffer base10 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10 0x03 // Ringbuffer write point 10 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE11_CHANGED 0x04 // Ringbuffer base11 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11 0x05 // Ringbuffer write point 11 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE12_CHANGED 0x06 // Ringbuffer base12 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12 0x07 // Ringbuffer write point 12 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE13_CHANGED 0x08 // Ringbuffer base13 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13 0x09 // Ringbuffer write point 13 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE14_CHANGED 0x0A // Ringbuffer base14 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14 0x0B // Ringbuffer write point 14 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE15_CHANGED 0x0C // Ringbuffer base15 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15 0x0D // Ringbuffer write point 15 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE16_CHANGED 0x0E // Ringbuffer base16 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16 0x0F // Ringbuffer write point 16 changed
#define ISP_4_1__SRCID__ISP_MIPI0 0x29 // MIPI0 interrupt
#define ISP_4_1__SRCID__ISP_MIPI1 0x2A // MIPI1 interrupt
#define ISP_4_1__SRCID__ISP_I2C0 0x2B // I2C0 PAD interrupt
#define ISP_4_1__SRCID__ISP_I2C1 0x2C // I2C1 PAD interrupt
#define ISP_4_1__SRCID__ISP_FLASH0 0x2D // Flash0 interrupt
#define ISP_4_1__SRCID__ISP_FLASH1 0x2E // Flash1 interrupt
#define ISP_4_1__SRCID__ISP_DEBUG 0x2F // Debug information
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
+299
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@@ -0,0 +1,299 @@
/*
* Volcanic Islands IV SRC Register documentation
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _IVSRCID_VISLANDS30_H_
#define _IVSRCID_VISLANDS30_H_
// IV Source IDs
#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
#define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
#define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
#define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
#define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
#define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c
#define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d
#define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e
#define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f
#define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10
#define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11
#define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12
#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 19 // 0x13
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0 7
#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1 19 // 0x13
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1 8
#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2 19 // 0x13
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS 19 // 0x13
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS 10
#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC 19 // 0x13
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC 11
#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL 19 // 0x13
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL 12
#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0 20 // 0x14
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0 7
#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1 20 // 0x14
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1 8
#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2 20 // 0x14
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS 20 // 0x14
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS 10
#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC 20 // 0x14
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC 11
#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL 20 // 0x14
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL 12
#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0 21 // 0x15
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0 7
#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1 21 // 0x15
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1 8
#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2 21 // 0x15
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS 21 // 0x15
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS 10
#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC 21 // 0x15
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC 11
#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL 21 // 0x15
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL 12
#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0 22 // 0x16
#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0 7
#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1 22 // 0x16
#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1 8
#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2 22 // 0x16
#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS 22 // 0x16
#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS 10
#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC 22 // 0x16
#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC 11
#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL 22 // 0x16
#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL 12
#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0 23 // 0x17
#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0 7
#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1 23 // 0x17
#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1 8
#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2 23 // 0x17
#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS 23 // 0x17
#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS 10
#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC 23 // 0x17
#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC 11
#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL 23 // 0x17
#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL 12
#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0 24 // 0x18
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0 7
#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1 24 // 0x18
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1 8
#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2 24 // 0x18
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A 0
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B 1
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C 2
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D 3
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E 4
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F 5
#define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_A 6
#define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_B 7
#define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_C 8
#define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_D 9
#define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_E 10
#define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_F 11
#define VISLANDS30_IV_SRCID_GPIO_19 0x00000053 /* 83 */
#define VISLANDS30_IV_SRCID_SRBM_READ_TIMEOUT_ERR 0x00000060 /* 96 */
#define VISLANDS30_IV_SRCID_SRBM_CTX_SWITCH 0x00000061 /* 97 */
#define VISLANDS30_IV_SRBM_REG_ACCESS_ERROR 0x00000062 /* 98 */
#define VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP 0x00000077 /* 119 */
#define VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 0x0000007c /* 124 */
#define VISLANDS30_IV_SRCID_BIF_PF_VF_MSGBUF_VALID 0x00000087 /* 135 */
#define VISLANDS30_IV_SRCID_BIF_VF_PF_MSGBUF_ACK 0x0000008a /* 138 */
#define VISLANDS30_IV_SRCID_SYS_PAGE_INV_FAULT 0x0000008c /* 140 */
#define VISLANDS30_IV_SRCID_SYS_MEM_PROT_FAULT 0x0000008d /* 141 */
#define VISLANDS30_IV_SRCID_SEM_PAGE_INV_FAULT 0x00000090 /* 144 */
#define VISLANDS30_IV_SRCID_SEM_MEM_PROT_FAULT 0x00000091 /* 145 */
#define VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT 0x00000092 /* 146 */
#define VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT 0x00000093 /* 147 */
#define VISLANDS30_IV_SRCID_ACP 0x000000a2 /* 162 */
#define VISLANDS30_IV_SRCID_VCE_TRAP 0x000000a7 /* 167 */
#define VISLANDS30_IV_EXTID_VCE_TRAP_GENERAL_PURPOSE 0
#define VISLANDS30_IV_EXTID_VCE_TRAP_LOW_LATENCY 1
#define VISLANDS30_IV_EXTID_VCE_TRAP_REAL_TIME 2
#define VISLANDS30_IV_SRCID_CP_INT_RB 0x000000b0 /* 176 */
#define VISLANDS30_IV_SRCID_CP_INT_IB1 0x000000b1 /* 177 */
#define VISLANDS30_IV_SRCID_CP_INT_IB2 0x000000b2 /* 178 */
#define VISLANDS30_IV_SRCID_CP_PM4_RES_BITS_ERR 0x000000b4 /* 180 */
#define VISLANDS30_IV_SRCID_CP_END_OF_PIPE 0x000000b5 /* 181 */
#define VISLANDS30_IV_SRCID_CP_BAD_OPCODE 0x000000b7 /* 183 */
#define VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT 0x000000b8 /* 184 */
#define VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT 0x000000b9 /* 185 */
#define VISLANDS30_IV_SRCID_CP_WAIT_MEM_SEM_FAULT 0x000000ba /* 186 */
#define VISLANDS30_IV_SRCID_CP_GUI_IDLE 0x000000bb /* 187 */
#define VISLANDS30_IV_SRCID_CP_GUI_BUSY 0x000000bc /* 188 */
#define VISLANDS30_IV_SRCID_CP_COMPUTE_QUERY_STATUS 0x000000bf /* 191 */
#define VISLANDS30_IV_SRCID_CP_ECC_ERROR 0x000000c5 /* 197 */
#define CARRIZO_IV_SRCID_CP_COMPUTE_QUERY_STATUS 0x000000c7 /* 199 */
#define VISLANDS30_IV_SRCID_CP_WAIT_REG_MEM_POLL_TIMEOUT 0x000000c0 /* 192 */
#define VISLANDS30_IV_SRCID_CP_SEM_SIG_INCOMPL 0x000000c1 /* 193 */
#define VISLANDS30_IV_SRCID_CP_PREEMPT_ACK 0x000000c2 /* 194 */
#define VISLANDS30_IV_SRCID_CP_GENERAL_PROT_FAULT 0x000000c3 /* 195 */
#define VISLANDS30_IV_SRCID_CP_GDS_ALLOC_ERROR 0x000000c4 /* 196 */
#define VISLANDS30_IV_SRCID_CP_ECC_ERROR 0x000000c5 /* 197 */
#define VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR 0x000000ca /* 202 */
#define VISLANDS30_IV_SDMA_ATOMIC_SRC_ID 0x000000da /* 218 */
#define VISLANDS30_IV_SRCID_SDMA_ECC_ERROR 0x000000dc /* 220 */
#define VISLANDS30_IV_SRCID_SDMA_TRAP 0x000000e0 /* 224 */
#define VISLANDS30_IV_SRCID_SDMA_SEM_INCOMPLETE 0x000000e1 /* 225 */
#define VISLANDS30_IV_SRCID_SDMA_SEM_WAIT 0x000000e2 /* 226 */
#define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER 0x000000e5 /* 229 */
#define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH 0x000000e6 /* 230 */
#define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW 0x000000e7 /* 231 */
#define VISLANDS30_IV_SRCID_GRBM_READ_TIMEOUT_ERR 0x000000e8 /* 232 */
#define VISLANDS30_IV_SRCID_GRBM_REG_GUI_IDLE 0x000000e9 /* 233 */
#define VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG 0x000000ef /* 239 */
#define VISLANDS30_IV_SRCID_SDMA_PREEMPT 0x000000f0 /* 240 */
#define VISLANDS30_IV_SRCID_SDMA_VM_HOLE 0x000000f2 /* 242 */
#define VISLANDS30_IV_SRCID_SDMA_CTXEMPTY 0x000000f3 /* 243 */
#define VISLANDS30_IV_SRCID_SDMA_DOORBELL_INVALID 0x000000f4 /* 244 */
#define VISLANDS30_IV_SRCID_SDMA_FROZEN 0x000000f5 /* 245 */
#define VISLANDS30_IV_SRCID_SDMA_POLL_TIMEOUT 0x000000f6 /* 246 */
#define VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE 0x000000f7 /* 247 */
#define VISLANDS30_IV_SRCID_CG_THERMAL_TRIG 0x000000f8 /* 248 */
#define VISLANDS30_IV_SRCID_SMU_DISP_TIMER_TRIGGER 0x000000fd /* 253 */
/* These are not "real" source ids defined by HW */
#define VISLANDS30_IV_SRCID_VM_CONTEXT_ALL 0x00000100 /* 256 */
#define VISLANDS30_IV_EXTID_VM_CONTEXT0_ALL 0
#define VISLANDS30_IV_EXTID_VM_CONTEXT1_ALL 1
/* IV Extended IDs */
#define VISLANDS30_IV_EXTID_NONE 0x00000000
#define VISLANDS30_IV_EXTID_INVALID 0xffffffff
#endif // _IVSRCID_VISLANDS30_H_
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+42
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@@ -0,0 +1,42 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_NBIF_7_4_H__
#define __IRQSRCS_NBIF_7_4_H__
#define NBIF_7_4__SRCID__CHIP_ERR_INT_EVENT 0x5E // Error generated
#define NBIF_7_4__SRCID__DOORBELL_INTERRUPT 0x5F // Interrupt for doorbell event during VDDGFX off
#define NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT 0x60 // Interrupt for ras_intr_valid from RAS controller
#define NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT 0x61 // Interrupt for SDP ErrEvent received from ATHUB
#define NBIF_7_4__SRCID__PF_VF_MSGBUF_VALID 0x87 // Valid message in PF->VF mailbox message buffer (The interrupt is sent on behalf of PF)
#define NBIF_7_4__SRCID__PF_VF_MSGBUF_ACK 0x88 // Acknowledge message in PF->VF mailbox message buffer (The interrupt is sent on behalf of VF)
#define NBIF_7_4__SRCID__VF_PF_MSGBUF_VALID 0x89 // Valid message in VF->PF mailbox message buffer (The interrupt is sent on behalf of VF)
#define NBIF_7_4__SRCID__VF_PF_MSGBUF_ACK 0x8A // Acknowledge message in VF->PF mailbox message buffer (The interrupt is sent on behalf of PF)
#define NBIF_7_4__SRCID__CHIP_DPA_INT_EVENT 0xA0 // BIF_CHIP_DPA_INT_EVENT
#define NBIF_7_4__SRCID__CHIP_SLOT_POWER_CHG_INT_EVENT 0xA1 // BIF_CHIP_SLOT_POWER_CHG_INT_EVENT
#define NBIF_7_4__SRCID__ATOMIC_UR_OPCODE 0xCE // BIF receives unsupported atomic opcode from MC
#define NBIF_7_4__SRCID__ATOMIC_REQESTEREN_LOW 0xCF // BIF receive atomic request from MC while AtomicOp Requester is not enabled in PCIE config space
#endif // __IRQSRCS_NBIF_7_4_H__
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_4_0.h
+50
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_SDMA0_4_0_H__
#define __IRQSRCS_SDMA0_4_0_H__
#define SDMA0_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA atomic*_rtn ops complete */
#define SDMA0_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA atomic CMPSWAP loop timeout */
#define SDMA0_4_0__SRCID__SDMA_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer preempt interrupt */
#define SDMA0_4_0__SRCID__SDMA_ECC 220 /* 0xDC ECC Error */
#define SDMA0_4_0__SRCID__SDMA_PAGE_FAULT 221 /* 0xDD Page Fault Error from UTCL2 when nack=3 */
#define SDMA0_4_0__SRCID__SDMA_PAGE_NULL 222 /* 0xDE Page Null from UTCL2 when nack=2 */
#define SDMA0_4_0__SRCID__SDMA_XNACK 223 /* 0xDF Page retry timeout after UTCL2 return nack=1 */
#define SDMA0_4_0__SRCID__SDMA_TRAP 224 /* 0xE0 Trap */
#define SDMA0_4_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 /* 0xE1 0xDAGPF (Sem incomplete timeout) */
#define SDMA0_4_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 /* 0xE2 Semaphore wait fail timeout */
#define SDMA0_4_0__SRCID__SDMA_SRAM_ECC 228 /* 0xE4 SRAM ECC Error */
#define SDMA0_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA New Run List */
#define SDMA0_4_0__SRCID__SDMA_VM_HOLE 242 /* 0xF2 MC or SEM address in VM hole */
#define SDMA0_4_0__SRCID__SDMA_CTXEMPTY 243 /* 0xF3 Context Empty */
#define SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID 244 /* 0xF4 Doorbell BE invalid */
#define SDMA0_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA Frozen */
#define SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT 246 /* 0xF6 SRBM read poll timeout */
#define SDMA0_4_0__SRCID__SDMA_SRBMWRITE 247 /* 0xF7 SRBM write Protection */
#endif /* __IRQSRCS_SDMA_4_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_SDMA0_5_0_H__
#define __IRQSRCS_SDMA0_5_0_H__
#define SDMA0_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
#define SDMA0_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
#define SDMA0_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
#define SDMA0_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
#define SDMA0_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3
#define SDMA0_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2
#define SDMA0_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1
#define SDMA0_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap
#define SDMA0_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout)
#define SDMA0_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout
#define SDMA0_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error
#define SDMA0_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
#define SDMA0_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole
#define SDMA0_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty
#define SDMA0_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid
#define SDMA0_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
#define SDMA0_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout
#define SDMA0_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_4_0.h
+50
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_SDMA1_4_0_H__
#define __IRQSRCS_SDMA1_4_0_H__
#define SDMA1_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA atomic*_rtn ops complete */
#define SDMA1_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA atomic CMPSWAP loop timeout */
#define SDMA1_4_0__SRCID__SDMA_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer preempt interrupt */
#define SDMA1_4_0__SRCID__SDMA_ECC 220 /* 0xDC ECC Error */
#define SDMA1_4_0__SRCID__SDMA_PAGE_FAULT 221 /* 0xDD Page Fault Error from UTCL2 when nack=3 */
#define SDMA1_4_0__SRCID__SDMA_PAGE_NULL 222 /* 0xDE Page Null from UTCL2 when nack=2 */
#define SDMA1_4_0__SRCID__SDMA_XNACK 223 /* 0xDF Page retry timeout after UTCL2 return nack=1 */
#define SDMA1_4_0__SRCID__SDMA_TRAP 224 /* 0xE0 Trap */
#define SDMA1_4_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 /* 0xE1 0xDAGPF (Sem incomplete timeout) */
#define SDMA1_4_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 /* 0xE2 Semaphore wait fail timeout */
#define SDMA1_4_0__SRCID__SDMA_SRAM_ECC 228 /* 0xE4 SRAM ECC Error */
#define SDMA1_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA New Run List */
#define SDMA1_4_0__SRCID__SDMA_VM_HOLE 242 /* 0xF2 MC or SEM address in VM hole */
#define SDMA1_4_0__SRCID__SDMA_CTXEMPTY 243 /* 0xF3 Context Empty */
#define SDMA1_4_0__SRCID__SDMA_DOORBELL_INVALID 244 /* 0xF4 Doorbell BE invalid */
#define SDMA1_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA Frozen */
#define SDMA1_4_0__SRCID__SDMA_POLL_TIMEOUT 246 /* 0xF6 SRBM read poll timeout */
#define SDMA1_4_0__SRCID__SDMA_SRBMWRITE 247 /* 0xF7 SRBM write Protection */
#endif /* __IRQSRCS_SDMA1_4_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h
+44
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_SDMA1_5_0_H__
#define __IRQSRCS_SDMA1_5_0_H__
#define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
#define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
#define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
#define SDMA1_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
#define SDMA1_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3
#define SDMA1_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2
#define SDMA1_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1
#define SDMA1_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap
#define SDMA1_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout)
#define SDMA1_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout
#define SDMA1_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error
#define SDMA1_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
#define SDMA1_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole
#define SDMA1_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty
#define SDMA1_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid
#define SDMA1_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
#define SDMA1_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout
#define SDMA1_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h
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/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_SDMA2_5_0_H__
#define __IRQSRCS_SDMA2_5_0_H__
#define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
#define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
#define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
#define SDMA2_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
#define SDMA2_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3
#define SDMA2_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2
#define SDMA2_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1
#define SDMA2_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap
#define SDMA2_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout)
#define SDMA2_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout
#define SDMA2_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error
#define SDMA2_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
#define SDMA2_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole
#define SDMA2_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty
#define SDMA2_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid
#define SDMA2_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
#define SDMA2_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout
#define SDMA2_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection
#endif // __IRQSRCS_SDMA2_5_0_H__
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h
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/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_SDMA3_5_0_H__
#define __IRQSRCS_SDMA3_5_0_H__
#define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
#define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
#define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
#define SDMA3_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
#define SDMA3_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3
#define SDMA3_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2
#define SDMA3_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1
#define SDMA3_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap
#define SDMA3_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout)
#define SDMA3_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout
#define SDMA3_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error
#define SDMA3_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
#define SDMA3_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole
#define SDMA3_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty
#define SDMA3_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid
#define SDMA3_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
#define SDMA3_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout
#define SDMA3_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection
#endif // __IRQSRCS_SDMA3_5_0_H__
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/smuio/irqsrcs_smuio_9_0.h
+32
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_SMUIO_9_0_H__
#define __IRQSRCS_SMUIO_9_0_H__
#define SMUIO_9_0__SRCID__SMUIO_GPIO19 83 /* GPIO19 interrupt */
#endif /* __IRQSRCS_SMUIO_9_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/thm/irqsrcs_thm_9_0.h
+33
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_THM_9_0_H__
#define __IRQSRCS_THM_9_0_H__
#define THM_9_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
#define THM_9_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
#endif /* __IRQSRCS_THM_9_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/uvd/irqsrcs_uvd_7_0.h
+34
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_UVD_7_0_H__
#define __IRQSRCS_UVD_7_0_H__
#define UVD_7_0__SRCID__UVD_ENC_GEN_PURP 119
#define UVD_7_0__SRCID__UVD_ENC_LOW_LATENCY 120
#define UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 /* UVD system message interrupt */
#endif /* __IRQSRCS_UVD_7_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vce/irqsrcs_vce_4_0.h
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_VCE_4_0_H__
#define __IRQSRCS_VCE_4_0_H__
#define VCE_4_0__CTXID__VCE_TRAP_GENERAL_PURPOSE 0
#define VCE_4_0__CTXID__VCE_TRAP_LOW_LATENCY 1
#define VCE_4_0__CTXID__VCE_TRAP_REAL_TIME 2
#endif /* __IRQSRCS_VCE_4_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_1_0.h
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_VCN_1_0_H__
#define __IRQSRCS_VCN_1_0_H__
#define VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE 119 /* 0x77 Encoder General Purpose */
#define VCN_1_0__SRCID__UVD_ENC_LOW_LATENCY 120 /* 0x78 Encoder Low Latency */
#define VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 /* 0x7c UVD system message interrupt */
#endif /* __IRQSRCS_VCN_1_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_VCN_2_0_H__
#define __IRQSRCS_VCN_2_0_H__
#define VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE 119 // 0x77 Encoder General Purpose
#define VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY 120 // 0x78 Encoder Low Latency
#define VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 // 0x7c UVD system message interrupt
#define VCN_2_0__SRCID__JPEG_ENCODE 151 // 0x97 JRBC Encode interrupt
#define VCN_2_0__SRCID__JPEG_DECODE 153 // 0x99 JRBC Decode interrupt
#define VCN_2_6__SRCID_UVD_POISON 160
#define VCN_2_6__SRCID_DJPEG0_POISON 161
#define VCN_2_6__SRCID_EJPEG0_POISON 162
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h
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/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_VCN_4_0_H__
#define __IRQSRCS_VCN_4_0_H__
#define VCN_4_0__SRCID__UVD_TRAP 114 // 0x72 UVD_TRAP
#define VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE 119 // 0x77 Encoder General Purpose
#define VCN_4_0__SRCID__UVD_ENC_LOW_LATENCY 120 // 0x78 Encoder Low Latency
#define VCN_4_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 // 0x7c UVD system message interrupt
#define VCN_4_0__SRCID__JPEG_ENCODE 151 // 0x97 JRBC Encode interrupt
#define VCN_4_0__SRCID__JPEG_DECODE 153 // 0x99 JRBC Decode interrupt
#define VCN_4_0__SRCID__JPEG1_DECODE 149 // 0x95 JRBC1 Decode interrupt
#define VCN_4_0__SRCID__JPEG2_DECODE VCN_4_0__SRCID__JPEG_ENCODE//0x97 JRBC2 Decode interrupt
#define VCN_4_0__SRCID__JPEG3_DECODE 171 // 0xab JRBC3 Decode interrupt
#define VCN_4_0__SRCID__JPEG4_DECODE 172 // 0xac JRBC4 Decode interrupt
#define VCN_4_0__SRCID__JPEG5_DECODE 173 // 0xad JRBC5 Decode interrupt
#define VCN_4_0__SRCID__JPEG6_DECODE 174 // 0xae JRBC6 Decode interrupt
#define VCN_4_0__SRCID__JPEG7_DECODE 175 // 0xaf JRBC7 Decode interrupt
#define VCN_4_0__SRCID_UVD_POISON 160
#define VCN_4_0__SRCID_DJPEG0_POISON 161
#define VCN_4_0__SRCID_EJPEG0_POISON 162
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h
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/* SPDX-License-Identifier: MIT */
/*
* Copyright 2024 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_VCN_5_0_H__
#define __IRQSRCS_VCN_5_0_H__
#define VCN_5_0__SRCID__UVD_TRAP 114 // 0x72 UVD_TRAP
#define VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE 119 // 0x77 Encoder General Purpose
#define VCN_5_0__SRCID__UVD_ENC_LOW_LATENCY 120 // 0x78 Encoder Low Latency
#define VCN_5_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 // 0x7c UVD system message interrupt
#define VCN_5_0__SRCID__JPEG_ENCODE 151 // 0x97 JRBC Encode interrupt
#define VCN_5_0__SRCID__JPEG_DECODE 153 // 0x99 JRBC Decode interrupt
#define VCN_5_0__SRCID__JPEG1_DECODE 149 // 0x95 JRBC1 Decode interrupt
#define VCN_5_0__SRCID__JPEG2_DECODE 151 // 0x97 JRBC2 Decode interrupt
#define VCN_5_0__SRCID__JPEG3_DECODE 171 // 0xab JRBC3 Decode interrupt
#define VCN_5_0__SRCID__JPEG4_DECODE 172 // 0xac JRBC4 Decode interrupt
#define VCN_5_0__SRCID__JPEG5_DECODE 173 // 0xad JRBC5 Decode interrupt
#define VCN_5_0__SRCID__JPEG6_DECODE 174 // 0xae JRBC6 Decode interrupt
#define VCN_5_0__SRCID__JPEG7_DECODE 175 // 0xaf JRBC7 Decode interrupt
#define VCN_5_0__SRCID__JPEG8_DECODE 177 // 0xb1 JRBC8 Decode interrupt
#define VCN_5_0__SRCID__JPEG9_DECODE 178 // 0xb2 JRBC9 Decode interrupt
#define VCN_5_0__SRCID_UVD_POISON 160
#define VCN_5_0__SRCID_DJPEG0_POISON 161
#define VCN_5_0__SRCID_EJPEG0_POISON 162
#endif
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vmc/irqsrcs_vmc_1_0.h
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __IRQSRCS_VMC_1_0_H__
#define __IRQSRCS_VMC_1_0_H__
#define VMC_1_0__SRCID__VM_FAULT 0
#define VMC_1_0__SRCID__VM_RETRY 1
#define VMC_1_0__SRCID__VM_CONTEXT0_ALL 256
#define VMC_1_0__SRCID__VM_CONTEXT1_ALL 257
#define UTCL2_1_0__SRCID__FAULT 0 /* UTC L2 has encountered a fault or retry scenario */
#define UTCL2_1_0__SRCID__RETRY 1 /* UTC L2 has encountered a retry scenario (GFX12.1) */
#endif /* __IRQSRCS_VMC_1_0_H__ */
linux-7.2.3/drivers/gpu/drm/amd/include/ivsrcid/vpe/irqsrcs_vpe_6_1.h
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/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_VPE_6_1_H__
#define __IRQSRCS_VPE_6_1_H__
#define VPE_6_1_SRCID__VPE_ATOMIC_RTN_DONE 0 // 0x0 VPE atomic*_rtn ops complete
#define VPE_6_1_SRCID__VPE_TRAP 1 // 0x1 Trap
#define VPE_6_1_SRCID__VPE_SRBMWRITE 2 // 0x2 SRBM write protection
#define VPE_6_1_SRCID__VPE_CTXEMPTY 3 // 0x3 Context Empty
#define VPE_6_1_SRCID__VPE_PREEMPT 4 // 0x4 Preemption
#define VPE_6_1_SRCID__VPE_QUEUE_HANG 5 // 0x5 Queue hang or Command timeout
#define VPE_6_1_SRCID__VPE_ATOMIC_TIMEOUT 6 // 0x6 Atomic CMPSWAP loop timeout
#define VPE_6_1_SRCID__VPE_POLL_TIMEOUT 7 // 0x7 SRBM read poll timeout
#define VPE_6_1_SRCID__VPE_VM_HOLE 8 // 0x8 Address in VM hole
#define VPE_6_1_SRCID__VPE_NACK_GEN_ERR 9 // 0x9 MMHUB return general error (nack = 3)
#define VPE_6_1_SRCID__VPE_NACK_PRT 10 // 0xA MMHUB return PRT (nack = 2)
#define VPE_6_1_SRCID__VPE_DOORBELL_INVALID 11 // 0xB Doorbell BE invalid
#define VPE_6_1_SRCID__VPE_IB_PREEMPT 12 // 0xC IB preemption
#endif