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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/amd_powerplay.h
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _AMD_POWERPLAY_H_
#define _AMD_POWERPLAY_H_
#include <linux/seq_file.h>
#include <linux/types.h>
#include <linux/errno.h>
#include "amd_shared.h"
#include "cgs_common.h"
#include "dm_pp_interface.h"
#include "kgd_pp_interface.h"
#include "amdgpu.h"
#endif /* _AMD_POWERPLAY_H_ */
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/cz_ppsmc.h
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/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef CZ_PP_SMC_H
#define CZ_PP_SMC_H
#pragma pack(push, 1)
/* Fan control algorithm:*/
#define FDO_MODE_HARDWARE 0
#define FDO_MODE_PIECE_WISE_LINEAR 1
enum FAN_CONTROL {
FAN_CONTROL_FUZZY,
FAN_CONTROL_TABLE
};
enum DPM_ARRAY {
DPM_ARRAY_HARD_MAX,
DPM_ARRAY_HARD_MIN,
DPM_ARRAY_SOFT_MAX,
DPM_ARRAY_SOFT_MIN
};
/*
* Return codes for driver to SMC communication.
* Leave these #define-s, enums might not be exactly 8-bits on the microcontroller.
*/
#define PPSMC_Result_OK ((uint16_t)0x01)
#define PPSMC_Result_NoMore ((uint16_t)0x02)
#define PPSMC_Result_NotNow ((uint16_t)0x03)
#define PPSMC_Result_Failed ((uint16_t)0xFF)
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
/*
* Supported driver messages
*/
#define PPSMC_MSG_Test ((uint16_t) 0x1)
#define PPSMC_MSG_GetFeatureStatus ((uint16_t) 0x2)
#define PPSMC_MSG_EnableAllSmuFeatures ((uint16_t) 0x3)
#define PPSMC_MSG_DisableAllSmuFeatures ((uint16_t) 0x4)
#define PPSMC_MSG_OptimizeBattery ((uint16_t) 0x5)
#define PPSMC_MSG_MaximizePerf ((uint16_t) 0x6)
#define PPSMC_MSG_UVDPowerOFF ((uint16_t) 0x7)
#define PPSMC_MSG_UVDPowerON ((uint16_t) 0x8)
#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x9)
#define PPSMC_MSG_VCEPowerON ((uint16_t) 0xA)
#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0xB)
#define PPSMC_MSG_ACPPowerON ((uint16_t) 0xC)
#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0xD)
#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0xE)
#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0xF)
#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x10)
#define PPSMC_MSG_SetMinDeepSleepSclk ((uint16_t) 0x11)
#define PPSMC_MSG_SetSclkSoftMin ((uint16_t) 0x12)
#define PPSMC_MSG_SetSclkSoftMax ((uint16_t) 0x13)
#define PPSMC_MSG_SetSclkHardMin ((uint16_t) 0x14)
#define PPSMC_MSG_SetSclkHardMax ((uint16_t) 0x15)
#define PPSMC_MSG_SetLclkSoftMin ((uint16_t) 0x16)
#define PPSMC_MSG_SetLclkSoftMax ((uint16_t) 0x17)
#define PPSMC_MSG_SetLclkHardMin ((uint16_t) 0x18)
#define PPSMC_MSG_SetLclkHardMax ((uint16_t) 0x19)
#define PPSMC_MSG_SetUvdSoftMin ((uint16_t) 0x1A)
#define PPSMC_MSG_SetUvdSoftMax ((uint16_t) 0x1B)
#define PPSMC_MSG_SetUvdHardMin ((uint16_t) 0x1C)
#define PPSMC_MSG_SetUvdHardMax ((uint16_t) 0x1D)
#define PPSMC_MSG_SetEclkSoftMin ((uint16_t) 0x1E)
#define PPSMC_MSG_SetEclkSoftMax ((uint16_t) 0x1F)
#define PPSMC_MSG_SetEclkHardMin ((uint16_t) 0x20)
#define PPSMC_MSG_SetEclkHardMax ((uint16_t) 0x21)
#define PPSMC_MSG_SetAclkSoftMin ((uint16_t) 0x22)
#define PPSMC_MSG_SetAclkSoftMax ((uint16_t) 0x23)
#define PPSMC_MSG_SetAclkHardMin ((uint16_t) 0x24)
#define PPSMC_MSG_SetAclkHardMax ((uint16_t) 0x25)
#define PPSMC_MSG_SetNclkSoftMin ((uint16_t) 0x26)
#define PPSMC_MSG_SetNclkSoftMax ((uint16_t) 0x27)
#define PPSMC_MSG_SetNclkHardMin ((uint16_t) 0x28)
#define PPSMC_MSG_SetNclkHardMax ((uint16_t) 0x29)
#define PPSMC_MSG_SetPstateSoftMin ((uint16_t) 0x2A)
#define PPSMC_MSG_SetPstateSoftMax ((uint16_t) 0x2B)
#define PPSMC_MSG_SetPstateHardMin ((uint16_t) 0x2C)
#define PPSMC_MSG_SetPstateHardMax ((uint16_t) 0x2D)
#define PPSMC_MSG_DisableLowMemoryPstate ((uint16_t) 0x2E)
#define PPSMC_MSG_EnableLowMemoryPstate ((uint16_t) 0x2F)
#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x30)
#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x31)
#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x32)
#define PPSMC_MSG_DriverDramAddrHi ((uint16_t) 0x33)
#define PPSMC_MSG_DriverDramAddrLo ((uint16_t) 0x34)
#define PPSMC_MSG_CondExecDramAddrHi ((uint16_t) 0x35)
#define PPSMC_MSG_CondExecDramAddrLo ((uint16_t) 0x36)
#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x37)
#define PPSMC_MSG_DriverResetMode ((uint16_t) 0x38)
#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x39)
#define PPSMC_MSG_SetDisplayPhyConfig ((uint16_t) 0x3A)
#define PPSMC_MSG_GetMaxSclkLevel ((uint16_t) 0x3B)
#define PPSMC_MSG_GetMaxLclkLevel ((uint16_t) 0x3C)
#define PPSMC_MSG_GetMaxUvdLevel ((uint16_t) 0x3D)
#define PPSMC_MSG_GetMaxEclkLevel ((uint16_t) 0x3E)
#define PPSMC_MSG_GetMaxAclkLevel ((uint16_t) 0x3F)
#define PPSMC_MSG_GetMaxNclkLevel ((uint16_t) 0x40)
#define PPSMC_MSG_GetMaxPstate ((uint16_t) 0x41)
#define PPSMC_MSG_DramAddrHiVirtual ((uint16_t) 0x42)
#define PPSMC_MSG_DramAddrLoVirtual ((uint16_t) 0x43)
#define PPSMC_MSG_DramAddrHiPhysical ((uint16_t) 0x44)
#define PPSMC_MSG_DramAddrLoPhysical ((uint16_t) 0x45)
#define PPSMC_MSG_DramBufferSize ((uint16_t) 0x46)
#define PPSMC_MSG_SetMmPwrLogDramAddrHi ((uint16_t) 0x47)
#define PPSMC_MSG_SetMmPwrLogDramAddrLo ((uint16_t) 0x48)
#define PPSMC_MSG_SetClkTableAddrHi ((uint16_t) 0x49)
#define PPSMC_MSG_SetClkTableAddrLo ((uint16_t) 0x4A)
#define PPSMC_MSG_GetConservativePowerLimit ((uint16_t) 0x4B)
#define PPSMC_MSG_InitJobs ((uint16_t) 0x252)
#define PPSMC_MSG_ExecuteJob ((uint16_t) 0x254)
#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170)
#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171)
#define PPSMC_MSG_AllowLowSclkInterrupt ((uint16_t) 0x184)
#define PPSMC_MSG_MmPowerMonitorStart ((uint16_t) 0x18F)
#define PPSMC_MSG_MmPowerMonitorStop ((uint16_t) 0x190)
#define PPSMC_MSG_MmPowerMonitorRestart ((uint16_t) 0x191)
#define PPSMC_MSG_SetClockGateMask ((uint16_t) 0x260)
#define PPSMC_MSG_SetFpsThresholdLo ((uint16_t) 0x264)
#define PPSMC_MSG_SetFpsThresholdHi ((uint16_t) 0x265)
#define PPSMC_MSG_SetLowSclkIntrThreshold ((uint16_t) 0x266)
#define PPSMC_MSG_ClkTableXferToDram ((uint16_t) 0x267)
#define PPSMC_MSG_ClkTableXferToSmu ((uint16_t) 0x268)
#define PPSMC_MSG_GetAverageGraphicsActivity ((uint16_t) 0x269)
#define PPSMC_MSG_GetAverageGioActivity ((uint16_t) 0x26A)
#define PPSMC_MSG_SetLoggerBufferSize ((uint16_t) 0x26B)
#define PPSMC_MSG_SetLoggerAddressHigh ((uint16_t) 0x26C)
#define PPSMC_MSG_SetLoggerAddressLow ((uint16_t) 0x26D)
#define PPSMC_MSG_SetWatermarkFrequency ((uint16_t) 0x26E)
#define PPSMC_MSG_SetDisplaySizePowerParams ((uint16_t) 0x26F)
/* REMOVE LATER*/
#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
/* Feature Enable Masks*/
#define NB_DPM_MASK 0x00000800
#define VDDGFX_MASK 0x00800000
#define VCE_DPM_MASK 0x00400000
#define ACP_DPM_MASK 0x00040000
#define UVD_DPM_MASK 0x00010000
#define GFX_CU_PG_MASK 0x00004000
#define SCLK_DPM_MASK 0x00080000
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/fiji_ppsmc.h
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _FIJI_PP_SMC_H_
#define _FIJI_PP_SMC_H_
#pragma pack(push, 1)
#define PPSMC_SWSTATE_FLAG_DC 0x01
#define PPSMC_SWSTATE_FLAG_UVD 0x02
#define PPSMC_SWSTATE_FLAG_VCE 0x04
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
/* Defines for DPM 2.0 */
#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
#define PPSMC_DPM2FLAGS_OCP 0x04
/* Defines for display watermark level */
#define PPSMC_DISPLAY_WATERMARK_LOW 0
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
/* In the HW performance level's state flags: */
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
#define PPSMC_STATEFLAG_POWERBOOST 0x02
#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
#define PPSMC_STATEFLAG_POWERSHIFT 0x08
#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
/* Fan control algorithm: */
#define FDO_MODE_HARDWARE 0
#define FDO_MODE_PIECE_WISE_LINEAR 1
enum FAN_CONTROL {
FAN_CONTROL_FUZZY,
FAN_CONTROL_TABLE
};
/* Gemini Modes*/
#define PPSMC_GeminiModeNone 0 /*Single GPU board*/
#define PPSMC_GeminiModeMaster 1 /*Master GPU on a Gemini board*/
#define PPSMC_GeminiModeSlave 2 /*Slave GPU on a Gemini board*/
/* Return codes for driver to SMC communication. */
#define PPSMC_Result_OK ((uint16_t)0x01)
#define PPSMC_Result_NoMore ((uint16_t)0x02)
#define PPSMC_Result_NotNow ((uint16_t)0x03)
#define PPSMC_Result_Failed ((uint16_t)0xFF)
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
#define PPSMC_MSG_Halt ((uint16_t)0x10)
#define PPSMC_MSG_Resume ((uint16_t)0x11)
#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
#define PPSMC_CACHistoryStart ((uint16_t)0x57)
#define PPSMC_CACHistoryStop ((uint16_t)0x58)
#define PPSMC_TDPClampingActive ((uint16_t)0x59)
#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
#define PPSMC_StartFanControl ((uint16_t)0x5B)
#define PPSMC_StopFanControl ((uint16_t)0x5C)
#define PPSMC_NoDisplay ((uint16_t)0x5D)
#define PPSMC_HasDisplay ((uint16_t)0x5E)
#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
#define PPSMC_OCPActive ((uint16_t)0x6C)
#define PPSMC_OCPInactive ((uint16_t)0x6D)
#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
#define PPSMC_FlushDataCache ((uint16_t)0x80)
#define PPSMC_FlushInstrCache ((uint16_t)0x81)
#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
/* Trinity Specific Messages*/
#define PPSMC_MSG_Test ((uint16_t) 0x100)
#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)
#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127)
#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e)
#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f)
#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150)
#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151)
#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152)
#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153)
#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154)
#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155)
#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156)
#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157)
#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158)
#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159)
#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a)
#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b)
#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c)
#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c)
#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d)
#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e)
#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f)
#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170)
#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171)
#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A)
#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B)
#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C)
#define PPSMC_MSG_GetHbmCode ((uint16_t) 0x26D)
#define PPSMC_MSG_GetVrVddcTemperature ((uint16_t) 0x26E)
#define PPSMC_MSG_GetVrMvddTemperature ((uint16_t) 0x26F)
#define PPSMC_MSG_GetLiquidTemperature ((uint16_t) 0x270)
#define PPSMC_MSG_GetPlxTemperature ((uint16_t) 0x271)
#define PPSMC_MSG_RequestI2CControl ((uint16_t) 0x272)
#define PPSMC_MSG_ReleaseI2CControl ((uint16_t) 0x273)
#define PPSMC_MSG_LedConfig ((uint16_t) 0x274)
#define PPSMC_MSG_SetHbmFanCode ((uint16_t) 0x275)
#define PPSMC_MSG_SetHbmThrottleCode ((uint16_t) 0x276)
#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400)
#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401)
#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402)
#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)
/* AVFS Only - Remove Later */
#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x666)
/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
#define PPSMC_EVENT_STATUS_DC 0x00000004
typedef uint16_t PPSMC_Msg;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
+462
View File
@@ -0,0 +1,462 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _HARDWARE_MANAGER_H_
#define _HARDWARE_MANAGER_H_
struct pp_hwmgr;
struct pp_hw_power_state;
struct pp_power_state;
enum amd_dpm_forced_level;
struct PP_TemperatureRange;
struct phm_fan_speed_info {
uint32_t min_percent;
uint32_t max_percent;
uint32_t min_rpm;
uint32_t max_rpm;
bool supports_percent_read;
bool supports_percent_write;
bool supports_rpm_read;
bool supports_rpm_write;
};
/* Automatic Power State Throttling */
enum PHM_AutoThrottleSource {
PHM_AutoThrottleSource_Thermal,
PHM_AutoThrottleSource_External
};
typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
enum phm_platform_caps {
PHM_PlatformCaps_AtomBiosPpV1 = 0,
PHM_PlatformCaps_PowerPlaySupport,
PHM_PlatformCaps_ACOverdriveSupport,
PHM_PlatformCaps_BacklightSupport,
PHM_PlatformCaps_ThermalController,
PHM_PlatformCaps_BiosPowerSourceControl,
PHM_PlatformCaps_DisableVoltageTransition,
PHM_PlatformCaps_DisableEngineTransition,
PHM_PlatformCaps_DisableMemoryTransition,
PHM_PlatformCaps_DynamicPowerManagement,
PHM_PlatformCaps_EnableASPML0s,
PHM_PlatformCaps_EnableASPML1,
PHM_PlatformCaps_OD5inACSupport,
PHM_PlatformCaps_OD5inDCSupport,
PHM_PlatformCaps_SoftStateOD5,
PHM_PlatformCaps_NoOD5Support,
PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
PHM_PlatformCaps_ActivityReporting,
PHM_PlatformCaps_EnableBackbias,
PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
PHM_PlatformCaps_ShowPowerBudgetWarning,
PHM_PlatformCaps_PowerBudgetWaiverAvailable,
PHM_PlatformCaps_GFXClockGatingSupport,
PHM_PlatformCaps_MMClockGatingSupport,
PHM_PlatformCaps_AutomaticDCTransition,
PHM_PlatformCaps_GeminiPrimary,
PHM_PlatformCaps_MemorySpreadSpectrumSupport,
PHM_PlatformCaps_EngineSpreadSpectrumSupport,
PHM_PlatformCaps_StepVddc,
PHM_PlatformCaps_DynamicPCIEGen2Support,
PHM_PlatformCaps_SMC,
PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */
PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */
PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */
PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */
PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */
PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */
PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */
PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */
PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */
PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */
PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */
PHM_PlatformCaps_ABM, /* ABM support.*/
PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */
PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */
PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */
PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */
PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */
PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */
PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */
PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */
PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */
PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */
PHM_PlatformCaps_AdjustUVDPriorityForSP,
PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */
PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */
PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */
PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */
PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */
PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */
PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */
PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */
PHM_PlatformCaps_BLControlledByGPU, /* support varibright */
PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */
PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */
PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */
PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */
PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */
PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */
PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */
PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */
PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */
PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */
PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */
PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */
PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */
PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */
PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/
PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */
PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */
PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */
PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */
PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */
PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */
PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */
PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */
PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */
PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */
PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */
PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */
PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */
PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */
PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */
PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */
PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */
PHM_PlatformCaps_DiDtSupport, /* for dI/dT feature */
PHM_PlatformCaps_DBRamping, /* for dI/dT feature */
PHM_PlatformCaps_TDRamping, /* for dI/dT feature */
PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */
PHM_PlatformCaps_DBRRamping, /* for dI/dT feature */
PHM_PlatformCaps_DiDtEDCEnable, /* for dI/dT feature */
PHM_PlatformCaps_GCEDC, /* for dI/dT feature */
PHM_PlatformCaps_PSM, /* for dI/dT feature */
PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */
PHM_PlatformCaps_FPS, /* FPS support */
PHM_PlatformCaps_ACP, /* ACP support */
PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */
PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */
PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */
PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */
PHM_PlatformCaps_VddNBDirectRequest,
PHM_PlatformCaps_PauseMMSessions,
PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */
PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */
PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */
PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */
PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */
PHM_PlatformCaps_ForceMclkHigh, /* Disable memory clock switching by forcing memory clock high */
PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */
PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */
PHM_PlatformCaps_IOIC3,
PHM_PlatformCaps_ConnectedStandby,
PHM_PlatformCaps_EVV,
PHM_PlatformCaps_EnableLongIdleBACOSupport,
PHM_PlatformCaps_CombinePCCWithThermalSignal,
PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
PHM_PlatformCaps_StablePState,
PHM_PlatformCaps_OD6PlusinACSupport,
PHM_PlatformCaps_OD6PlusinDCSupport,
PHM_PlatformCaps_ODThermalLimitUnlock,
PHM_PlatformCaps_ReducePowerLimit,
PHM_PlatformCaps_ODFuzzyFanControlSupport,
PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
PHM_PlatformCaps_ControlVDDGFX,
PHM_PlatformCaps_BBBSupported,
PHM_PlatformCaps_DisableVoltageIsland,
PHM_PlatformCaps_FanSpeedInTableIsRPM,
PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
PHM_PlatformCaps_IcelandULPSSWWorkAround,
PHM_PlatformCaps_FPSEnhancement,
PHM_PlatformCaps_LoadPostProductionFirmware,
PHM_PlatformCaps_VpuRecoveryInProgress,
PHM_PlatformCaps_Falcon_QuickTransition,
PHM_PlatformCaps_AVFS,
PHM_PlatformCaps_ClockStretcher,
PHM_PlatformCaps_TablelessHardwareInterface,
PHM_PlatformCaps_EnableDriverEVV,
PHM_PlatformCaps_SPLLShutdownSupport,
PHM_PlatformCaps_VirtualBatteryState,
PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
PHM_PlatformCaps_DisableMclkSwitchForVR,
PHM_PlatformCaps_SMU8,
PHM_PlatformCaps_VRHotPolarityHigh,
PHM_PlatformCaps_IPS_UlpsExclusive,
PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
PHM_PlatformCaps_GeminiAsymmetricPower,
PHM_PlatformCaps_OCLPowerOptimization,
PHM_PlatformCaps_MaxPCIEBandWidth,
PHM_PlatformCaps_PerfPerWattOptimizationSupport,
PHM_PlatformCaps_UVDClientMCTuning,
PHM_PlatformCaps_ODNinACSupport,
PHM_PlatformCaps_ODNinDCSupport,
PHM_PlatformCaps_OD8inACSupport,
PHM_PlatformCaps_OD8inDCSupport,
PHM_PlatformCaps_UMDPState,
PHM_PlatformCaps_AutoWattmanSupport,
PHM_PlatformCaps_AutoWattmanEnable_CCCState,
PHM_PlatformCaps_FreeSyncActive,
PHM_PlatformCaps_EnableShadowPstate,
PHM_PlatformCaps_customThermalManagement,
PHM_PlatformCaps_staticFanControl,
PHM_PlatformCaps_Virtual_System,
PHM_PlatformCaps_LowestUclkReservedForUlv,
PHM_PlatformCaps_EnableBoostState,
PHM_PlatformCaps_AVFSSupport,
PHM_PlatformCaps_ThermalPolicyDelay,
PHM_PlatformCaps_CustomFanControlSupport,
PHM_PlatformCaps_BAMACO,
PHM_PlatformCaps_Max
};
#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
/* Number of uint32_t entries used by CAPS table */
#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
struct pp_hw_descriptor {
uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
};
enum PHM_PerformanceLevelDesignation {
PHM_PerformanceLevelDesignation_Activity,
PHM_PerformanceLevelDesignation_PowerContainment
};
typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
struct PHM_PerformanceLevel {
uint32_t coreClock;
uint32_t memory_clock;
uint32_t vddc;
uint32_t vddci;
uint32_t nonLocalMemoryFreq;
uint32_t nonLocalMemoryWidth;
};
typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
/* Function for setting a platform cap */
static inline void phm_cap_set(uint32_t *caps,
enum phm_platform_caps c)
{
caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
(c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
}
static inline void phm_cap_unset(uint32_t *caps,
enum phm_platform_caps c)
{
caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
}
static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
{
return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
}
#define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
#define PP_PCIEGenInvalid 0xffff
enum PP_PCIEGen {
PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
};
typedef enum PP_PCIEGen PP_PCIEGen;
#define PP_Min_PCIEGen PP_PCIEGen1
#define PP_Max_PCIEGen PP_PCIEGen3
#define PP_Min_PCIELane 1
#define PP_Max_PCIELane 16
enum phm_clock_Type {
PHM_DispClock = 1,
PHM_SClock,
PHM_MemClock
};
#define MAX_NUM_CLOCKS 16
struct PP_Clocks {
uint32_t engineClock;
uint32_t memoryClock;
uint32_t BusBandwidth;
uint32_t engineClockInSR;
uint32_t dcefClock;
uint32_t dcefClockInSR;
};
struct pp_clock_info {
uint32_t min_mem_clk;
uint32_t max_mem_clk;
uint32_t min_eng_clk;
uint32_t max_eng_clk;
uint32_t min_bus_bandwidth;
uint32_t max_bus_bandwidth;
};
struct phm_platform_descriptor {
uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
uint32_t vbiosInterruptId;
struct PP_Clocks overdriveLimit;
struct PP_Clocks clockStep;
uint32_t hardwareActivityPerformanceLevels;
uint32_t minimumClocksReductionPercentage;
uint32_t minOverdriveVDDC;
uint32_t maxOverdriveVDDC;
uint32_t overdriveVDDCStep;
uint32_t hardwarePerformanceLevels;
uint16_t powerBudget;
uint32_t TDPLimit;
uint32_t nearTDPLimit;
uint32_t nearTDPLimitAdjusted;
uint32_t SQRampingThreshold;
uint32_t CACLeakage;
uint16_t TDPODLimit;
uint32_t TDPAdjustment;
bool TDPAdjustmentPolarity;
uint16_t LoadLineSlope;
uint32_t VidMinLimit;
uint32_t VidMaxLimit;
uint32_t VidStep;
uint32_t VidAdjustment;
bool VidAdjustmentPolarity;
};
struct phm_clocks {
uint32_t num_of_entries;
uint32_t clock[MAX_NUM_CLOCKS];
};
#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
#define DPMTABLE_UPDATE_SCLK 0x00000004
#define DPMTABLE_UPDATE_MCLK 0x00000008
#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
#define DPMTABLE_UPDATE_SOCCLK 0x00000020
struct phm_odn_performance_level {
uint32_t clock;
uint32_t vddc;
bool enabled;
};
struct phm_odn_clock_levels {
uint32_t size;
uint32_t options;
uint32_t flags;
uint32_t num_of_pl;
/* variable-sized array, specify by num_of_pl. */
struct phm_odn_performance_level entries[8];
};
extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *pcurrent_state,
const struct pp_hw_power_state *pnew_power_state);
extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *adjusted_ps,
const struct pp_power_state *current_ps);
extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *pstate1,
const struct pp_hw_power_state *pstate2,
bool *equal);
extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
const struct amd_pp_display_configuration *display_config);
extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level);
extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
struct pp_clock_info *pclock_info,
PHM_PerformanceLevelDesignation designation);
extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks);
extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks);
extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
void *clock_ranges);
extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock);
extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);
#endif /* _HARDWARE_MANAGER_H_ */
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
+837
View File
@@ -0,0 +1,837 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _HWMGR_H_
#define _HWMGR_H_
#include <linux/seq_file.h>
#include "amd_powerplay.h"
#include "hardwaremanager.h"
#include "hwmgr_ppt.h"
#include "ppatomctrl.h"
#include "power_state.h"
#include "smu_helper.h"
struct pp_hwmgr;
struct phm_fan_speed_info;
struct pp_atomctrl_voltage_table;
/* Decode legacy unsigned Q24.8 watts to internal milliwatts. */
#define PP_PWR_Q24_8_TO_MW(power) \
DIV_ROUND_CLOSEST_ULL((u64)(power) * MILLIWATT_PER_WATT, \
BIT(8))
#define VOLTAGE_SCALE 4
#define VOLTAGE_VID_OFFSET_SCALE1 625
#define VOLTAGE_VID_OFFSET_SCALE2 100
enum DISPLAY_GAP {
DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
};
typedef enum DISPLAY_GAP DISPLAY_GAP;
enum BACO_STATE {
BACO_STATE_OUT = 0,
BACO_STATE_IN,
};
struct vi_dpm_level {
bool enabled;
uint32_t value;
uint32_t param1;
};
struct vi_dpm_table {
uint32_t count;
struct vi_dpm_level dpm_level[];
};
#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
#define PCIE_PERF_REQ_GEN1 2
#define PCIE_PERF_REQ_GEN2 3
#define PCIE_PERF_REQ_GEN3 4
enum PHM_BackEnd_Magic {
PHM_Dummy_Magic = 0xAA5555AA,
PHM_RV770_Magic = 0xDCBAABCD,
PHM_Kong_Magic = 0x239478DF,
PHM_NIslands_Magic = 0x736C494E,
PHM_Sumo_Magic = 0x8339FA11,
PHM_SIslands_Magic = 0x369431AC,
PHM_Trinity_Magic = 0x96751873,
PHM_CIslands_Magic = 0x38AC78B0,
PHM_Kv_Magic = 0xDCBBABC0,
PHM_VIslands_Magic = 0x20130307,
PHM_Cz_Magic = 0x67DCBA25,
PHM_Rv_Magic = 0x20161121
};
struct phm_set_power_state_input {
const struct pp_hw_power_state *pcurrent_state;
const struct pp_hw_power_state *pnew_state;
};
struct phm_clock_array {
uint32_t count;
uint32_t values[];
};
struct phm_clock_voltage_dependency_record {
uint32_t clk;
uint32_t v;
};
struct phm_vceclock_voltage_dependency_record {
uint32_t ecclk;
uint32_t evclk;
uint32_t v;
};
struct phm_uvdclock_voltage_dependency_record {
uint32_t vclk;
uint32_t dclk;
uint32_t v;
};
struct phm_samuclock_voltage_dependency_record {
uint32_t samclk;
uint32_t v;
};
struct phm_acpclock_voltage_dependency_record {
uint32_t acpclk;
uint32_t v;
};
struct phm_clock_voltage_dependency_table {
uint32_t count;
struct phm_clock_voltage_dependency_record entries[];
};
struct phm_phase_shedding_limits_record {
uint32_t Voltage;
uint32_t Sclk;
uint32_t Mclk;
};
struct phm_uvd_clock_voltage_dependency_record {
uint32_t vclk;
uint32_t dclk;
uint32_t v;
};
struct phm_uvd_clock_voltage_dependency_table {
uint8_t count;
struct phm_uvd_clock_voltage_dependency_record entries[];
};
struct phm_acp_clock_voltage_dependency_record {
uint32_t acpclk;
uint32_t v;
};
struct phm_acp_clock_voltage_dependency_table {
uint32_t count;
struct phm_acp_clock_voltage_dependency_record entries[];
};
struct phm_vce_clock_voltage_dependency_record {
uint32_t ecclk;
uint32_t evclk;
uint32_t v;
};
struct phm_phase_shedding_limits_table {
uint32_t count;
struct phm_phase_shedding_limits_record entries[];
};
struct phm_vceclock_voltage_dependency_table {
uint8_t count;
struct phm_vceclock_voltage_dependency_record entries[];
};
struct phm_uvdclock_voltage_dependency_table {
uint8_t count;
struct phm_uvdclock_voltage_dependency_record entries[];
};
struct phm_samuclock_voltage_dependency_table {
uint8_t count;
struct phm_samuclock_voltage_dependency_record entries[];
};
struct phm_acpclock_voltage_dependency_table {
uint32_t count;
struct phm_acpclock_voltage_dependency_record entries[];
};
struct phm_vce_clock_voltage_dependency_table {
uint8_t count;
struct phm_vce_clock_voltage_dependency_record entries[];
};
enum SMU_ASIC_RESET_MODE {
SMU_ASIC_RESET_MODE_0,
SMU_ASIC_RESET_MODE_1,
SMU_ASIC_RESET_MODE_2,
};
struct pp_smumgr_func {
char *name;
int (*smu_init)(struct pp_hwmgr *hwmgr);
int (*smu_fini)(struct pp_hwmgr *hwmgr);
int (*start_smu)(struct pp_hwmgr *hwmgr);
int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
uint32_t firmware);
int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
uint32_t firmware);
uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
void **table);
int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
int (*init_smc_table)(struct pp_hwmgr *hwmgr);
int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
uint32_t (*get_mac_definition)(uint32_t value);
bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
int (*stop_smc)(struct pp_hwmgr *hwmgr);
};
struct pp_hwmgr_func {
int (*backend_init)(struct pp_hwmgr *hw_mgr);
int (*backend_fini)(struct pp_hwmgr *hw_mgr);
int (*asic_setup)(struct pp_hwmgr *hw_mgr);
int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
struct pp_power_state *prequest_ps,
const struct pp_power_state *pcurrent_ps);
int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
enum amd_dpm_forced_level level);
int (*dynamic_state_management_enable)(
struct pp_hwmgr *hw_mgr);
int (*dynamic_state_management_disable)(
struct pp_hwmgr *hw_mgr);
int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps);
int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
unsigned long, struct pp_power_state *);
int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
int (*power_state_set)(struct pp_hwmgr *hwmgr,
const void *state);
int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
int (*display_config_changed)(struct pp_hwmgr *hwmgr);
int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id);
int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed);
int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed);
int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
int (*check_states_equal)(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *pstate1,
const struct pp_hw_power_state *pstate2,
bool *equal);
int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
bool cc6_disable, bool pstate_disable,
bool pstate_switch_disable);
int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks);
int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks);
int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock);
int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
int (*power_off_asic)(struct pp_hwmgr *hwmgr);
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
int (*emit_clock_levels)(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf, int *offset);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
enum PP_OD_DPM_TABLE_COMMAND type,
long *input, uint32_t size);
int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
int (*get_bamaco_support)(struct pp_hwmgr *hwmgr);
int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool acquire);
int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
bool disable);
ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
void (*notify_ac_dc)(struct pp_hwmgr *hwmgr);
};
struct pp_table_func {
int (*pptable_init)(struct pp_hwmgr *hw_mgr);
int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
int (*pptable_get_vce_state_table_entry)(
struct pp_hwmgr *hwmgr,
unsigned long i,
struct amd_vce_state *vce_state,
void **clock_info,
unsigned long *flag);
};
union phm_cac_leakage_record {
struct {
uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
};
struct {
uint16_t Vddc1;
uint16_t Vddc2;
uint16_t Vddc3;
};
};
struct phm_cac_leakage_table {
uint32_t count;
union phm_cac_leakage_record entries[];
};
struct phm_samu_clock_voltage_dependency_record {
uint32_t samclk;
uint32_t v;
};
struct phm_samu_clock_voltage_dependency_table {
uint8_t count;
struct phm_samu_clock_voltage_dependency_record entries[];
};
struct phm_cac_tdp_table {
uint16_t usTDP;
uint16_t usConfigurableTDP;
uint16_t usTDC;
uint16_t usBatteryPowerLimit;
uint16_t usSmallPowerLimit;
uint16_t usLowCACLeakage;
uint16_t usHighCACLeakage;
uint16_t usMaximumPowerDeliveryLimit;
uint16_t usEDCLimit;
uint16_t usOperatingTempMinLimit;
uint16_t usOperatingTempMaxLimit;
uint16_t usOperatingTempStep;
uint16_t usOperatingTempHyst;
uint16_t usDefaultTargetOperatingTemp;
uint16_t usTargetOperatingTemp;
uint16_t usPowerTuneDataSetID;
uint16_t usSoftwareShutdownTemp;
uint16_t usClockStretchAmount;
uint16_t usTemperatureLimitHotspot;
uint16_t usTemperatureLimitLiquid1;
uint16_t usTemperatureLimitLiquid2;
uint16_t usTemperatureLimitVrVddc;
uint16_t usTemperatureLimitVrMvdd;
uint16_t usTemperatureLimitPlx;
uint8_t ucLiquid1_I2C_address;
uint8_t ucLiquid2_I2C_address;
uint8_t ucLiquid_I2C_Line;
uint8_t ucVr_I2C_address;
uint8_t ucVr_I2C_Line;
uint8_t ucPlx_I2C_address;
uint8_t ucPlx_I2C_Line;
uint32_t usBoostPowerLimit;
uint8_t ucCKS_LDO_REFSEL;
uint8_t ucHotSpotOnly;
};
struct phm_tdp_table {
uint16_t usTDP;
uint16_t usConfigurableTDP;
uint16_t usTDC;
uint16_t usBatteryPowerLimit;
uint16_t usSmallPowerLimit;
uint16_t usLowCACLeakage;
uint16_t usHighCACLeakage;
uint16_t usMaximumPowerDeliveryLimit;
uint16_t usEDCLimit;
uint16_t usOperatingTempMinLimit;
uint16_t usOperatingTempMaxLimit;
uint16_t usOperatingTempStep;
uint16_t usOperatingTempHyst;
uint16_t usDefaultTargetOperatingTemp;
uint16_t usTargetOperatingTemp;
uint16_t usPowerTuneDataSetID;
uint16_t usSoftwareShutdownTemp;
uint16_t usClockStretchAmount;
uint16_t usTemperatureLimitTedge;
uint16_t usTemperatureLimitHotspot;
uint16_t usTemperatureLimitLiquid1;
uint16_t usTemperatureLimitLiquid2;
uint16_t usTemperatureLimitHBM;
uint16_t usTemperatureLimitVrVddc;
uint16_t usTemperatureLimitVrMvdd;
uint16_t usTemperatureLimitPlx;
uint8_t ucLiquid1_I2C_address;
uint8_t ucLiquid2_I2C_address;
uint8_t ucLiquid_I2C_Line;
uint8_t ucVr_I2C_address;
uint8_t ucVr_I2C_Line;
uint8_t ucPlx_I2C_address;
uint8_t ucPlx_I2C_Line;
uint8_t ucLiquid_I2C_LineSDA;
uint8_t ucVr_I2C_LineSDA;
uint8_t ucPlx_I2C_LineSDA;
uint32_t usBoostPowerLimit;
uint16_t usBoostStartTemperature;
uint16_t usBoostStopTemperature;
uint32_t ulBoostClock;
};
struct phm_ppm_table {
uint8_t ppm_design;
uint16_t cpu_core_number;
uint32_t platform_tdp;
uint32_t small_ac_platform_tdp;
uint32_t platform_tdc;
uint32_t small_ac_platform_tdc;
uint32_t apu_tdp;
uint32_t dgpu_tdp;
uint32_t dgpu_ulv_power;
uint32_t tj_max;
};
struct phm_vq_budgeting_record {
uint32_t ulCUs;
uint32_t ulSustainableSOCPowerLimitLow;
uint32_t ulSustainableSOCPowerLimitHigh;
uint32_t ulMinSclkLow;
uint32_t ulMinSclkHigh;
uint8_t ucDispConfig;
uint32_t ulDClk;
uint32_t ulEClk;
uint32_t ulSustainableSclk;
uint32_t ulSustainableCUs;
};
struct phm_vq_budgeting_table {
uint8_t numEntries;
struct phm_vq_budgeting_record entries[0];
};
struct phm_clock_and_voltage_limits {
uint32_t sclk;
uint32_t mclk;
uint32_t gfxclk;
uint16_t vddc;
uint16_t vddci;
uint16_t vddgfx;
uint16_t vddmem;
};
/* Structure to hold PPTable information */
struct phm_ppt_v1_information {
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
struct phm_clock_array *valid_sclk_values;
struct phm_clock_array *valid_mclk_values;
struct phm_clock_array *valid_socclk_values;
struct phm_clock_array *valid_dcefclk_values;
struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
struct phm_tdp_table *tdp_table;
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
struct phm_ppt_v1_pcie_table *pcie_table;
struct phm_ppt_v1_gpio_table *gpio_table;
uint16_t us_ulv_voltage_offset;
uint16_t us_ulv_smnclk_did;
uint16_t us_ulv_mp1clk_did;
uint16_t us_ulv_gfxclk_bypass;
uint16_t us_gfxclk_slew_rate;
uint16_t us_min_gfxclk_freq_limit;
};
struct phm_ppt_v2_information {
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
struct phm_clock_array *valid_sclk_values;
struct phm_clock_array *valid_mclk_values;
struct phm_clock_array *valid_socclk_values;
struct phm_clock_array *valid_dcefclk_values;
struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
struct phm_tdp_table *tdp_table;
struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
struct phm_ppt_v1_pcie_table *pcie_table;
uint16_t us_ulv_voltage_offset;
uint16_t us_ulv_smnclk_did;
uint16_t us_ulv_mp1clk_did;
uint16_t us_ulv_gfxclk_bypass;
uint16_t us_gfxclk_slew_rate;
uint16_t us_min_gfxclk_freq_limit;
uint8_t uc_gfx_dpm_voltage_mode;
uint8_t uc_soc_dpm_voltage_mode;
uint8_t uc_uclk_dpm_voltage_mode;
uint8_t uc_uvd_dpm_voltage_mode;
uint8_t uc_vce_dpm_voltage_mode;
uint8_t uc_mp0_dpm_voltage_mode;
uint8_t uc_dcef_dpm_voltage_mode;
};
struct phm_ppt_v3_information {
uint8_t uc_thermal_controller_type;
uint16_t us_small_power_limit1;
uint16_t us_small_power_limit2;
uint16_t us_boost_power_limit;
uint16_t us_od_turbo_power_limit;
uint16_t us_od_powersave_power_limit;
uint16_t us_software_shutdown_temp;
uint32_t *power_saving_clock_max;
uint32_t *power_saving_clock_min;
uint8_t *od_feature_capabilities;
uint32_t *od_settings_max;
uint32_t *od_settings_min;
void *smc_pptable;
};
struct phm_dynamic_state_info {
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
struct phm_clock_voltage_dependency_table *vddc_dependency_on_display_clock;
struct phm_clock_array *valid_sclk_values;
struct phm_clock_array *valid_mclk_values;
struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
uint32_t mclk_sclk_ratio;
uint32_t sclk_mclk_delta;
uint32_t vddc_vddci_delta;
uint32_t min_vddc_for_pcie_gen2;
struct phm_cac_leakage_table *cac_leakage_table;
struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
struct phm_vce_clock_voltage_dependency_table
*vce_clock_voltage_dependency_table;
struct phm_uvd_clock_voltage_dependency_table
*uvd_clock_voltage_dependency_table;
struct phm_acp_clock_voltage_dependency_table
*acp_clock_voltage_dependency_table;
struct phm_samu_clock_voltage_dependency_table
*samu_clock_voltage_dependency_table;
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
};
struct pp_fan_info {
bool bNoFan;
uint8_t ucTachometerPulsesPerRevolution;
uint32_t ulMinRPM;
uint32_t ulMaxRPM;
};
struct pp_advance_fan_control_parameters {
uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
uint16_t usTMed; /* The middle temperature where we change slopes. */
uint16_t usTHigh; /* The high temperature for setting the second slope. */
uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
uint16_t usPWMHigh; /* The PWM value at THigh. */
uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
uint16_t usTMax; /* The max temperature */
uint8_t ucFanControlMode;
uint16_t usFanPWMMinLimit;
uint16_t usFanPWMMaxLimit;
uint16_t usFanPWMStep;
uint16_t usDefaultMaxFanPWM;
uint16_t usFanOutputSensitivity;
uint16_t usDefaultFanOutputSensitivity;
uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
uint16_t usFanCurrentLow; /* Low current */
uint16_t usFanCurrentHigh; /* High current */
uint16_t usFanRPMLow; /* Low RPM */
uint16_t usFanRPMHigh; /* High RPM */
uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
uint16_t usFanGainEdge; /* The following is added for Fiji */
uint16_t usFanGainHotspot;
uint16_t usFanGainLiquid;
uint16_t usFanGainVrVddc;
uint16_t usFanGainVrMvdd;
uint16_t usFanGainPlx;
uint16_t usFanGainHbm;
uint8_t ucEnableZeroRPM;
uint8_t ucFanStopTemperature;
uint8_t ucFanStartTemperature;
uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
uint32_t ulTargetGfxClk;
uint16_t usZeroRPMStartTemperature;
uint16_t usZeroRPMStopTemperature;
uint16_t usMGpuThrottlingRPMLimit;
};
struct pp_thermal_controller_info {
uint8_t ucType;
uint8_t ucI2cLine;
uint8_t ucI2cAddress;
uint8_t use_hw_fan_control;
struct pp_fan_info fanInfo;
struct pp_advance_fan_control_parameters advanceFanControlParameters;
};
struct phm_microcode_version_info {
uint32_t SMC;
uint32_t DMCU;
uint32_t MC;
uint32_t NB;
};
enum PP_TABLE_VERSION {
PP_TABLE_V0 = 0,
PP_TABLE_V1,
PP_TABLE_V2,
PP_TABLE_MAX
};
/**
* The main hardware manager structure.
*/
#define Workload_Policy_Max 6
struct pp_hwmgr {
void *adev;
uint32_t chip_family;
uint32_t chip_id;
uint32_t smu_version;
bool not_vf;
bool pm_en;
bool pp_one_vf;
struct mutex msg_lock;
uint32_t pp_table_version;
void *device;
struct pp_smumgr *smumgr;
const void *soft_pp_table;
uint32_t soft_pp_table_size;
void *hardcode_pp_table;
bool need_pp_table_upload;
struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
uint32_t num_vce_state_tables;
enum amd_dpm_forced_level dpm_level;
enum amd_dpm_forced_level saved_dpm_level;
enum amd_dpm_forced_level request_dpm_level;
uint32_t usec_timeout;
void *pptable;
struct phm_platform_descriptor platform_descriptor;
void *backend;
void *smu_backend;
const struct pp_smumgr_func *smumgr_funcs;
bool is_kicker;
struct phm_dynamic_state_info dyn_state;
const struct pp_hwmgr_func *hwmgr_func;
const struct pp_table_func *pptable_func;
struct pp_power_state *ps;
uint32_t num_ps;
struct pp_thermal_controller_info thermal_controller;
bool fan_ctrl_is_in_default_mode;
uint32_t fan_ctrl_default_mode;
bool fan_ctrl_enabled;
uint32_t tmin;
struct phm_microcode_version_info microcode_version_info;
uint32_t ps_size;
struct pp_power_state *current_ps;
struct pp_power_state *request_ps;
struct pp_power_state *boot_ps;
struct pp_power_state *uvd_ps;
const struct amd_pp_display_configuration *display_config;
uint32_t feature_mask;
bool avfs_supported;
/* UMD Pstate */
bool en_umd_pstate;
uint32_t power_profile_mode;
uint32_t default_power_profile_mode;
uint32_t pstate_sclk;
uint32_t pstate_mclk;
bool od_enabled;
uint32_t power_limit;
uint32_t default_power_limit;
uint32_t workload_mask;
uint32_t workload_prority[Workload_Policy_Max];
uint32_t workload_setting[Workload_Policy_Max];
bool gfxoff_state_changed_by_workload;
uint32_t pstate_sclk_peak;
uint32_t pstate_mclk_peak;
struct delayed_work swctf_delayed_work;
};
int hwmgr_early_init(struct pp_hwmgr *hwmgr);
int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
int hwmgr_suspend(struct pp_hwmgr *hwmgr);
int hwmgr_resume(struct pp_hwmgr *hwmgr);
int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
#endif /* _HWMGR_H_ */
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h
+1793
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h
+197
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@@ -0,0 +1,197 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_POWERSTATE_H
#define PP_POWERSTATE_H
struct pp_hw_power_state {
unsigned int magic;
};
struct pp_power_state;
#define PP_INVALID_POWER_STATE_ID (0)
/*
* An item of a list containing Power States.
*/
struct PP_StateLinkedList {
struct pp_power_state *next;
struct pp_power_state *prev;
};
enum PP_StateUILabel {
PP_StateUILabel_None,
PP_StateUILabel_Battery,
PP_StateUILabel_MiddleLow,
PP_StateUILabel_Balanced,
PP_StateUILabel_MiddleHigh,
PP_StateUILabel_Performance,
PP_StateUILabel_BACO
};
enum PP_StateClassificationFlag {
PP_StateClassificationFlag_Boot = 0x0001,
PP_StateClassificationFlag_Thermal = 0x0002,
PP_StateClassificationFlag_LimitedPowerSource = 0x0004,
PP_StateClassificationFlag_Rest = 0x0008,
PP_StateClassificationFlag_Forced = 0x0010,
PP_StateClassificationFlag_User3DPerformance = 0x0020,
PP_StateClassificationFlag_User2DPerformance = 0x0040,
PP_StateClassificationFlag_3DPerformance = 0x0080,
PP_StateClassificationFlag_ACOverdriveTemplate = 0x0100,
PP_StateClassificationFlag_Uvd = 0x0200,
PP_StateClassificationFlag_3DPerformanceLow = 0x0400,
PP_StateClassificationFlag_ACPI = 0x0800,
PP_StateClassificationFlag_HD2 = 0x1000,
PP_StateClassificationFlag_UvdHD = 0x2000,
PP_StateClassificationFlag_UvdSD = 0x4000,
PP_StateClassificationFlag_UserDCPerformance = 0x8000,
PP_StateClassificationFlag_DCOverdriveTemplate = 0x10000,
PP_StateClassificationFlag_BACO = 0x20000,
PP_StateClassificationFlag_LimitedPowerSource_2 = 0x40000,
PP_StateClassificationFlag_ULV = 0x80000,
PP_StateClassificationFlag_UvdMVC = 0x100000,
};
typedef unsigned int PP_StateClassificationFlags;
struct PP_StateClassificationBlock {
enum PP_StateUILabel ui_label;
enum PP_StateClassificationFlag flags;
int bios_index;
bool temporary_state;
bool to_be_deleted;
};
struct PP_StatePcieBlock {
unsigned int lanes;
};
enum PP_RefreshrateSource {
PP_RefreshrateSource_EDID,
PP_RefreshrateSource_Explicit
};
struct PP_StateDisplayBlock {
bool disableFrameModulation;
bool limitRefreshrate;
enum PP_RefreshrateSource refreshrateSource;
int explicitRefreshrate;
int edidRefreshrateIndex;
bool enableVariBright;
};
struct PP_StateMemroyBlock {
bool dllOff;
uint8_t m3arb;
uint8_t unused[3];
};
struct PP_StateSoftwareAlgorithmBlock {
bool disableLoadBalancing;
bool enableSleepForTimestamps;
};
#define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
/**
* Type to hold a temperature range.
*/
struct PP_TemperatureRange {
int min;
int max;
int edge_emergency_max;
int hotspot_min;
int hotspot_crit_max;
int hotspot_emergency_max;
int mem_min;
int mem_crit_max;
int mem_emergency_max;
int sw_ctf_threshold;
};
struct PP_StateValidationBlock {
bool singleDisplayOnly;
bool disallowOnDC;
uint8_t supportedPowerLevels;
};
struct PP_UVD_CLOCKS {
uint32_t VCLK;
uint32_t DCLK;
};
/**
* Structure to hold a PowerPlay Power State.
*/
struct pp_power_state {
uint32_t id;
struct PP_StateLinkedList orderedList;
struct PP_StateLinkedList allStatesList;
struct PP_StateClassificationBlock classification;
struct PP_StateValidationBlock validation;
struct PP_StatePcieBlock pcie;
struct PP_StateDisplayBlock display;
struct PP_StateMemroyBlock memory;
struct PP_TemperatureRange temperatures;
struct PP_StateSoftwareAlgorithmBlock software;
struct PP_UVD_CLOCKS uvd_clocks;
struct pp_hw_power_state hardware;
};
enum PP_MMProfilingState {
PP_MMProfilingState_NA = 0,
PP_MMProfilingState_Started,
PP_MMProfilingState_Stopped
};
struct pp_clock_engine_request {
unsigned long client_type;
unsigned long ctx_id;
uint64_t context_handle;
unsigned long sclk;
unsigned long sclk_hard_min;
unsigned long mclk;
unsigned long iclk;
unsigned long evclk;
unsigned long ecclk;
unsigned long ecclk_hard_min;
unsigned long vclk;
unsigned long dclk;
unsigned long sclk_over_drive;
unsigned long mclk_over_drive;
unsigned long sclk_threshold;
unsigned long flag;
unsigned long vclk_ceiling;
unsigned long dclk_ceiling;
unsigned long num_cus;
unsigned long pm_flag;
enum PP_MMProfilingState mm_profiling_state;
};
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/pp_debug.h
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_DEBUG_H
#define PP_DEBUG_H
#ifdef pr_fmt
#undef pr_fmt
#endif
#define pr_fmt(fmt) "amdgpu: [powerplay] " fmt
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#define PP_ASSERT_WITH_CODE(cond, msg, code) \
do { \
if (!(cond)) { \
pr_warn_ratelimited("%s\n", msg); \
code; \
} \
} while (0)
#define PP_ASSERT(cond, msg) \
do { \
if (!(cond)) { \
pr_warn_ratelimited("%s\n", msg); \
} \
} while (0)
#define PP_DBG_LOG(fmt, ...) \
do { \
pr_debug(fmt, ##__VA_ARGS__); \
} while (0)
#define GET_FLEXIBLE_ARRAY_MEMBER_ADDR(type, member, ptr, n) \
(type *)((char *)&(ptr)->member + (sizeof(type) * (n)))
#endif /* PP_DEBUG_H */
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/pp_endian.h
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _PP_ENDIAN_H_
#define _PP_ENDIAN_H_
#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
#endif /* _PP_ENDIAN_H_ */
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/pp_thermal.h
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_THERMAL_H
#define PP_THERMAL_H
#include "power_state.h"
static const struct PP_TemperatureRange __maybe_unused SMU7ThermalWithDelayPolicy[] = {
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
};
static const struct PP_TemperatureRange __maybe_unused SMU7ThermalPolicy[] = {
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
};
#define CTF_OFFSET_EDGE 5
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_HBM 5
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/ppinterrupt.h
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _PP_INTERRUPT_H_
#define _PP_INTERRUPT_H_
enum amd_thermal_irq {
AMD_THERMAL_IRQ_LOW_TO_HIGH = 0,
AMD_THERMAL_IRQ_HIGH_TO_LOW,
AMD_THERMAL_IRQ_LAST
};
/* The type of the interrupt callback functions in PowerPlay */
typedef int (*irq_handler_func_t)(void *private_data,
unsigned src_id, const uint32_t *iv_entry);
/* Event Manager action chain list information */
struct pp_interrupt_registration_info {
irq_handler_func_t call_back; /* Pointer to callback function */
void *context; /* Pointer to callback function context */
uint32_t src_id; /* Registered interrupt id */
const uint32_t *iv_entry;
};
#endif /* _PP_INTERRUPT_H_ */
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/rv_ppsmc.h
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef RAVEN_PP_SMC_H
#define RAVEN_PP_SMC_H
#pragma pack(push, 1)
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_PowerUpGfx 0x6
#define PPSMC_MSG_EnableGfxOff 0x7
#define PPSMC_MSG_DisableGfxOff 0x8
#define PPSMC_MSG_PowerDownIspByTile 0x9
#define PPSMC_MSG_PowerUpIspByTile 0xA
#define PPSMC_MSG_PowerDownVcn 0xB
#define PPSMC_MSG_PowerUpVcn 0xC
#define PPSMC_MSG_PowerDownSdma 0xD
#define PPSMC_MSG_PowerUpSdma 0xE
#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF
#define PPSMC_MSG_SetHardMinVcn 0x10
#define PPSMC_MSG_SetMinDisplayClock 0x11
#define PPSMC_MSG_SetHardMinFclkByFreq 0x12
#define PPSMC_MSG_SetAllowFclkSwitch 0x13
#define PPSMC_MSG_SetMinVideoGfxclkFreq 0x14
#define PPSMC_MSG_ActiveProcessNotify 0x15
#define PPSMC_MSG_SetCustomPolicy 0x16
#define PPSMC_MSG_SetVideoFps 0x17
#define PPSMC_MSG_SetDisplayCount 0x18
#define PPSMC_MSG_QueryPowerLimit 0x19
#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A
#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
#define PPSMC_MSG_TransferTableDram2Smu 0x1D
#define PPSMC_MSG_DeviceDriverReset 0x1E
#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
#define PPSMC_MSG_SetMinVddcrSocVoltage 0x22
#define PPSMC_MSG_SetMinVideoFclkFreq 0x23
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x24
#define PPSMC_MSG_ForcePowerDownGfx 0x25
#define PPSMC_MSG_SetPhyclkVoltageByFreq 0x26
#define PPSMC_MSG_SetDppclkVoltageByFreq 0x27
#define PPSMC_MSG_SetSoftMinVcn 0x28
#define PPSMC_MSG_GetGfxclkFrequency 0x2A
#define PPSMC_MSG_GetFclkFrequency 0x2B
#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
#define PPSMC_MSG_SoftReset 0x2E
#define PPSMC_MSG_SetGfxCGPG 0x2F
#define PPSMC_MSG_SetSoftMaxGfxClk 0x30
#define PPSMC_MSG_SetHardMinGfxClk 0x31
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33
#define PPSMC_MSG_SetSoftMaxVcn 0x34
#define PPSMC_MSG_PowerGateMmHub 0x35
#define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36
#define PPSMC_MSG_GpuChangeState 0x37
#define PPSMC_MSG_GetGfxBusy 0x3D
#define PPSMC_Message_Count 0x42
typedef uint16_t PPSMC_Result;
typedef int PPSMC_Msg;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu10.h
+188
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/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU10_H
#define SMU10_H
#pragma pack(push, 1)
#define ENABLE_DEBUG_FEATURES
/* Feature Control Defines */
#define FEATURE_CCLK_CONTROLLER_BIT 0
#define FEATURE_FAN_CONTROLLER_BIT 1
#define FEATURE_DATA_CALCULATION_BIT 2
#define FEATURE_PPT_BIT 3
#define FEATURE_TDC_BIT 4
#define FEATURE_THERMAL_BIT 5
#define FEATURE_FIT_BIT 6
#define FEATURE_EDC_BIT 7
#define FEATURE_PLL_POWER_DOWN_BIT 8
#define FEATURE_ULV_BIT 9
#define FEATURE_VDDOFF_BIT 10
#define FEATURE_VCN_DPM_BIT 11
#define FEATURE_ACP_DPM_BIT 12
#define FEATURE_ISP_DPM_BIT 13
#define FEATURE_FCLK_DPM_BIT 14
#define FEATURE_SOCCLK_DPM_BIT 15
#define FEATURE_MP0CLK_DPM_BIT 16
#define FEATURE_LCLK_DPM_BIT 17
#define FEATURE_SHUBCLK_DPM_BIT 18
#define FEATURE_DCEFCLK_DPM_BIT 19
#define FEATURE_GFX_DPM_BIT 20
#define FEATURE_DS_GFXCLK_BIT 21
#define FEATURE_DS_SOCCLK_BIT 22
#define FEATURE_DS_LCLK_BIT 23
#define FEATURE_DS_DCEFCLK_BIT 24
#define FEATURE_DS_SHUBCLK_BIT 25
#define FEATURE_RM_BIT 26
#define FEATURE_S0i2_BIT 27
#define FEATURE_WHISPER_MODE_BIT 28
#define FEATURE_DS_FCLK_BIT 29
#define FEATURE_DS_SMNCLK_BIT 30
#define FEATURE_DS_MP1CLK_BIT 31
#define FEATURE_DS_MP0CLK_BIT 32
#define FEATURE_MGCG_BIT 33
#define FEATURE_DS_FUSE_SRAM_BIT 34
#define FEATURE_GFX_CKS 35
#define FEATURE_PSI0_BIT 36
#define FEATURE_PROCHOT_BIT 37
#define FEATURE_CPUOFF_BIT 38
#define FEATURE_STAPM_BIT 39
#define FEATURE_CORE_CSTATES_BIT 40
#define FEATURE_SPARE_41_BIT 41
#define FEATURE_SPARE_42_BIT 42
#define FEATURE_SPARE_43_BIT 43
#define FEATURE_SPARE_44_BIT 44
#define FEATURE_SPARE_45_BIT 45
#define FEATURE_SPARE_46_BIT 46
#define FEATURE_SPARE_47_BIT 47
#define FEATURE_SPARE_48_BIT 48
#define FEATURE_SPARE_49_BIT 49
#define FEATURE_SPARE_50_BIT 50
#define FEATURE_SPARE_51_BIT 51
#define FEATURE_SPARE_52_BIT 52
#define FEATURE_SPARE_53_BIT 53
#define FEATURE_SPARE_54_BIT 54
#define FEATURE_SPARE_55_BIT 55
#define FEATURE_SPARE_56_BIT 56
#define FEATURE_SPARE_57_BIT 57
#define FEATURE_SPARE_58_BIT 58
#define FEATURE_SPARE_59_BIT 59
#define FEATURE_SPARE_60_BIT 60
#define FEATURE_SPARE_61_BIT 61
#define FEATURE_SPARE_62_BIT 62
#define FEATURE_SPARE_63_BIT 63
#define NUM_FEATURES 64
#define FEATURE_CCLK_CONTROLLER_MASK (1 << FEATURE_CCLK_CONTROLLER_BIT)
#define FEATURE_FAN_CONTROLLER_MASK (1 << FEATURE_FAN_CONTROLLER_BIT)
#define FEATURE_DATA_CALCULATION_MASK (1 << FEATURE_DATA_CALCULATION_BIT)
#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT)
#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT)
#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT)
#define FEATURE_FIT_MASK (1 << FEATURE_FIT_BIT)
#define FEATURE_EDC_MASK (1 << FEATURE_EDC_BIT)
#define FEATURE_PLL_POWER_DOWN_MASK (1 << FEATURE_PLL_POWER_DOWN_BIT)
#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT)
#define FEATURE_VDDOFF_MASK (1 << FEATURE_VDDOFF_BIT)
#define FEATURE_VCN_DPM_MASK (1 << FEATURE_VCN_DPM_BIT)
#define FEATURE_ACP_DPM_MASK (1 << FEATURE_ACP_DPM_BIT)
#define FEATURE_ISP_DPM_MASK (1 << FEATURE_ISP_DPM_BIT)
#define FEATURE_FCLK_DPM_MASK (1 << FEATURE_FCLK_DPM_BIT)
#define FEATURE_SOCCLK_DPM_MASK (1 << FEATURE_SOCCLK_DPM_BIT)
#define FEATURE_MP0CLK_DPM_MASK (1 << FEATURE_MP0CLK_DPM_BIT)
#define FEATURE_LCLK_DPM_MASK (1 << FEATURE_LCLK_DPM_BIT)
#define FEATURE_SHUBCLK_DPM_MASK (1 << FEATURE_SHUBCLK_DPM_BIT)
#define FEATURE_DCEFCLK_DPM_MASK (1 << FEATURE_DCEFCLK_DPM_BIT)
#define FEATURE_GFX_DPM_MASK (1 << FEATURE_GFX_DPM_BIT)
#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT)
#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT)
#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT)
#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT)
#define FEATURE_DS_SHUBCLK_MASK (1 << FEATURE_DS_SHUBCLK_BIT)
#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT)
#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT)
#define FEATURE_DS_SMNCLK_MASK (1 << FEATURE_DS_SMNCLK_BIT)
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT)
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT)
#define FEATURE_MGCG_MASK (1 << FEATURE_MGCG_BIT)
#define FEATURE_DS_FUSE_SRAM_MASK (1 << FEATURE_DS_FUSE_SRAM_BIT)
#define FEATURE_PSI0_MASK (1 << FEATURE_PSI0_BIT)
#define FEATURE_STAPM_MASK (1 << FEATURE_STAPM_BIT)
#define FEATURE_PROCHOT_MASK (1 << FEATURE_PROCHOT_BIT)
#define FEATURE_CPUOFF_MASK (1 << FEATURE_CPUOFF_BIT)
#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)
/* Workload bits */
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
#define WORKLOAD_PPLIB_VIDEO_BIT 2
#define WORKLOAD_PPLIB_VR_BIT 3
#define WORKLOAD_PPLIB_COMPUTE_BIT 4
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
#define WORKLOAD_PPLIB_COUNT 6
typedef struct {
/* MP1_EXT_SCRATCH0 */
uint32_t CurrLevel_ACP : 4;
uint32_t CurrLevel_ISP : 4;
uint32_t CurrLevel_VCN : 4;
uint32_t CurrLevel_LCLK : 4;
uint32_t CurrLevel_MP0CLK : 4;
uint32_t CurrLevel_FCLK : 4;
uint32_t CurrLevel_SOCCLK : 4;
uint32_t CurrLevel_DCEFCLK : 4;
/* MP1_EXT_SCRATCH1 */
uint32_t TargLevel_ACP : 4;
uint32_t TargLevel_ISP : 4;
uint32_t TargLevel_VCN : 4;
uint32_t TargLevel_LCLK : 4;
uint32_t TargLevel_MP0CLK : 4;
uint32_t TargLevel_FCLK : 4;
uint32_t TargLevel_SOCCLK : 4;
uint32_t TargLevel_DCEFCLK : 4;
/* MP1_EXT_SCRATCH2 */
uint32_t CurrLevel_SHUBCLK : 4;
uint32_t TargLevel_SHUBCLK : 4;
uint32_t InUlv : 1;
uint32_t InS0i2 : 1;
uint32_t InWhisperMode : 1;
uint32_t Reserved : 21;
/* MP1_EXT_SCRATCH3-4 */
uint32_t Reserved2[2];
/* MP1_EXT_SCRATCH5 */
uint32_t FeatureStatus[NUM_FEATURES / 32];
} FwStatus_t;
#define TABLE_BIOS_IF 0 /* Called by BIOS */
#define TABLE_WATERMARKS 1 /* Called by Driver */
#define TABLE_CUSTOM_DPM 2 /* Called by Driver */
#define TABLE_PMSTATUSLOG 3 /* Called by Tools for Agm logging */
#define TABLE_DPMCLOCKS 4 /* Called by Driver */
#define TABLE_MOMENTARY_PM 5 /* Called by Tools */
#define TABLE_COUNT 6
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h
+117
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@@ -0,0 +1,117 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU10_DRIVER_IF_H
#define SMU10_DRIVER_IF_H
#define SMU10_DRIVER_IF_VERSION 0x6
#define NUM_DSPCLK_LEVELS 8
typedef struct {
int32_t value;
uint32_t numFractionalBits;
} FloatInIntFormat_t;
typedef enum {
DSPCLK_DCEFCLK = 0,
DSPCLK_DISPCLK,
DSPCLK_PIXCLK,
DSPCLK_PHYCLK,
DSPCLK_COUNT,
} DSPCLK_e;
typedef struct {
uint16_t Freq;
uint16_t Vid;
} DisplayClockTable_t;
typedef struct {
uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
uint16_t MinMclk;
uint16_t MaxMclk;
uint8_t WmSetting;
uint8_t WmType;
uint8_t Padding[2];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
typedef enum {
WM_SOCCLK = 0,
WM_DCFCLK,
WM_COUNT,
} WM_CLOCK_e;
typedef struct {
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
uint32_t MmHubPadding[7];
} Watermarks_t;
typedef enum {
CUSTOM_DPM_SETTING_GFXCLK,
CUSTOM_DPM_SETTING_CCLK,
CUSTOM_DPM_SETTING_FCLK_CCX,
CUSTOM_DPM_SETTING_FCLK_GFX,
CUSTOM_DPM_SETTING_FCLK_STALLS,
CUSTOM_DPM_SETTING_LCLK,
CUSTOM_DPM_SETTING_COUNT,
} CUSTOM_DPM_SETTING_e;
typedef struct {
uint8_t ActiveHystLimit;
uint8_t IdleHystLimit;
uint8_t FPS;
uint8_t MinActiveFreqType;
FloatInIntFormat_t MinActiveFreq;
FloatInIntFormat_t PD_Data_limit;
FloatInIntFormat_t PD_Data_time_constant;
FloatInIntFormat_t PD_Data_error_coeff;
FloatInIntFormat_t PD_Data_error_rate_coeff;
} DpmActivityMonitorCoeffExt_t;
typedef struct {
DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
} CustomDpmSettings_t;
#define NUM_SOCCLK_DPM_LEVELS 8
#define NUM_DCEFCLK_DPM_LEVELS 4
#define NUM_FCLK_DPM_LEVELS 4
#define NUM_MEMCLK_DPM_LEVELS 4
typedef struct {
uint32_t Freq; /* In MHz */
uint32_t Vol; /* Millivolts with 2 fractional bits */
} DpmClock_t;
typedef struct {
DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
} DpmClocks_t;
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h
+895
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@@ -0,0 +1,895 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU11_DRIVER_IF_H
#define SMU11_DRIVER_IF_H
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
// Be aware of that the version should be updated in
// smu_v11_0.h, rename is also needed.
// #define SMU11_DRIVER_IF_VERSION 0x13
#define PPTABLE_V20_SMU_VERSION 3
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_VCLK_DPM_LEVELS 8
#define NUM_DCLK_DPM_LEVELS 8
#define NUM_ECLK_DPM_LEVELS 8
#define NUM_MP0CLK_DPM_LEVELS 2
#define NUM_SOCCLK_DPM_LEVELS 8
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_FCLK_DPM_LEVELS 8
#define NUM_DCEFCLK_DPM_LEVELS 8
#define NUM_DISPCLK_DPM_LEVELS 8
#define NUM_PIXCLK_DPM_LEVELS 8
#define NUM_PHYCLK_DPM_LEVELS 8
#define NUM_LINK_LEVELS 2
#define NUM_XGMI_LEVELS 2
#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
#define MAX_ECLK_DPM_LEVEL (NUM_ECLK_DPM_LEVELS - 1)
#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
#define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
#define PPSMC_GeminiModeNone 0
#define PPSMC_GeminiModeMaster 1
#define PPSMC_GeminiModeSlave 2
#define FEATURE_DPM_PREFETCHER_BIT 0
#define FEATURE_DPM_GFXCLK_BIT 1
#define FEATURE_DPM_UCLK_BIT 2
#define FEATURE_DPM_SOCCLK_BIT 3
#define FEATURE_DPM_UVD_BIT 4
#define FEATURE_DPM_VCE_BIT 5
#define FEATURE_ULV_BIT 6
#define FEATURE_DPM_MP0CLK_BIT 7
#define FEATURE_DPM_LINK_BIT 8
#define FEATURE_DPM_DCEFCLK_BIT 9
#define FEATURE_DS_GFXCLK_BIT 10
#define FEATURE_DS_SOCCLK_BIT 11
#define FEATURE_DS_LCLK_BIT 12
#define FEATURE_PPT_BIT 13
#define FEATURE_TDC_BIT 14
#define FEATURE_THERMAL_BIT 15
#define FEATURE_GFX_PER_CU_CG_BIT 16
#define FEATURE_RM_BIT 17
#define FEATURE_DS_DCEFCLK_BIT 18
#define FEATURE_ACDC_BIT 19
#define FEATURE_VR0HOT_BIT 20
#define FEATURE_VR1HOT_BIT 21
#define FEATURE_FW_CTF_BIT 22
#define FEATURE_LED_DISPLAY_BIT 23
#define FEATURE_FAN_CONTROL_BIT 24
#define FEATURE_GFX_EDC_BIT 25
#define FEATURE_GFXOFF_BIT 26
#define FEATURE_CG_BIT 27
#define FEATURE_DPM_FCLK_BIT 28
#define FEATURE_DS_FCLK_BIT 29
#define FEATURE_DS_MP1CLK_BIT 30
#define FEATURE_DS_MP0CLK_BIT 31
#define FEATURE_XGMI_BIT 32
#define FEATURE_ECC_BIT 33
#define FEATURE_SPARE_34_BIT 34
#define FEATURE_SPARE_35_BIT 35
#define FEATURE_SPARE_36_BIT 36
#define FEATURE_SPARE_37_BIT 37
#define FEATURE_SPARE_38_BIT 38
#define FEATURE_SPARE_39_BIT 39
#define FEATURE_SPARE_40_BIT 40
#define FEATURE_SPARE_41_BIT 41
#define FEATURE_SPARE_42_BIT 42
#define FEATURE_SPARE_43_BIT 43
#define FEATURE_SPARE_44_BIT 44
#define FEATURE_SPARE_45_BIT 45
#define FEATURE_SPARE_46_BIT 46
#define FEATURE_SPARE_47_BIT 47
#define FEATURE_SPARE_48_BIT 48
#define FEATURE_SPARE_49_BIT 49
#define FEATURE_SPARE_50_BIT 50
#define FEATURE_SPARE_51_BIT 51
#define FEATURE_SPARE_52_BIT 52
#define FEATURE_SPARE_53_BIT 53
#define FEATURE_SPARE_54_BIT 54
#define FEATURE_SPARE_55_BIT 55
#define FEATURE_SPARE_56_BIT 56
#define FEATURE_SPARE_57_BIT 57
#define FEATURE_SPARE_58_BIT 58
#define FEATURE_SPARE_59_BIT 59
#define FEATURE_SPARE_60_BIT 60
#define FEATURE_SPARE_61_BIT 61
#define FEATURE_SPARE_62_BIT 62
#define FEATURE_SPARE_63_BIT 63
#define NUM_FEATURES 64
#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
#define FEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
#define FEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
#define FEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
#define FEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
#define FEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT )
#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
#define FEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
#define FEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT )
#define FEATURE_CG_MASK (1 << FEATURE_CG_BIT )
#define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT )
#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
#define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT )
#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT )
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK 0x00000004
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK 0x00000008
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000010
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK 0x00000020
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000040
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK 0x00000080
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK 0x00000100
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK 0x00000200
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK 0x00000400
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK 0x00000800
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00002000
#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH 0x00004000
#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000
#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000
#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000
#define I2C_CONTROLLER_ENABLED 1
#define I2C_CONTROLLER_DISABLED 0
#define VR_MAPPING_VR_SELECT_MASK 0x01
#define VR_MAPPING_VR_SELECT_SHIFT 0x00
#define VR_MAPPING_PLANE_SELECT_MASK 0x02
#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
#define PSI_SEL_VR0_PLANE0_PSI0 0x01
#define PSI_SEL_VR0_PLANE0_PSI1 0x02
#define PSI_SEL_VR0_PLANE1_PSI0 0x04
#define PSI_SEL_VR0_PLANE1_PSI1 0x08
#define PSI_SEL_VR1_PLANE0_PSI0 0x10
#define PSI_SEL_VR1_PLANE0_PSI1 0x20
#define PSI_SEL_VR1_PLANE1_PSI0 0x40
#define PSI_SEL_VR1_PLANE1_PSI1 0x80
#define THROTTLER_STATUS_PADDING_BIT 0
#define THROTTLER_STATUS_TEMP_EDGE_BIT 1
#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
#define THROTTLER_STATUS_TEMP_HBM_BIT 3
#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4
#define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5
#define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6
#define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7
#define THROTTLER_STATUS_TEMP_LIQUID_BIT 8
#define THROTTLER_STATUS_TEMP_PLX_BIT 9
#define THROTTLER_STATUS_TEMP_SKIN_BIT 10
#define THROTTLER_STATUS_TDC_GFX_BIT 11
#define THROTTLER_STATUS_TDC_SOC_BIT 12
#define THROTTLER_STATUS_PPT_BIT 13
#define THROTTLER_STATUS_FIT_BIT 14
#define THROTTLER_STATUS_PPM_BIT 15
#define TABLE_TRANSFER_OK 0x0
#define TABLE_TRANSFER_FAILED 0xFF
#define WORKLOAD_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_COUNT 7
#define XGMI_STATE_D0 1
#define XGMI_STATE_D3 0
typedef enum {
I2C_CONTROLLER_PORT_0 = 0,
I2C_CONTROLLER_PORT_1 = 1,
} I2cControllerPort_e;
typedef enum {
I2C_CONTROLLER_NAME_VR_GFX = 0,
I2C_CONTROLLER_NAME_VR_SOC,
I2C_CONTROLLER_NAME_VR_VDDCI,
I2C_CONTROLLER_NAME_VR_HBM,
I2C_CONTROLLER_NAME_LIQUID_0,
I2C_CONTROLLER_NAME_LIQUID_1,
I2C_CONTROLLER_NAME_PLX,
I2C_CONTROLLER_NAME_COUNT,
} I2cControllerName_e;
typedef enum {
I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
I2C_CONTROLLER_THROTTLER_VR_GFX,
I2C_CONTROLLER_THROTTLER_VR_SOC,
I2C_CONTROLLER_THROTTLER_VR_VDDCI,
I2C_CONTROLLER_THROTTLER_VR_HBM,
I2C_CONTROLLER_THROTTLER_LIQUID_0,
I2C_CONTROLLER_THROTTLER_LIQUID_1,
I2C_CONTROLLER_THROTTLER_PLX,
} I2cControllerThrottler_e;
typedef enum {
I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
I2C_CONTROLLER_PROTOCOL_SPARE_0,
I2C_CONTROLLER_PROTOCOL_SPARE_1,
I2C_CONTROLLER_PROTOCOL_SPARE_2,
} I2cControllerProtocol_e;
typedef enum {
I2C_CONTROLLER_SPEED_SLOW = 0,
I2C_CONTROLLER_SPEED_FAST = 1,
} I2cControllerSpeed_e;
typedef struct {
uint32_t Enabled;
uint32_t SlaveAddress;
uint32_t ControllerPort;
uint32_t ControllerName;
uint32_t ThermalThrottler;
uint32_t I2cProtocol;
uint32_t I2cSpeed;
} I2cControllerConfig_t;
typedef struct {
uint32_t a;
uint32_t b;
uint32_t c;
} QuadraticInt_t;
typedef struct {
uint32_t m;
uint32_t b;
} LinearInt_t;
typedef struct {
uint32_t a;
uint32_t b;
uint32_t c;
} DroopInt_t;
typedef enum {
PPCLK_GFXCLK,
PPCLK_VCLK,
PPCLK_DCLK,
PPCLK_ECLK,
PPCLK_SOCCLK,
PPCLK_UCLK,
PPCLK_DCEFCLK,
PPCLK_DISPCLK,
PPCLK_PIXCLK,
PPCLK_PHYCLK,
PPCLK_FCLK,
PPCLK_COUNT,
} PPCLK_e;
typedef enum {
POWER_SOURCE_AC,
POWER_SOURCE_DC,
POWER_SOURCE_COUNT,
} POWER_SOURCE_e;
typedef enum {
VOLTAGE_MODE_AVFS = 0,
VOLTAGE_MODE_AVFS_SS,
VOLTAGE_MODE_SS,
VOLTAGE_MODE_COUNT,
} VOLTAGE_MODE_e;
typedef enum {
AVFS_VOLTAGE_GFX = 0,
AVFS_VOLTAGE_SOC,
AVFS_VOLTAGE_COUNT,
} AVFS_VOLTAGE_TYPE_e;
typedef struct {
uint8_t VoltageMode;
uint8_t SnapToDiscrete;
uint8_t NumDiscreteLevels;
uint8_t padding;
LinearInt_t ConversionToAvfsClk;
QuadraticInt_t SsCurve;
} DpmDescriptor_t;
#pragma pack(push, 1)
typedef struct {
uint32_t Version;
uint32_t FeaturesToRun[2];
uint16_t SocketPowerLimitAc0;
uint16_t SocketPowerLimitAc0Tau;
uint16_t SocketPowerLimitAc1;
uint16_t SocketPowerLimitAc1Tau;
uint16_t SocketPowerLimitAc2;
uint16_t SocketPowerLimitAc2Tau;
uint16_t SocketPowerLimitAc3;
uint16_t SocketPowerLimitAc3Tau;
uint16_t SocketPowerLimitDc;
uint16_t SocketPowerLimitDcTau;
uint16_t TdcLimitSoc;
uint16_t TdcLimitSocTau;
uint16_t TdcLimitGfx;
uint16_t TdcLimitGfxTau;
uint16_t TedgeLimit;
uint16_t ThotspotLimit;
uint16_t ThbmLimit;
uint16_t Tvr_gfxLimit;
uint16_t Tvr_memLimit;
uint16_t Tliquid1Limit;
uint16_t Tliquid2Limit;
uint16_t TplxLimit;
uint32_t FitLimit;
uint16_t PpmPowerLimit;
uint16_t PpmTemperatureThreshold;
uint8_t MemoryOnPackage;
uint8_t padding8_limits;
uint16_t Tvr_SocLimit;
uint16_t UlvVoltageOffsetSoc;
uint16_t UlvVoltageOffsetGfx;
uint8_t UlvSmnclkDid;
uint8_t UlvMp1clkDid;
uint8_t UlvGfxclkBypass;
uint8_t Padding234;
uint16_t MinVoltageGfx;
uint16_t MinVoltageSoc;
uint16_t MaxVoltageGfx;
uint16_t MaxVoltageSoc;
uint16_t LoadLineResistanceGfx;
uint16_t LoadLineResistanceSoc;
DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ];
uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ];
uint16_t FreqTableEclk [NUM_ECLK_DPM_LEVELS ];
uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ];
uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ];
uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ];
uint16_t DcModeMaxFreq [PPCLK_COUNT ];
uint16_t Padding8_Clks;
uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
uint16_t GfxclkFidle;
uint16_t GfxclkSlewRate;
uint16_t CksEnableFreq;
uint16_t Padding789;
QuadraticInt_t CksVoltageOffset;
uint8_t Padding567[4];
uint16_t GfxclkDsMaxFreq;
uint8_t GfxclkSource;
uint8_t Padding456;
uint8_t LowestUclkReservedForUlv;
uint8_t Padding8_Uclk[3];
uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
uint8_t PcieLaneCount[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint16_t EnableTdpm;
uint16_t TdpmHighHystTemperature;
uint16_t TdpmLowHystTemperature;
uint16_t GfxclkFreqHighTempLimit;
uint16_t FanStopTemp;
uint16_t FanStartTemp;
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint16_t FanGainLiquid;
uint16_t FanGainVrGfx;
uint16_t FanGainVrSoc;
uint16_t FanGainPlx;
uint16_t FanGainHbm;
uint16_t FanPwmMin;
uint16_t FanAcousticLimitRpm;
uint16_t FanThrottlingRpm;
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t FuzzyFan_Reserved;
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
uint8_t Padding8_Avfs[2];
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT];
DroopInt_t dBtcGbGfxCksOn;
DroopInt_t dBtcGbGfxCksOff;
DroopInt_t dBtcGbGfxAfll;
DroopInt_t dBtcGbSoc;
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT];
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT];
uint16_t DcTol[AVFS_VOLTAGE_COUNT];
uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
uint8_t Padding8_GfxBtc[2];
int16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT];
uint8_t XgmiLinkSpeed [NUM_XGMI_LEVELS];
uint8_t XgmiLinkWidth [NUM_XGMI_LEVELS];
uint16_t XgmiFclkFreq [NUM_XGMI_LEVELS];
uint16_t XgmiUclkFreq [NUM_XGMI_LEVELS];
uint16_t XgmiSocclkFreq [NUM_XGMI_LEVELS];
uint16_t XgmiSocVoltage [NUM_XGMI_LEVELS];
uint32_t DebugOverrides;
QuadraticInt_t ReservedEquation0;
QuadraticInt_t ReservedEquation1;
QuadraticInt_t ReservedEquation2;
QuadraticInt_t ReservedEquation3;
uint16_t MinVoltageUlvGfx;
uint16_t MinVoltageUlvSoc;
uint16_t MGpuFanBoostLimitRpm;
uint16_t padding16_Fan;
uint16_t FanGainVrMem0;
uint16_t FanGainVrMem1;
uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
uint32_t Reserved[11];
uint32_t Padding32[3];
uint16_t MaxVoltageStepGfx;
uint16_t MaxVoltageStepSoc;
uint8_t VddGfxVrMapping;
uint8_t VddSocVrMapping;
uint8_t VddMem0VrMapping;
uint8_t VddMem1VrMapping;
uint8_t GfxUlvPhaseSheddingMask;
uint8_t SocUlvPhaseSheddingMask;
uint8_t ExternalSensorPresent;
uint8_t Padding8_V;
uint16_t GfxMaxCurrent;
int8_t GfxOffset;
uint8_t Padding_TelemetryGfx;
uint16_t SocMaxCurrent;
int8_t SocOffset;
uint8_t Padding_TelemetrySoc;
uint16_t Mem0MaxCurrent;
int8_t Mem0Offset;
uint8_t Padding_TelemetryMem0;
uint16_t Mem1MaxCurrent;
int8_t Mem1Offset;
uint8_t Padding_TelemetryMem1;
uint8_t AcDcGpio;
uint8_t AcDcPolarity;
uint8_t VR0HotGpio;
uint8_t VR0HotPolarity;
uint8_t VR1HotGpio;
uint8_t VR1HotPolarity;
uint8_t Padding1;
uint8_t Padding2;
uint8_t LedPin0;
uint8_t LedPin1;
uint8_t LedPin2;
uint8_t padding8_4;
uint8_t PllGfxclkSpreadEnabled;
uint8_t PllGfxclkSpreadPercent;
uint16_t PllGfxclkSpreadFreq;
uint8_t UclkSpreadEnabled;
uint8_t UclkSpreadPercent;
uint16_t UclkSpreadFreq;
uint8_t FclkSpreadEnabled;
uint8_t FclkSpreadPercent;
uint16_t FclkSpreadFreq;
uint8_t FllGfxclkSpreadEnabled;
uint8_t FllGfxclkSpreadPercent;
uint16_t FllGfxclkSpreadFreq;
I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT];
uint32_t BoardReserved[10];
uint32_t MmHubPadding[8];
} PPTable_t;
#pragma pack(pop)
typedef struct {
uint16_t GfxclkAverageLpfTau;
uint16_t SocclkAverageLpfTau;
uint16_t UclkAverageLpfTau;
uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau;
uint16_t SocketPowerLpfTau;
uint32_t MmHubPadding[8];
} DriverSmuConfig_t;
typedef struct {
uint16_t GfxclkFmin;
uint16_t GfxclkFmax;
uint16_t GfxclkFreq1;
uint16_t GfxclkVolt1;
uint16_t GfxclkFreq2;
uint16_t GfxclkVolt2;
uint16_t GfxclkFreq3;
uint16_t GfxclkVolt3;
uint16_t UclkFmax;
int16_t OverDrivePct;
uint16_t FanMaximumRpm;
uint16_t FanMinimumPwm;
uint16_t FanTargetTemperature;
uint16_t MaxOpTemp;
uint16_t FanZeroRpmEnable;
uint16_t Padding;
} OverDriveTable_t;
typedef struct {
uint16_t CurrClock[PPCLK_COUNT];
uint16_t AverageGfxclkFrequency;
uint16_t AverageSocclkFrequency;
uint16_t AverageUclkFrequency ;
uint16_t AverageGfxActivity ;
uint16_t AverageUclkActivity ;
uint8_t CurrSocVoltageOffset ;
uint8_t CurrGfxVoltageOffset ;
uint8_t CurrMemVidOffset ;
uint8_t Padding8 ;
uint16_t CurrSocketPower ;
uint16_t TemperatureEdge ;
uint16_t TemperatureHotspot ;
uint16_t TemperatureHBM ;
uint16_t TemperatureVrGfx ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureVrMem0 ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureLiquid ;
uint16_t TemperaturePlx ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
uint16_t AverageSocketPower;
uint8_t Padding;
uint32_t MmHubPadding[7];
} SmuMetrics_t;
typedef struct {
uint16_t MinClock;
uint16_t MaxClock;
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Padding[3];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
typedef enum {
WM_SOCCLK = 0,
WM_DCEFCLK,
WM_COUNT_PP,
} WM_CLOCK_e;
typedef struct {
WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
uint32_t MmHubPadding[7];
} Watermarks_t;
typedef struct {
uint16_t avgPsmCount[45];
uint16_t minPsmCount[45];
float avgPsmVoltage[45];
float minPsmVoltage[45];
uint16_t avgScsPsmCount;
uint16_t minScsPsmCount;
float avgScsPsmVoltage;
float minScsPsmVoltage;
uint32_t MmHubPadding[6];
} AvfsDebugTable_t;
typedef struct {
uint8_t AvfsVersion;
uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];
uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];
uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];
uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
int32_t VFT0_m1[AVFS_VOLTAGE_COUNT];
int32_t VFT0_m2[AVFS_VOLTAGE_COUNT];
int32_t VFT0_b[AVFS_VOLTAGE_COUNT];
int32_t VFT1_m1[AVFS_VOLTAGE_COUNT];
int32_t VFT1_m2[AVFS_VOLTAGE_COUNT];
int32_t VFT1_b[AVFS_VOLTAGE_COUNT];
int32_t VFT2_m1[AVFS_VOLTAGE_COUNT];
int32_t VFT2_m2[AVFS_VOLTAGE_COUNT];
int32_t VFT2_b[AVFS_VOLTAGE_COUNT];
int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT];
int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT];
int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];
int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT];
int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT];
int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];
uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
uint32_t VInversion[AVFS_VOLTAGE_COUNT];
int32_t P2V_m1[AVFS_VOLTAGE_COUNT];
int32_t P2V_m2[AVFS_VOLTAGE_COUNT];
int32_t P2V_b[AVFS_VOLTAGE_COUNT];
uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT];
uint32_t EnabledAvfsModules;
uint32_t MmHubPadding[7];
} AvfsFuseOverride_t;
typedef struct {
uint8_t Gfx_ActiveHystLimit;
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
uint32_t Gfx_PD_Data_limit_a;
uint32_t Gfx_PD_Data_limit_b;
uint32_t Gfx_PD_Data_limit_c;
uint32_t Gfx_PD_Data_error_coeff;
uint32_t Gfx_PD_Data_error_rate_coeff;
uint8_t Soc_ActiveHystLimit;
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
uint16_t Soc_PD_Data_time_constant;
uint32_t Soc_PD_Data_limit_a;
uint32_t Soc_PD_Data_limit_b;
uint32_t Soc_PD_Data_limit_c;
uint32_t Soc_PD_Data_error_coeff;
uint32_t Soc_PD_Data_error_rate_coeff;
uint8_t Mem_ActiveHystLimit;
uint8_t Mem_IdleHystLimit;
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;
uint32_t Mem_PD_Data_limit_a;
uint32_t Mem_PD_Data_limit_b;
uint32_t Mem_PD_Data_limit_c;
uint32_t Mem_PD_Data_error_coeff;
uint32_t Mem_PD_Data_error_rate_coeff;
uint8_t Fclk_ActiveHystLimit;
uint8_t Fclk_IdleHystLimit;
uint8_t Fclk_FPS;
uint8_t Fclk_MinActiveFreqType;
uint8_t Fclk_BoosterFreqType;
uint8_t Fclk_UseRlcBusy;
uint16_t Fclk_MinActiveFreq;
uint16_t Fclk_BoosterFreq;
uint16_t Fclk_PD_Data_time_constant;
uint32_t Fclk_PD_Data_limit_a;
uint32_t Fclk_PD_Data_limit_b;
uint32_t Fclk_PD_Data_limit_c;
uint32_t Fclk_PD_Data_error_coeff;
uint32_t Fclk_PD_Data_error_rate_coeff;
} DpmActivityMonitorCoeffInt_t;
#define TABLE_PPTABLE 0
#define TABLE_WATERMARKS 1
#define TABLE_AVFS 2
#define TABLE_AVFS_PSM_DEBUG 3
#define TABLE_AVFS_FUSE_OVERRIDE 4
#define TABLE_PMSTATUSLOG 5
#define TABLE_SMU_METRICS 6
#define TABLE_DRIVER_SMU_CONFIG 7
#define TABLE_ACTIVITY_MONITOR_COEFF 8
#define TABLE_OVERDRIVE 9
#define TABLE_COUNT 10
#define UCLK_SWITCH_SLOW 0
#define UCLK_SWITCH_FAST 1
#define SQ_Enable_MASK 0x1
#define SQ_IR_MASK 0x2
#define SQ_PCC_MASK 0x4
#define SQ_EDC_MASK 0x8
#define TCP_Enable_MASK 0x100
#define TCP_IR_MASK 0x200
#define TCP_PCC_MASK 0x400
#define TCP_EDC_MASK 0x800
#define TD_Enable_MASK 0x10000
#define TD_IR_MASK 0x20000
#define TD_PCC_MASK 0x40000
#define TD_EDC_MASK 0x80000
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
#define SQ_IR_SHIFT 1
#define SQ_PCC_SHIFT 2
#define SQ_EDC_SHIFT 3
#define TCP_Enable_SHIFT 8
#define TCP_IR_SHIFT 9
#define TCP_PCC_SHIFT 10
#define TCP_EDC_SHIFT 11
#define TD_Enable_SHIFT 16
#define TD_IR_SHIFT 17
#define TD_PCC_SHIFT 18
#define TD_EDC_SHIFT 19
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#define REMOVE_FMAX_MARGIN_BIT 0x0
#define REMOVE_DCTOL_MARGIN_BIT 0x1
#define REMOVE_PLATFORM_MARGIN_BIT 0x2
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu7.h
+187
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@@ -0,0 +1,187 @@
/*
* Copyright 2013 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU7_H
#define SMU7_H
#pragma pack(push, 1)
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU7_MAX_LEVELS_VDDC 8
#define SMU7_MAX_LEVELS_VDDCI 4
#define SMU7_MAX_LEVELS_MVDD 4
#define SMU7_MAX_LEVELS_VDDNB 8
#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
#define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
#define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels
#define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
#define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD.
#define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE.
#define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP.
#define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU.
#define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table.
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
/* Voltage Regulator Configuration */
/* VR Config info is contained in dpmTable */
#define VRCONF_VDDC_MASK 0x000000FF
#define VRCONF_VDDC_SHIFT 0
#define VRCONF_VDDGFX_MASK 0x0000FF00
#define VRCONF_VDDGFX_SHIFT 8
#define VRCONF_VDDCI_MASK 0x00FF0000
#define VRCONF_VDDCI_SHIFT 16
#define VRCONF_MVDD_MASK 0xFF000000
#define VRCONF_MVDD_SHIFT 24
#define VR_MERGED_WITH_VDDC 0
#define VR_SVI2_PLANE_1 1
#define VR_SVI2_PLANE_2 2
#define VR_SMIO_PATTERN_1 3
#define VR_SMIO_PATTERN_2 4
#define VR_STATIC_VOLTAGE 5
struct SMU7_PIDController {
uint32_t Ki;
int32_t LFWindupUL;
int32_t LFWindupLL;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU7_PIDController SMU7_PIDController;
// -------------------------------------------------------------------------------------------------------------------------
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
struct SMU7_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t Reserved[42];
uint32_t Signature;
};
typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h
+504
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@@ -0,0 +1,504 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU71_H
#define SMU71_H
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define SMU__NUM_PCIE_DPM_LEVELS 8
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__VARIANT__ICELAND 1
#define SMU__DGPU_ONLY 1
#define SMU__DYNAMIC_MCARB_SETTINGS 1
enum SID_OPTION {
SID_OPTION_HI,
SID_OPTION_LO,
SID_OPTION_COUNT
};
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU71_MAX_LEVELS_VDDC 8
#define SMU71_MAX_LEVELS_VDDCI 4
#define SMU71_MAX_LEVELS_MVDD 4
#define SMU71_MAX_LEVELS_VDDNB 8
#define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
#define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
#define SMU71_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS
#define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
#define SMU71_MAX_ENTRIES_SMIO 32
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
#if defined SMU__DGPU_ONLY
#define SMU71_DTE_ITERATIONS 5
#define SMU71_DTE_SOURCES 3
#define SMU71_DTE_SINKS 1
#define SMU71_NUM_CPU_TES 0
#define SMU71_NUM_GPU_TES 1
#define SMU71_NUM_NON_TES 2
#endif
#if defined SMU__FUSION_ONLY
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
#endif
struct SMU71_PIDController {
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU71_PIDController SMU71_PIDController;
struct SMU7_LocalDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode;
uint8_t FpsFilterWeight;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters[SMU71_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters[SMU71_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
struct SMU7_VoltageScoreboard {
uint16_t CurrentVoltage;
uint16_t HighestVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
#if defined (SMU__DGPU_ONLY)
uint8_t CurrentPhases;
uint8_t HighestPhases;
#else
uint8_t AvsOffset;
uint8_t AvsOffsetApplied;
#endif
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
#if defined (SMU__DGPU_ONLY)
uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];
#endif
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t TargetIndex;
uint8_t Delay;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
#if defined (SMU__DGPU_ONLY)
uint16_t RequestedVddci;
uint16_t CurrentVddci;
uint16_t HighestVddci;
uint8_t CurrentVddciVid;
uint8_t TargetVddciIndex;
#endif
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
// -------------------------------------------------------------------------------------------------------------------------
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
struct SMU7_PCIeLinkSpeedScoreboard
{
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
// -------------------------------------------------------- CAC table ------------------------------------------------------
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard
{
uint16_t MinVoltage;
uint16_t MaxVoltage;
uint32_t AvgGpuPower;
uint16_t VddcLeakagePower[SID_OPTION_COUNT];
uint16_t VddcSclkConstantPower[SID_OPTION_COUNT];
uint16_t VddcSclkDynamicPower[SID_OPTION_COUNT];
uint16_t VddcNonSclkDynamicPower[SID_OPTION_COUNT];
uint16_t VddcTotalPower[SID_OPTION_COUNT];
uint16_t VddcTotalCurrent[SID_OPTION_COUNT];
uint16_t VddcLoadVoltage[SID_OPTION_COUNT];
uint16_t VddcNoLoadVoltage[SID_OPTION_COUNT];
uint16_t DisplayPhyPower;
uint16_t PciePhyPower;
uint16_t VddciTotalPower;
uint16_t Vddr1TotalPower;
uint32_t RocPower;
uint32_t last_power;
uint32_t enableWinAvg;
uint32_t lkg_acc;
uint16_t VoltLkgeScaler;
uint16_t TempLkgeScaler;
uint32_t uvd_cac_dclk;
uint32_t uvd_cac_vclk;
uint32_t vce_cac_eclk;
uint32_t samu_cac_samclk;
uint32_t display_cac_dispclk;
uint32_t acp_cac_aclk;
uint32_t unb_cac;
uint32_t WinTime;
uint16_t GpuPwr_MAWt;
uint16_t FilteredVddcTotalPower;
uint8_t CalculationRepeats;
uint8_t WaterfallUp;
uint8_t WaterfallDown;
uint8_t WaterfallLimit;
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
// --------------------------------------------------------------------------------------------------
struct SMU7_ThermalScoreboard {
int16_t GpuLimit;
int16_t GpuHyst;
uint16_t CurrGnbTemp;
uint16_t FilteredGnbTemp;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint8_t WaterfallUp;
uint8_t WaterfallDown;
uint8_t WaterfallLimit;
uint8_t padding[3];
};
typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
// For FeatureEnables:
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
// All 'soft registers' should be uint32_t.
struct SMU71_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
#if defined (SMU__DGPU_ONLY)
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
#endif
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint8_t DPMFreezeAndForced;
uint8_t Activity_Weight;
uint8_t Reserved8[2];
uint32_t Reserved;
};
typedef struct SMU71_SoftRegisters SMU71_SoftRegisters;
struct SMU71_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t UvdDpmTable;
uint32_t AcpDpmTable;
uint32_t VceDpmTable;
uint32_t SamuDpmTable;
uint32_t UlvSettings;
uint32_t Reserved[37];
uint32_t Signature;
};
typedef struct SMU71_Firmware_Header SMU71_Firmware_Header;
struct SMU7_HystController_Data
{
uint8_t waterfall_up;
uint8_t waterfall_down;
uint8_t pstate;
uint8_t clamp_mode;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
#define SMU71_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
//#define SX_BLOCK_COUNT 8
//#define MC_BLOCK_COUNT 1
//#define CPL_BLOCK_COUNT 27
#if defined SMU__VARIANT__ICELAND
#define SX_BLOCK_COUNT 8
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 29
#endif
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT];
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h
+631
View File
@@ -0,0 +1,631 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU71_DISCRETE_H
#define SMU71_DISCRETE_H
#include "smu71.h"
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define VDDC_ON_SVI2 0x1
#define VDDCI_ON_SVI2 0x2
#define MVDD_ON_SVI2 0x4
struct SMU71_Discrete_VoltageLevel
{
uint16_t Voltage;
uint16_t StdVoltageHiSidd;
uint16_t StdVoltageLoSidd;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel;
struct SMU71_Discrete_GraphicsLevel
{
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t SclkFrequency;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
};
typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel;
struct SMU71_Discrete_ACPILevel
{
uint32_t Flags;
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CgSpllFuncCntl;
uint32_t CgSpllFuncCntl2;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
};
typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel;
struct SMU71_Discrete_Ulv
{
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint32_t Reserved;
};
typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv;
struct SMU71_Discrete_MemoryLevel
{
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t MinVddci;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t EdcReadEnable;
uint8_t EdcWriteEnable;
uint8_t RttEnable;
uint8_t StutterEnable;
uint8_t StrobeEnable;
uint8_t StrobeRatio;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t padding1;
uint32_t MpllFuncCntl;
uint32_t MpllFuncCntl_1;
uint32_t MpllFuncCntl_2;
uint32_t MpllAdFuncCntl;
uint32_t MpllDqFuncCntl;
uint32_t MclkPwrmgtCntl;
uint32_t DllCntl;
uint32_t MpllSs1;
uint32_t MpllSs2;
};
typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel;
struct SMU71_Discrete_LinkLevel
{
uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint32_t Reserved;
};
typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel;
#ifdef SMU__DYNAMIC_MCARB_SETTINGS
// MC ARB DRAM Timing registers.
struct SMU71_Discrete_MCArbDramTimingTableEntry
{
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t padding[3];
};
typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry;
struct SMU71_Discrete_MCArbDramTimingTable
{
SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable;
#endif
// UVD VCLK/DCLK state (level) definition.
struct SMU71_Discrete_UvdLevel
{
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint16_t MinVddc;
uint8_t MinVddcPhases;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[3];
};
typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel;
// Clocks for other external blocks (VCE, ACP, SAMU).
struct SMU71_Discrete_ExtClkLevel
{
uint32_t Frequency;
uint16_t MinVoltage;
uint8_t MinPhases;
uint8_t Divider;
};
typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel;
// Everything that we need to keep track of about the current state.
// Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
// that need to be checked later.
// We don't need to cache everything about a state, just a few parameters.
struct SMU71_Discrete_StateInfo
{
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo;
struct SMU71_Discrete_DpmTable
{
// Multi-DPM controller settings
SMU71_PIDController GraphicsPIDController;
SMU71_PIDController MemoryPIDController;
SMU71_PIDController LinkPIDController;
uint32_t SystemFlags;
// SMIO masks for voltage and phase controls
uint32_t SmioMaskVddcVid;
uint32_t SmioMaskVddcPhase;
uint32_t SmioMaskVddciVid;
uint32_t SmioMaskMvddVid;
uint32_t VddcLevelCount;
uint32_t VddciLevelCount;
uint32_t MvddLevelCount;
SMU71_Discrete_VoltageLevel VddcLevel [SMU71_MAX_LEVELS_VDDC];
SMU71_Discrete_VoltageLevel VddciLevel [SMU71_MAX_LEVELS_VDDCI];
SMU71_Discrete_VoltageLevel MvddLevel [SMU71_MAX_LEVELS_MVDD];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint32_t Reserved[5];
// State table entries for each DPM state
SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS];
SMU71_Discrete_MemoryLevel MemoryACPILevel;
SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY];
SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK];
SMU71_Discrete_ACPILevel ACPILevel;
uint32_t SclkStepSize;
uint32_t Smio [SMU71_MAX_ENTRIES_SMIO];
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint8_t MergedVddci;
uint8_t padding2;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint32_t DisplayCac;
uint16_t MaxPwr;
uint16_t NomPwr;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t BAPMTI_R [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
uint16_t BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
uint16_t BootVddc;
uint16_t BootVddci;
uint16_t BootMVdd;
uint16_t padding;
uint32_t BAPM_TEMP_GRADIENT;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
};
typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable;
// --------------------------------------------------- AC Timing Parameters ------------------------------------------------
#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY
struct SMU71_Discrete_MCRegisterAddress
{
uint16_t s0;
uint16_t s1;
};
typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress;
struct SMU71_Discrete_MCRegisterSet
{
uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet;
struct SMU71_Discrete_MCRegisters
{
uint8_t last;
uint8_t reserved[3];
SMU71_Discrete_MCRegisterAddress address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU71_Discrete_MCRegisterSet data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
};
typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters;
// --------------------------------------------------- Fan Table -----------------------------------------------------------
struct SMU71_Discrete_FanTable
{
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t Padding;
};
typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU71_MclkDpmScoreboard
{
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t TargetMclkIndex;
uint8_t TargetMvddIndex;
uint8_t MclkSwitchResult;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t MclkSwitchingTime;
uint8_t padding[2];
};
typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard;
struct SMU71_UlvScoreboard
{
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard;
struct SMU71_VddGfxScoreboard
{
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t padding[2];
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
};
typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard;
struct SMU71_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU71_Discrete_ACPILevel D0Level;
};
typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard;
struct SMU71_Discrete_PmFuses {
// dw0-dw1
uint8_t BapmVddCVidHiSidd[8];
// dw2-dw3
uint8_t BapmVddCVidLoSidd[8];
// dw4-dw5
uint8_t VddCVid[8];
// dw6
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
// dw7
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
// dw8
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
// dw9-dw12
uint8_t LPMLTemperatureScaler[16];
// dw13-dw14
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
// dw15
uint8_t GnbLPML[16];
// dw15
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
// dw16
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
};
typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses;
struct SMU71_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table;
struct SMU71_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl;
#if defined SMU__DGPU_ONLY
#define CAC_ACC_NW_NUM_OF_SIGNALS 83
#endif
struct SMU71_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
uint32_t filler[4];
};
typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table;
struct SMU71_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[8];
uint32_t temperature;
};
typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h
+687
View File
@@ -0,0 +1,687 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU72_H
#define SMU72_H
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8
enum SID_OPTION {
SID_OPTION_HI,
SID_OPTION_LO,
SID_OPTION_COUNT
};
enum Poly3rdOrderCoeff {
LEAKAGE_TEMPERATURE_SCALAR,
LEAKAGE_VOLTAGE_SCALAR,
DYNAMIC_VOLTAGE_SCALAR,
POLY_3RD_ORDER_COUNT
};
struct SMU7_Poly3rdOrder_Data {
int32_t a;
int32_t b;
int32_t c;
int32_t d;
uint8_t a_shift;
uint8_t b_shift;
uint8_t c_shift;
uint8_t x_shift;
};
typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
struct Power_Calculator_Data {
uint16_t NoLoadVoltage;
uint16_t LoadVoltage;
uint16_t Resistance;
uint16_t Temperature;
uint16_t BaseLeakage;
uint16_t LkgTempScalar;
uint16_t LkgVoltScalar;
uint16_t LkgAreaScalar;
uint16_t LkgPower;
uint16_t DynVoltScalar;
uint32_t Cac;
uint32_t DynPower;
uint32_t TotalCurrent;
uint32_t TotalPower;
};
typedef struct Power_Calculator_Data PowerCalculatorData_t;
struct Gc_Cac_Weight_Data {
uint8_t index;
uint32_t value;
};
typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU72_MAX_LEVELS_VDDC 16
#define SMU72_MAX_LEVELS_VDDGFX 16
#define SMU72_MAX_LEVELS_VDDCI 8
#define SMU72_MAX_LEVELS_MVDD 4
#define SMU_MAX_SMIO_LEVELS 4
#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */
#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */
#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */
#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */
#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */
#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
/* Virtualization Defines */
#define CG_XDMA_MASK 0x1
#define CG_XDMA_SHIFT 0
#define CG_UVD_MASK 0x2
#define CG_UVD_SHIFT 1
#define CG_VCE_MASK 0x4
#define CG_VCE_SHIFT 2
#define CG_SAMU_MASK 0x8
#define CG_SAMU_SHIFT 3
#define CG_GFX_MASK 0x10
#define CG_GFX_SHIFT 4
#define CG_SDMA_MASK 0x20
#define CG_SDMA_SHIFT 5
#define CG_HDP_MASK 0x40
#define CG_HDP_SHIFT 6
#define CG_MC_MASK 0x80
#define CG_MC_SHIFT 7
#define CG_DRM_MASK 0x100
#define CG_DRM_SHIFT 8
#define CG_ROM_MASK 0x200
#define CG_ROM_SHIFT 9
#define CG_BIF_MASK 0x400
#define CG_BIF_SHIFT 10
#define SMU72_DTE_ITERATIONS 5
#define SMU72_DTE_SOURCES 3
#define SMU72_DTE_SINKS 1
#define SMU72_NUM_CPU_TES 0
#define SMU72_NUM_GPU_TES 1
#define SMU72_NUM_NON_TES 2
#define SMU72_DTE_FAN_SCALAR_MIN 0x100
#define SMU72_DTE_FAN_SCALAR_MAX 0x166
#define SMU72_DTE_FAN_TEMP_MAX 93
#define SMU72_DTE_FAN_TEMP_MIN 83
#if defined SMU__FUSION_ONLY
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
#endif
struct SMU7_HystController_Data {
uint8_t waterfall_up;
uint8_t waterfall_down;
uint8_t waterfall_limit;
uint8_t spare;
uint16_t release_cnt;
uint16_t release_limit;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
struct SMU72_PIDController {
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU72_PIDController SMU72_PIDController;
struct SMU7_LocalDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
uint8_t FpsFilterWeight;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
uint32_t FilteredSclkFrequency;
uint32_t LastSclkFrequency;
uint32_t FilteredSclkFrequencyCnt;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
struct SMU_VoltageLevel {
uint8_t Vddc;
uint8_t Vddci;
uint8_t VddGfx;
uint8_t Phases;
};
typedef struct SMU_VoltageLevel SMU_VoltageLevel;
struct SMU7_VoltageScoreboard {
SMU_VoltageLevel CurrentVoltage;
SMU_VoltageLevel TargetVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint8_t CurrentVddciVid;
uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t TargetIndex;
uint8_t Delay;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
uint8_t OverrideVoltage;
uint8_t VddcUseUlvOffset;
uint8_t VddGfxUseUlvOffset;
uint8_t padding;
VoltageChangeHandler_t ChangeVddc;
VoltageChangeHandler_t ChangeVddGfx;
VoltageChangeHandler_t ChangeVddci;
VoltageChangeHandler_t ChangePhase;
VoltageChangeHandler_t ChangeMvdd;
VoltageChangeHandler_t functionLinks[6];
uint8_t *VddcFollower1;
uint8_t *VddcFollower2;
int16_t Driver_OD_RequestedVidOffset1;
int16_t Driver_OD_RequestedVidOffset2;
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
struct SMU7_PCIeLinkSpeedScoreboard {
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
/* -------------------------------------------------------- CAC table ------------------------------------------------------ */
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard {
PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
uint32_t TotalGpuPower;
uint32_t TdcCurrent;
uint16_t VddciTotalPower;
uint16_t sparesasfsdfd;
uint16_t Vddr1Power;
uint16_t RocPower;
uint16_t CalcMeasPowerBlend;
uint8_t SidOptionPower;
uint8_t SidOptionCurrent;
uint32_t WinTime;
uint16_t Telemetry_1_slope;
uint16_t Telemetry_2_slope;
int32_t Telemetry_1_offset;
int32_t Telemetry_2_offset;
uint32_t VddcCurrentTelemetry;
uint32_t VddGfxCurrentTelemetry;
uint32_t VddcPowerTelemetry;
uint32_t VddGfxPowerTelemetry;
uint32_t VddciPowerTelemetry;
uint32_t VddcPower;
uint32_t VddGfxPower;
uint32_t VddciPower;
uint32_t TelemetryCurrent[2];
uint32_t TelemetryVoltage[2];
uint32_t TelemetryPower[2];
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
struct SMU7_ThermalScoreboard {
int16_t GpuLimit;
int16_t GpuHyst;
uint16_t CurrGnbTemp;
uint16_t FilteredGnbTemp;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint8_t AutoTmonCalInterval;
uint8_t AutoTmonCalEnable;
uint8_t ThermalDpmEnabled;
uint8_t SclkEnabledMask;
uint8_t spare[2];
int32_t temperature_gradient;
SMU7_HystController_Data HystControllerData;
int32_t WeightedSensorTemperature;
uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
uint32_t Alpha;
};
typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
/* For FeatureEnables: */
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
/* All 'soft registers' should be uint32_t. */
struct SMU72_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint32_t Reserved[2];
};
typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
struct SMU72_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t ClockStretcherTable;
uint32_t Reserved[41];
uint32_t Signature;
};
typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 5
#define SE_BLOCK_COUNT 15
#define GC_BLOCK_COUNT 24
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
/* Description of Clock Gating bitmask for Tonga: */
/* System Clock Gating */
#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */
#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */
#define CG_SYS_BIF_MGLS_SHIFT 0
#define CG_SYS_ROM_SHIFT 1
#define CG_SYS_MC_MGCG_SHIFT 2
#define CG_SYS_MC_MGLS_SHIFT 3
#define CG_SYS_SDMA_MGCG_SHIFT 4
#define CG_SYS_SDMA_MGLS_SHIFT 5
#define CG_SYS_DRM_MGCG_SHIFT 6
#define CG_SYS_HDP_MGCG_SHIFT 7
#define CG_SYS_HDP_MGLS_SHIFT 8
#define CG_SYS_DRM_MGLS_SHIFT 9
#define CG_SYS_BIF_MGLS_MASK 0x1
#define CG_SYS_ROM_MASK 0x2
#define CG_SYS_MC_MGCG_MASK 0x4
#define CG_SYS_MC_MGLS_MASK 0x8
#define CG_SYS_SDMA_MGCG_MASK 0x10
#define CG_SYS_SDMA_MGLS_MASK 0x20
#define CG_SYS_DRM_MGCG_MASK 0x40
#define CG_SYS_HDP_MGCG_MASK 0x80
#define CG_SYS_HDP_MGLS_MASK 0x100
#define CG_SYS_DRM_MGLS_MASK 0x200
/* Graphics Clock Gating */
#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */
#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */
#define CG_GFX_CGCG_SHIFT 16
#define CG_GFX_CGLS_SHIFT 17
#define CG_CPF_MGCG_SHIFT 18
#define CG_RLC_MGCG_SHIFT 19
#define CG_GFX_OTHERS_MGCG_SHIFT 20
#define CG_GFX_CGCG_MASK 0x00010000
#define CG_GFX_CGLS_MASK 0x00020000
#define CG_CPF_MGCG_MASK 0x00040000
#define CG_RLC_MGCG_MASK 0x00080000
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
/* Voltage Regulator Configuration */
/* VR Config info is contained in dpmTable.VRConfig */
#define VRCONF_VDDC_MASK 0x000000FF
#define VRCONF_VDDC_SHIFT 0
#define VRCONF_VDDGFX_MASK 0x0000FF00
#define VRCONF_VDDGFX_SHIFT 8
#define VRCONF_VDDCI_MASK 0x00FF0000
#define VRCONF_VDDCI_SHIFT 16
#define VRCONF_MVDD_MASK 0xFF000000
#define VRCONF_MVDD_SHIFT 24
#define VR_MERGED_WITH_VDDC 0
#define VR_SVI2_PLANE_1 1
#define VR_SVI2_PLANE_2 2
#define VR_SMIO_PATTERN_1 3
#define VR_SMIO_PATTERN_2 4
#define VR_STATIC_VOLTAGE 5
/* Clock Stretcher Configuration */
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
/* The 'settings' field is subdivided in the following way: */
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
struct SMU_ClockStretcherDataTableEntry {
uint8_t minVID;
uint8_t maxVID;
uint16_t setting;
};
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
struct SMU_ClockStretcherDataTable {
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
};
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
struct SMU_CKS_LOOKUPTableEntry {
uint16_t minFreq;
uint16_t maxFreq;
uint8_t setting;
uint8_t padding[3];
};
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
struct SMU_CKS_LOOKUPTable {
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
};
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h
+783
View File
@@ -0,0 +1,783 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU72_DISCRETE_H
#define SMU72_DISCRETE_H
#include "smu72.h"
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
struct SMIO_Pattern {
uint16_t Voltage;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMIO_Pattern SMIO_Pattern;
struct SMIO_Table {
SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};
typedef struct SMIO_Table SMIO_Table;
struct SMU72_Discrete_GraphicsLevel {
SMU_VoltageLevel MinVoltage;
uint32_t SclkFrequency;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
};
typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
struct SMU72_Discrete_ACPILevel {
uint32_t Flags;
SMU_VoltageLevel MinVoltage;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CgSpllFuncCntl;
uint32_t CgSpllFuncCntl2;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
};
typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
struct SMU72_Discrete_Ulv {
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint32_t Reserved;
};
typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
struct SMU72_Discrete_MemoryLevel {
SMU_VoltageLevel MinVoltage;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t EdcReadEnable;
uint8_t EdcWriteEnable;
uint8_t RttEnable;
uint8_t StutterEnable;
uint8_t StrobeEnable;
uint8_t StrobeRatio;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t padding1;
uint32_t MpllFuncCntl;
uint32_t MpllFuncCntl_1;
uint32_t MpllFuncCntl_2;
uint32_t MpllAdFuncCntl;
uint32_t MpllDqFuncCntl;
uint32_t MclkPwrmgtCntl;
uint32_t DllCntl;
uint32_t MpllSs1;
uint32_t MpllSs2;
};
typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
struct SMU72_Discrete_LinkLevel {
uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint32_t Reserved;
};
typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
/* MC ARB DRAM Timing registers. */
struct SMU72_Discrete_MCArbDramTimingTableEntry {
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t padding[3];
};
typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
struct SMU72_Discrete_MCArbDramTimingTable {
SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
/* UVD VCLK/DCLK state (level) definition. */
struct SMU72_Discrete_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
SMU_VoltageLevel MinVoltage;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[2];
};
typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
/* Clocks for other external blocks (VCE, ACP, SAMU). */
struct SMU72_Discrete_ExtClkLevel {
uint32_t Frequency;
SMU_VoltageLevel MinVoltage;
uint8_t Divider;
uint8_t padding[3];
};
typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
struct SMU72_Discrete_StateInfo {
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
struct SMU72_Discrete_DpmTable {
/* Multi-DPM controller settings */
SMU72_PIDController GraphicsPIDController;
SMU72_PIDController MemoryPIDController;
SMU72_PIDController LinkPIDController;
uint32_t SystemFlags;
/* SMIO masks for voltage and phase controls */
uint32_t VRConfig;
uint32_t SmioMask1;
uint32_t SmioMask2;
SMIO_Table SmioTable1;
SMIO_Table SmioTable2;
uint32_t VddcLevelCount;
uint32_t VddciLevelCount;
uint32_t VddGfxLevelCount;
uint32_t MvddLevelCount;
uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC];
uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI];
uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t ThermOutGpio;
uint8_t ThermOutPolarity;
uint8_t ThermOutMode;
uint8_t DPMFreezeAndForced;
uint32_t Reserved[4];
/* State table entries for each DPM state */
SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
SMU72_Discrete_MemoryLevel MemoryACPILevel;
SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK];
SMU72_Discrete_ACPILevel ACPILevel;
SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD];
SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE];
SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP];
SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU];
SMU72_Discrete_Ulv Ulv;
uint32_t SclkStepSize;
uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint16_t BootMVdd;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
SMU_VoltageLevel BootVoltage;
uint32_t BAPM_TEMP_GRADIENT;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint8_t ClockStretcherAmount;
uint8_t Sclk_CKS_masterEn0_7;
uint8_t Sclk_CKS_masterEn8_15;
uint8_t padding[1];
uint8_t Sclk_voltageOffset[8];
SMU_ClockStretcherDataTable ClockStretcherDataTable;
SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
};
typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
struct SMU72_Discrete_MCRegisterAddress {
uint16_t s0;
uint16_t s1;
};
typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
struct SMU72_Discrete_MCRegisterSet {
uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
struct SMU72_Discrete_MCRegisters {
uint8_t last;
uint8_t reserved[3];
SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
};
typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
struct SMU72_Discrete_FanTable {
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t FanControl_GL_Flag;
};
typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU7_MclkDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t IgnoreVBlank;
uint8_t TargetMclkIndex;
uint8_t TargetMvddIndex;
uint8_t MclkSwitchResult;
uint16_t VbiFailureCount;
uint8_t VbiWaitCounter;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t VbiTimeoutCount;
uint16_t MclkSwitchingTime;
uint8_t fastSwitch;
uint8_t Save_PIC_VDDGFX_EXIT;
uint8_t Save_PIC_VDDGFX_ENTER;
uint8_t padding;
};
typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
struct SMU7_UlvScoreboard {
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
struct VddgfxSavedRegisters {
uint32_t GPU_DBG[3];
uint32_t MEC_BaseAddress_Hi;
uint32_t MEC_BaseAddress_Lo;
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
uint32_t CP_INT_CNTL;
};
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
struct SMU7_VddGfxScoreboard {
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t VPUResetOccured;
uint8_t padding;
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
uint32_t VddGfxVid;
VddgfxSavedRegisters SavedRegisters;
};
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
struct SMU7_TdcLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredIddc;
uint32_t IddcLimit;
uint32_t IddcHyst;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
struct SMU7_PkgPwrLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredPkgPwr;
uint32_t Limit;
uint32_t Hyst;
uint32_t LimitFromDriver;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
struct SMU7_BapmScoreboard {
uint32_t source_powers[SMU72_DTE_SOURCES];
uint32_t source_powers_last[SMU72_DTE_SOURCES];
int32_t entity_temperatures[SMU72_NUM_GPU_TES];
int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
int32_t Limit;
int32_t Hyst;
int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
uint16_t ConfigTDPPowerScalar;
uint16_t FanSpeedPowerScalar;
uint16_t OverDrivePowerScalar;
uint16_t OverDriveLimitScalar;
uint16_t FinalPowerScalar;
uint8_t VariantID;
uint8_t spare997;
SMU7_HystController_Data HystControllerData;
int32_t temperature_gradient_slope;
int32_t temperature_gradient;
uint32_t measured_temperature;
};
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
struct SMU7_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU72_Discrete_ACPILevel D0Level;
};
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
struct SMU72_Discrete_PmFuses {
/* dw1 */
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
/* dw2 */
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
/* dw3 */
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
/* dw4-dw7 */
uint8_t LPMLTemperatureScaler[16];
/* dw8-dw9 */
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
/* dw10-dw14 */
uint8_t GnbLPML[16];
/* dw15 */
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
/* dw16 */
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
};
typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
struct SMU7_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
struct SMU7_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
struct SMU7_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
};
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
struct SMU7_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[4];
uint32_t temperature;
};
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
struct SMU7_Discrete_Pm_Status_Table {
/* Thermal entities */
int32_t T_meas_max;
int32_t T_meas_acc;
int32_t T_calc_max;
int32_t T_calc_acc;
uint32_t P_scalar_acc;
uint32_t P_calc_max;
uint32_t P_calc_acc;
/*Voltage domains */
uint32_t I_calc_max;
uint32_t I_calc_acc;
uint32_t I_calc_acc_vddci;
uint32_t V_calc_noload_acc;
uint32_t V_calc_load_acc;
uint32_t V_calc_noload_acc_vddci;
uint32_t P_meas_acc;
uint32_t V_meas_noload_acc;
uint32_t V_meas_load_acc;
uint32_t I_meas_acc;
uint32_t P_meas_acc_vddci;
uint32_t V_meas_noload_acc_vddci;
uint32_t V_meas_load_acc_vddci;
uint32_t I_meas_acc_vddci;
/*Frequency */
uint16_t Sclk_dpm_residency[8];
uint16_t Uvd_dpm_residency[8];
uint16_t Vce_dpm_residency[8];
uint16_t Mclk_dpm_residency[4];
/*Chip */
uint32_t P_vddci_acc;
uint32_t P_vddr1_acc;
uint32_t P_nte1_acc;
uint32_t PkgPwr_max;
uint32_t PkgPwr_acc;
uint32_t MclkSwitchingTime_max;
uint32_t MclkSwitchingTime_acc;
uint32_t FanPwm_acc;
uint32_t FanRpm_acc;
uint32_t AccCnt;
};
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
/*FIXME THESE NEED TO BE UPDATED */
#define SMU7_SCLK_CAC 0x561
#define SMU7_MCLK_CAC 0xF9
#define SMU7_VCLK_CAC 0x2DE
#define SMU7_DCLK_CAC 0x2DE
#define SMU7_ECLK_CAC 0x25E
#define SMU7_ACLK_CAC 0x25E
#define SMU7_SAMCLK_CAC 0x25E
#define SMU7_DISPCLK_CAC 0x100
#define SMU7_CAC_CONSTANT 0x2EE3430
#define SMU7_CAC_CONSTANT_SHIFT 18
#define SMU7_VDDCI_MCLK_CONST 1765
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
#define SMU7_VDDCI_VDDCI_CONST 50958
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
#define SMU7_VDDCI_CONST 11781
#define SMU7_12C_VDDCI_MCLK_CONST 1623
#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15
#define SMU7_12C_VDDCI_VDDCI_CONST 40088
#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
#define SMU7_12C_VDDCI_CONST 20856
#define SMU7_VDDCI_STROBE_PWR 1331
#define SMU7_VDDR1_CONST 693
#define SMU7_VDDR1_CAC_WEIGHT 20
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
#define SMU7_VDDR1_STROBE_PWR 512
#define SMU7_AREA_COEFF_UVD 0xA78
#define SMU7_AREA_COEFF_VCE 0x190A
#define SMU7_AREA_COEFF_ACP 0x22D1
#define SMU7_AREA_COEFF_SAMU 0x534
/*ThermOutMode values */
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h
+709
View File
@@ -0,0 +1,709 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _SMU73_H_
#define _SMU73_H_
#pragma pack(push, 1)
enum SID_OPTION {
SID_OPTION_HI,
SID_OPTION_LO,
SID_OPTION_COUNT
};
enum Poly3rdOrderCoeff {
LEAKAGE_TEMPERATURE_SCALAR,
LEAKAGE_VOLTAGE_SCALAR,
DYNAMIC_VOLTAGE_SCALAR,
POLY_3RD_ORDER_COUNT
};
struct SMU7_Poly3rdOrder_Data {
int32_t a;
int32_t b;
int32_t c;
int32_t d;
uint8_t a_shift;
uint8_t b_shift;
uint8_t c_shift;
uint8_t x_shift;
};
typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
struct Power_Calculator_Data {
uint16_t NoLoadVoltage;
uint16_t LoadVoltage;
uint16_t Resistance;
uint16_t Temperature;
uint16_t BaseLeakage;
uint16_t LkgTempScalar;
uint16_t LkgVoltScalar;
uint16_t LkgAreaScalar;
uint16_t LkgPower;
uint16_t DynVoltScalar;
uint32_t Cac;
uint32_t DynPower;
uint32_t TotalCurrent;
uint32_t TotalPower;
};
typedef struct Power_Calculator_Data PowerCalculatorData_t;
struct Gc_Cac_Weight_Data {
uint8_t index;
uint32_t value;
};
typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU73_MAX_LEVELS_VDDC 16
#define SMU73_MAX_LEVELS_VDDGFX 16
#define SMU73_MAX_LEVELS_VDDCI 8
#define SMU73_MAX_LEVELS_MVDD 4
#define SMU_MAX_SMIO_LEVELS 4
#define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
#define SMU73_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM
#define SMU73_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels
#define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
#define SMU73_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD.
#define SMU73_MAX_LEVELS_VCE 8 // ECLK levels for VCE.
#define SMU73_MAX_LEVELS_ACP 8 // ACLK levels for ACP.
#define SMU73_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU.
#define SMU73_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table.
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
// Virtualization Defines
#define CG_XDMA_MASK 0x1
#define CG_XDMA_SHIFT 0
#define CG_UVD_MASK 0x2
#define CG_UVD_SHIFT 1
#define CG_VCE_MASK 0x4
#define CG_VCE_SHIFT 2
#define CG_SAMU_MASK 0x8
#define CG_SAMU_SHIFT 3
#define CG_GFX_MASK 0x10
#define CG_GFX_SHIFT 4
#define CG_SDMA_MASK 0x20
#define CG_SDMA_SHIFT 5
#define CG_HDP_MASK 0x40
#define CG_HDP_SHIFT 6
#define CG_MC_MASK 0x80
#define CG_MC_SHIFT 7
#define CG_DRM_MASK 0x100
#define CG_DRM_SHIFT 8
#define CG_ROM_MASK 0x200
#define CG_ROM_SHIFT 9
#define CG_BIF_MASK 0x400
#define CG_BIF_SHIFT 10
#define SMU73_DTE_ITERATIONS 5
#define SMU73_DTE_SOURCES 3
#define SMU73_DTE_SINKS 1
#define SMU73_NUM_CPU_TES 0
#define SMU73_NUM_GPU_TES 1
#define SMU73_NUM_NON_TES 2
#define SMU73_DTE_FAN_SCALAR_MIN 0x100
#define SMU73_DTE_FAN_SCALAR_MAX 0x166
#define SMU73_DTE_FAN_TEMP_MAX 93
#define SMU73_DTE_FAN_TEMP_MIN 83
#define SMU73_THERMAL_INPUT_LOOP_COUNT 6
#define SMU73_THERMAL_CLAMP_MODE_COUNT 8
struct SMU7_HystController_Data {
uint16_t waterfall_up;
uint16_t waterfall_down;
uint16_t waterfall_limit;
uint16_t release_cnt;
uint16_t release_limit;
uint16_t spare;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
struct SMU73_PIDController {
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU73_PIDController SMU73_PIDController;
struct SMU7_LocalDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode;
uint8_t spare2;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters[SMU73_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters[SMU73_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
uint32_t FilteredSclkFrequency;
uint32_t LastSclkFrequency;
uint32_t FilteredSclkFrequencyCnt;
uint8_t LedEnable;
uint8_t LedPin0;
uint8_t LedPin1;
uint8_t LedPin2;
uint32_t LedAndMask;
uint16_t FpsAlpha;
uint16_t DeltaTime;
uint32_t CurrentFps;
uint32_t FilteredFps;
uint32_t FrameCount;
uint32_t FrameCountLast;
uint16_t FpsTargetScalar;
uint16_t FpsWaterfallLimitScalar;
uint16_t FpsAlphaScalar;
uint16_t spare8;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
#define VDDC_MASK 0x00007FFF
#define VDDC_SHIFT 0
#define VDDCI_MASK 0x3FFF8000
#define VDDCI_SHIFT 15
#define PHASES_MASK 0xC0000000
#define PHASES_SHIFT 30
typedef uint32_t SMU_VoltageLevel;
struct SMU7_VoltageScoreboard {
SMU_VoltageLevel TargetVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
uint16_t CurrentVddc;
uint16_t CurrentVddci;
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint8_t CurrentVddciVid;
uint8_t padding;
SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
SMU_VoltageLevel TargetVoltageState;
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t padding2;
uint8_t padding3;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
uint8_t OverrideVoltage;
uint8_t padding4;
uint8_t padding5;
uint8_t CurrentPhases;
VoltageChangeHandler_t ChangeVddc;
VoltageChangeHandler_t ChangeVddci;
VoltageChangeHandler_t ChangePhase;
VoltageChangeHandler_t ChangeMvdd;
VoltageChangeHandler_t functionLinks[6];
uint16_t *VddcFollower1;
int16_t Driver_OD_RequestedVidOffset1;
int16_t Driver_OD_RequestedVidOffset2;
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
// -------------------------------------------------------------------------------------------------------------------------
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
struct SMU7_PCIeLinkSpeedScoreboard {
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
// -------------------------------------------------------- CAC table ------------------------------------------------------
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard {
uint32_t GpuPower;
uint32_t VddcPower;
uint32_t VddcVoltage;
uint32_t VddcCurrent;
uint32_t MvddPower;
uint32_t MvddVoltage;
uint32_t MvddCurrent;
uint32_t RocPower;
uint16_t Telemetry_1_slope;
uint16_t Telemetry_2_slope;
int32_t Telemetry_1_offset;
int32_t Telemetry_2_offset;
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
// For FeatureEnables:
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
// All 'soft registers' should be uint32_t.
struct SMU73_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint32_t Reserved[2];
};
typedef struct SMU73_SoftRegisters SMU73_SoftRegisters;
struct SMU73_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t ClockStretcherTable;
uint32_t Reserved[41];
uint32_t Signature;
};
typedef struct SMU73_Firmware_Header SMU73_Firmware_Header;
#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 5
#define SE_BLOCK_COUNT 15
#define GC_BLOCK_COUNT 24
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
// Description of Clock Gating bitmask for Tonga:
// System Clock Gating
#define CG_SYS_BITMASK_FIRST_BIT 0 // First bit of Sys CG bitmask
#define CG_SYS_BITMASK_LAST_BIT 9 // Last bit of Sys CG bitmask
#define CG_SYS_BIF_MGLS_SHIFT 0
#define CG_SYS_ROM_SHIFT 1
#define CG_SYS_MC_MGCG_SHIFT 2
#define CG_SYS_MC_MGLS_SHIFT 3
#define CG_SYS_SDMA_MGCG_SHIFT 4
#define CG_SYS_SDMA_MGLS_SHIFT 5
#define CG_SYS_DRM_MGCG_SHIFT 6
#define CG_SYS_HDP_MGCG_SHIFT 7
#define CG_SYS_HDP_MGLS_SHIFT 8
#define CG_SYS_DRM_MGLS_SHIFT 9
#define CG_SYS_BIF_MGLS_MASK 0x1
#define CG_SYS_ROM_MASK 0x2
#define CG_SYS_MC_MGCG_MASK 0x4
#define CG_SYS_MC_MGLS_MASK 0x8
#define CG_SYS_SDMA_MGCG_MASK 0x10
#define CG_SYS_SDMA_MGLS_MASK 0x20
#define CG_SYS_DRM_MGCG_MASK 0x40
#define CG_SYS_HDP_MGCG_MASK 0x80
#define CG_SYS_HDP_MGLS_MASK 0x100
#define CG_SYS_DRM_MGLS_MASK 0x200
// Graphics Clock Gating
#define CG_GFX_BITMASK_FIRST_BIT 16 // First bit of Gfx CG bitmask
#define CG_GFX_BITMASK_LAST_BIT 20 // Last bit of Gfx CG bitmask
#define CG_GFX_CGCG_SHIFT 16
#define CG_GFX_CGLS_SHIFT 17
#define CG_CPF_MGCG_SHIFT 18
#define CG_RLC_MGCG_SHIFT 19
#define CG_GFX_OTHERS_MGCG_SHIFT 20
#define CG_GFX_CGCG_MASK 0x00010000
#define CG_GFX_CGLS_MASK 0x00020000
#define CG_CPF_MGCG_MASK 0x00040000
#define CG_RLC_MGCG_MASK 0x00080000
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
// Voltage Regulator Configuration
// VR Config info is contained in dpmTable.VRConfig
#define VRCONF_VDDC_MASK 0x000000FF
#define VRCONF_VDDC_SHIFT 0
#define VRCONF_VDDGFX_MASK 0x0000FF00
#define VRCONF_VDDGFX_SHIFT 8
#define VRCONF_VDDCI_MASK 0x00FF0000
#define VRCONF_VDDCI_SHIFT 16
#define VRCONF_MVDD_MASK 0xFF000000
#define VRCONF_MVDD_SHIFT 24
#define VR_MERGED_WITH_VDDC 0
#define VR_SVI2_PLANE_1 1
#define VR_SVI2_PLANE_2 2
#define VR_SMIO_PATTERN_1 3
#define VR_SMIO_PATTERN_2 4
#define VR_STATIC_VOLTAGE 5
// Clock Stretcher Configuration
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
// The 'settings' field is subdivided in the following way:
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
struct SMU_ClockStretcherDataTableEntry {
uint8_t minVID;
uint8_t maxVID;
uint16_t setting;
};
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
struct SMU_ClockStretcherDataTable {
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
};
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
struct SMU_CKS_LOOKUPTableEntry {
uint16_t minFreq;
uint16_t maxFreq;
uint8_t setting;
uint8_t padding[3];
};
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
struct SMU_CKS_LOOKUPTable {
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
};
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
struct AgmAvfsData_t {
uint16_t avgPsmCount[28];
uint16_t minPsmCount[28];
};
typedef struct AgmAvfsData_t AgmAvfsData_t;
// AVFS DEFINES
enum VFT_COLUMNS {
SCLK0,
SCLK1,
SCLK2,
SCLK3,
SCLK4,
SCLK5,
SCLK6,
SCLK7,
NUM_VFT_COLUMNS
};
#define TEMP_RANGE_MAXSTEPS 12
struct VFT_CELL_t {
uint16_t Voltage;
};
typedef struct VFT_CELL_t VFT_CELL_t;
struct VFT_TABLE_t {
VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
uint16_t AvfsGbv[NUM_VFT_COLUMNS];
uint16_t BtcGbv[NUM_VFT_COLUMNS];
uint16_t Temperature[TEMP_RANGE_MAXSTEPS];
uint8_t NumTemperatureSteps;
uint8_t padding[3];
};
typedef struct VFT_TABLE_t VFT_TABLE_t;
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h
+784
View File
@@ -0,0 +1,784 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _SMU73_DISCRETE_H_
#define _SMU73_DISCRETE_H_
#include "smu73.h"
#pragma pack(push, 1)
struct SMIO_Pattern {
uint16_t Voltage;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMIO_Pattern SMIO_Pattern;
struct SMIO_Table {
SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};
typedef struct SMIO_Table SMIO_Table;
struct SMU73_Discrete_GraphicsLevel {
uint32_t MinVoltage;
uint32_t SclkFrequency;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
};
typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel;
struct SMU73_Discrete_ACPILevel {
uint32_t Flags;
uint32_t MinVoltage;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CgSpllFuncCntl;
uint32_t CgSpllFuncCntl2;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
};
typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel;
struct SMU73_Discrete_Ulv {
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint32_t Reserved;
};
typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv;
struct SMU73_Discrete_MemoryLevel {
uint32_t MinVoltage;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t StutterEnable;
uint8_t FreqRange;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t MclkDivider;
};
typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel;
struct SMU73_Discrete_LinkLevel {
uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint32_t Reserved;
};
typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel;
// MC ARB DRAM Timing registers.
struct SMU73_Discrete_MCArbDramTimingTableEntry {
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t TRRDS;
uint8_t TRRDL;
uint8_t padding;
};
typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry;
struct SMU73_Discrete_MCArbDramTimingTable {
SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable;
// UVD VCLK/DCLK state (level) definition.
struct SMU73_Discrete_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t MinVoltage;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[2];
};
typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel;
// Clocks for other external blocks (VCE, ACP, SAMU).
struct SMU73_Discrete_ExtClkLevel {
uint32_t Frequency;
uint32_t MinVoltage;
uint8_t Divider;
uint8_t padding[3];
};
typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel;
struct SMU73_Discrete_StateInfo {
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo;
struct SMU73_Discrete_DpmTable {
// Multi-DPM controller settings
SMU73_PIDController GraphicsPIDController;
SMU73_PIDController MemoryPIDController;
SMU73_PIDController LinkPIDController;
uint32_t SystemFlags;
// SMIO masks for voltage and phase controls
uint32_t VRConfig;
uint32_t SmioMask1;
uint32_t SmioMask2;
SMIO_Table SmioTable1;
SMIO_Table SmioTable2;
uint32_t MvddLevelCount;
uint8_t BapmVddcVidHiSidd[SMU73_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidLoSidd[SMU73_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidHiSidd2[SMU73_MAX_LEVELS_VDDC];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t ThermOutGpio;
uint8_t ThermOutPolarity;
uint8_t ThermOutMode;
uint8_t BootPhases;
uint32_t Reserved[4];
// State table entries for each DPM state
SMU73_Discrete_GraphicsLevel GraphicsLevel[SMU73_MAX_LEVELS_GRAPHICS];
SMU73_Discrete_MemoryLevel MemoryACPILevel;
SMU73_Discrete_MemoryLevel MemoryLevel[SMU73_MAX_LEVELS_MEMORY];
SMU73_Discrete_LinkLevel LinkLevel[SMU73_MAX_LEVELS_LINK];
SMU73_Discrete_ACPILevel ACPILevel;
SMU73_Discrete_UvdLevel UvdLevel[SMU73_MAX_LEVELS_UVD];
SMU73_Discrete_ExtClkLevel VceLevel[SMU73_MAX_LEVELS_VCE];
SMU73_Discrete_ExtClkLevel AcpLevel[SMU73_MAX_LEVELS_ACP];
SMU73_Discrete_ExtClkLevel SamuLevel[SMU73_MAX_LEVELS_SAMU];
SMU73_Discrete_Ulv Ulv;
uint32_t SclkStepSize;
uint32_t Smio[SMU73_MAX_ENTRIES_SMIO];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint16_t BootMVdd;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t TemperatureLimitEdge;
uint16_t TemperatureLimitHotspot;
uint16_t TemperatureLimitLiquid1;
uint16_t TemperatureLimitLiquid2;
uint16_t TemperatureLimitVrVddc;
uint16_t TemperatureLimitVrMvdd;
uint16_t TemperatureLimitPlx;
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint16_t FanGainLiquid;
uint16_t FanGainVrVddc;
uint16_t FanGainVrMvdd;
uint16_t FanGainPlx;
uint16_t FanGainHbm;
uint8_t Liquid1_I2C_address;
uint8_t Liquid2_I2C_address;
uint8_t Vr_I2C_address;
uint8_t Plx_I2C_address;
uint8_t GeminiMode;
uint8_t spare17[3];
uint32_t GeminiApertureHigh;
uint32_t GeminiApertureLow;
uint8_t Liquid_I2C_LineSCL;
uint8_t Liquid_I2C_LineSDA;
uint8_t Vr_I2C_LineSCL;
uint8_t Vr_I2C_LineSDA;
uint8_t Plx_I2C_LineSCL;
uint8_t Plx_I2C_LineSDA;
uint8_t spare1253[2];
uint32_t spare123[2];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
uint16_t BootVddc;
uint16_t BootVddci;
uint32_t BAPM_TEMP_GRADIENT;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint8_t ClockStretcherAmount;
uint8_t Sclk_CKS_masterEn0_7;
uint8_t Sclk_CKS_masterEn8_15;
uint8_t DPMFreezeAndForced;
uint8_t Sclk_voltageOffset[8];
SMU_ClockStretcherDataTable ClockStretcherDataTable;
SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
};
typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;
// --------------------------------------------------- Fan Table -----------------------------------------------------------
struct SMU73_Discrete_FanTable {
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t Padding;
};
typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU7_MclkDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t IgnoreVBlank;
uint8_t TargetMclkIndex;
uint8_t TargetMvddIndex;
uint8_t MclkSwitchResult;
uint16_t VbiFailureCount;
uint8_t VbiWaitCounter;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCounters[SMU73_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters[SMU73_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t VbiTimeoutCount;
uint16_t MclkSwitchingTime;
uint8_t fastSwitch;
uint8_t Save_PIC_VDDGFX_EXIT;
uint8_t Save_PIC_VDDGFX_ENTER;
uint8_t padding;
};
typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
struct SMU7_UlvScoreboard {
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
struct VddgfxSavedRegisters {
uint32_t GPU_DBG[3];
uint32_t MEC_BaseAddress_Hi;
uint32_t MEC_BaseAddress_Lo;
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
uint32_t CP_INT_CNTL;
};
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
struct SMU7_VddGfxScoreboard {
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t VPUResetOccured;
uint8_t padding;
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
uint32_t VddGfxVid;
VddgfxSavedRegisters SavedRegisters;
};
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
struct SMU7_TdcLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredIddc;
uint32_t IddcLimit;
uint32_t IddcHyst;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
struct SMU7_PkgPwrLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredPkgPwr;
uint32_t Limit;
uint32_t Hyst;
uint32_t LimitFromDriver;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
struct SMU7_BapmScoreboard {
uint32_t source_powers[SMU73_DTE_SOURCES];
uint32_t source_powers_last[SMU73_DTE_SOURCES];
int32_t entity_temperatures[SMU73_NUM_GPU_TES];
int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES];
int32_t Limit;
int32_t Hyst;
int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2];
int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS];
uint16_t ConfigTDPPowerScalar;
uint16_t FanSpeedPowerScalar;
uint16_t OverDrivePowerScalar;
uint16_t OverDriveLimitScalar;
uint16_t FinalPowerScalar;
uint8_t VariantID;
uint8_t spare997;
SMU7_HystController_Data HystControllerData;
int32_t temperature_gradient_slope;
int32_t temperature_gradient;
uint32_t measured_temperature;
};
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
struct SMU7_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU73_Discrete_ACPILevel D0Level;
};
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
struct SMU_QuadraticCoeffs {
int32_t m1;
uint32_t b;
int16_t m2;
uint8_t m1_shift;
uint8_t m2_shift;
};
typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
struct SMU73_Discrete_PmFuses {
/* dw0-dw1 */
uint8_t BapmVddCVidHiSidd[8];
/* dw2-dw3 */
uint8_t BapmVddCVidLoSidd[8];
/* dw4-dw5 */
uint8_t VddCVid[8];
/* dw1*/
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
/* dw2 */
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
/* dw3 */
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
/* dw4-dw7 */
uint8_t LPMLTemperatureScaler[16];
/* dw8-dw9 */
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
/* dw10-dw14 */
uint8_t GnbLPML[16];
/* dw15 */
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
/* dw16 */
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
/* AVFS */
uint16_t VFT_Temp[3];
uint16_t padding;
SMU_QuadraticCoeffs VFT_ATE[3];
SMU_QuadraticCoeffs AVFS_GB;
SMU_QuadraticCoeffs ATE_ACBTC_GB;
SMU_QuadraticCoeffs P2V;
uint32_t PsmCharzFreq;
uint16_t InversionVoltage;
uint16_t PsmCharzTemp;
uint32_t EnabledAvfsModules;
};
typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses;
struct SMU7_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
struct SMU7_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
struct SMU7_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
};
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
struct SMU7_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[4];
uint32_t temperature;
};
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
struct SMU7_Discrete_Pm_Status_Table {
//Thermal entities
int32_t T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT];
int32_t T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT];
int32_t T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT];
uint32_t T_hbm_acc;
//Voltage domains
uint32_t I_calc_max;
uint32_t I_calc_acc;
uint32_t P_meas_acc;
uint32_t V_meas_load_acc;
uint32_t I_meas_acc;
uint32_t P_meas_acc_vddci;
uint32_t V_meas_load_acc_vddci;
uint32_t I_meas_acc_vddci;
//Frequency
uint16_t Sclk_dpm_residency[8];
uint16_t Uvd_dpm_residency[8];
uint16_t Vce_dpm_residency[8];
//Chip
uint32_t P_roc_acc;
uint32_t PkgPwr_max;
uint32_t PkgPwr_acc;
uint32_t MclkSwitchingTime_max;
uint32_t MclkSwitchingTime_acc;
uint32_t FanPwm_acc;
uint32_t FanRpm_acc;
uint32_t Gfx_busy_acc;
uint32_t Mc_busy_acc;
uint32_t Fps_acc;
uint32_t AccCnt;
};
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
//FIXME THESE NEED TO BE UPDATED
#define SMU7_SCLK_CAC 0x561
#define SMU7_MCLK_CAC 0xF9
#define SMU7_VCLK_CAC 0x2DE
#define SMU7_DCLK_CAC 0x2DE
#define SMU7_ECLK_CAC 0x25E
#define SMU7_ACLK_CAC 0x25E
#define SMU7_SAMCLK_CAC 0x25E
#define SMU7_DISPCLK_CAC 0x100
#define SMU7_CAC_CONSTANT 0x2EE3430
#define SMU7_CAC_CONSTANT_SHIFT 18
#define SMU7_VDDCI_MCLK_CONST 1765
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
#define SMU7_VDDCI_VDDCI_CONST 50958
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
#define SMU7_VDDCI_CONST 11781
#define SMU7_VDDCI_STROBE_PWR 1331
#define SMU7_VDDR1_CONST 693
#define SMU7_VDDR1_CAC_WEIGHT 20
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
#define SMU7_VDDR1_STROBE_PWR 512
#define SMU7_AREA_COEFF_UVD 0xA78
#define SMU7_AREA_COEFF_VCE 0x190A
#define SMU7_AREA_COEFF_ACP 0x22D1
#define SMU7_AREA_COEFF_SAMU 0x534
//ThermOutMode values
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h
+833
View File
@@ -0,0 +1,833 @@
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU74_H
#define SMU74_H
#pragma pack(push, 1)
#define SMU__DGPU_ONLY
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8
#define EXP_M1 35
#define EXP_M2 92821
#define EXP_B 66629747
#define EXP_M1_1 365
#define EXP_M2_1 658700
#define EXP_B_1 305506134
#define EXP_M1_2 189
#define EXP_M2_2 379692
#define EXP_B_2 194609469
#define EXP_M1_3 99
#define EXP_M2_3 217915
#define EXP_B_3 122255994
#define EXP_M1_4 51
#define EXP_M2_4 122643
#define EXP_B_4 74893384
#define EXP_M1_5 423
#define EXP_M2_5 1103326
#define EXP_B_5 728122621
enum SID_OPTION {
SID_OPTION_HI,
SID_OPTION_LO,
SID_OPTION_COUNT
};
enum Poly3rdOrderCoeff {
LEAKAGE_TEMPERATURE_SCALAR,
LEAKAGE_VOLTAGE_SCALAR,
DYNAMIC_VOLTAGE_SCALAR,
POLY_3RD_ORDER_COUNT
};
struct SMU7_Poly3rdOrder_Data {
int32_t a;
int32_t b;
int32_t c;
int32_t d;
uint8_t a_shift;
uint8_t b_shift;
uint8_t c_shift;
uint8_t x_shift;
};
typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
struct Power_Calculator_Data {
uint16_t NoLoadVoltage;
uint16_t LoadVoltage;
uint16_t Resistance;
uint16_t Temperature;
uint16_t BaseLeakage;
uint16_t LkgTempScalar;
uint16_t LkgVoltScalar;
uint16_t LkgAreaScalar;
uint16_t LkgPower;
uint16_t DynVoltScalar;
uint32_t Cac;
uint32_t DynPower;
uint32_t TotalCurrent;
uint32_t TotalPower;
};
typedef struct Power_Calculator_Data PowerCalculatorData_t;
struct Gc_Cac_Weight_Data {
uint8_t index;
uint32_t value;
};
typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU74_MAX_LEVELS_VDDC 16
#define SMU74_MAX_LEVELS_VDDGFX 16
#define SMU74_MAX_LEVELS_VDDCI 8
#define SMU74_MAX_LEVELS_MVDD 4
#define SMU_MAX_SMIO_LEVELS 4
#define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
#define SMU74_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
#define SMU74_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
#define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes */
#define SMU74_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD */
#define SMU74_MAX_LEVELS_VCE 8 /* ECLK levels for VCE */
#define SMU74_MAX_LEVELS_ACP 8 /* ACLK levels for ACP */
#define SMU74_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU */
#define SMU74_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table */
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
/* Virtualization Defines */
#define CG_XDMA_MASK 0x1
#define CG_XDMA_SHIFT 0
#define CG_UVD_MASK 0x2
#define CG_UVD_SHIFT 1
#define CG_VCE_MASK 0x4
#define CG_VCE_SHIFT 2
#define CG_SAMU_MASK 0x8
#define CG_SAMU_SHIFT 3
#define CG_GFX_MASK 0x10
#define CG_GFX_SHIFT 4
#define CG_SDMA_MASK 0x20
#define CG_SDMA_SHIFT 5
#define CG_HDP_MASK 0x40
#define CG_HDP_SHIFT 6
#define CG_MC_MASK 0x80
#define CG_MC_SHIFT 7
#define CG_DRM_MASK 0x100
#define CG_DRM_SHIFT 8
#define CG_ROM_MASK 0x200
#define CG_ROM_SHIFT 9
#define CG_BIF_MASK 0x400
#define CG_BIF_SHIFT 10
#define SMU74_DTE_ITERATIONS 5
#define SMU74_DTE_SOURCES 3
#define SMU74_DTE_SINKS 1
#define SMU74_NUM_CPU_TES 0
#define SMU74_NUM_GPU_TES 1
#define SMU74_NUM_NON_TES 2
#define SMU74_DTE_FAN_SCALAR_MIN 0x100
#define SMU74_DTE_FAN_SCALAR_MAX 0x166
#define SMU74_DTE_FAN_TEMP_MAX 93
#define SMU74_DTE_FAN_TEMP_MIN 83
#if defined SMU__FUSION_ONLY
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
#endif
struct SMU7_HystController_Data {
uint8_t waterfall_up;
uint8_t waterfall_down;
uint8_t waterfall_limit;
uint8_t spare;
uint16_t release_cnt;
uint16_t release_limit;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
struct SMU74_PIDController {
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU74_PIDController SMU74_PIDController;
struct SMU7_LocalDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode;
uint8_t spare2;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
uint32_t FilteredSclkFrequency;
uint32_t LastSclkFrequency;
uint32_t FilteredSclkFrequencyCnt;
uint8_t MinPerfLevel;
uint8_t padding[3];
uint16_t FpsAlpha;
uint16_t DeltaTime;
uint32_t CurrentFps;
uint32_t FilteredFps;
uint32_t FrameCount;
uint32_t FrameCountLast;
uint16_t FpsTargetScalar;
uint16_t FpsWaterfallLimitScalar;
uint16_t FpsAlphaScalar;
uint16_t spare8;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
#define VDDC_MASK 0x00007FFF
#define VDDC_SHIFT 0
#define VDDCI_MASK 0x3FFF8000
#define VDDCI_SHIFT 15
#define PHASES_MASK 0xC0000000
#define PHASES_SHIFT 30
typedef uint32_t SMU_VoltageLevel;
struct SMU7_VoltageScoreboard {
SMU_VoltageLevel TargetVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
uint16_t CurrentVddc;
uint16_t CurrentVddci;
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint8_t CurrentVddciVid;
uint8_t padding;
SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
SMU_VoltageLevel TargetVoltageState;
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t padding2;
uint8_t padding3;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
uint8_t OverrideVoltage;
uint8_t padding4;
uint8_t padding5;
uint8_t CurrentPhases;
VoltageChangeHandler_t ChangeVddc;
VoltageChangeHandler_t ChangeVddci;
VoltageChangeHandler_t ChangePhase;
VoltageChangeHandler_t ChangeMvdd;
VoltageChangeHandler_t functionLinks[6];
uint16_t *VddcFollower1;
int16_t Driver_OD_RequestedVidOffset1;
int16_t Driver_OD_RequestedVidOffset2;
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
struct SMU7_PCIeLinkSpeedScoreboard {
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard {
PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
uint32_t TotalGpuPower;
uint32_t TdcCurrent;
uint16_t VddciTotalPower;
uint16_t sparesasfsdfd;
uint16_t Vddr1Power;
uint16_t RocPower;
uint16_t CalcMeasPowerBlend;
uint8_t SidOptionPower;
uint8_t SidOptionCurrent;
uint32_t WinTime;
uint16_t Telemetry_1_slope;
uint16_t Telemetry_2_slope;
int32_t Telemetry_1_offset;
int32_t Telemetry_2_offset;
uint32_t VddcCurrentTelemetry;
uint32_t VddGfxCurrentTelemetry;
uint32_t VddcPowerTelemetry;
uint32_t VddGfxPowerTelemetry;
uint32_t VddciPowerTelemetry;
uint32_t VddcPower;
uint32_t VddGfxPower;
uint32_t VddciPower;
uint32_t TelemetryCurrent[2];
uint32_t TelemetryVoltage[2];
uint32_t TelemetryPower[2];
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
struct SMU7_ThermalScoreboard {
int16_t GpuLimit;
int16_t GpuHyst;
uint16_t CurrGnbTemp;
uint16_t FilteredGnbTemp;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint8_t AutoTmonCalInterval;
uint8_t AutoTmonCalEnable;
uint8_t ThermalDpmEnabled;
uint8_t SclkEnabledMask;
uint8_t spare[2];
int32_t temperature_gradient;
SMU7_HystController_Data HystControllerData;
int32_t WeightedSensorTemperature;
uint16_t TemperatureLimit[SMU74_MAX_LEVELS_GRAPHICS];
uint32_t Alpha;
};
typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
/* All 'soft registers' should be uint32_t. */
struct SMU74_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint32_t AllowMvddSwitch;
uint8_t Activity_Weight;
uint8_t Reserved8[3];
};
typedef struct SMU74_SoftRegisters SMU74_SoftRegisters;
struct SMU74_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t ClockStretcherTable;
uint32_t VftTable;
uint32_t Reserved1;
uint32_t AvfsTable;
uint32_t AvfsCksOffGbvTable;
uint32_t AvfsMeanNSigma;
uint32_t AvfsSclkOffsetTable;
uint32_t Reserved[16];
uint32_t Signature;
};
typedef struct SMU74_Firmware_Header SMU74_Firmware_Header;
#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 5
#define SE_BLOCK_COUNT 15
#define GC_BLOCK_COUNT 24
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#pragma pack(pop)
/* Description of Clock Gating bitmask for Tonga:
* System Clock Gating
*/
#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */
#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */
#define CG_SYS_BIF_MGLS_SHIFT 0
#define CG_SYS_ROM_SHIFT 1
#define CG_SYS_MC_MGCG_SHIFT 2
#define CG_SYS_MC_MGLS_SHIFT 3
#define CG_SYS_SDMA_MGCG_SHIFT 4
#define CG_SYS_SDMA_MGLS_SHIFT 5
#define CG_SYS_DRM_MGCG_SHIFT 6
#define CG_SYS_HDP_MGCG_SHIFT 7
#define CG_SYS_HDP_MGLS_SHIFT 8
#define CG_SYS_DRM_MGLS_SHIFT 9
#define CG_SYS_BIF_MGCG_SHIFT 10
#define CG_SYS_BIF_MGLS_MASK 0x1
#define CG_SYS_ROM_MASK 0x2
#define CG_SYS_MC_MGCG_MASK 0x4
#define CG_SYS_MC_MGLS_MASK 0x8
#define CG_SYS_SDMA_MGCG_MASK 0x10
#define CG_SYS_SDMA_MGLS_MASK 0x20
#define CG_SYS_DRM_MGCG_MASK 0x40
#define CG_SYS_HDP_MGCG_MASK 0x80
#define CG_SYS_HDP_MGLS_MASK 0x100
#define CG_SYS_DRM_MGLS_MASK 0x200
#define CG_SYS_BIF_MGCG_MASK 0x400
/* Graphics Clock Gating */
#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */
#define CG_GFX_BITMASK_LAST_BIT 24 /* Last bit of Gfx CG bitmask */
#define CG_GFX_CGCG_SHIFT 16
#define CG_GFX_CGLS_SHIFT 17
#define CG_CPF_MGCG_SHIFT 18
#define CG_RLC_MGCG_SHIFT 19
#define CG_GFX_OTHERS_MGCG_SHIFT 20
#define CG_GFX_3DCG_SHIFT 21
#define CG_GFX_3DLS_SHIFT 22
#define CG_GFX_RLC_LS_SHIFT 23
#define CG_GFX_CP_LS_SHIFT 24
#define CG_GFX_CGCG_MASK 0x00010000
#define CG_GFX_CGLS_MASK 0x00020000
#define CG_CPF_MGCG_MASK 0x00040000
#define CG_RLC_MGCG_MASK 0x00080000
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
#define CG_GFX_3DCG_MASK 0x00200000
#define CG_GFX_3DLS_MASK 0x00400000
#define CG_GFX_RLC_LS_MASK 0x00800000
#define CG_GFX_CP_LS_MASK 0x01000000
/* Voltage Regulator Configuration
VR Config info is contained in dpmTable.VRConfig */
#define VRCONF_VDDC_MASK 0x000000FF
#define VRCONF_VDDC_SHIFT 0
#define VRCONF_VDDGFX_MASK 0x0000FF00
#define VRCONF_VDDGFX_SHIFT 8
#define VRCONF_VDDCI_MASK 0x00FF0000
#define VRCONF_VDDCI_SHIFT 16
#define VRCONF_MVDD_MASK 0xFF000000
#define VRCONF_MVDD_SHIFT 24
#define VR_MERGED_WITH_VDDC 0
#define VR_SVI2_PLANE_1 1
#define VR_SVI2_PLANE_2 2
#define VR_SMIO_PATTERN_1 3
#define VR_SMIO_PATTERN_2 4
#define VR_STATIC_VOLTAGE 5
/* Clock Stretcher Configuration */
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
/* The 'settings' field is subdivided in the following way: */
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
struct SMU_ClockStretcherDataTableEntry {
uint8_t minVID;
uint8_t maxVID;
uint16_t setting;
};
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
struct SMU_ClockStretcherDataTable {
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
};
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
struct SMU_CKS_LOOKUPTableEntry {
uint16_t minFreq;
uint16_t maxFreq;
uint8_t setting;
uint8_t padding[3];
};
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
struct SMU_CKS_LOOKUPTable {
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
};
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
struct AgmAvfsData_t {
uint16_t avgPsmCount[28];
uint16_t minPsmCount[28];
};
typedef struct AgmAvfsData_t AgmAvfsData_t;
enum VFT_COLUMNS {
SCLK0,
SCLK1,
SCLK2,
SCLK3,
SCLK4,
SCLK5,
SCLK6,
SCLK7,
NUM_VFT_COLUMNS
};
#define VFT_TABLE_DEFINED
#define TEMP_RANGE_MAXSTEPS 12
struct VFT_CELL_t {
uint16_t Voltage;
};
typedef struct VFT_CELL_t VFT_CELL_t;
struct VFT_TABLE_t {
VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
uint16_t AvfsGbv[NUM_VFT_COLUMNS];
uint16_t BtcGbv[NUM_VFT_COLUMNS];
uint16_t Temperature[TEMP_RANGE_MAXSTEPS];
uint8_t NumTemperatureSteps;
uint8_t padding[3];
};
typedef struct VFT_TABLE_t VFT_TABLE_t;
/* Total margin, root mean square of Fmax + DC + Platform */
struct AVFS_Margin_t {
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
};
typedef struct AVFS_Margin_t AVFS_Margin_t;
#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
struct GB_VDROOP_TABLE_t {
int32_t a0;
int32_t a1;
int32_t a2;
uint32_t spare;
};
typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
struct AVFS_CksOff_Gbv_t {
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
};
typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
struct AVFS_meanNsigma_t {
uint32_t Aconstant[3];
uint16_t DC_tol_sigma;
uint16_t Platform_mean;
uint16_t Platform_sigma;
uint16_t PSM_Age_CompFactor;
uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];
};
typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
struct AVFS_Sclk_Offset_t {
uint16_t Sclk_Offset[8];
};
typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h
+850
View File
@@ -0,0 +1,850 @@
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU74_DISCRETE_H
#define SMU74_DISCRETE_H
#include "smu74.h"
#pragma pack(push, 1)
#define NUM_SCLK_RANGE 8
#define VCO_3_6 1
#define VCO_2_4 3
#define POSTDIV_DIV_BY_1 0
#define POSTDIV_DIV_BY_2 1
#define POSTDIV_DIV_BY_4 2
#define POSTDIV_DIV_BY_8 3
#define POSTDIV_DIV_BY_16 4
struct sclkFcwRange_t {
uint8_t vco_setting;
uint8_t postdiv;
uint16_t fcw_pcc;
uint16_t fcw_trans_upper;
uint16_t fcw_trans_lower;
};
typedef struct sclkFcwRange_t sclkFcwRange_t;
struct SMIO_Pattern {
uint16_t Voltage;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMIO_Pattern SMIO_Pattern;
struct SMIO_Table {
SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};
typedef struct SMIO_Table SMIO_Table;
struct SMU_SclkSetting {
uint32_t SclkFrequency;
uint16_t Fcw_int;
uint16_t Fcw_frac;
uint16_t Pcc_fcw_int;
uint8_t PllRange;
uint8_t SSc_En;
uint16_t Sclk_slew_rate;
uint16_t Pcc_up_slew_rate;
uint16_t Pcc_down_slew_rate;
uint16_t Fcw1_int;
uint16_t Fcw1_frac;
uint16_t Sclk_ss_slew_rate;
};
typedef struct SMU_SclkSetting SMU_SclkSetting;
struct SMU74_Discrete_GraphicsLevel {
SMU_VoltageLevel MinVoltage;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t padding;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
SMU_SclkSetting SclkSetting;
};
typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
struct SMU74_Discrete_ACPILevel {
uint32_t Flags;
SMU_VoltageLevel MinVoltage;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
SMU_SclkSetting SclkSetting;
};
typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
struct SMU74_Discrete_Ulv {
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint16_t BifSclkDfs;
uint16_t Reserved;
};
typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
struct SMU74_Discrete_MemoryLevel {
SMU_VoltageLevel MinVoltage;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t StutterEnable;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t padding_0;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding_1;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t Reserved;
};
typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
struct SMU74_Discrete_LinkLevel {
uint8_t PcieGenSpeed;
uint8_t PcieLaneCount;
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint16_t BifSclkDfs;
uint16_t Reserved;
};
typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
struct SMU74_Discrete_MCArbDramTimingTableEntry {
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t padding[3];
};
typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
struct SMU74_Discrete_MCArbDramTimingTable {
SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
struct SMU74_Discrete_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
SMU_VoltageLevel MinVoltage;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[2];
};
typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
struct SMU74_Discrete_ExtClkLevel {
uint32_t Frequency;
SMU_VoltageLevel MinVoltage;
uint8_t Divider;
uint8_t padding[3];
};
typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
struct SMU74_Discrete_StateInfo {
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
struct SMU_QuadraticCoeffs {
int32_t m1;
uint32_t b;
int16_t m2;
uint8_t m1_shift;
uint8_t m2_shift;
};
typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
struct SMU74_Discrete_DpmTable {
SMU74_PIDController GraphicsPIDController;
SMU74_PIDController MemoryPIDController;
SMU74_PIDController LinkPIDController;
uint32_t SystemFlags;
uint32_t VRConfig;
uint32_t SmioMask1;
uint32_t SmioMask2;
SMIO_Table SmioTable1;
SMIO_Table SmioTable2;
uint32_t MvddLevelCount;
uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t ThermOutGpio;
uint8_t ThermOutPolarity;
uint8_t ThermOutMode;
uint8_t BootPhases;
uint8_t VRHotLevel;
uint8_t LdoRefSel;
uint8_t SharedRails;
uint8_t Reserved1;
uint16_t FanStartTemperature;
uint16_t FanStopTemperature;
uint16_t MaxVoltage;
uint16_t Reserved2;
uint32_t Reserved[1];
SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
SMU74_Discrete_MemoryLevel MemoryACPILevel;
SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
SMU74_Discrete_ACPILevel ACPILevel;
SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU];
SMU74_Discrete_Ulv Ulv;
uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
uint32_t SclkStepSize;
uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint16_t BootMVdd;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
uint16_t TemperatureLimitEdge;
uint16_t TemperatureLimitHotspot;
uint16_t BootVddc;
uint16_t BootVddci;
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint8_t ClockStretcherAmount;
uint8_t Sclk_CKS_masterEn0_7;
uint8_t Sclk_CKS_masterEn8_15;
uint8_t DPMFreezeAndForced;
uint8_t Sclk_voltageOffset[8];
SMU_ClockStretcherDataTable ClockStretcherDataTable;
SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
uint32_t CurrSclkPllRange;
sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
};
typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
struct SMU74_Discrete_FanTable {
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t Padding;
};
typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU7_MclkDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t padding2;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t IgnoreVBlank;
uint8_t TargetMclkIndex;
uint16_t VbiFailureCount;
uint8_t VbiWaitCounter;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t VbiTimeoutCount;
uint16_t MclkSwitchingTime;
uint8_t fastSwitch;
uint8_t Save_PIC_VDDGFX_EXIT;
uint8_t Save_PIC_VDDGFX_ENTER;
uint8_t padding;
};
typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
struct SMU7_UlvScoreboard {
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
struct VddgfxSavedRegisters {
uint32_t GPU_DBG[3];
uint32_t MEC_BaseAddress_Hi;
uint32_t MEC_BaseAddress_Lo;
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
uint32_t CP_INT_CNTL;
};
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
struct SMU7_VddGfxScoreboard {
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t VPUResetOccured;
uint8_t padding;
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
uint32_t VddGfxVid;
VddgfxSavedRegisters SavedRegisters;
};
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
struct SMU7_TdcLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredIddc;
uint32_t IddcLimit;
uint32_t IddcHyst;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
struct SMU7_PkgPwrLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredPkgPwr;
uint32_t Limit;
uint32_t Hyst;
uint32_t LimitFromDriver;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
struct SMU7_BapmScoreboard {
uint32_t source_powers[SMU74_DTE_SOURCES];
uint32_t source_powers_last[SMU74_DTE_SOURCES];
int32_t entity_temperatures[SMU74_NUM_GPU_TES];
int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
int32_t Limit;
int32_t Hyst;
int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
uint16_t ConfigTDPPowerScalar;
uint16_t FanSpeedPowerScalar;
uint16_t OverDrivePowerScalar;
uint16_t OverDriveLimitScalar;
uint16_t FinalPowerScalar;
uint8_t VariantID;
uint8_t spare997;
SMU7_HystController_Data HystControllerData;
int32_t temperature_gradient_slope;
int32_t temperature_gradient;
uint32_t measured_temperature;
};
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
struct SMU7_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU74_Discrete_ACPILevel D0Level;
};
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
struct SMU74_Discrete_PmFuses {
uint8_t BapmVddCVidHiSidd[8];
uint8_t BapmVddCVidLoSidd[8];
uint8_t VddCVid[8];
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
uint8_t LPMLTemperatureScaler[16];
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
uint8_t GnbLPML[16];
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
uint16_t VFT_Temp[3];
uint16_t padding;
SMU_QuadraticCoeffs VFT_ATE[3];
SMU_QuadraticCoeffs AVFS_GB;
SMU_QuadraticCoeffs ATE_ACBTC_GB;
SMU_QuadraticCoeffs P2V;
uint32_t PsmCharzFreq;
uint16_t InversionVoltage;
uint16_t PsmCharzTemp;
uint32_t EnabledAvfsModules;
};
typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
struct SMU7_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
struct SMU7_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
#if defined SMU__DGPU_ONLY
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
#endif
struct SMU7_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
};
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
struct SMU7_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[4];
uint32_t temperature;
};
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
struct SMU7_Discrete_Pm_Status_Table {
int32_t T_meas_max;
int32_t T_meas_acc;
int32_t T_calc_max;
int32_t T_calc_acc;
uint32_t P_scalar_acc;
uint32_t P_calc_max;
uint32_t P_calc_acc;
uint32_t I_calc_max;
uint32_t I_calc_acc;
uint32_t I_calc_acc_vddci;
uint32_t V_calc_noload_acc;
uint32_t V_calc_load_acc;
uint32_t V_calc_noload_acc_vddci;
uint32_t P_meas_acc;
uint32_t V_meas_noload_acc;
uint32_t V_meas_load_acc;
uint32_t I_meas_acc;
uint32_t P_meas_acc_vddci;
uint32_t V_meas_noload_acc_vddci;
uint32_t V_meas_load_acc_vddci;
uint32_t I_meas_acc_vddci;
uint16_t Sclk_dpm_residency[8];
uint16_t Uvd_dpm_residency[8];
uint16_t Vce_dpm_residency[8];
uint16_t Mclk_dpm_residency[4];
uint32_t P_vddci_acc;
uint32_t P_vddr1_acc;
uint32_t P_nte1_acc;
uint32_t PkgPwr_max;
uint32_t PkgPwr_acc;
uint32_t MclkSwitchingTime_max;
uint32_t MclkSwitchingTime_acc;
uint32_t FanPwm_acc;
uint32_t FanRpm_acc;
uint32_t AccCnt;
};
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
#define SMU7_MAX_GFX_CU_COUNT 16
struct SMU7_GfxCuPgScoreboard {
uint8_t Enabled;
uint8_t WaterfallUp;
uint8_t WaterfallDown;
uint8_t WaterfallLimit;
uint8_t CurrMaxCu;
uint8_t TargMaxCu;
uint8_t ClampMode;
uint8_t Active;
uint8_t MaxSupportedCu;
uint8_t MinSupportedCu;
uint8_t PendingGfxCuHostInterrupt;
uint8_t LastFilteredMaxCuInteger;
uint16_t FilteredMaxCu;
uint16_t FilteredMaxCuAlpha;
uint16_t FilterResetCount;
uint16_t FilterResetCountLimit;
uint8_t ForceCu;
uint8_t ForceCuCount;
uint8_t spare[2];
};
typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
#define SMU7_SCLK_CAC 0x561
#define SMU7_MCLK_CAC 0xF9
#define SMU7_VCLK_CAC 0x2DE
#define SMU7_DCLK_CAC 0x2DE
#define SMU7_ECLK_CAC 0x25E
#define SMU7_ACLK_CAC 0x25E
#define SMU7_SAMCLK_CAC 0x25E
#define SMU7_DISPCLK_CAC 0x100
#define SMU7_CAC_CONSTANT 0x2EE3430
#define SMU7_CAC_CONSTANT_SHIFT 18
#define SMU7_VDDCI_MCLK_CONST 1765
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
#define SMU7_VDDCI_VDDCI_CONST 50958
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
#define SMU7_VDDCI_CONST 11781
#define SMU7_VDDCI_STROBE_PWR 1331
#define SMU7_VDDR1_CONST 693
#define SMU7_VDDR1_CAC_WEIGHT 20
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
#define SMU7_VDDR1_STROBE_PWR 512
#define SMU7_AREA_COEFF_UVD 0xA78
#define SMU7_AREA_COEFF_VCE 0x190A
#define SMU7_AREA_COEFF_ACP 0x22D1
#define SMU7_AREA_COEFF_SAMU 0x534
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
// DIDT Defines
#define SQ_Enable_MASK 0x1
#define SQ_IR_MASK 0x2
#define SQ_PCC_MASK 0x4
#define SQ_EDC_MASK 0x8
#define TCP_Enable_MASK 0x100
#define TCP_IR_MASK 0x200
#define TCP_PCC_MASK 0x400
#define TCP_EDC_MASK 0x800
#define TD_Enable_MASK 0x10000
#define TD_IR_MASK 0x20000
#define TD_PCC_MASK 0x40000
#define TD_EDC_MASK 0x80000
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
#define SQ_IR_SHIFT 1
#define SQ_PCC_SHIFT 2
#define SQ_EDC_SHIFT 3
#define TCP_Enable_SHIFT 8
#define TCP_IR_SHIFT 9
#define TCP_PCC_SHIFT 10
#define TCP_EDC_SHIFT 11
#define TD_Enable_SHIFT 16
#define TD_IR_SHIFT 17
#define TD_PCC_SHIFT 18
#define TD_EDC_SHIFT 19
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#define BTCGB0_Vdroop_Enable_MASK 0x1
#define BTCGB1_Vdroop_Enable_MASK 0x2
#define AVFSGB0_Vdroop_Enable_MASK 0x4
#define AVFSGB1_Vdroop_Enable_MASK 0x8
#define BTCGB0_Vdroop_Enable_SHIFT 0
#define BTCGB1_Vdroop_Enable_SHIFT 1
#define AVFSGB0_Vdroop_Enable_SHIFT 2
#define AVFSGB1_Vdroop_Enable_SHIFT 3
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h
+760
View File
@@ -0,0 +1,760 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU75_H
#define SMU75_H
#pragma pack(push, 1)
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU__DGPU_ONLY
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU75_MAX_LEVELS_VDDC 16
#define SMU75_MAX_LEVELS_VDDGFX 16
#define SMU75_MAX_LEVELS_VDDCI 8
#define SMU75_MAX_LEVELS_MVDD 4
#define SMU_MAX_SMIO_LEVELS 4
#define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
#define SMU75_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
#define SMU75_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS
#define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
#define SMU75_MAX_LEVELS_UVD 8
#define SMU75_MAX_LEVELS_VCE 8
#define SMU75_MAX_LEVELS_ACP 8
#define SMU75_MAX_LEVELS_SAMU 8
#define SMU75_MAX_ENTRIES_SMIO 32
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
/* Virtualization Defines */
#define CG_XDMA_MASK 0x1
#define CG_XDMA_SHIFT 0
#define CG_UVD_MASK 0x2
#define CG_UVD_SHIFT 1
#define CG_VCE_MASK 0x4
#define CG_VCE_SHIFT 2
#define CG_SAMU_MASK 0x8
#define CG_SAMU_SHIFT 3
#define CG_GFX_MASK 0x10
#define CG_GFX_SHIFT 4
#define CG_SDMA_MASK 0x20
#define CG_SDMA_SHIFT 5
#define CG_HDP_MASK 0x40
#define CG_HDP_SHIFT 6
#define CG_MC_MASK 0x80
#define CG_MC_SHIFT 7
#define CG_DRM_MASK 0x100
#define CG_DRM_SHIFT 8
#define CG_ROM_MASK 0x200
#define CG_ROM_SHIFT 9
#define CG_BIF_MASK 0x400
#define CG_BIF_SHIFT 10
#if defined SMU__DGPU_ONLY
#define SMU75_DTE_ITERATIONS 5
#define SMU75_DTE_SOURCES 3
#define SMU75_DTE_SINKS 1
#define SMU75_NUM_CPU_TES 0
#define SMU75_NUM_GPU_TES 1
#define SMU75_NUM_NON_TES 2
#define SMU75_DTE_FAN_SCALAR_MIN 0x100
#define SMU75_DTE_FAN_SCALAR_MAX 0x166
#define SMU75_DTE_FAN_TEMP_MAX 93
#define SMU75_DTE_FAN_TEMP_MIN 83
#endif
#define SMU75_THERMAL_INPUT_LOOP_COUNT 2
#define SMU75_THERMAL_CLAMP_MODE_COUNT 2
#define EXP_M1_1 93
#define EXP_M2_1 195759
#define EXP_B_1 111176531
#define EXP_M1_2 67
#define EXP_M2_2 153720
#define EXP_B_2 94415767
#define EXP_M1_3 48
#define EXP_M2_3 119796
#define EXP_B_3 79195279
#define EXP_M1_4 550
#define EXP_M2_4 1484190
#define EXP_B_4 1051432828
#define EXP_M1_5 394
#define EXP_M2_5 1143049
#define EXP_B_5 864288432
struct SMU7_HystController_Data {
uint16_t waterfall_up;
uint16_t waterfall_down;
uint16_t waterfall_limit;
uint16_t release_cnt;
uint16_t release_limit;
uint16_t spare;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
struct SMU75_PIDController {
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU75_PIDController SMU75_PIDController;
struct SMU7_LocalDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode;
uint8_t EnableModeSwitchRLCNotification;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters[SMU75_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters[SMU75_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
uint32_t FilteredSclkFrequency;
uint32_t LastSclkFrequency;
uint32_t FilteredSclkFrequencyCnt;
uint8_t MinPerfLevel;
#ifdef SMU__FIRMWARE_SCKS_PRESENT__1
uint8_t ScksClampMode;
uint8_t padding[2];
#else
uint8_t padding[3];
#endif
uint16_t FpsAlpha;
uint16_t DeltaTime;
uint32_t CurrentFps;
uint32_t FilteredFps;
uint32_t FrameCount;
uint32_t FrameCountLast;
uint16_t FpsTargetScalar;
uint16_t FpsWaterfallLimitScalar;
uint16_t FpsAlphaScalar;
uint16_t spare8;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
#define VDDC_MASK 0x00007FFF
#define VDDC_SHIFT 0
#define VDDCI_MASK 0x3FFF8000
#define VDDCI_SHIFT 15
#define PHASES_MASK 0xC0000000
#define PHASES_SHIFT 30
typedef uint32_t SMU_VoltageLevel;
struct SMU7_VoltageScoreboard {
SMU_VoltageLevel TargetVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
uint16_t CurrentVddc;
uint16_t CurrentVddci;
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint8_t CurrentVddciVid;
uint8_t padding;
SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
SMU_VoltageLevel TargetVoltageState;
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t padding2;
uint8_t padding3;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
uint8_t OverrideVoltage;
uint8_t padding4;
uint8_t padding5;
uint8_t CurrentPhases;
VoltageChangeHandler_t ChangeVddc;
VoltageChangeHandler_t ChangeVddci;
VoltageChangeHandler_t ChangePhase;
VoltageChangeHandler_t ChangeMvdd;
VoltageChangeHandler_t functionLinks[6];
uint16_t *VddcFollower1;
int16_t Driver_OD_RequestedVidOffset1;
int16_t Driver_OD_RequestedVidOffset2;
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
#define SMU7_MAX_PCIE_LINK_SPEEDS 3
struct SMU7_PCIeLinkSpeedScoreboard {
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard {
uint32_t GpuPower;
uint32_t VddcPower;
uint32_t VddcVoltage;
uint32_t VddcCurrent;
uint32_t VddciPower;
uint32_t VddciVoltage;
uint32_t VddciCurrent;
uint32_t RocPower;
uint16_t Telemetry_1_slope;
uint16_t Telemetry_2_slope;
int32_t Telemetry_1_offset;
int32_t Telemetry_2_offset;
uint8_t MCLK_patch_flag;
uint8_t reserved[3];
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
struct SMU75_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
#if defined (SMU__DGPU_ONLY)
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
#endif
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint32_t AllowMvddSwitch;
uint8_t Activity_Weight;
uint8_t Reserved8[3];
};
typedef struct SMU75_SoftRegisters SMU75_SoftRegisters;
struct SMU75_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t ClockStretcherTable;
uint32_t VftTable;
uint32_t Reserved1;
uint32_t AvfsCksOff_AvfsGbvTable;
uint32_t AvfsCksOff_BtcGbvTable;
uint32_t MM_AvfsTable;
uint32_t PowerSharingTable;
uint32_t AvfsTable;
uint32_t AvfsCksOffGbvTable;
uint32_t AvfsMeanNSigma;
uint32_t AvfsSclkOffsetTable;
uint32_t Reserved[12];
uint32_t Signature;
};
typedef struct SMU75_Firmware_Header SMU75_Firmware_Header;
#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 5
#define SE_BLOCK_COUNT 15
#define GC_BLOCK_COUNT 24
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#pragma pack(pop)
#define CG_SYS_BITMASK_FIRST_BIT 0
#define CG_SYS_BITMASK_LAST_BIT 10
#define CG_SYS_BIF_MGLS_SHIFT 0
#define CG_SYS_ROM_SHIFT 1
#define CG_SYS_MC_MGCG_SHIFT 2
#define CG_SYS_MC_MGLS_SHIFT 3
#define CG_SYS_SDMA_MGCG_SHIFT 4
#define CG_SYS_SDMA_MGLS_SHIFT 5
#define CG_SYS_DRM_MGCG_SHIFT 6
#define CG_SYS_HDP_MGCG_SHIFT 7
#define CG_SYS_HDP_MGLS_SHIFT 8
#define CG_SYS_DRM_MGLS_SHIFT 9
#define CG_SYS_BIF_MGCG_SHIFT 10
#define CG_SYS_BIF_MGLS_MASK 0x1
#define CG_SYS_ROM_MASK 0x2
#define CG_SYS_MC_MGCG_MASK 0x4
#define CG_SYS_MC_MGLS_MASK 0x8
#define CG_SYS_SDMA_MGCG_MASK 0x10
#define CG_SYS_SDMA_MGLS_MASK 0x20
#define CG_SYS_DRM_MGCG_MASK 0x40
#define CG_SYS_HDP_MGCG_MASK 0x80
#define CG_SYS_HDP_MGLS_MASK 0x100
#define CG_SYS_DRM_MGLS_MASK 0x200
#define CG_SYS_BIF_MGCG_MASK 0x400
#define CG_GFX_BITMASK_FIRST_BIT 16
#define CG_GFX_BITMASK_LAST_BIT 24
#define CG_GFX_CGCG_SHIFT 16
#define CG_GFX_CGLS_SHIFT 17
#define CG_CPF_MGCG_SHIFT 18
#define CG_RLC_MGCG_SHIFT 19
#define CG_GFX_OTHERS_MGCG_SHIFT 20
#define CG_GFX_3DCG_SHIFT 21
#define CG_GFX_3DLS_SHIFT 22
#define CG_GFX_RLC_LS_SHIFT 23
#define CG_GFX_CP_LS_SHIFT 24
#define CG_GFX_CGCG_MASK 0x00010000
#define CG_GFX_CGLS_MASK 0x00020000
#define CG_CPF_MGCG_MASK 0x00040000
#define CG_RLC_MGCG_MASK 0x00080000
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
#define CG_GFX_3DCG_MASK 0x00200000
#define CG_GFX_3DLS_MASK 0x00400000
#define CG_GFX_RLC_LS_MASK 0x00800000
#define CG_GFX_CP_LS_MASK 0x01000000
#define VRCONF_VDDC_MASK 0x000000FF
#define VRCONF_VDDC_SHIFT 0
#define VRCONF_VDDGFX_MASK 0x0000FF00
#define VRCONF_VDDGFX_SHIFT 8
#define VRCONF_VDDCI_MASK 0x00FF0000
#define VRCONF_VDDCI_SHIFT 16
#define VRCONF_MVDD_MASK 0xFF000000
#define VRCONF_MVDD_SHIFT 24
#define VR_MERGED_WITH_VDDC 0
#define VR_SVI2_PLANE_1 1
#define VR_SVI2_PLANE_2 2
#define VR_SMIO_PATTERN_1 3
#define VR_SMIO_PATTERN_2 4
#define VR_STATIC_VOLTAGE 5
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
struct SMU_ClockStretcherDataTableEntry {
uint8_t minVID;
uint8_t maxVID;
uint16_t setting;
};
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
struct SMU_ClockStretcherDataTable {
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
};
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
struct SMU_CKS_LOOKUPTableEntry {
uint16_t minFreq;
uint16_t maxFreq;
uint8_t setting;
uint8_t padding[3];
};
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
struct SMU_CKS_LOOKUPTable {
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
};
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
struct AgmAvfsData_t {
uint16_t avgPsmCount[28];
uint16_t minPsmCount[28];
};
typedef struct AgmAvfsData_t AgmAvfsData_t;
enum VFT_COLUMNS {
SCLK0,
SCLK1,
SCLK2,
SCLK3,
SCLK4,
SCLK5,
SCLK6,
SCLK7,
NUM_VFT_COLUMNS
};
enum {
SCS_FUSE_T0,
SCS_FUSE_T1,
NUM_SCS_FUSE_TEMPERATURE
};
enum {
SCKS_ON,
SCKS_OFF,
NUM_SCKS_STATE_TYPES
};
#define VFT_TABLE_DEFINED
#define TEMP_RANGE_MAXSTEPS 12
struct VFT_CELL_t {
uint16_t Voltage;
};
typedef struct VFT_CELL_t VFT_CELL_t;
#ifdef SMU__FIRMWARE_SCKS_PRESENT__1
struct SCS_CELL_t {
uint16_t PsmCnt[NUM_SCKS_STATE_TYPES];
};
typedef struct SCS_CELL_t SCS_CELL_t;
#endif
struct VFT_TABLE_t {
VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
uint16_t AvfsGbv[NUM_VFT_COLUMNS];
uint16_t BtcGbv[NUM_VFT_COLUMNS];
int16_t Temperature[TEMP_RANGE_MAXSTEPS];
#ifdef SMU__FIRMWARE_SCKS_PRESENT__1
SCS_CELL_t ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
#endif
uint8_t NumTemperatureSteps;
uint8_t padding[3];
};
typedef struct VFT_TABLE_t VFT_TABLE_t;
#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
struct GB_VDROOP_TABLE_t {
int32_t a0;
int32_t a1;
int32_t a2;
uint32_t spare;
};
typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
struct SMU_QuadraticCoeffs {
int32_t m1;
int32_t b;
int16_t m2;
uint8_t m1_shift;
uint8_t m2_shift;
};
typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
struct AVFS_Margin_t {
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
};
typedef struct AVFS_Margin_t AVFS_Margin_t;
struct AVFS_CksOff_Gbv_t {
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
};
typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
struct AVFS_CksOff_AvfsGbv_t {
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
};
typedef struct AVFS_CksOff_AvfsGbv_t AVFS_CksOff_AvfsGbv_t;
struct AVFS_CksOff_BtcGbv_t {
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
};
typedef struct AVFS_CksOff_BtcGbv_t AVFS_CksOff_BtcGbv_t;
struct AVFS_meanNsigma_t {
uint32_t Aconstant[3];
uint16_t DC_tol_sigma;
uint16_t Platform_mean;
uint16_t Platform_sigma;
uint16_t PSM_Age_CompFactor;
uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];
};
typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
struct AVFS_Sclk_Offset_t {
uint16_t Sclk_Offset[8];
};
typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
struct Power_Sharing_t {
uint32_t EnergyCounter;
uint32_t EngeryThreshold;
uint64_t AM_SCLK_CNT;
uint64_t AM_0_BUSY_CNT;
};
typedef struct Power_Sharing_t Power_Sharing_t;
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h
+886
View File
@@ -0,0 +1,886 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU75_DISCRETE_H
#define SMU75_DISCRETE_H
#include "smu75.h"
#pragma pack(push, 1)
#define NUM_SCLK_RANGE 8
#define VCO_3_6 1
#define VCO_2_4 3
#define POSTDIV_DIV_BY_1 0
#define POSTDIV_DIV_BY_2 1
#define POSTDIV_DIV_BY_4 2
#define POSTDIV_DIV_BY_8 3
#define POSTDIV_DIV_BY_16 4
struct sclkFcwRange_t {
uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
uint8_t postdiv; /* divide by 2^n */
uint16_t fcw_pcc;
uint16_t fcw_trans_upper;
uint16_t fcw_trans_lower;
};
typedef struct sclkFcwRange_t sclkFcwRange_t;
struct SMIO_Pattern {
uint16_t Voltage;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMIO_Pattern SMIO_Pattern;
struct SMIO_Table {
SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};
typedef struct SMIO_Table SMIO_Table;
struct SMU_SclkSetting {
uint32_t SclkFrequency;
uint16_t Fcw_int;
uint16_t Fcw_frac;
uint16_t Pcc_fcw_int;
uint8_t PllRange;
uint8_t SSc_En;
uint16_t Sclk_slew_rate;
uint16_t Pcc_up_slew_rate;
uint16_t Pcc_down_slew_rate;
uint16_t Fcw1_int;
uint16_t Fcw1_frac;
uint16_t Sclk_ss_slew_rate;
};
typedef struct SMU_SclkSetting SMU_SclkSetting;
struct SMU75_Discrete_GraphicsLevel {
SMU_VoltageLevel MinVoltage;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t padding;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
SMU_SclkSetting SclkSetting;
uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];
uint16_t Padding;
};
typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel;
struct SMU75_Discrete_ACPILevel {
uint32_t Flags;
SMU_VoltageLevel MinVoltage;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
SMU_SclkSetting SclkSetting;
};
typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel;
struct SMU75_Discrete_Ulv {
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint16_t BifSclkDfs;
uint16_t Reserved;
};
typedef struct SMU75_Discrete_Ulv SMU75_Discrete_Ulv;
struct SMU75_Discrete_MemoryLevel {
SMU_VoltageLevel MinVoltage;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t StutterEnable;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t padding_0;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding_1;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t padding_2;
uint16_t Fcw_int;
uint16_t Fcw_frac;
uint8_t Postdiv;
uint8_t padding_3[3];
};
typedef struct SMU75_Discrete_MemoryLevel SMU75_Discrete_MemoryLevel;
struct SMU75_Discrete_LinkLevel {
uint8_t PcieGenSpeed;
uint8_t PcieLaneCount;
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint16_t BifSclkDfs;
uint16_t Reserved;
};
typedef struct SMU75_Discrete_LinkLevel SMU75_Discrete_LinkLevel;
/* MC ARB DRAM Timing registers. */
struct SMU75_Discrete_MCArbDramTimingTableEntry {
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint32_t McArbBurstTime;
uint32_t McArbRfshRate;
uint32_t McArbMisc3;
};
typedef struct SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MCArbDramTimingTableEntry;
struct SMU75_Discrete_MCArbDramTimingTable {
SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_MCArbDramTimingTable;
/* UVD VCLK/DCLK state (level) definition. */
struct SMU75_Discrete_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
SMU_VoltageLevel MinVoltage;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[2];
};
typedef struct SMU75_Discrete_UvdLevel SMU75_Discrete_UvdLevel;
/* Clocks for other external blocks (VCE, ACP, SAMU). */
struct SMU75_Discrete_ExtClkLevel {
uint32_t Frequency;
SMU_VoltageLevel MinVoltage;
uint8_t Divider;
uint8_t padding[3];
};
typedef struct SMU75_Discrete_ExtClkLevel SMU75_Discrete_ExtClkLevel;
struct SMU75_Discrete_StateInfo {
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU75_Discrete_StateInfo SMU75_Discrete_StateInfo;
struct SMU75_Discrete_DpmTable {
SMU75_PIDController GraphicsPIDController;
SMU75_PIDController MemoryPIDController;
SMU75_PIDController LinkPIDController;
uint32_t SystemFlags;
uint32_t VRConfig;
uint32_t SmioMask1;
uint32_t SmioMask2;
SMIO_Table SmioTable1;
SMIO_Table SmioTable2;
uint32_t MvddLevelCount;
uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t ThermOutGpio;
uint8_t ThermOutPolarity;
uint8_t ThermOutMode;
uint8_t BootPhases;
uint8_t VRHotLevel;
uint8_t LdoRefSel;
uint8_t Reserved1[2];
uint16_t FanStartTemperature;
uint16_t FanStopTemperature;
uint16_t MaxVoltage;
uint16_t Reserved2;
uint32_t Reserved;
SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS];
SMU75_Discrete_MemoryLevel MemoryACPILevel;
SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY];
SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK];
SMU75_Discrete_ACPILevel ACPILevel;
SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD];
SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE];
SMU75_Discrete_ExtClkLevel AcpLevel [SMU75_MAX_LEVELS_ACP];
SMU75_Discrete_ExtClkLevel SamuLevel [SMU75_MAX_LEVELS_SAMU];
SMU75_Discrete_Ulv Ulv;
uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS];
uint32_t SclkStepSize;
uint32_t Smio [SMU75_MAX_ENTRIES_SMIO];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint16_t BootMVdd;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t BAPMTI_R [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
uint16_t BAPMTI_RC [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
uint16_t TemperatureLimitEdge;
uint16_t TemperatureLimitHotspot;
uint16_t BootVddc;
uint16_t BootVddci;
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint8_t ClockStretcherAmount;
uint8_t Sclk_CKS_masterEn0_7;
uint8_t Sclk_CKS_masterEn8_15;
uint8_t DPMFreezeAndForced;
uint8_t Sclk_voltageOffset[8];
SMU_ClockStretcherDataTable ClockStretcherDataTable;
SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
uint32_t CurrSclkPllRange;
sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
SMU_QuadraticCoeffs AVFSGB_FUSE_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
};
typedef struct SMU75_Discrete_DpmTable SMU75_Discrete_DpmTable;
struct SMU75_Discrete_FanTable {
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t Padding;
};
typedef struct SMU75_Discrete_FanTable SMU75_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU7_MclkDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t padding2;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t IgnoreVBlank;
uint8_t TargetMclkIndex;
uint8_t TargetMvddIndex;
uint8_t MclkSwitchResult;
uint16_t VbiFailureCount;
uint8_t VbiWaitCounter;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t VbiTimeoutCount;
uint16_t MclkSwitchingTime;
uint8_t fastSwitch;
uint8_t Save_PIC_VDDGFX_EXIT;
uint8_t Save_PIC_VDDGFX_ENTER;
uint8_t VbiTimeout;
uint32_t HbmTempRegBackup;
};
typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
struct SMU7_UlvScoreboard {
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
struct VddgfxSavedRegisters {
uint32_t GPU_DBG[3];
uint32_t MEC_BaseAddress_Hi;
uint32_t MEC_BaseAddress_Lo;
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
uint32_t CP_INT_CNTL;
};
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
struct SMU7_VddGfxScoreboard {
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t VPUResetOccured;
uint8_t padding;
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
uint32_t VddGfxVid;
VddgfxSavedRegisters SavedRegisters;
};
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
struct SMU7_TdcLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredIddc;
uint32_t IddcLimit;
uint32_t IddcHyst;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
struct SMU7_PkgPwrLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredPkgPwr;
uint32_t Limit;
uint32_t Hyst;
uint32_t LimitFromDriver;
uint8_t PowerSharingEnabled;
uint8_t PowerSharingCounter;
uint8_t PowerSharingINTEnabled;
uint8_t GFXActivityCounterEnabled;
uint32_t EnergyCount;
uint32_t PSACTCount;
uint8_t RollOverRequired;
uint8_t RollOverCount;
uint8_t padding[2];
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
struct SMU7_BapmScoreboard {
uint32_t source_powers[SMU75_DTE_SOURCES];
uint32_t source_powers_last[SMU75_DTE_SOURCES];
int32_t entity_temperatures[SMU75_NUM_GPU_TES];
int32_t initial_entity_temperatures[SMU75_NUM_GPU_TES];
int32_t Limit;
int32_t Hyst;
int32_t therm_influence_coeff_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS * 2];
int32_t therm_node_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
uint16_t ConfigTDPPowerScalar;
uint16_t FanSpeedPowerScalar;
uint16_t OverDrivePowerScalar;
uint16_t OverDriveLimitScalar;
uint16_t FinalPowerScalar;
uint8_t VariantID;
uint8_t spare997;
SMU7_HystController_Data HystControllerData;
int32_t temperature_gradient_slope;
int32_t temperature_gradient;
uint32_t measured_temperature;
};
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
struct SMU7_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU75_Discrete_ACPILevel D0Level;
};
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
struct SMU75_Discrete_PmFuses {
uint8_t BapmVddCVidHiSidd[8];
uint8_t BapmVddCVidLoSidd[8];
uint8_t VddCVid[8];
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
uint8_t LPMLTemperatureScaler[16];
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
uint8_t GnbLPML[16];
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
uint16_t VFT_Temp[3];
uint8_t Version;
uint8_t padding;
SMU_QuadraticCoeffs VFT_ATE[3];
SMU_QuadraticCoeffs AVFS_GB;
SMU_QuadraticCoeffs ATE_ACBTC_GB;
SMU_QuadraticCoeffs P2V;
uint32_t PsmCharzFreq;
uint16_t InversionVoltage;
uint16_t PsmCharzTemp;
uint32_t EnabledAvfsModules;
SMU_QuadraticCoeffs BtcGbv_CksOff;
};
typedef struct SMU75_Discrete_PmFuses SMU75_Discrete_PmFuses;
struct SMU7_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
struct SMU7_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
#if defined SMU__DGPU_ONLY
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
#endif
struct SMU7_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
};
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
struct SMU7_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[4];
uint32_t temperature;
};
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
struct SMU7_Discrete_Pm_Status_Table {
int32_t T_meas_max[SMU75_THERMAL_INPUT_LOOP_COUNT];
int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
uint32_t I_calc_max;
uint32_t I_calc_acc;
uint32_t P_meas_acc;
uint32_t V_meas_load_acc;
uint32_t I_meas_acc;
uint32_t P_meas_acc_vddci;
uint32_t V_meas_load_acc_vddci;
uint32_t I_meas_acc_vddci;
uint16_t Sclk_dpm_residency[8];
uint16_t Uvd_dpm_residency[8];
uint16_t Vce_dpm_residency[8];
uint16_t Mclk_dpm_residency[4];
uint32_t P_roc_acc;
uint32_t PkgPwr_max;
uint32_t PkgPwr_acc;
uint32_t MclkSwitchingTime_max;
uint32_t MclkSwitchingTime_acc;
uint32_t FanPwm_acc;
uint32_t FanRpm_acc;
uint32_t Gfx_busy_acc;
uint32_t Mc_busy_acc;
uint32_t Fps_acc;
uint32_t AccCnt;
};
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
struct SMU7_Discrete_AutoWattMan_Status_Table {
int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
uint16_t Sclk_dpm_residency[8];
uint16_t Mclk_dpm_residency[4];
uint32_t TgpPwr_acc;
uint32_t Gfx_busy_acc;
uint32_t Mc_busy_acc;
uint32_t AccCnt;
};
typedef struct SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_AutoWattMan_Status_Table;
#define SMU7_MAX_GFX_CU_COUNT 24
#define SMU7_MIN_GFX_CU_COUNT 8
#define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT 0
#define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT)
#define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT 16
#define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT)
struct SMU7_GfxCuPgScoreboard {
uint8_t Enabled;
uint8_t WaterfallUp;
uint8_t WaterfallDown;
uint8_t WaterfallLimit;
uint8_t CurrMaxCu;
uint8_t TargMaxCu;
uint8_t ClampMode;
uint8_t Active;
uint8_t MaxSupportedCu;
uint8_t MinSupportedCu;
uint8_t PendingGfxCuHostInterrupt;
uint8_t LastFilteredMaxCuInteger;
uint16_t FilteredMaxCu;
uint16_t FilteredMaxCuAlpha;
uint16_t FilterResetCount;
uint16_t FilterResetCountLimit;
uint8_t ForceCu;
uint8_t ForceCuCount;
uint8_t AcModeMaxCu;
uint8_t DcModeMaxCu;
};
typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
#define SMU7_SCLK_CAC 0x561
#define SMU7_MCLK_CAC 0xF9
#define SMU7_VCLK_CAC 0x2DE
#define SMU7_DCLK_CAC 0x2DE
#define SMU7_ECLK_CAC 0x25E
#define SMU7_ACLK_CAC 0x25E
#define SMU7_SAMCLK_CAC 0x25E
#define SMU7_DISPCLK_CAC 0x100
#define SMU7_CAC_CONSTANT 0x2EE3430
#define SMU7_CAC_CONSTANT_SHIFT 18
#define SMU7_VDDCI_MCLK_CONST 1765
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
#define SMU7_VDDCI_VDDCI_CONST 50958
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
#define SMU7_VDDCI_CONST 11781
#define SMU7_VDDCI_STROBE_PWR 1331
#define SMU7_VDDR1_CONST 693
#define SMU7_VDDR1_CAC_WEIGHT 20
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
#define SMU7_VDDR1_STROBE_PWR 512
#define SMU7_AREA_COEFF_UVD 0xA78
#define SMU7_AREA_COEFF_VCE 0x190A
#define SMU7_AREA_COEFF_ACP 0x22D1
#define SMU7_AREA_COEFF_SAMU 0x534
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
#define SQ_Enable_MASK 0x1
#define SQ_IR_MASK 0x2
#define SQ_PCC_MASK 0x4
#define SQ_EDC_MASK 0x8
#define TCP_Enable_MASK 0x100
#define TCP_IR_MASK 0x200
#define TCP_PCC_MASK 0x400
#define TCP_EDC_MASK 0x800
#define TD_Enable_MASK 0x10000
#define TD_IR_MASK 0x20000
#define TD_PCC_MASK 0x40000
#define TD_EDC_MASK 0x80000
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
#define SQ_IR_SHIFT 1
#define SQ_PCC_SHIFT 2
#define SQ_EDC_SHIFT 3
#define TCP_Enable_SHIFT 8
#define TCP_IR_SHIFT 9
#define TCP_PCC_SHIFT 10
#define TCP_EDC_SHIFT 11
#define TD_Enable_SHIFT 16
#define TD_IR_SHIFT 17
#define TD_PCC_SHIFT 18
#define TD_EDC_SHIFT 19
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#define PMFUSES_AVFSSIZE 104
#define BTCGB0_Vdroop_Enable_MASK 0x1
#define BTCGB1_Vdroop_Enable_MASK 0x2
#define AVFSGB0_Vdroop_Enable_MASK 0x4
#define AVFSGB1_Vdroop_Enable_MASK 0x8
#define BTCGB0_Vdroop_Enable_SHIFT 0
#define BTCGB1_Vdroop_Enable_SHIFT 1
#define AVFSGB0_Vdroop_Enable_SHIFT 2
#define AVFSGB1_Vdroop_Enable_SHIFT 3
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu7_common.h
+54
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@@ -0,0 +1,54 @@
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _PP_COMMON_H
#define _PP_COMMON_H
#include "smu7_ppsmc.h"
#include "cgs_common.h"
#include "smu/smu_7_1_3_d.h"
#include "smu/smu_7_1_3_sh_mask.h"
#include "smu74.h"
#include "smu74_discrete.h"
#include "gmc/gmc_8_1_d.h"
#include "gmc/gmc_8_1_sh_mask.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
#include "gca/gfx_8_0_d.h"
#include "gca/gfx_8_0_sh_mask.h"
#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h
+515
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@@ -0,0 +1,515 @@
/*
* Copyright 2013 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU7_DISCRETE_H
#define SMU7_DISCRETE_H
#include "smu7.h"
#pragma pack(push, 1)
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 3
#define SMU7_DTE_SINKS 1
#define SMU7_NUM_CPU_TES 0
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
struct SMU7_SoftRegisters
{
uint32_t RefClockFrequency;
uint32_t PmTimerP;
uint32_t FeatureEnables;
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsA;
uint32_t AverageMemoryA;
uint32_t AverageGioA;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterC;
uint32_t UlvTime;
uint32_t Reserved[3];
};
typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
struct SMU7_Discrete_VoltageLevel
{
uint16_t Voltage;
uint16_t StdVoltageHiSidd;
uint16_t StdVoltageLoSidd;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
struct SMU7_Discrete_GraphicsLevel
{
uint32_t Flags;
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t SclkFrequency;
uint8_t padding1[2];
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpH;
uint8_t DownH;
uint8_t VoltageDownH;
uint8_t PowerThrottle;
uint8_t DeepSleepDivId;
uint8_t padding[3];
};
typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
struct SMU7_Discrete_ACPILevel
{
uint32_t Flags;
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CgSpllFuncCntl;
uint32_t CgSpllFuncCntl2;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
};
typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
struct SMU7_Discrete_Ulv
{
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint32_t Reserved;
};
typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
struct SMU7_Discrete_MemoryLevel
{
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t MinVddci;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t EdcReadEnable;
uint8_t EdcWriteEnable;
uint8_t RttEnable;
uint8_t StutterEnable;
uint8_t StrobeEnable;
uint8_t StrobeRatio;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t UpH;
uint8_t DownH;
uint8_t VoltageDownH;
uint8_t padding;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t padding1;
uint32_t MpllFuncCntl;
uint32_t MpllFuncCntl_1;
uint32_t MpllFuncCntl_2;
uint32_t MpllAdFuncCntl;
uint32_t MpllDqFuncCntl;
uint32_t MclkPwrmgtCntl;
uint32_t DllCntl;
uint32_t MpllSs1;
uint32_t MpllSs2;
};
typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
struct SMU7_Discrete_LinkLevel
{
uint8_t PcieGenSpeed;
uint8_t PcieLaneCount;
uint8_t EnabledForActivity;
uint8_t Padding;
uint32_t DownT;
uint32_t UpT;
uint32_t Reserved;
};
typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
struct SMU7_Discrete_MCArbDramTimingTableEntry
{
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t padding[3];
};
typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
struct SMU7_Discrete_MCArbDramTimingTable
{
SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
struct SMU7_Discrete_UvdLevel
{
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint16_t MinVddc;
uint8_t MinVddcPhases;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[3];
};
typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
struct SMU7_Discrete_ExtClkLevel
{
uint32_t Frequency;
uint16_t MinVoltage;
uint8_t MinPhases;
uint8_t Divider;
};
typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
struct SMU7_Discrete_StateInfo
{
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
struct SMU7_Discrete_DpmTable
{
SMU7_PIDController GraphicsPIDController;
SMU7_PIDController MemoryPIDController;
SMU7_PIDController LinkPIDController;
uint32_t SystemFlags;
uint32_t SmioMaskVddcVid;
uint32_t SmioMaskVddcPhase;
uint32_t SmioMaskVddciVid;
uint32_t SmioMaskMvddVid;
uint32_t VddcLevelCount;
uint32_t VddciLevelCount;
uint32_t MvddLevelCount;
SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC];
// SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC];
SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI];
SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t MasterDeepSleepControl;
uint32_t VRConfig;
uint32_t Reserved[4];
// uint32_t SamuDefaultLevel;
SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
SMU7_Discrete_MemoryLevel MemoryACPILevel;
SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY];
SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
SMU7_Discrete_ACPILevel ACPILevel;
SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU];
SMU7_Discrete_Ulv Ulv;
uint32_t SclkStepSize;
uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t UVDInterval;
uint8_t VCEInterval;
uint8_t ACPInterval;
uint8_t SAMUInterval;
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint16_t VddcVddciDelta;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
uint16_t FpsHighT;
uint16_t FpsLowT;
uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
uint16_t BootVddc;
uint16_t BootVddci;
uint16_t BootMVdd;
uint16_t padding;
uint32_t BAPM_TEMP_GRADIENT;
uint32_t LowSclkInterruptT;
};
typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
struct SMU7_Discrete_MCRegisterAddress
{
uint16_t s0;
uint16_t s1;
};
typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
struct SMU7_Discrete_MCRegisterSet
{
uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
struct SMU7_Discrete_MCRegisters
{
uint8_t last;
uint8_t reserved[3];
SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
};
typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
struct SMU7_Discrete_FanTable
{
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t Padding;
};
typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
struct SMU7_Discrete_PmFuses {
// dw0-dw1
uint8_t BapmVddCVidHiSidd[8];
// dw2-dw3
uint8_t BapmVddCVidLoSidd[8];
// dw4-dw5
uint8_t VddCVid[8];
// dw6
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
// dw7
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
// dw8
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
// dw9-dw10
uint8_t BapmVddCVidHiSidd2[8];
// dw11-dw12
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t CalcMeasPowerBlend;
// dw13-dw16
uint8_t GnbLPML[16];
// dw17
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
// dw18
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
};
typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h
+290
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@@ -0,0 +1,290 @@
/*
* Copyright 2013 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU7_FUSION_H
#define SMU7_FUSION_H
#include "smu7.h"
#pragma pack(push, 1)
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
// All 'soft registers' should be uint32_t.
struct SMU7_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerP;
uint32_t FeatureEnables;
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsA;
uint32_t AverageMemoryA;
uint32_t AverageGioA;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterC;
uint32_t UlvTime;
uint32_t Reserved[3];
};
typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
struct SMU7_Fusion_GraphicsLevel {
uint32_t MinVddNb;
uint32_t SclkFrequency;
uint8_t Vid;
uint8_t VidOffset;
uint16_t AT;
uint8_t PowerThrottle;
uint8_t GnbSlow;
uint8_t ForceNbPs1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpH;
uint8_t DownH;
uint8_t VoltageDownH;
uint8_t DeepSleepDivId;
uint8_t ClkBypassCntl;
uint32_t reserved;
};
typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
struct SMU7_Fusion_GIOLevel {
uint8_t EnabledForActivity;
uint8_t LclkDid;
uint8_t Vid;
uint8_t VoltageDownH;
uint32_t MinVddNb;
uint16_t ResidencyCounter;
uint8_t UpH;
uint8_t DownH;
uint32_t LclkFrequency;
uint8_t ActivityLevel;
uint8_t EnabledForThrottle;
uint8_t ClkBypassCntl;
uint8_t padding;
};
typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
// UVD VCLK/DCLK state (level) definition.
struct SMU7_Fusion_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint16_t MinVddNb;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t VClkBypassCntl;
uint8_t DClkBypassCntl;
uint8_t padding[2];
};
typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
// Clocks for other external blocks (VCE, ACP, SAMU).
struct SMU7_Fusion_ExtClkLevel {
uint32_t Frequency;
uint16_t MinVoltage;
uint8_t Divider;
uint8_t ClkBypassCntl;
uint32_t Reserved;
};
typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
struct SMU7_Fusion_ACPILevel {
uint32_t Flags;
uint32_t MinVddNb;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t GnbSlow;
uint8_t ForceNbPs1;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding[3];
};
typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
struct SMU7_Fusion_NbDpm {
uint8_t DpmXNbPsHi;
uint8_t DpmXNbPsLo;
uint8_t Dpm0PgNbPsHi;
uint8_t Dpm0PgNbPsLo;
uint8_t EnablePsi1;
uint8_t SkipDPM0;
uint8_t SkipPG;
uint8_t Hysteresis;
uint8_t EnableDpmPstatePoll;
uint8_t padding[3];
};
typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
struct SMU7_Fusion_StateInfo {
uint32_t SclkFrequency;
uint32_t LclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
int8_t SclkIndex;
int8_t MclkIndex;
};
typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
struct SMU7_Fusion_DpmTable {
uint32_t SystemFlags;
SMU7_PIDController GraphicsPIDController;
SMU7_PIDController GioPIDController;
uint8_t GraphicsDpmLevelCount;
uint8_t GIOLevelCount;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint16_t FpsHighT;
SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];
SMU7_Fusion_ACPILevel ACPILevel;
SMU7_Fusion_UvdLevel UvdLevel[SMU7_MAX_LEVELS_UVD];
SMU7_Fusion_ExtClkLevel VceLevel[SMU7_MAX_LEVELS_VCE];
SMU7_Fusion_ExtClkLevel AcpLevel[SMU7_MAX_LEVELS_ACP];
SMU7_Fusion_ExtClkLevel SamuLevel[SMU7_MAX_LEVELS_SAMU];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t UVDInterval;
uint8_t VCEInterval;
uint8_t ACPInterval;
uint8_t SAMUInterval;
uint8_t GraphicsBootLevel;
uint8_t GraphicsInterval;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsClkSlowEnable;
uint8_t GraphicsClkSlowDivider;
uint16_t FpsLowT;
uint32_t DisplayCac;
uint32_t LowSclkInterruptT;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
};
struct SMU7_Fusion_GIODpmTable {
SMU7_Fusion_GIOLevel GIOLevel[SMU7_MAX_LEVELS_GIO];
SMU7_PIDController GioPIDController;
uint32_t GIOLevelCount;
uint8_t Enable;
uint8_t GIOVoltageChangeEnable;
uint8_t GIOBootLevel;
uint8_t padding;
uint8_t padding1[2];
uint8_t TargetState;
uint8_t CurrenttState;
uint8_t ThrottleOnHtc;
uint8_t ThermThrottleStatus;
uint8_t ThermThrottleTempSelect;
uint8_t ThermThrottleEnable;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
};
typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu7_ppsmc.h
+427
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@@ -0,0 +1,427 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef DGPU_VI_PP_SMC_H
#define DGPU_VI_PP_SMC_H
#pragma pack(push, 1)
#define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
#define PPSMC_SWSTATE_FLAG_DC 0x01
#define PPSMC_SWSTATE_FLAG_UVD 0x02
#define PPSMC_SWSTATE_FLAG_VCE 0x04
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
#define PPSMC_DPM2FLAGS_OCP 0x04
#define PPSMC_DISPLAY_WATERMARK_LOW 0
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
#define PPSMC_STATEFLAG_POWERBOOST 0x02
#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
#define PPSMC_STATEFLAG_POWERSHIFT 0x08
#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
#define FDO_MODE_HARDWARE 0
#define FDO_MODE_PIECE_WISE_LINEAR 1
enum FAN_CONTROL {
FAN_CONTROL_FUZZY,
FAN_CONTROL_TABLE
};
#define PPSMC_Result_OK ((uint16_t)0x01)
#define PPSMC_Result_NoMore ((uint16_t)0x02)
#define PPSMC_Result_NotNow ((uint16_t)0x03)
#define PPSMC_Result_Failed ((uint16_t)0xFF)
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
typedef uint16_t PPSMC_Result;
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
#define PPSMC_MSG_Halt ((uint16_t)0x10)
#define PPSMC_MSG_Resume ((uint16_t)0x11)
#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
#define PPSMC_CACHistoryStart ((uint16_t)0x57)
#define PPSMC_CACHistoryStop ((uint16_t)0x58)
#define PPSMC_TDPClampingActive ((uint16_t)0x59)
#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
#define PPSMC_StartFanControl ((uint16_t)0x5B)
#define PPSMC_StopFanControl ((uint16_t)0x5C)
#define PPSMC_NoDisplay ((uint16_t)0x5D)
#define PPSMC_HasDisplay ((uint16_t)0x5E)
#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
#define PPSMC_OCPActive ((uint16_t)0x6C)
#define PPSMC_OCPInactive ((uint16_t)0x6D)
#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
#define PPSMC_FlushDataCache ((uint16_t)0x80)
#define PPSMC_FlushInstrCache ((uint16_t)0x81)
#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
#define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A)
#define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B)
#define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C)
#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
#define PPSMC_MSG_Test ((uint16_t) 0x100)
#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)
#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127)
#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e)
#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f)
#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150)
#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151)
#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152)
#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153)
#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154)
#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155)
#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156)
#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157)
#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158)
#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159)
#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a)
#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b)
#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c)
#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c)
#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d)
#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e)
#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f)
#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170)
#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171)
#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A)
#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B)
#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C)
#define PPSMC_MSG_LedConfig ((uint16_t) 0x274)
#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275)
#define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277)
#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400)
#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401)
#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402)
#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)
#define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280)
#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281)
#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282)
#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)
#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)
#define PPSMC_MSG_EnableZeroRpm ((uint16_t) 0x302)
#define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306)
#define PPSMC_MSG_EnableFFC ((uint16_t) 0x307)
#define PPSMC_MSG_DisableFFC ((uint16_t) 0x308)
#define PPSMC_MSG_EnableDpmDidt ((uint16_t) 0x309)
#define PPSMC_MSG_DisableDpmDidt ((uint16_t) 0x30A)
#define PPSMC_MSG_EnableDpmMcBlackout ((uint16_t) 0x30B)
#define PPSMC_MSG_DisableDpmMcBlackout ((uint16_t) 0x30C)
#define PPSMC_MSG_EnableEDCController ((uint16_t) 0x316)
#define PPSMC_MSG_DisableEDCController ((uint16_t) 0x317)
#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)
#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)
#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)
#define PPSMC_MSG_GetData ((uint16_t) 0x801)
#define PPSMC_MSG_SetData ((uint16_t) 0x802)
typedef uint16_t PPSMC_Msg;
#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
#define PPSMC_EVENT_STATUS_DC 0x00000004
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu8.h
+72
View File
@@ -0,0 +1,72 @@
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU8_H
#define SMU8_H
#pragma pack(push, 1)
#define ENABLE_DEBUG_FEATURES
struct SMU8_Firmware_Header {
uint32_t Version;
uint32_t ImageSize;
uint32_t CodeSize;
uint32_t HeaderSize;
uint32_t EntryPoint;
uint32_t Rtos;
uint32_t UcodeLoadStatus;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t Reserved[20];
uint32_t Signature;
};
struct SMU8_MultimediaPowerLogData {
uint32_t avgTotalPower;
uint32_t avgGpuPower;
uint32_t avgUvdPower;
uint32_t avgVcePower;
uint32_t avgSclk;
uint32_t avgDclk;
uint32_t avgVclk;
uint32_t avgEclk;
uint32_t startTimeHi;
uint32_t startTimeLo;
uint32_t endTimeHi;
uint32_t endTimeLo;
};
#define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
#define SMU8_UNBCSR_START_ADDR 0xC0100000
#define SMN_MP1_SRAM_START_ADDR 0x10000000
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h
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/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU8_FUSION_H
#define SMU8_FUSION_H
#include "smu8.h"
#pragma pack(push, 1)
#define SMU8_MAX_CUS 2
#define SMU8_PSMS_PER_CU 4
#define SMU8_CACS_PER_CU 4
struct SMU8_GfxCuPgScoreboard {
uint8_t Enabled;
uint8_t spare[3];
};
struct SMU8_Port80MonitorTable {
uint32_t MmioAddress;
uint32_t MemoryBaseHi;
uint32_t MemoryBaseLo;
uint16_t MemoryBufferSize;
uint16_t MemoryPosition;
uint16_t PollingInterval;
uint8_t EnableCsrShadow;
uint8_t EnableDramShadow;
};
/* Display specific power management parameters */
#define PWRMGT_SEPARATION_TIME_SHIFT 0
#define PWRMGT_SEPARATION_TIME_MASK 0xFFFF
#define PWRMGT_DISABLE_CPU_CSTATES_SHIFT 16
#define PWRMGT_DISABLE_CPU_CSTATES_MASK 0x1
#define PWRMGT_DISABLE_CPU_PSTATES_SHIFT 24
#define PWRMGT_DISABLE_CPU_PSTATES_MASK 0x1
/* Clock Table Definitions */
#define NUM_SCLK_LEVELS 8
#define NUM_LCLK_LEVELS 8
#define NUM_UVD_LEVELS 8
#define NUM_ECLK_LEVELS 8
#define NUM_ACLK_LEVELS 8
struct SMU8_Fusion_ClkLevel {
uint8_t GnbVid;
uint8_t GfxVid;
uint8_t DfsDid;
uint8_t DeepSleepDid;
uint32_t DfsBypass;
uint32_t Frequency;
};
struct SMU8_Fusion_SclkBreakdownTable {
struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
struct SMU8_Fusion_ClkLevel DpmOffLevel;
/* SMU8_Fusion_ClkLevel PwrOffLevel; */
uint32_t SclkValidMask;
uint32_t MaxSclkIndex;
};
struct SMU8_Fusion_LclkBreakdownTable {
struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
struct SMU8_Fusion_ClkLevel DpmOffLevel;
/* SMU8_Fusion_ClkLevel PwrOffLevel; */
uint32_t LclkValidMask;
uint32_t MaxLclkIndex;
};
struct SMU8_Fusion_EclkBreakdownTable {
struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
struct SMU8_Fusion_ClkLevel DpmOffLevel;
struct SMU8_Fusion_ClkLevel PwrOffLevel;
uint32_t EclkValidMask;
uint32_t MaxEclkIndex;
};
struct SMU8_Fusion_VclkBreakdownTable {
struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
struct SMU8_Fusion_ClkLevel DpmOffLevel;
struct SMU8_Fusion_ClkLevel PwrOffLevel;
uint32_t VclkValidMask;
uint32_t MaxVclkIndex;
};
struct SMU8_Fusion_DclkBreakdownTable {
struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
struct SMU8_Fusion_ClkLevel DpmOffLevel;
struct SMU8_Fusion_ClkLevel PwrOffLevel;
uint32_t DclkValidMask;
uint32_t MaxDclkIndex;
};
struct SMU8_Fusion_AclkBreakdownTable {
struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
struct SMU8_Fusion_ClkLevel DpmOffLevel;
struct SMU8_Fusion_ClkLevel PwrOffLevel;
uint32_t AclkValidMask;
uint32_t MaxAclkIndex;
};
struct SMU8_Fusion_ClkTable {
struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
};
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu9.h
+148
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU9_H
#define SMU9_H
#pragma pack(push, 1)
#define ENABLE_DEBUG_FEATURES
/* Feature Control Defines */
#define FEATURE_DPM_PREFETCHER_BIT 0
#define FEATURE_DPM_GFXCLK_BIT 1
#define FEATURE_DPM_UCLK_BIT 2
#define FEATURE_DPM_SOCCLK_BIT 3
#define FEATURE_DPM_UVD_BIT 4
#define FEATURE_DPM_VCE_BIT 5
#define FEATURE_ULV_BIT 6
#define FEATURE_DPM_MP0CLK_BIT 7
#define FEATURE_DPM_LINK_BIT 8
#define FEATURE_DPM_DCEFCLK_BIT 9
#define FEATURE_AVFS_BIT 10
#define FEATURE_DS_GFXCLK_BIT 11
#define FEATURE_DS_SOCCLK_BIT 12
#define FEATURE_DS_LCLK_BIT 13
#define FEATURE_PPT_BIT 14
#define FEATURE_TDC_BIT 15
#define FEATURE_THERMAL_BIT 16
#define FEATURE_GFX_PER_CU_CG_BIT 17
#define FEATURE_RM_BIT 18
#define FEATURE_DS_DCEFCLK_BIT 19
#define FEATURE_ACDC_BIT 20
#define FEATURE_VR0HOT_BIT 21
#define FEATURE_VR1HOT_BIT 22
#define FEATURE_FW_CTF_BIT 23
#define FEATURE_LED_DISPLAY_BIT 24
#define FEATURE_FAN_CONTROL_BIT 25
#define FEATURE_FAST_PPT_BIT 26
#define FEATURE_GFX_EDC_BIT 27
#define FEATURE_ACG_BIT 28
#define FEATURE_PCC_LIMIT_CONTROL_BIT 29
#define FEATURE_SPARE_30_BIT 30
#define FEATURE_SPARE_31_BIT 31
#define NUM_FEATURES 32
#define FFEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
#define FFEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
#define FFEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
#define FFEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
#define FFEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
#define FFEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
#define FFEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
#define FFEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
#define FFEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
#define FFEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
#define FFEATURE_AVFS_MASK (1 << FEATURE_AVFS_BIT )
#define FFEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
#define FFEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
#define FFEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
#define FFEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
#define FFEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
#define FFEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
#define FFEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
#define FFEATURE_RM_MASK (1 << FEATURE_RM_BIT )
#define FFEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
#define FFEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
#define FFEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
#define FFEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
#define FFEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
#define FFEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
#define FFEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
#define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT )
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT )
#define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT )
#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
/* Workload types */
#define WORKLOAD_VR_BIT 0
#define WORKLOAD_FRTC_BIT 1
#define WORKLOAD_VIDEO_BIT 2
#define WORKLOAD_COMPUTE_BIT 3
#define NUM_WORKLOADS 4
/* ULV Client Masks */
#define ULV_CLIENT_RLC_MASK 0x00000001
#define ULV_CLIENT_UVD_MASK 0x00000002
#define ULV_CLIENT_VCE_MASK 0x00000004
#define ULV_CLIENT_SDMA0_MASK 0x00000008
#define ULV_CLIENT_SDMA1_MASK 0x00000010
#define ULV_CLIENT_JPEG_MASK 0x00000020
#define ULV_CLIENT_GFXCLK_DPM_MASK 0x00000040
#define ULV_CLIENT_UVD_DPM_MASK 0x00000080
#define ULV_CLIENT_VCE_DPM_MASK 0x00000100
#define ULV_CLIENT_MP0CLK_DPM_MASK 0x00000200
#define ULV_CLIENT_UCLK_DPM_MASK 0x00000400
#define ULV_CLIENT_SOCCLK_DPM_MASK 0x00000800
#define ULV_CLIENT_DCEFCLK_DPM_MASK 0x00001000
typedef struct {
/* MP1_EXT_SCRATCH0 */
uint32_t CurrLevel_GFXCLK : 4;
uint32_t CurrLevel_UVD : 4;
uint32_t CurrLevel_VCE : 4;
uint32_t CurrLevel_LCLK : 4;
uint32_t CurrLevel_MP0CLK : 4;
uint32_t CurrLevel_UCLK : 4;
uint32_t CurrLevel_SOCCLK : 4;
uint32_t CurrLevel_DCEFCLK : 4;
/* MP1_EXT_SCRATCH1 */
uint32_t TargLevel_GFXCLK : 4;
uint32_t TargLevel_UVD : 4;
uint32_t TargLevel_VCE : 4;
uint32_t TargLevel_LCLK : 4;
uint32_t TargLevel_MP0CLK : 4;
uint32_t TargLevel_UCLK : 4;
uint32_t TargLevel_SOCCLK : 4;
uint32_t TargLevel_DCEFCLK : 4;
/* MP1_EXT_SCRATCH2-7 */
uint32_t Reserved[6];
} FwStatus_t;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h
+488
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU9_DRIVER_IF_H
#define SMU9_DRIVER_IF_H
#include "smu9.h"
/**** IMPORTANT ***
* SMU TEAM: Always increment the interface version if
* any structure is changed in this file
*/
#define SMU9_DRIVER_IF_VERSION 0xE
#define PPTABLE_V10_SMU_VERSION 1
#define NUM_GFXCLK_DPM_LEVELS 8
#define NUM_UVD_DPM_LEVELS 8
#define NUM_VCE_DPM_LEVELS 8
#define NUM_MP0CLK_DPM_LEVELS 8
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_SOCCLK_DPM_LEVELS 8
#define NUM_DCEFCLK_DPM_LEVELS 8
#define NUM_LINK_LEVELS 2
#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
#define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
#define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
#define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
#define MIN_GFXCLK_DPM_LEVEL 0
#define MIN_UVD_DPM_LEVEL 0
#define MIN_VCE_DPM_LEVEL 0
#define MIN_MP0CLK_DPM_LEVEL 0
#define MIN_UCLK_DPM_LEVEL 0
#define MIN_SOCCLK_DPM_LEVEL 0
#define MIN_DCEFCLK_DPM_LEVEL 0
#define MIN_LINK_DPM_LEVEL 0
#define NUM_EVV_VOLTAGE_LEVELS 8
#define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
#define MIN_EVV_VOLTAGE_LEVEL 0
#define NUM_PSP_LEVEL_MAP 4
/* Gemini Modes */
#define PPSMC_GeminiModeNone 0 /* Single GPU board */
#define PPSMC_GeminiModeMaster 1 /* Master GPU on a Gemini board */
#define PPSMC_GeminiModeSlave 2 /* Slave GPU on a Gemini board */
/* Voltage Modes for DPMs */
#define VOLTAGE_MODE_AVFS_INTERPOLATE 0
#define VOLTAGE_MODE_AVFS_WORST_CASE 1
#define VOLTAGE_MODE_STATIC 2
typedef struct {
uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
uint16_t SsSlewFrac;
uint8_t SsOn;
uint8_t Did; /* DID */
} PllSetting_t;
typedef struct {
int32_t a0;
int32_t a1;
int32_t a2;
uint8_t a0_shift;
uint8_t a1_shift;
uint8_t a2_shift;
uint8_t padding;
} GbVdroopTable_t;
typedef struct {
int32_t m1;
int32_t m2;
int32_t b;
uint8_t m1_shift;
uint8_t m2_shift;
uint8_t b_shift;
uint8_t padding;
} QuadraticInt_t;
#define NUM_DSPCLK_LEVELS 8
typedef enum {
DSPCLK_DCEFCLK = 0,
DSPCLK_DISPCLK,
DSPCLK_PIXCLK,
DSPCLK_PHYCLK,
DSPCLK_COUNT,
} DSPCLK_e;
typedef struct {
uint16_t Freq; /* in MHz */
uint16_t Vid; /* min voltage in SVI2 VID */
} DisplayClockTable_t;
#pragma pack(push, 1)
typedef struct {
/* PowerTune */
uint16_t SocketPowerLimit; /* Watts */
uint16_t TdcLimit; /* Amps */
uint16_t EdcLimit; /* Amps */
uint16_t TedgeLimit; /* Celcius */
uint16_t ThotspotLimit; /* Celcius */
uint16_t ThbmLimit; /* Celcius */
uint16_t Tvr_socLimit; /* Celcius */
uint16_t Tvr_memLimit; /* Celcius */
uint16_t Tliquid1Limit; /* Celcius */
uint16_t Tliquid2Limit; /* Celcius */
uint16_t TplxLimit; /* Celcius */
uint16_t LoadLineResistance; /* in mOhms */
uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */
/* External Component Communication Settings */
uint8_t Liquid1_I2C_address;
uint8_t Liquid2_I2C_address;
uint8_t Vr_I2C_address;
uint8_t Plx_I2C_address;
uint8_t GeminiMode;
uint8_t spare17[3];
uint32_t GeminiApertureHigh;
uint32_t GeminiApertureLow;
uint8_t Liquid_I2C_LineSCL;
uint8_t Liquid_I2C_LineSDA;
uint8_t Vr_I2C_LineSCL;
uint8_t Vr_I2C_LineSDA;
uint8_t Plx_I2C_LineSCL;
uint8_t Plx_I2C_LineSDA;
uint8_t paddingx[2];
/* ULV Settings */
uint8_t UlvOffsetVid; /* SVI2 VID */
uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
/* VDDCR_SOC Voltages */
uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS];
/* This is the minimum voltage needed to run the SOC. */
uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
uint8_t MaxVoltageVid; /* Maximum Voltage allowable */
uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
uint8_t padding8;
uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
uint8_t padding8_2[2];
/* SOC Frequencies */
PllSetting_t GfxclkLevel[NUM_GFXCLK_DPM_LEVELS];
uint8_t SocclkDid[NUM_SOCCLK_DPM_LEVELS]; /* DID */
uint8_t SocDpmVoltageIndex[NUM_SOCCLK_DPM_LEVELS];
uint8_t VclkDid[NUM_UVD_DPM_LEVELS]; /* DID */
uint8_t DclkDid[NUM_UVD_DPM_LEVELS]; /* DID */
uint8_t UvdDpmVoltageIndex[NUM_UVD_DPM_LEVELS];
uint8_t EclkDid[NUM_VCE_DPM_LEVELS]; /* DID */
uint8_t VceDpmVoltageIndex[NUM_VCE_DPM_LEVELS];
uint8_t Mp0clkDid[NUM_MP0CLK_DPM_LEVELS]; /* DID */
uint8_t Mp0DpmVoltageIndex[NUM_MP0CLK_DPM_LEVELS];
DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
QuadraticInt_t DisplayClock2Gfxclk[DSPCLK_COUNT];
uint8_t GfxDpmVoltageMode;
uint8_t SocDpmVoltageMode;
uint8_t UclkDpmVoltageMode;
uint8_t UvdDpmVoltageMode;
uint8_t VceDpmVoltageMode;
uint8_t Mp0DpmVoltageMode;
uint8_t DisplayDpmVoltageMode;
uint8_t padding8_3;
uint16_t GfxclkSlewRate;
uint16_t padding;
uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */
/* Alpha parameters for clock averages. ("255"=1) */
uint8_t GfxclkAverageAlpha;
uint8_t SocclkAverageAlpha;
uint8_t UclkAverageAlpha;
uint8_t GfxActivityAverageAlpha;
/* UCLK States */
uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
uint8_t paddingUclk[3];
uint16_t NumMemoryChannels; /* Used for memory bandwidth calculations */
uint16_t MemoryChannelWidth; /* Used for memory bandwidth calculations */
/* CKS Settings */
uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];
uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
/* MP0 Mapping Table */
uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP];
/* Link DPM Settings */
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
uint8_t paddingLinkDpm[2];
/* Fan Control */
uint16_t FanStopTemp; /* Celcius */
uint16_t FanStartTemp; /* Celcius */
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint16_t FanGainLiquid;
uint16_t FanGainVrVddc;
uint16_t FanGainVrMvdd;
uint16_t FanGainPlx;
uint16_t FanGainHbm;
uint16_t FanPwmMin;
uint16_t FanAcousticLimitRpm;
uint16_t FanThrottlingRpm;
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanSpare;
/* The following are AFC override parameters. Leave at 0 to use FW defaults. */
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t FuzzyFan_Reserved;
/* GPIO Settings */
uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */
uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */
uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */
uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */
uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */
uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */
uint8_t Padding1; /* replace GPIO pin configured for CTF */
uint8_t Padding2; /* replace GPIO polarity for CTF */
/* LED Display Settings */
uint8_t LedPin0; /* GPIO number for LedPin[0] */
uint8_t LedPin1; /* GPIO number for LedPin[1] */
uint8_t LedPin2; /* GPIO number for LedPin[2] */
uint8_t padding8_4;
/* AVFS */
uint8_t OverrideBtcGbCksOn;
uint8_t OverrideAvfsGbCksOn;
uint8_t PaddingAvfs8[2];
GbVdroopTable_t BtcGbVdroopTableCksOn;
GbVdroopTable_t BtcGbVdroopTableCksOff;
QuadraticInt_t AvfsGbCksOn; /* Replacement equation */
QuadraticInt_t AvfsGbCksOff; /* Replacement equation */
uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
/* Ageing Guardband Parameters */
uint32_t AConstant[3];
uint16_t DC_tol_sigma;
uint16_t Platform_mean;
uint16_t Platform_sigma;
uint16_t PSM_Age_CompFactor;
uint32_t DpmLevelPowerDelta;
uint8_t EnableBoostState;
uint8_t AConstant_Shift;
uint8_t DC_tol_sigma_Shift;
uint8_t PSM_Age_CompFactor_Shift;
uint16_t BoostStartTemperature;
uint16_t BoostStopTemperature;
PllSetting_t GfxBoostState;
uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS];
GbVdroopTable_t AcgBtcGbVdroopTable;
QuadraticInt_t AcgAvfsGb;
/* ACG Frequency Table, in Mhz */
uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];
/* Padding - ignore */
uint32_t MmHubPadding[3]; /* SMU internal use */
} PPTable_t;
#pragma pack(pop)
typedef struct {
uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Padding[3];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
typedef enum {
WM_SOCCLK = 0,
WM_DCEFCLK,
WM_COUNT,
} WM_CLOCK_e;
typedef struct {
/* Watermarks */
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
uint32_t MmHubPadding[7]; /* SMU internal use */
} Watermarks_t;
#ifdef PPTABLE_V10_SMU_VERSION
typedef struct {
float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
float AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
float AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
float DcBtcGb;
uint32_t MmHubPadding[7]; /* SMU internal use */
} AvfsTable_t;
#else
typedef struct {
uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
uint32_t DcBtcGb;
uint32_t MmHubPadding[7]; /* SMU internal use */
} AvfsTable_t;
#endif
typedef struct {
uint16_t avgPsmCount[30];
uint16_t minPsmCount[30];
float avgPsmVoltage[30];
float minPsmVoltage[30];
uint32_t MmHubPadding[7]; /* SMU internal use */
} AvfsDebugTable_t;
typedef struct {
uint8_t AvfsEn;
uint8_t AvfsVersion;
uint8_t Padding[2];
int32_t VFT0_m1; /* Q8.24 */
int32_t VFT0_m2; /* Q12.12 */
int32_t VFT0_b; /* Q32 */
int32_t VFT1_m1; /* Q8.16 */
int32_t VFT1_m2; /* Q12.12 */
int32_t VFT1_b; /* Q32 */
int32_t VFT2_m1; /* Q8.16 */
int32_t VFT2_m2; /* Q12.12 */
int32_t VFT2_b; /* Q32 */
int32_t AvfsGb0_m1; /* Q8.16 */
int32_t AvfsGb0_m2; /* Q12.12 */
int32_t AvfsGb0_b; /* Q32 */
int32_t AcBtcGb_m1; /* Q8.24 */
int32_t AcBtcGb_m2; /* Q12.12 */
int32_t AcBtcGb_b; /* Q32 */
uint32_t AvfsTempCold;
uint32_t AvfsTempMid;
uint32_t AvfsTempHot;
uint32_t InversionVoltage; /* in mV with 2 fractional bits */
int32_t P2V_m1; /* Q8.24 */
int32_t P2V_m2; /* Q12.12 */
int32_t P2V_b; /* Q32 */
uint32_t P2VCharzFreq; /* in 10KHz units */
uint32_t EnabledAvfsModules;
uint32_t MmHubPadding[7]; /* SMU internal use */
} AvfsFuseOverride_t;
/* These defines are used with the following messages:
* SMC_MSG_TransferTableDram2Smu
* SMC_MSG_TransferTableSmu2Dram
*/
#define TABLE_PPTABLE 0
#define TABLE_WATERMARKS 1
#define TABLE_AVFS 2
#define TABLE_AVFS_PSM_DEBUG 3
#define TABLE_AVFS_FUSE_OVERRIDE 4
#define TABLE_PMSTATUSLOG 5
#define TABLE_COUNT 6
/* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
#define UCLK_SWITCH_SLOW 0
#define UCLK_SWITCH_FAST 1
/* GFX DIDT Configuration */
#define SQ_Enable_MASK 0x1
#define SQ_IR_MASK 0x2
#define SQ_PCC_MASK 0x4
#define SQ_EDC_MASK 0x8
#define TCP_Enable_MASK 0x100
#define TCP_IR_MASK 0x200
#define TCP_PCC_MASK 0x400
#define TCP_EDC_MASK 0x800
#define TD_Enable_MASK 0x10000
#define TD_IR_MASK 0x20000
#define TD_PCC_MASK 0x40000
#define TD_EDC_MASK 0x80000
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
#define SQ_IR_SHIFT 1
#define SQ_PCC_SHIFT 2
#define SQ_EDC_SHIFT 3
#define TCP_Enable_SHIFT 8
#define TCP_IR_SHIFT 9
#define TCP_PCC_SHIFT 10
#define TCP_EDC_SHIFT 11
#define TD_Enable_SHIFT 16
#define TD_IR_SHIFT 17
#define TD_PCC_SHIFT 18
#define TD_EDC_SHIFT 19
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#define REMOVE_FMAX_MARGIN_BIT 0x0
#define REMOVE_DCTOL_MARGIN_BIT 0x1
#define REMOVE_PLATFORM_MARGIN_BIT 0x2
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h
+169
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
// CZ Ucode Loading Definitions
#ifndef SMU_UCODE_XFER_CZ_H
#define SMU_UCODE_XFER_CZ_H
#define NUM_JOBLIST_ENTRIES 32
#define TASK_TYPE_NO_ACTION 0
#define TASK_TYPE_UCODE_LOAD 1
#define TASK_TYPE_UCODE_SAVE 2
#define TASK_TYPE_REG_LOAD 3
#define TASK_TYPE_REG_SAVE 4
#define TASK_TYPE_INITIALIZE 5
#define TASK_ARG_REG_SMCIND 0
#define TASK_ARG_REG_MMIO 1
#define TASK_ARG_REG_FCH 2
#define TASK_ARG_REG_UNB 3
#define TASK_ARG_INIT_MM_PWR_LOG 0
#define TASK_ARG_INIT_CLK_TABLE 1
#define JOB_GFX_SAVE 0
#define JOB_GFX_RESTORE 1
#define JOB_FCH_SAVE 2
#define JOB_FCH_RESTORE 3
#define JOB_UNB_SAVE 4
#define JOB_UNB_RESTORE 5
#define JOB_GMC_SAVE 6
#define JOB_GMC_RESTORE 7
#define JOB_GNB_SAVE 8
#define JOB_GNB_RESTORE 9
#define IGNORE_JOB 0xff
#define END_OF_TASK_LIST (uint16_t)0xffff
// Size of DRAM regions (in bytes) requested by SMU:
#define SMU_DRAM_REQ_MM_PWR_LOG 48
#define UCODE_ID_SDMA0 0
#define UCODE_ID_SDMA1 1
#define UCODE_ID_CP_CE 2
#define UCODE_ID_CP_PFP 3
#define UCODE_ID_CP_ME 4
#define UCODE_ID_CP_MEC_JT1 5
#define UCODE_ID_CP_MEC_JT2 6
#define UCODE_ID_GMCON_RENG 7
#define UCODE_ID_RLC_G 8
#define UCODE_ID_RLC_SCRATCH 9
#define UCODE_ID_RLC_SRM_ARAM 10
#define UCODE_ID_RLC_SRM_DRAM 11
#define UCODE_ID_DMCU_ERAM 12
#define UCODE_ID_DMCU_IRAM 13
#define UCODE_ID_SDMA0_MASK 0x00000001
#define UCODE_ID_SDMA1_MASK 0x00000002
#define UCODE_ID_CP_CE_MASK 0x00000004
#define UCODE_ID_CP_PFP_MASK 0x00000008
#define UCODE_ID_CP_ME_MASK 0x00000010
#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020
#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040
#define UCODE_ID_GMCON_RENG_MASK 0x00000080
#define UCODE_ID_RLC_G_MASK 0x00000100
#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200
#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400
#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800
#define UCODE_ID_DMCU_ERAM_MASK 0x00001000
#define UCODE_ID_DMCU_IRAM_MASK 0x00002000
#define UCODE_ID_SDMA0_SIZE_BYTE 10368
#define UCODE_ID_SDMA1_SIZE_BYTE 10368
#define UCODE_ID_CP_CE_SIZE_BYTE 8576
#define UCODE_ID_CP_PFP_SIZE_BYTE 16768
#define UCODE_ID_CP_ME_SIZE_BYTE 16768
#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384
#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384
#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096
#define UCODE_ID_RLC_G_SIZE_BYTE 2048
#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132
#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192
#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096
#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576
#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024
#define NUM_UCODES 14
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
struct SMU_Task {
uint8_t type;
uint8_t arg;
uint16_t next;
data_64_t addr;
uint32_t size_bytes;
};
typedef struct SMU_Task SMU_Task;
struct TOC {
uint8_t JobList[NUM_JOBLIST_ENTRIES];
SMU_Task tasks[];
};
// META DATA COMMAND Definitions
#define METADATA_CMD_MODE0 0x00000103
#define METADATA_CMD_MODE1 0x00000113
#define METADATA_CMD_MODE2 0x00000123
#define METADATA_CMD_MODE3 0x00000133
#define METADATA_CMD_DELAY 0x00000203
#define METADATA_CMD_CHNG_REGSPACE 0x00000303
#define METADATA_PERFORM_ON_SAVE 0x00001000
#define METADATA_PERFORM_ON_LOAD 0x00002000
#define METADATA_CMD_ARG_MASK 0xFFFF0000
#define METADATA_CMD_ARG_SHIFT 16
// Simple register addr/data fields
struct SMU_MetaData_Mode0 {
uint32_t register_address;
uint32_t register_data;
};
typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0;
// Register addr/data with mask
struct SMU_MetaData_Mode1 {
uint32_t register_address;
uint32_t register_mask;
uint32_t register_data;
};
typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1;
struct SMU_MetaData_Mode2 {
uint32_t register_address;
uint32_t register_mask;
uint32_t target_value;
};
typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2;
// Always write data (even on a save operation)
struct SMU_MetaData_Mode3 {
uint32_t register_address;
uint32_t register_mask;
uint32_t register_data;
};
typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3;
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h
+101
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/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU_UCODE_XFER_VI_H
#define SMU_UCODE_XFER_VI_H
#define SMU_DRAMData_TOC_VERSION 1
#define MAX_IH_REGISTER_COUNT 65535
#define SMU_DIGEST_SIZE_BYTES 20
#define SMU_FB_SIZE_BYTES 1048576
#define SMU_MAX_ENTRIES 12
#define UCODE_ID_SMU 0
#define UCODE_ID_SDMA0 1
#define UCODE_ID_SDMA1 2
#define UCODE_ID_CP_CE 3
#define UCODE_ID_CP_PFP 4
#define UCODE_ID_CP_ME 5
#define UCODE_ID_CP_MEC 6
#define UCODE_ID_CP_MEC_JT1 7
#define UCODE_ID_CP_MEC_JT2 8
#define UCODE_ID_GMCON_RENG 9
#define UCODE_ID_RLC_G 10
#define UCODE_ID_IH_REG_RESTORE 11
#define UCODE_ID_VBIOS 12
#define UCODE_ID_MISC_METADATA 13
#define UCODE_ID_SMU_SK 14
#define UCODE_ID_RLC_SCRATCH 32
#define UCODE_ID_RLC_SRM_ARAM 33
#define UCODE_ID_RLC_SRM_DRAM 34
#define UCODE_ID_MEC_STORAGE 35
#define UCODE_ID_VBIOS_PARAMETERS 36
#define UCODE_META_DATA 0xFF
#define UCODE_ID_SMU_MASK 0x00000001
#define UCODE_ID_SDMA0_MASK 0x00000002
#define UCODE_ID_SDMA1_MASK 0x00000004
#define UCODE_ID_CP_CE_MASK 0x00000008
#define UCODE_ID_CP_PFP_MASK 0x00000010
#define UCODE_ID_CP_ME_MASK 0x00000020
#define UCODE_ID_CP_MEC_MASK 0x00000040
#define UCODE_ID_CP_MEC_JT1_MASK 0x00000080
#define UCODE_ID_CP_MEC_JT2_MASK 0x00000100
#define UCODE_ID_GMCON_RENG_MASK 0x00000200
#define UCODE_ID_RLC_G_MASK 0x00000400
#define UCODE_ID_IH_REG_RESTORE_MASK 0x00000800
#define UCODE_ID_VBIOS_MASK 0x00001000
#define UCODE_FLAG_UNHALT_MASK 0x1
struct SMU_Entry {
#ifndef __BIG_ENDIAN
uint16_t id;
uint16_t version;
uint32_t image_addr_high;
uint32_t image_addr_low;
uint32_t meta_data_addr_high;
uint32_t meta_data_addr_low;
uint32_t data_size_byte;
uint16_t flags;
uint16_t num_register_entries;
#else
uint16_t version;
uint16_t id;
uint32_t image_addr_high;
uint32_t image_addr_low;
uint32_t meta_data_addr_high;
uint32_t meta_data_addr_low;
uint32_t data_size_byte;
uint16_t num_register_entries;
uint16_t flags;
#endif
};
struct SMU_DRAMData_TOC {
uint32_t structure_version;
uint32_t num_entries;
struct SMU_Entry entry[SMU_MAX_ENTRIES];
};
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/smumgr.h
+118
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@@ -0,0 +1,118 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _SMUMGR_H_
#define _SMUMGR_H_
#include <linux/types.h>
#include "amd_powerplay.h"
#include "hwmgr.h"
enum SMU_TABLE {
SMU_UVD_TABLE = 0,
SMU_VCE_TABLE,
SMU_BIF_TABLE,
};
enum SMU_TYPE {
SMU_SoftRegisters = 0,
SMU_Discrete_DpmTable,
};
enum SMU_MEMBER {
HandshakeDisables = 0,
VoltageChangeTimeout,
AverageGraphicsActivity,
AverageMemoryActivity,
PreVBlankGap,
VBlankTimeout,
UcodeLoadStatus,
UvdBootLevel,
VceBootLevel,
LowSclkInterruptThreshold,
DRAM_LOG_ADDR_H,
DRAM_LOG_ADDR_L,
DRAM_LOG_PHY_ADDR_H,
DRAM_LOG_PHY_ADDR_L,
DRAM_LOG_BUFF_SIZE,
};
enum SMU_MAC_DEFINITION {
SMU_MAX_LEVELS_GRAPHICS = 0,
SMU_MAX_LEVELS_MEMORY,
SMU_MAX_LEVELS_LINK,
SMU_MAX_ENTRIES_SMIO,
SMU_MAX_LEVELS_VDDC,
SMU_MAX_LEVELS_VDDGFX,
SMU_MAX_LEVELS_VDDCI,
SMU_MAX_LEVELS_MVDD,
SMU_UVD_MCLK_HANDSHAKE_DISABLE,
};
enum SMU9_TABLE_ID {
PPTABLE = 0,
WMTABLE,
AVFSTABLE,
TOOLSTABLE,
AVFSFUSETABLE
};
enum SMU10_TABLE_ID {
SMU10_WMTABLE = 0,
SMU10_CLOCKTABLE,
};
extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp);
extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter,
uint32_t *resp);
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
uint32_t type, uint32_t member);
extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting);
extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
extern int smum_stop_smc(struct pp_hwmgr *hwmgr);
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/tonga_ppsmc.h
+420
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@@ -0,0 +1,420 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TONGA_PP_SMC_H
#define TONGA_PP_SMC_H
#pragma pack(push, 1)
#define PPSMC_SWSTATE_FLAG_DC 0x01
#define PPSMC_SWSTATE_FLAG_UVD 0x02
#define PPSMC_SWSTATE_FLAG_VCE 0x04
#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10
#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20
#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40
/* Defines for DPM 2.0 */
#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
#define PPSMC_DPM2FLAGS_OCP 0x04
/* Defines for display watermark level */
#define PPSMC_DISPLAY_WATERMARK_LOW 0
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
/* In the HW performance level's state flags:*/
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
#define PPSMC_STATEFLAG_POWERBOOST 0x02
#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
#define PPSMC_STATEFLAG_POWERSHIFT 0x08
#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
/* Fan control algorithm:*/
#define FDO_MODE_HARDWARE 0
#define FDO_MODE_PIECE_WISE_LINEAR 1
enum FAN_CONTROL {
FAN_CONTROL_FUZZY,
FAN_CONTROL_TABLE
};
/* Return codes for driver to SMC communication.*/
#define PPSMC_Result_OK ((uint16_t)0x01)
#define PPSMC_Result_NoMore ((uint16_t)0x02)
#define PPSMC_Result_NotNow ((uint16_t)0x03)
#define PPSMC_Result_Failed ((uint16_t)0xFF)
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
typedef uint16_t PPSMC_Result;
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
#define PPSMC_MSG_Halt ((uint16_t)0x10)
#define PPSMC_MSG_Resume ((uint16_t)0x11)
#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
#define PPSMC_CACHistoryStart ((uint16_t)0x57)
#define PPSMC_CACHistoryStop ((uint16_t)0x58)
#define PPSMC_TDPClampingActive ((uint16_t)0x59)
#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
#define PPSMC_StartFanControl ((uint16_t)0x5B)
#define PPSMC_StopFanControl ((uint16_t)0x5C)
#define PPSMC_NoDisplay ((uint16_t)0x5D)
#define PPSMC_HasDisplay ((uint16_t)0x5E)
#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
#define PPSMC_OCPActive ((uint16_t)0x6C)
#define PPSMC_OCPInactive ((uint16_t)0x6D)
#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
#define PPSMC_FlushDataCache ((uint16_t)0x80)
#define PPSMC_FlushInstrCache ((uint16_t)0x81)
#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90)
#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91)
#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92)
#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93)
#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94)
#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95)
#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96)
#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97)
#define PPSMC_MSG_GPIO17 ((uint16_t)0x98)
#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99)
#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A)
#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B)
#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C)
#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D)
#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E)
#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
/* Trinity Specific Messages*/
#define PPSMC_MSG_Test ((uint16_t) 0x100)
#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
#define PPSMC_MSG_PCIE_PHYPowerDown ((uint16_t) 0x122)
#define PPSMC_MSG_PCIE_PHYPowerUp ((uint16_t) 0x123)
#define PPSMC_MSG_UVD_DPM_Config ((uint16_t) 0x124)
#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
#define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125)
#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint16_t) 0x126)
#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint16_t) 0x127)
#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
#define PPSMC_MSG_DPM_Enable ((uint16_t)0x14e)
#define PPSMC_MSG_DPM_Disable ((uint16_t)0x14f)
#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t)0x150)
#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t)0x151)
#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t)0x152)
#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t)0x153)
#define PPSMC_MSG_UVDDPM_Enable ((uint16_t)0x154)
#define PPSMC_MSG_UVDDPM_Disable ((uint16_t)0x155)
#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t)0x156)
#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t)0x157)
#define PPSMC_MSG_ACPDPM_Enable ((uint16_t)0x158)
#define PPSMC_MSG_ACPDPM_Disable ((uint16_t)0x159)
#define PPSMC_MSG_VCEDPM_Enable ((uint16_t)0x15a)
#define PPSMC_MSG_VCEDPM_Disable ((uint16_t)0x15b)
#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t)0x15c)
#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t)0x16c)
#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t)0x16d)
#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t)0x16e)
#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t)0x16f)
#define PPSMC_MSG_PmStatusLogStart ((uint16_t)0x170)
#define PPSMC_MSG_PmStatusLogSample ((uint16_t)0x171)
#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
#define PPSMC_MSG_UVD_HANDSHAKE_OFF ((uint16_t) 0x183)
#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
#define PPSMC_MSG_Enable_PCC ((uint16_t) 0x19E)
#define PPSMC_MSG_Disable_PCC ((uint16_t) 0x19F)
#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
typedef uint16_t PPSMC_Msg;
/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
#define PPSMC_EVENT_STATUS_DC 0x00000004
#define PPSMC_EVENT_STATUS_GPIO17 0x00000008
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/vega10_ppsmc.h
+144
View File
@@ -0,0 +1,144 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_SMC_H
#define PP_SMC_H
#pragma pack(push, 1)
#define SMU_UCODE_VERSION 0x001c0800
/* SMU Response Codes: */
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
typedef uint16_t PPSMC_Result;
/* Message Definitions */
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_EnableSmuFeatures 0x4
#define PPSMC_MSG_DisableSmuFeatures 0x5
#define PPSMC_MSG_GetEnabledSmuFeatures 0x6
#define PPSMC_MSG_SetWorkloadMask 0x7
#define PPSMC_MSG_SetPptLimit 0x8
#define PPSMC_MSG_SetDriverDramAddrHigh 0x9
#define PPSMC_MSG_SetDriverDramAddrLow 0xA
#define PPSMC_MSG_SetToolsDramAddrHigh 0xB
#define PPSMC_MSG_SetToolsDramAddrLow 0xC
#define PPSMC_MSG_TransferTableSmu2Dram 0xD
#define PPSMC_MSG_TransferTableDram2Smu 0xE
#define PPSMC_MSG_UseDefaultPPTable 0xF
#define PPSMC_MSG_UseBackupPPTable 0x10
#define PPSMC_MSG_RunBtc 0x11
#define PPSMC_MSG_RequestI2CBus 0x12
#define PPSMC_MSG_ReleaseI2CBus 0x13
#define PPSMC_MSG_ConfigureTelemetry 0x14
#define PPSMC_MSG_SetUlvIpMask 0x15
#define PPSMC_MSG_SetSocVidOffset 0x16
#define PPSMC_MSG_SetMemVidOffset 0x17
#define PPSMC_MSG_GetSocVidOffset 0x18
#define PPSMC_MSG_GetMemVidOffset 0x19
#define PPSMC_MSG_SetFloorSocVoltage 0x1A
#define PPSMC_MSG_SoftReset 0x1B
#define PPSMC_MSG_StartBacoMonitor 0x1C
#define PPSMC_MSG_CancelBacoMonitor 0x1D
#define PPSMC_MSG_EnterBaco 0x1E
#define PPSMC_MSG_AllowLowGfxclkInterrupt 0x1F
#define PPSMC_MSG_SetLowGfxclkInterruptThreshold 0x20
#define PPSMC_MSG_SetSoftMinGfxclkByIndex 0x21
#define PPSMC_MSG_SetSoftMaxGfxclkByIndex 0x22
#define PPSMC_MSG_GetCurrentGfxclkIndex 0x23
#define PPSMC_MSG_SetSoftMinUclkByIndex 0x24
#define PPSMC_MSG_SetSoftMaxUclkByIndex 0x25
#define PPSMC_MSG_GetCurrentUclkIndex 0x26
#define PPSMC_MSG_SetSoftMinUvdByIndex 0x27
#define PPSMC_MSG_SetSoftMaxUvdByIndex 0x28
#define PPSMC_MSG_GetCurrentUvdIndex 0x29
#define PPSMC_MSG_SetSoftMinVceByIndex 0x2A
#define PPSMC_MSG_SetSoftMaxVceByIndex 0x2B
#define PPSMC_MSG_SetHardMinVceByIndex 0x2C
#define PPSMC_MSG_GetCurrentVceIndex 0x2D
#define PPSMC_MSG_SetSoftMinSocclkByIndex 0x2E
#define PPSMC_MSG_SetHardMinSocclkByIndex 0x2F
#define PPSMC_MSG_SetSoftMaxSocclkByIndex 0x30
#define PPSMC_MSG_GetCurrentSocclkIndex 0x31
#define PPSMC_MSG_SetMinLinkDpmByIndex 0x32
#define PPSMC_MSG_GetCurrentLinkIndex 0x33
#define PPSMC_MSG_GetAverageGfxclkFrequency 0x34
#define PPSMC_MSG_GetAverageSocclkFrequency 0x35
#define PPSMC_MSG_GetAverageUclkFrequency 0x36
#define PPSMC_MSG_GetAverageGfxActivity 0x37
#define PPSMC_MSG_GetTemperatureEdge 0x38
#define PPSMC_MSG_GetTemperatureHotspot 0x39
#define PPSMC_MSG_GetTemperatureHBM 0x3A
#define PPSMC_MSG_GetTemperatureVrSoc 0x3B
#define PPSMC_MSG_GetTemperatureVrMem 0x3C
#define PPSMC_MSG_GetTemperatureLiquid 0x3D
#define PPSMC_MSG_GetTemperaturePlx 0x3E
#define PPSMC_MSG_OverDriveSetPercentage 0x3F
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x40
#define PPSMC_MSG_SwitchToAC 0x41
#define PPSMC_MSG_SetUclkFastSwitch 0x42
#define PPSMC_MSG_SetUclkDownHyst 0x43
#define PPSMC_MSG_RemoveDCClamp 0x44
#define PPSMC_MSG_GfxDeviceDriverReset 0x45
#define PPSMC_MSG_GetCurrentRpm 0x46
#define PPSMC_MSG_SetVideoFps 0x47
#define PPSMC_MSG_SetCustomGfxDpmParameters 0x48
#define PPSMC_MSG_SetTjMax 0x49
#define PPSMC_MSG_SetFanTemperatureTarget 0x4A
#define PPSMC_MSG_PrepareMp1ForUnload 0x4B
#define PPSMC_MSG_RequestDisplayClockByFreq 0x4C
#define PPSMC_MSG_GetClockFreqMHz 0x4D
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x4E
#define PPSMC_MSG_DramLogSetDramAddrLow 0x4F
#define PPSMC_MSG_DramLogSetDramSize 0x50
#define PPSMC_MSG_SetFanMaxRpm 0x51
#define PPSMC_MSG_SetFanMinPwm 0x52
#define PPSMC_MSG_ConfigureGfxDidt 0x55
#define PPSMC_MSG_NumOfDisplays 0x56
#define PPSMC_MSG_ReadSerialNumTop32 0x58
#define PPSMC_MSG_ReadSerialNumBottom32 0x59
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x5A
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x5B
#define PPSMC_MSG_RunAcgBtc 0x5C
#define PPSMC_MSG_RunAcgInClosedLoop 0x5D
#define PPSMC_MSG_RunAcgInOpenLoop 0x5E
#define PPSMC_MSG_InitializeAcg 0x5F
#define PPSMC_MSG_GetCurrPkgPwr 0x61
#define PPSMC_MSG_GetAverageGfxclkActualFrequency 0x63
#define PPSMC_MSG_SetPccThrottleLevel 0x67
#define PPSMC_MSG_UpdatePkgPwrPidAlpha 0x68
#define PPSMC_Message_Count 0x69
typedef int PPSMC_Msg;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
+769
View File
@@ -0,0 +1,769 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef VEGA12_SMU9_DRIVER_IF_H
#define VEGA12_SMU9_DRIVER_IF_H
/**** IMPORTANT ***
* SMU TEAM: Always increment the interface version if
* any structure is changed in this file
*/
#define SMU9_DRIVER_IF_VERSION 0x10
#define PPTABLE_V12_SMU_VERSION 1
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_VCLK_DPM_LEVELS 8
#define NUM_DCLK_DPM_LEVELS 8
#define NUM_ECLK_DPM_LEVELS 8
#define NUM_MP0CLK_DPM_LEVELS 2
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_SOCCLK_DPM_LEVELS 8
#define NUM_DCEFCLK_DPM_LEVELS 8
#define NUM_DISPCLK_DPM_LEVELS 8
#define NUM_PIXCLK_DPM_LEVELS 8
#define NUM_PHYCLK_DPM_LEVELS 8
#define NUM_LINK_LEVELS 2
#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
#define MAX_ECLK_DPM_LEVEL (NUM_ECLK_DPM_LEVELS - 1)
#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
#define PPSMC_GeminiModeNone 0
#define PPSMC_GeminiModeMaster 1
#define PPSMC_GeminiModeSlave 2
#define FEATURE_DPM_PREFETCHER_BIT 0
#define FEATURE_DPM_GFXCLK_BIT 1
#define FEATURE_DPM_UCLK_BIT 2
#define FEATURE_DPM_SOCCLK_BIT 3
#define FEATURE_DPM_UVD_BIT 4
#define FEATURE_DPM_VCE_BIT 5
#define FEATURE_ULV_BIT 6
#define FEATURE_DPM_MP0CLK_BIT 7
#define FEATURE_DPM_LINK_BIT 8
#define FEATURE_DPM_DCEFCLK_BIT 9
#define FEATURE_DS_GFXCLK_BIT 10
#define FEATURE_DS_SOCCLK_BIT 11
#define FEATURE_DS_LCLK_BIT 12
#define FEATURE_PPT_BIT 13
#define FEATURE_TDC_BIT 14
#define FEATURE_THERMAL_BIT 15
#define FEATURE_GFX_PER_CU_CG_BIT 16
#define FEATURE_RM_BIT 17
#define FEATURE_DS_DCEFCLK_BIT 18
#define FEATURE_ACDC_BIT 19
#define FEATURE_VR0HOT_BIT 20
#define FEATURE_VR1HOT_BIT 21
#define FEATURE_FW_CTF_BIT 22
#define FEATURE_LED_DISPLAY_BIT 23
#define FEATURE_FAN_CONTROL_BIT 24
#define FEATURE_GFX_EDC_BIT 25
#define FEATURE_GFXOFF_BIT 26
#define FEATURE_CG_BIT 27
#define FEATURE_ACG_BIT 28
#define FEATURE_SPARE_29_BIT 29
#define FEATURE_SPARE_30_BIT 30
#define FEATURE_SPARE_31_BIT 31
#define NUM_FEATURES 32
#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
#define FEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
#define FEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
#define FEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
#define FEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
#define FEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT )
#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
#define FEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
#define FEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT )
#define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT )
#define FEATURE_CG_MASK (1 << FEATURE_CG_BIT )
#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT)
#define FEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
#define FEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
#define FEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK 0x00000004
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK 0x00000008
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000010
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK 0x00000020
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000040
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK 0x00000080
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK 0x00000100
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK 0x00000200
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK 0x00000400
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK 0x00000800
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00002000
#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH 0x00004000
#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000
#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000
#define VR_MAPPING_VR_SELECT_MASK 0x01
#define VR_MAPPING_VR_SELECT_SHIFT 0x00
#define VR_MAPPING_PLANE_SELECT_MASK 0x02
#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
#define PSI_SEL_VR0_PLANE0_PSI0 0x01
#define PSI_SEL_VR0_PLANE0_PSI1 0x02
#define PSI_SEL_VR0_PLANE1_PSI0 0x04
#define PSI_SEL_VR0_PLANE1_PSI1 0x08
#define PSI_SEL_VR1_PLANE0_PSI0 0x10
#define PSI_SEL_VR1_PLANE0_PSI1 0x20
#define PSI_SEL_VR1_PLANE1_PSI0 0x40
#define PSI_SEL_VR1_PLANE1_PSI1 0x80
#define THROTTLER_STATUS_PADDING_BIT 0
#define THROTTLER_STATUS_TEMP_EDGE_BIT 1
#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
#define THROTTLER_STATUS_TEMP_HBM_BIT 3
#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4
#define THROTTLER_STATUS_TEMP_VR_MEM_BIT 5
#define THROTTLER_STATUS_TEMP_LIQUID_BIT 6
#define THROTTLER_STATUS_TEMP_PLX_BIT 7
#define THROTTLER_STATUS_TEMP_SKIN_BIT 8
#define THROTTLER_STATUS_TDC_GFX_BIT 9
#define THROTTLER_STATUS_TDC_SOC_BIT 10
#define THROTTLER_STATUS_PPT_BIT 11
#define THROTTLER_STATUS_FIT_BIT 12
#define THROTTLER_STATUS_PPM_BIT 13
#define TABLE_TRANSFER_OK 0x0
#define TABLE_TRANSFER_FAILED 0xFF
#define WORKLOAD_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_COUNT 7
typedef struct {
uint32_t a;
uint32_t b;
uint32_t c;
} QuadraticInt_t;
typedef struct {
uint32_t m;
uint32_t b;
} LinearInt_t;
typedef struct {
uint32_t a;
uint32_t b;
uint32_t c;
} DroopInt_t;
typedef enum {
PPCLK_GFXCLK,
PPCLK_VCLK,
PPCLK_DCLK,
PPCLK_ECLK,
PPCLK_SOCCLK,
PPCLK_UCLK,
PPCLK_DCEFCLK,
PPCLK_DISPCLK,
PPCLK_PIXCLK,
PPCLK_PHYCLK,
PPCLK_COUNT,
} PPCLK_e;
enum {
VOLTAGE_MODE_AVFS,
VOLTAGE_MODE_AVFS_SS,
VOLTAGE_MODE_SS,
VOLTAGE_MODE_COUNT,
};
typedef struct {
uint8_t VoltageMode;
uint8_t SnapToDiscrete;
uint8_t NumDiscreteLevels;
uint8_t padding;
LinearInt_t ConversionToAvfsClk;
QuadraticInt_t SsCurve;
} DpmDescriptor_t;
#pragma pack(push, 1)
typedef struct {
uint32_t Version;
uint32_t FeaturesToRun[2];
uint16_t SocketPowerLimitAc0;
uint16_t SocketPowerLimitAc0Tau;
uint16_t SocketPowerLimitAc1;
uint16_t SocketPowerLimitAc1Tau;
uint16_t SocketPowerLimitAc2;
uint16_t SocketPowerLimitAc2Tau;
uint16_t SocketPowerLimitAc3;
uint16_t SocketPowerLimitAc3Tau;
uint16_t SocketPowerLimitDc;
uint16_t SocketPowerLimitDcTau;
uint16_t TdcLimitSoc;
uint16_t TdcLimitSocTau;
uint16_t TdcLimitGfx;
uint16_t TdcLimitGfxTau;
uint16_t TedgeLimit;
uint16_t ThotspotLimit;
uint16_t ThbmLimit;
uint16_t Tvr_gfxLimit;
uint16_t Tvr_memLimit;
uint16_t Tliquid1Limit;
uint16_t Tliquid2Limit;
uint16_t TplxLimit;
uint32_t FitLimit;
uint16_t PpmPowerLimit;
uint16_t PpmTemperatureThreshold;
uint8_t MemoryOnPackage;
uint8_t padding8_limits[3];
uint16_t UlvVoltageOffsetSoc;
uint16_t UlvVoltageOffsetGfx;
uint8_t UlvSmnclkDid;
uint8_t UlvMp1clkDid;
uint8_t UlvGfxclkBypass;
uint8_t Padding234;
uint16_t MinVoltageGfx;
uint16_t MinVoltageSoc;
uint16_t MaxVoltageGfx;
uint16_t MaxVoltageSoc;
uint16_t LoadLineResistance;
uint16_t LoadLine_padding;
DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ];
uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ];
uint16_t FreqTableEclk [NUM_ECLK_DPM_LEVELS ];
uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ];
uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ];
uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ];
uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ];
uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ];
uint16_t DcModeMaxFreq [PPCLK_COUNT ];
uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS];
uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS];
uint16_t GfxclkFidle;
uint16_t GfxclkSlewRate;
uint16_t CksEnableFreq;
uint16_t Padding789;
QuadraticInt_t CksVoltageOffset;
uint16_t AcgThresholdFreqHigh;
uint16_t AcgThresholdFreqLow;
uint16_t GfxclkDsMaxFreq;
uint8_t Padding456[2];
uint8_t LowestUclkReservedForUlv;
uint8_t Padding8_Uclk[3];
uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
uint8_t PcieLaneCount[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint16_t EnableTdpm;
uint16_t TdpmHighHystTemperature;
uint16_t TdpmLowHystTemperature;
uint16_t GfxclkFreqHighTempLimit;
uint16_t FanStopTemp;
uint16_t FanStartTemp;
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint16_t FanGainLiquid;
uint16_t FanGainVrVddc;
uint16_t FanGainVrMvdd;
uint16_t FanGainPlx;
uint16_t FanGainHbm;
uint16_t FanPwmMin;
uint16_t FanAcousticLimitRpm;
uint16_t FanThrottlingRpm;
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t FuzzyFan_Reserved;
uint8_t OverrideAvfsGb;
uint8_t Padding8_Avfs[3];
QuadraticInt_t qAvfsGb;
DroopInt_t dBtcGbGfxCksOn;
DroopInt_t dBtcGbGfxCksOff;
DroopInt_t dBtcGbGfxAcg;
DroopInt_t dBtcGbSoc;
LinearInt_t qAgingGbGfx;
LinearInt_t qAgingGbSoc;
QuadraticInt_t qStaticVoltageOffsetGfx;
QuadraticInt_t qStaticVoltageOffsetSoc;
uint16_t DcTolGfx;
uint16_t DcTolSoc;
uint8_t DcBtcGfxEnabled;
uint8_t DcBtcSocEnabled;
uint8_t Padding8_GfxBtc[2];
uint16_t DcBtcGfxMin;
uint16_t DcBtcGfxMax;
uint16_t DcBtcSocMin;
uint16_t DcBtcSocMax;
uint32_t DebugOverrides;
QuadraticInt_t ReservedEquation0;
QuadraticInt_t ReservedEquation1;
QuadraticInt_t ReservedEquation2;
QuadraticInt_t ReservedEquation3;
uint16_t MinVoltageUlvGfx;
uint16_t MinVoltageUlvSoc;
uint32_t Reserved[14];
uint8_t Liquid1_I2C_address;
uint8_t Liquid2_I2C_address;
uint8_t Vr_I2C_address;
uint8_t Plx_I2C_address;
uint8_t Liquid_I2C_LineSCL;
uint8_t Liquid_I2C_LineSDA;
uint8_t Vr_I2C_LineSCL;
uint8_t Vr_I2C_LineSDA;
uint8_t Plx_I2C_LineSCL;
uint8_t Plx_I2C_LineSDA;
uint8_t VrSensorPresent;
uint8_t LiquidSensorPresent;
uint16_t MaxVoltageStepGfx;
uint16_t MaxVoltageStepSoc;
uint8_t VddGfxVrMapping;
uint8_t VddSocVrMapping;
uint8_t VddMem0VrMapping;
uint8_t VddMem1VrMapping;
uint8_t GfxUlvPhaseSheddingMask;
uint8_t SocUlvPhaseSheddingMask;
uint8_t ExternalSensorPresent;
uint8_t Padding8_V;
uint16_t GfxMaxCurrent;
int8_t GfxOffset;
uint8_t Padding_TelemetryGfx;
uint16_t SocMaxCurrent;
int8_t SocOffset;
uint8_t Padding_TelemetrySoc;
uint16_t Mem0MaxCurrent;
int8_t Mem0Offset;
uint8_t Padding_TelemetryMem0;
uint16_t Mem1MaxCurrent;
int8_t Mem1Offset;
uint8_t Padding_TelemetryMem1;
uint8_t AcDcGpio;
uint8_t AcDcPolarity;
uint8_t VR0HotGpio;
uint8_t VR0HotPolarity;
uint8_t VR1HotGpio;
uint8_t VR1HotPolarity;
uint8_t Padding1;
uint8_t Padding2;
uint8_t LedPin0;
uint8_t LedPin1;
uint8_t LedPin2;
uint8_t padding8_4;
uint8_t PllGfxclkSpreadEnabled;
uint8_t PllGfxclkSpreadPercent;
uint16_t PllGfxclkSpreadFreq;
uint8_t UclkSpreadEnabled;
uint8_t UclkSpreadPercent;
uint16_t UclkSpreadFreq;
uint8_t SocclkSpreadEnabled;
uint8_t SocclkSpreadPercent;
uint16_t SocclkSpreadFreq;
uint8_t AcgGfxclkSpreadEnabled;
uint8_t AcgGfxclkSpreadPercent;
uint16_t AcgGfxclkSpreadFreq;
uint8_t Vr2_I2C_address;
uint8_t padding_vr2[3];
uint32_t BoardReserved[9];
uint32_t MmHubPadding[7];
} PPTable_t;
#pragma pack(pop)
typedef struct {
uint16_t GfxclkAverageLpfTau;
uint16_t SocclkAverageLpfTau;
uint16_t UclkAverageLpfTau;
uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau;
uint32_t MmHubPadding[7];
} DriverSmuConfig_t;
typedef struct {
uint16_t GfxclkFmin;
uint16_t GfxclkFmax;
uint16_t GfxclkFreq1;
uint16_t GfxclkOffsetVolt1;
uint16_t GfxclkFreq2;
uint16_t GfxclkOffsetVolt2;
uint16_t GfxclkFreq3;
uint16_t GfxclkOffsetVolt3;
uint16_t UclkFmax;
int16_t OverDrivePct;
uint16_t FanMaximumRpm;
uint16_t FanMinimumPwm;
uint16_t FanTargetTemperature;
uint16_t MaxOpTemp;
} OverDriveTable_t;
typedef struct {
uint16_t CurrClock[PPCLK_COUNT];
uint16_t AverageGfxclkFrequency;
uint16_t AverageSocclkFrequency;
uint16_t AverageUclkFrequency ;
uint16_t AverageGfxActivity ;
uint16_t AverageUclkActivity ;
uint8_t CurrSocVoltageOffset ;
uint8_t CurrGfxVoltageOffset ;
uint8_t CurrMemVidOffset ;
uint8_t Padding8 ;
uint16_t CurrSocketPower ;
uint16_t TemperatureEdge ;
uint16_t TemperatureHotspot ;
uint16_t TemperatureHBM ;
uint16_t TemperatureVrGfx ;
uint16_t TemperatureVrMem ;
uint16_t TemperatureLiquid ;
uint16_t TemperaturePlx ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
uint8_t Padding[3];
uint32_t MmHubPadding[7];
} SmuMetrics_t;
typedef struct {
uint16_t MinClock;
uint16_t MaxClock;
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Padding[3];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
typedef enum {
WM_SOCCLK = 0,
WM_DCEFCLK,
WM_COUNT_PP,
} WM_CLOCK_e;
typedef struct {
WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
uint32_t MmHubPadding[7];
} Watermarks_t;
typedef struct {
uint16_t avgPsmCount[30];
uint16_t minPsmCount[30];
float avgPsmVoltage[30];
float minPsmVoltage[30];
uint32_t MmHubPadding[7];
} AvfsDebugTable_t;
typedef struct {
uint8_t AvfsEn;
uint8_t AvfsVersion;
uint8_t OverrideVFT;
uint8_t OverrideAvfsGb;
uint8_t OverrideTemperatures;
uint8_t OverrideVInversion;
uint8_t OverrideP2V;
uint8_t OverrideP2VCharzFreq;
int32_t VFT0_m1;
int32_t VFT0_m2;
int32_t VFT0_b;
int32_t VFT1_m1;
int32_t VFT1_m2;
int32_t VFT1_b;
int32_t VFT2_m1;
int32_t VFT2_m2;
int32_t VFT2_b;
int32_t AvfsGb0_m1;
int32_t AvfsGb0_m2;
int32_t AvfsGb0_b;
int32_t AcBtcGb_m1;
int32_t AcBtcGb_m2;
int32_t AcBtcGb_b;
uint32_t AvfsTempCold;
uint32_t AvfsTempMid;
uint32_t AvfsTempHot;
uint32_t GfxVInversion;
uint32_t SocVInversion;
int32_t P2V_m1;
int32_t P2V_m2;
int32_t P2V_b;
uint32_t P2VCharzFreq;
uint32_t EnabledAvfsModules;
uint32_t MmHubPadding[7];
} AvfsFuseOverride_t;
typedef struct {
uint8_t Gfx_ActiveHystLimit;
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
uint32_t Gfx_PD_Data_limit_a;
uint32_t Gfx_PD_Data_limit_b;
uint32_t Gfx_PD_Data_limit_c;
uint32_t Gfx_PD_Data_error_coeff;
uint32_t Gfx_PD_Data_error_rate_coeff;
uint8_t Soc_ActiveHystLimit;
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
uint16_t Soc_PD_Data_time_constant;
uint32_t Soc_PD_Data_limit_a;
uint32_t Soc_PD_Data_limit_b;
uint32_t Soc_PD_Data_limit_c;
uint32_t Soc_PD_Data_error_coeff;
uint32_t Soc_PD_Data_error_rate_coeff;
uint8_t Mem_ActiveHystLimit;
uint8_t Mem_IdleHystLimit;
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;
uint32_t Mem_PD_Data_limit_a;
uint32_t Mem_PD_Data_limit_b;
uint32_t Mem_PD_Data_limit_c;
uint32_t Mem_PD_Data_error_coeff;
uint32_t Mem_PD_Data_error_rate_coeff;
} DpmActivityMonitorCoeffInt_t;
#define TABLE_PPTABLE 0
#define TABLE_WATERMARKS 1
#define TABLE_AVFS 2
#define TABLE_AVFS_PSM_DEBUG 3
#define TABLE_AVFS_FUSE_OVERRIDE 4
#define TABLE_PMSTATUSLOG 5
#define TABLE_SMU_METRICS 6
#define TABLE_DRIVER_SMU_CONFIG 7
#define TABLE_ACTIVITY_MONITOR_COEFF 8
#define TABLE_OVERDRIVE 9
#define TABLE_COUNT 10
#define UCLK_SWITCH_SLOW 0
#define UCLK_SWITCH_FAST 1
#define SQ_Enable_MASK 0x1
#define SQ_IR_MASK 0x2
#define SQ_PCC_MASK 0x4
#define SQ_EDC_MASK 0x8
#define TCP_Enable_MASK 0x100
#define TCP_IR_MASK 0x200
#define TCP_PCC_MASK 0x400
#define TCP_EDC_MASK 0x800
#define TD_Enable_MASK 0x10000
#define TD_IR_MASK 0x20000
#define TD_PCC_MASK 0x40000
#define TD_EDC_MASK 0x80000
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
#define SQ_IR_SHIFT 1
#define SQ_PCC_SHIFT 2
#define SQ_EDC_SHIFT 3
#define TCP_Enable_SHIFT 8
#define TCP_IR_SHIFT 9
#define TCP_PCC_SHIFT 10
#define TCP_EDC_SHIFT 11
#define TD_Enable_SHIFT 16
#define TD_IR_SHIFT 17
#define TD_PCC_SHIFT 18
#define TD_EDC_SHIFT 19
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#define REMOVE_FMAX_MARGIN_BIT 0x0
#define REMOVE_DCTOL_MARGIN_BIT 0x1
#define REMOVE_PLATFORM_MARGIN_BIT 0x2
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/vega12_ppsmc.h
+123
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@@ -0,0 +1,123 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef VEGA12_PP_SMC_H
#define VEGA12_PP_SMC_H
#pragma pack(push, 1)
#define SMU_UCODE_VERSION 0x00270a00
/* SMU Response Codes: */
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
#define PPSMC_MSG_EnableAllSmuFeatures 0x6
#define PPSMC_MSG_DisableAllSmuFeatures 0x7
#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xC
#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xD
#define PPSMC_MSG_SetWorkloadMask 0xE
#define PPSMC_MSG_SetPptLimit 0xF
#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
#define PPSMC_MSG_SetDriverDramAddrLow 0x11
#define PPSMC_MSG_SetToolsDramAddrHigh 0x12
#define PPSMC_MSG_SetToolsDramAddrLow 0x13
#define PPSMC_MSG_TransferTableSmu2Dram 0x14
#define PPSMC_MSG_TransferTableDram2Smu 0x15
#define PPSMC_MSG_UseDefaultPPTable 0x16
#define PPSMC_MSG_UseBackupPPTable 0x17
#define PPSMC_MSG_RunBtc 0x18
#define PPSMC_MSG_RequestI2CBus 0x19
#define PPSMC_MSG_ReleaseI2CBus 0x1A
#define PPSMC_MSG_SetFloorSocVoltage 0x21
#define PPSMC_MSG_SoftReset 0x22
#define PPSMC_MSG_StartBacoMonitor 0x23
#define PPSMC_MSG_CancelBacoMonitor 0x24
#define PPSMC_MSG_EnterBaco 0x25
#define PPSMC_MSG_SetSoftMinByFreq 0x26
#define PPSMC_MSG_SetSoftMaxByFreq 0x27
#define PPSMC_MSG_SetHardMinByFreq 0x28
#define PPSMC_MSG_SetHardMaxByFreq 0x29
#define PPSMC_MSG_GetMinDpmFreq 0x2A
#define PPSMC_MSG_GetMaxDpmFreq 0x2B
#define PPSMC_MSG_GetDpmFreqByIndex 0x2C
#define PPSMC_MSG_GetDpmClockFreq 0x2D
#define PPSMC_MSG_GetSsVoltageByDpm 0x2E
#define PPSMC_MSG_SetMemoryChannelConfig 0x2F
#define PPSMC_MSG_SetGeminiMode 0x30
#define PPSMC_MSG_SetGeminiApertureHigh 0x31
#define PPSMC_MSG_SetGeminiApertureLow 0x32
#define PPSMC_MSG_SetMinLinkDpmByIndex 0x33
#define PPSMC_MSG_OverridePcieParameters 0x34
#define PPSMC_MSG_OverDriveSetPercentage 0x35
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x36
#define PPSMC_MSG_ReenableAcDcInterrupt 0x37
#define PPSMC_MSG_NotifyPowerSource 0x38
#define PPSMC_MSG_SetUclkFastSwitch 0x39
#define PPSMC_MSG_SetUclkDownHyst 0x3A
#define PPSMC_MSG_GfxDeviceDriverReset 0x3B
#define PPSMC_MSG_GetCurrentRpm 0x3C
#define PPSMC_MSG_SetVideoFps 0x3D
#define PPSMC_MSG_SetTjMax 0x3E
#define PPSMC_MSG_SetFanTemperatureTarget 0x3F
#define PPSMC_MSG_PrepareMp1ForUnload 0x40
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x41
#define PPSMC_MSG_DramLogSetDramAddrLow 0x42
#define PPSMC_MSG_DramLogSetDramSize 0x43
#define PPSMC_MSG_SetFanMaxRpm 0x44
#define PPSMC_MSG_SetFanMinPwm 0x45
#define PPSMC_MSG_ConfigureGfxDidt 0x46
#define PPSMC_MSG_NumOfDisplays 0x47
#define PPSMC_MSG_RemoveMargins 0x48
#define PPSMC_MSG_ReadSerialNumTop32 0x49
#define PPSMC_MSG_ReadSerialNumBottom32 0x4A
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C
#define PPSMC_MSG_RunAcgBtc 0x4D
#define PPSMC_MSG_InitializeAcg 0x4E
#define PPSMC_MSG_EnableAcgBtcTestMode 0x4F
#define PPSMC_MSG_EnableAcgSpreadSpectrum 0x50
#define PPSMC_MSG_AllowGfxOff 0x51
#define PPSMC_MSG_DisallowGfxOff 0x52
#define PPSMC_MSG_GetPptLimit 0x53
#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x54
#define PPSMC_Message_Count 0x56
typedef uint16_t PPSMC_Result;
typedef int PPSMC_Msg;
#pragma pack(pop)
#endif
linux-7.2.3/drivers/gpu/drm/amd/pm/powerplay/inc/vega20_ppsmc.h
+131
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef VEGA20_PP_SMC_H
#define VEGA20_PP_SMC_H
#pragma pack(push, 1)
// SMU Response Codes:
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
// Message Definitions:
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
#define PPSMC_MSG_EnableAllSmuFeatures 0x6
#define PPSMC_MSG_DisableAllSmuFeatures 0x7
#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xC
#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xD
#define PPSMC_MSG_SetWorkloadMask 0xE
#define PPSMC_MSG_SetPptLimit 0xF
#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
#define PPSMC_MSG_SetDriverDramAddrLow 0x11
#define PPSMC_MSG_SetToolsDramAddrHigh 0x12
#define PPSMC_MSG_SetToolsDramAddrLow 0x13
#define PPSMC_MSG_TransferTableSmu2Dram 0x14
#define PPSMC_MSG_TransferTableDram2Smu 0x15
#define PPSMC_MSG_UseDefaultPPTable 0x16
#define PPSMC_MSG_UseBackupPPTable 0x17
#define PPSMC_MSG_RunBtc 0x18
#define PPSMC_MSG_RequestI2CBus 0x19
#define PPSMC_MSG_ReleaseI2CBus 0x1A
#define PPSMC_MSG_SetFloorSocVoltage 0x21
#define PPSMC_MSG_SoftReset 0x22
#define PPSMC_MSG_StartBacoMonitor 0x23
#define PPSMC_MSG_CancelBacoMonitor 0x24
#define PPSMC_MSG_EnterBaco 0x25
#define PPSMC_MSG_SetSoftMinByFreq 0x26
#define PPSMC_MSG_SetSoftMaxByFreq 0x27
#define PPSMC_MSG_SetHardMinByFreq 0x28
#define PPSMC_MSG_SetHardMaxByFreq 0x29
#define PPSMC_MSG_GetMinDpmFreq 0x2A
#define PPSMC_MSG_GetMaxDpmFreq 0x2B
#define PPSMC_MSG_GetDpmFreqByIndex 0x2C
#define PPSMC_MSG_GetDpmClockFreq 0x2D
#define PPSMC_MSG_GetSsVoltageByDpm 0x2E
#define PPSMC_MSG_SetMemoryChannelConfig 0x2F
#define PPSMC_MSG_SetGeminiMode 0x30
#define PPSMC_MSG_SetGeminiApertureHigh 0x31
#define PPSMC_MSG_SetGeminiApertureLow 0x32
#define PPSMC_MSG_SetMinLinkDpmByIndex 0x33
#define PPSMC_MSG_OverridePcieParameters 0x34
#define PPSMC_MSG_OverDriveSetPercentage 0x35
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x36
#define PPSMC_MSG_ReenableAcDcInterrupt 0x37
#define PPSMC_MSG_NotifyPowerSource 0x38
#define PPSMC_MSG_SetUclkFastSwitch 0x39
#define PPSMC_MSG_SetUclkDownHyst 0x3A
//#define PPSMC_MSG_GfxDeviceDriverReset 0x3B
#define PPSMC_MSG_GetCurrentRpm 0x3C
#define PPSMC_MSG_SetVideoFps 0x3D
#define PPSMC_MSG_SetTjMax 0x3E
#define PPSMC_MSG_SetFanTemperatureTarget 0x3F
#define PPSMC_MSG_PrepareMp1ForUnload 0x40
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x41
#define PPSMC_MSG_DramLogSetDramAddrLow 0x42
#define PPSMC_MSG_DramLogSetDramSize 0x43
#define PPSMC_MSG_SetFanMaxRpm 0x44
#define PPSMC_MSG_SetFanMinPwm 0x45
#define PPSMC_MSG_ConfigureGfxDidt 0x46
#define PPSMC_MSG_NumOfDisplays 0x47
#define PPSMC_MSG_RemoveMargins 0x48
#define PPSMC_MSG_ReadSerialNumTop32 0x49
#define PPSMC_MSG_ReadSerialNumBottom32 0x4A
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C
#define PPSMC_MSG_WaflTest 0x4D
#define PPSMC_MSG_SetFclkGfxClkRatio 0x4E
// Unused ID 0x4F to 0x50
#define PPSMC_MSG_AllowGfxOff 0x51
#define PPSMC_MSG_DisallowGfxOff 0x52
#define PPSMC_MSG_GetPptLimit 0x53
#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x54
#define PPSMC_MSG_GetDebugData 0x55
#define PPSMC_MSG_SetXgmiMode 0x56
#define PPSMC_MSG_RunAfllBtc 0x57
#define PPSMC_MSG_ExitBaco 0x58
#define PPSMC_MSG_PrepareMp1ForReset 0x59
#define PPSMC_MSG_PrepareMp1ForShutdown 0x5A
#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x5D
#define PPSMC_MSG_GetAVFSVoltageByDpm 0x5F
#define PPSMC_MSG_BacoWorkAroundFlushVDCI 0x60
#define PPSMC_MSG_DFCstateControl 0x63
#define PPSMC_Message_Count 0x64
typedef uint32_t PPSMC_Result;
typedef uint32_t PPSMC_Msg;
#pragma pack(pop)
#endif