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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
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linux-7.2.3/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <drm/drm_blend.h>
#include <drm/drm_print.h>
#include "d71_dev.h"
#include "malidp_io.h"
static u64 get_lpu_event(struct d71_pipeline *d71_pipeline)
{
u32 __iomem *reg = d71_pipeline->lpu_addr;
u32 status, raw_status;
u64 evts = 0ULL;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
if (raw_status & LPU_IRQ_IBSY)
evts |= KOMEDA_EVENT_IBSY;
if (raw_status & LPU_IRQ_EOW)
evts |= KOMEDA_EVENT_EOW;
if (raw_status & LPU_IRQ_OVR)
evts |= KOMEDA_EVENT_OVR;
if (raw_status & (LPU_IRQ_ERR | LPU_IRQ_IBSY | LPU_IRQ_OVR)) {
u32 restore = 0, tbu_status;
/* Check error of LPU status */
status = malidp_read32(reg, BLK_STATUS);
if (status & LPU_STATUS_AXIE) {
restore |= LPU_STATUS_AXIE;
evts |= KOMEDA_ERR_AXIE;
}
if (status & LPU_STATUS_ACE0) {
restore |= LPU_STATUS_ACE0;
evts |= KOMEDA_ERR_ACE0;
}
if (status & LPU_STATUS_ACE1) {
restore |= LPU_STATUS_ACE1;
evts |= KOMEDA_ERR_ACE1;
}
if (status & LPU_STATUS_ACE2) {
restore |= LPU_STATUS_ACE2;
evts |= KOMEDA_ERR_ACE2;
}
if (status & LPU_STATUS_ACE3) {
restore |= LPU_STATUS_ACE3;
evts |= KOMEDA_ERR_ACE3;
}
if (status & LPU_STATUS_FEMPTY) {
restore |= LPU_STATUS_FEMPTY;
evts |= KOMEDA_EVENT_EMPTY;
}
if (status & LPU_STATUS_FFULL) {
restore |= LPU_STATUS_FFULL;
evts |= KOMEDA_EVENT_FULL;
}
if (restore != 0)
malidp_write32_mask(reg, BLK_STATUS, restore, 0);
restore = 0;
/* Check errors of TBU status */
tbu_status = malidp_read32(reg, LPU_TBU_STATUS);
if (tbu_status & LPU_TBU_STATUS_TCF) {
restore |= LPU_TBU_STATUS_TCF;
evts |= KOMEDA_ERR_TCF;
}
if (tbu_status & LPU_TBU_STATUS_TTNG) {
restore |= LPU_TBU_STATUS_TTNG;
evts |= KOMEDA_ERR_TTNG;
}
if (tbu_status & LPU_TBU_STATUS_TITR) {
restore |= LPU_TBU_STATUS_TITR;
evts |= KOMEDA_ERR_TITR;
}
if (tbu_status & LPU_TBU_STATUS_TEMR) {
restore |= LPU_TBU_STATUS_TEMR;
evts |= KOMEDA_ERR_TEMR;
}
if (tbu_status & LPU_TBU_STATUS_TTF) {
restore |= LPU_TBU_STATUS_TTF;
evts |= KOMEDA_ERR_TTF;
}
if (restore != 0)
malidp_write32_mask(reg, LPU_TBU_STATUS, restore, 0);
}
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
return evts;
}
static u64 get_cu_event(struct d71_pipeline *d71_pipeline)
{
u32 __iomem *reg = d71_pipeline->cu_addr;
u32 status, raw_status;
u64 evts = 0ULL;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
if (raw_status & CU_IRQ_OVR)
evts |= KOMEDA_EVENT_OVR;
if (raw_status & (CU_IRQ_ERR | CU_IRQ_OVR)) {
status = malidp_read32(reg, BLK_STATUS) & 0x7FFFFFFF;
if (status & CU_STATUS_CPE)
evts |= KOMEDA_ERR_CPE;
if (status & CU_STATUS_ZME)
evts |= KOMEDA_ERR_ZME;
if (status & CU_STATUS_CFGE)
evts |= KOMEDA_ERR_CFGE;
if (status)
malidp_write32_mask(reg, BLK_STATUS, status, 0);
}
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
return evts;
}
static u64 get_dou_event(struct d71_pipeline *d71_pipeline)
{
u32 __iomem *reg = d71_pipeline->dou_addr;
u32 status, raw_status;
u64 evts = 0ULL;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
if (raw_status & DOU_IRQ_PL0)
evts |= KOMEDA_EVENT_VSYNC;
if (raw_status & DOU_IRQ_UND)
evts |= KOMEDA_EVENT_URUN;
if (raw_status & (DOU_IRQ_ERR | DOU_IRQ_UND)) {
u32 restore = 0;
status = malidp_read32(reg, BLK_STATUS);
if (status & DOU_STATUS_DRIFTTO) {
restore |= DOU_STATUS_DRIFTTO;
evts |= KOMEDA_ERR_DRIFTTO;
}
if (status & DOU_STATUS_FRAMETO) {
restore |= DOU_STATUS_FRAMETO;
evts |= KOMEDA_ERR_FRAMETO;
}
if (status & DOU_STATUS_TETO) {
restore |= DOU_STATUS_TETO;
evts |= KOMEDA_ERR_TETO;
}
if (status & DOU_STATUS_CSCE) {
restore |= DOU_STATUS_CSCE;
evts |= KOMEDA_ERR_CSCE;
}
if (restore != 0)
malidp_write32_mask(reg, BLK_STATUS, restore, 0);
}
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
return evts;
}
static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32 gcu_status)
{
u32 evts = 0ULL;
if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
evts |= get_lpu_event(d71_pipeline);
if (gcu_status & (GLB_IRQ_STATUS_CU0 | GLB_IRQ_STATUS_CU1))
evts |= get_cu_event(d71_pipeline);
if (gcu_status & (GLB_IRQ_STATUS_DOU0 | GLB_IRQ_STATUS_DOU1))
evts |= get_dou_event(d71_pipeline);
return evts;
}
static irqreturn_t
d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
{
struct d71_dev *d71 = mdev->chip_data;
u32 status, gcu_status, raw_status;
gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);
if (gcu_status & GLB_IRQ_STATUS_GCU) {
raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS);
if (raw_status & GCU_IRQ_CVAL0)
evts->pipes[0] |= KOMEDA_EVENT_FLIP;
if (raw_status & GCU_IRQ_CVAL1)
evts->pipes[1] |= KOMEDA_EVENT_FLIP;
if (raw_status & GCU_IRQ_ERR) {
status = malidp_read32(d71->gcu_addr, BLK_STATUS);
if (status & GCU_STATUS_MERR) {
evts->global |= KOMEDA_ERR_MERR;
malidp_write32_mask(d71->gcu_addr, BLK_STATUS,
GCU_STATUS_MERR, 0);
}
}
malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status);
}
if (gcu_status & GLB_IRQ_STATUS_PIPE0)
evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status);
if (gcu_status & GLB_IRQ_STATUS_PIPE1)
evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status);
return IRQ_RETVAL(gcu_status);
}
#define ENABLED_GCU_IRQS (GCU_IRQ_CVAL0 | GCU_IRQ_CVAL1 | \
GCU_IRQ_MODE | GCU_IRQ_ERR)
#define ENABLED_LPU_IRQS (LPU_IRQ_IBSY | LPU_IRQ_ERR | LPU_IRQ_EOW)
#define ENABLED_CU_IRQS (CU_IRQ_OVR | CU_IRQ_ERR)
#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR)
static int d71_enable_irq(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
struct d71_pipeline *pipe;
u32 i;
malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK,
ENABLED_GCU_IRQS, ENABLED_GCU_IRQS);
for (i = 0; i < d71->num_pipelines; i++) {
pipe = d71->pipes[i];
malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
ENABLED_CU_IRQS, ENABLED_CU_IRQS);
malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
ENABLED_LPU_IRQS, ENABLED_LPU_IRQS);
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
ENABLED_DOU_IRQS, ENABLED_DOU_IRQS);
}
return 0;
}
static int d71_disable_irq(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
struct d71_pipeline *pipe;
u32 i;
malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0);
for (i = 0; i < d71->num_pipelines; i++) {
pipe = d71->pipes[i];
malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
ENABLED_CU_IRQS, 0);
malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
ENABLED_LPU_IRQS, 0);
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
ENABLED_DOU_IRQS, 0);
}
return 0;
}
static void d71_on_off_vblank(struct komeda_dev *mdev, int master_pipe, bool on)
{
struct d71_dev *d71 = mdev->chip_data;
struct d71_pipeline *pipe = d71->pipes[master_pipe];
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
DOU_IRQ_PL0, on ? DOU_IRQ_PL0 : 0);
}
static int to_d71_opmode(int core_mode)
{
switch (core_mode) {
case KOMEDA_MODE_DISP0:
return DO0_ACTIVE_MODE;
case KOMEDA_MODE_DISP1:
return DO1_ACTIVE_MODE;
case KOMEDA_MODE_DUAL_DISP:
return DO01_ACTIVE_MODE;
case KOMEDA_MODE_INACTIVE:
return INACTIVE_MODE;
default:
WARN(1, "Unknown operation mode");
return INACTIVE_MODE;
}
}
static int d71_change_opmode(struct komeda_dev *mdev, int new_mode)
{
struct d71_dev *d71 = mdev->chip_data;
u32 opmode = to_d71_opmode(new_mode);
int ret;
malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode);
ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode),
100, 1000, 10000);
return ret;
}
static void d71_flush(struct komeda_dev *mdev,
int master_pipe, u32 active_pipes)
{
struct d71_dev *d71 = mdev->chip_data;
u32 reg_offset = (master_pipe == 0) ?
GCU_CONFIG_VALID0 : GCU_CONFIG_VALID1;
malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);
}
static int d71_reset(struct d71_dev *d71)
{
u32 __iomem *gcu = d71->gcu_addr;
int ret;
malidp_write32(gcu, BLK_CONTROL, GCU_CONTROL_SRST);
ret = dp_wait_cond(!(malidp_read32(gcu, BLK_CONTROL) & GCU_CONTROL_SRST),
100, 1000, 10000);
return ret;
}
void d71_read_block_header(u32 __iomem *reg, struct block_header *blk)
{
int i;
blk->block_info = malidp_read32(reg, BLK_BLOCK_INFO);
if (BLOCK_INFO_BLK_TYPE(blk->block_info) == D71_BLK_TYPE_RESERVED)
return;
blk->pipeline_info = malidp_read32(reg, BLK_PIPELINE_INFO);
/* get valid input and output ids */
for (i = 0; i < PIPELINE_INFO_N_VALID_INPUTS(blk->pipeline_info); i++)
blk->input_ids[i] = malidp_read32(reg + i, BLK_VALID_INPUT_ID0);
for (i = 0; i < PIPELINE_INFO_N_OUTPUTS(blk->pipeline_info); i++)
blk->output_ids[i] = malidp_read32(reg + i, BLK_OUTPUT_ID0);
}
static void d71_cleanup(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
if (!d71)
return;
devm_kfree(mdev->dev, d71);
mdev->chip_data = NULL;
}
static int d71_enum_resources(struct komeda_dev *mdev)
{
struct d71_dev *d71;
struct komeda_pipeline *pipe;
struct block_header blk;
u32 __iomem *blk_base;
u32 i, value, offset;
int err;
d71 = devm_kzalloc(mdev->dev, sizeof(*d71), GFP_KERNEL);
if (!d71)
return -ENOMEM;
mdev->chip_data = d71;
d71->mdev = mdev;
d71->gcu_addr = mdev->reg_base;
d71->periph_addr = mdev->reg_base + (D71_BLOCK_OFFSET_PERIPH >> 2);
err = d71_reset(d71);
if (err) {
DRM_ERROR("Fail to reset d71 device.\n");
goto err_cleanup;
}
/* probe GCU */
value = malidp_read32(d71->gcu_addr, GLB_CORE_INFO);
d71->num_blocks = value & 0xFF;
d71->num_pipelines = (value >> 8) & 0x7;
if (d71->num_pipelines > D71_MAX_PIPELINE) {
DRM_ERROR("d71 supports %d pipelines, but got: %d.\n",
D71_MAX_PIPELINE, d71->num_pipelines);
err = -EINVAL;
goto err_cleanup;
}
/* Only the legacy HW has the periph block, the newer merges the periph
* into GCU
*/
value = malidp_read32(d71->periph_addr, BLK_BLOCK_INFO);
if (BLOCK_INFO_BLK_TYPE(value) != D71_BLK_TYPE_PERIPH)
d71->periph_addr = NULL;
if (d71->periph_addr) {
/* probe PERIPHERAL in legacy HW */
value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
d71->max_line_size = value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;
d71->max_vsize = 4096;
d71->num_rich_layers = value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;
d71->supports_dual_link = !!(value & PERIPH_SPLIT_EN);
d71->integrates_tbu = !!(value & PERIPH_TBU_EN);
} else {
value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID0);
d71->max_line_size = GCU_MAX_LINE_SIZE(value);
d71->max_vsize = GCU_MAX_NUM_LINES(value);
value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID1);
d71->num_rich_layers = GCU_NUM_RICH_LAYERS(value);
d71->supports_dual_link = GCU_DISPLAY_SPLIT_EN(value);
d71->integrates_tbu = GCU_DISPLAY_TBU_EN(value);
}
for (i = 0; i < d71->num_pipelines; i++) {
pipe = komeda_pipeline_add(mdev, sizeof(struct d71_pipeline),
&d71_pipeline_funcs);
if (IS_ERR(pipe)) {
err = PTR_ERR(pipe);
goto err_cleanup;
}
/* D71 HW doesn't update shadow registers when display output
* is turning off, so when we disable all pipeline components
* together with display output disable by one flush or one
* operation, the disable operation updated registers will not
* be flush to or valid in HW, which may leads problem.
* To workaround this problem, introduce a two phase disable.
* Phase1: Disabling components with display is on to make sure
* the disable can be flushed to HW.
* Phase2: Only turn-off display output.
*/
value = KOMEDA_PIPELINE_IMPROCS |
BIT(KOMEDA_COMPONENT_TIMING_CTRLR);
pipe->standalone_disabled_comps = value;
d71->pipes[i] = to_d71_pipeline(pipe);
}
/* loop the register blks and probe.
* NOTE: d71->num_blocks includes reserved blocks.
* d71->num_blocks = GCU + valid blocks + reserved blocks
*/
i = 1; /* exclude GCU */
offset = D71_BLOCK_SIZE; /* skip GCU */
while (i < d71->num_blocks) {
blk_base = mdev->reg_base + (offset >> 2);
d71_read_block_header(blk_base, &blk);
if (BLOCK_INFO_BLK_TYPE(blk.block_info) != D71_BLK_TYPE_RESERVED) {
err = d71_probe_block(d71, &blk, blk_base);
if (err)
goto err_cleanup;
}
i++;
offset += D71_BLOCK_SIZE;
}
DRM_DEBUG("total %d (out of %d) blocks are found.\n",
i, d71->num_blocks);
return 0;
err_cleanup:
d71_cleanup(mdev);
return err;
}
#define __HW_ID(__group, __format) \
((((__group) & 0x7) << 3) | ((__format) & 0x7))
#define RICH KOMEDA_FMT_RICH_LAYER
#define SIMPLE KOMEDA_FMT_SIMPLE_LAYER
#define RICH_SIMPLE (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_SIMPLE_LAYER)
#define RICH_WB (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_WB_LAYER)
#define RICH_SIMPLE_WB (RICH_SIMPLE | KOMEDA_FMT_WB_LAYER)
#define Rot_0 DRM_MODE_ROTATE_0
#define Flip_H_V (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | Rot_0)
#define Rot_ALL_H_V (DRM_MODE_ROTATE_MASK | Flip_H_V)
#define LYT_NM BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16)
#define LYT_WB BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
#define LYT_NM_WB (LYT_NM | LYT_WB)
#define AFB_TH AFBC(_TILED | _SPARSE)
#define AFB_TH_SC_YTR AFBC(_TILED | _SC | _SPARSE | _YTR)
#define AFB_TH_SC_YTR_BS AFBC(_TILED | _SC | _SPARSE | _YTR | _SPLIT)
static struct komeda_format_caps d71_format_caps_table[] = {
/* HW_ID | fourcc | layer_types | rots | afbc_layouts | afbc_features */
/* ABGR_2101010*/
{__HW_ID(0, 0), DRM_FORMAT_ARGB2101010, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
{__HW_ID(0, 2), DRM_FORMAT_RGBA1010102, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(0, 3), DRM_FORMAT_BGRA1010102, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
/* ABGR_8888*/
{__HW_ID(1, 0), DRM_FORMAT_ARGB8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(1, 1), DRM_FORMAT_ABGR8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(1, 1), DRM_FORMAT_ABGR8888, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
{__HW_ID(1, 2), DRM_FORMAT_RGBA8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(1, 3), DRM_FORMAT_BGRA8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
/* XBGB_8888 */
{__HW_ID(2, 0), DRM_FORMAT_XRGB8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(2, 1), DRM_FORMAT_XBGR8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(2, 2), DRM_FORMAT_RGBX8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(2, 3), DRM_FORMAT_BGRX8888, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
/* BGR_888 */ /* none-afbc RGB888 doesn't support rotation and flip */
{__HW_ID(3, 0), DRM_FORMAT_RGB888, RICH_SIMPLE_WB, Rot_0, 0, 0},
{__HW_ID(3, 1), DRM_FORMAT_BGR888, RICH_SIMPLE_WB, Rot_0, 0, 0},
{__HW_ID(3, 1), DRM_FORMAT_BGR888, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
/* BGR 16bpp */
{__HW_ID(4, 0), DRM_FORMAT_RGBA5551, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 1), DRM_FORMAT_ABGR1555, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 1), DRM_FORMAT_ABGR1555, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR}, /* afbc */
{__HW_ID(4, 2), DRM_FORMAT_RGB565, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 3), DRM_FORMAT_BGR565, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 3), DRM_FORMAT_BGR565, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR}, /* afbc */
{__HW_ID(4, 4), DRM_FORMAT_R8, SIMPLE, Rot_0, 0, 0},
/* YUV 444/422/420 8bit */
{__HW_ID(5, 1), DRM_FORMAT_YUYV, RICH, Rot_ALL_H_V, LYT_NM, AFB_TH}, /* afbc */
{__HW_ID(5, 2), DRM_FORMAT_YUYV, RICH, Flip_H_V, 0, 0},
{__HW_ID(5, 3), DRM_FORMAT_UYVY, RICH, Flip_H_V, 0, 0},
{__HW_ID(5, 6), DRM_FORMAT_NV12, RICH_WB, Flip_H_V, 0, 0},
{__HW_ID(5, 6), DRM_FORMAT_YUV420_8BIT, RICH, Rot_ALL_H_V, LYT_NM, AFB_TH}, /* afbc */
{__HW_ID(5, 7), DRM_FORMAT_YUV420, RICH, Flip_H_V, 0, 0},
/* YUV 10bit*/
{__HW_ID(6, 6), DRM_FORMAT_X0L2, RICH, Flip_H_V, 0, 0},
{__HW_ID(6, 7), DRM_FORMAT_P010, RICH, Flip_H_V, 0, 0},
{__HW_ID(6, 7), DRM_FORMAT_YUV420_10BIT, RICH, Rot_ALL_H_V, LYT_NM, AFB_TH},
};
static bool d71_format_mod_supported(const struct komeda_format_caps *caps,
u32 layer_type, u64 modifier, u32 rot)
{
uint64_t layout = modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK;
if ((layout == AFBC_FORMAT_MOD_BLOCK_SIZE_32x8) &&
drm_rotation_90_or_270(rot)) {
DRM_DEBUG_ATOMIC("D71 doesn't support ROT90 for WB-AFBC.\n");
return false;
}
return true;
}
static void d71_init_fmt_tbl(struct komeda_dev *mdev)
{
struct komeda_format_caps_table *table = &mdev->fmt_tbl;
table->format_caps = d71_format_caps_table;
table->format_mod_supported = d71_format_mod_supported;
table->n_formats = ARRAY_SIZE(d71_format_caps_table);
}
static int d71_connect_iommu(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
u32 __iomem *reg = d71->gcu_addr;
u32 check_bits = (d71->num_pipelines == 2) ?
GCU_STATUS_TCS0 | GCU_STATUS_TCS1 : GCU_STATUS_TCS0;
int i, ret;
if (!d71->integrates_tbu)
return -1;
malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_CONNECT_MODE);
ret = dp_wait_cond(has_bits(check_bits, malidp_read32(reg, BLK_STATUS)),
100, 1000, 1000);
if (ret < 0) {
DRM_ERROR("timed out connecting to TCU!\n");
malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE);
return ret;
}
for (i = 0; i < d71->num_pipelines; i++)
malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL,
LPU_TBU_CTRL_TLBPEN, LPU_TBU_CTRL_TLBPEN);
return 0;
}
static int d71_disconnect_iommu(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
u32 __iomem *reg = d71->gcu_addr;
u32 check_bits = (d71->num_pipelines == 2) ?
GCU_STATUS_TCS0 | GCU_STATUS_TCS1 : GCU_STATUS_TCS0;
int ret;
malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_DISCONNECT_MODE);
ret = dp_wait_cond(((malidp_read32(reg, BLK_STATUS) & check_bits) == 0),
100, 1000, 1000);
if (ret < 0) {
DRM_ERROR("timed out disconnecting from TCU!\n");
malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE);
}
return ret;
}
static const struct komeda_dev_funcs d71_chip_funcs = {
.init_format_table = d71_init_fmt_tbl,
.enum_resources = d71_enum_resources,
.cleanup = d71_cleanup,
.irq_handler = d71_irq_handler,
.enable_irq = d71_enable_irq,
.disable_irq = d71_disable_irq,
.on_off_vblank = d71_on_off_vblank,
.change_opmode = d71_change_opmode,
.flush = d71_flush,
.connect_iommu = d71_connect_iommu,
.disconnect_iommu = d71_disconnect_iommu,
.dump_register = d71_dump,
};
const struct komeda_dev_funcs *
d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
{
const struct komeda_dev_funcs *funcs;
u32 product_id;
chip->core_id = malidp_read32(reg_base, GLB_CORE_ID);
product_id = MALIDP_CORE_ID_PRODUCT_ID(chip->core_id);
switch (product_id) {
case MALIDP_D71_PRODUCT_ID:
case MALIDP_D32_PRODUCT_ID:
case LINLONDP_D6_PRODUCT_ID:
funcs = &d71_chip_funcs;
break;
default:
DRM_ERROR("Unsupported product: 0x%x\n", product_id);
return NULL;
}
chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID);
chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
chip->bus_width = D71_BUS_WIDTH_16_BYTES;
return funcs;
}
linux-7.2.3/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h
+54
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _D71_DEV_H_
#define _D71_DEV_H_
#include "komeda_dev.h"
#include "komeda_pipeline.h"
#include "d71_regs.h"
struct d71_pipeline {
struct komeda_pipeline base;
/* d71 private pipeline blocks */
u32 __iomem *lpu_addr;
u32 __iomem *cu_addr;
u32 __iomem *dou_addr;
u32 __iomem *dou_ft_coeff_addr; /* forward transform coeffs table */
};
struct d71_dev {
struct komeda_dev *mdev;
int num_blocks;
int num_pipelines;
int num_rich_layers;
u32 max_line_size;
u32 max_vsize;
u32 supports_dual_link : 1;
u32 integrates_tbu : 1;
/* global register blocks */
u32 __iomem *gcu_addr;
/* scaling coeffs table */
u32 __iomem *glb_scl_coeff_addr[D71_MAX_GLB_SCL_COEFF];
u32 __iomem *periph_addr;
struct d71_pipeline *pipes[D71_MAX_PIPELINE];
};
#define to_d71_pipeline(x) container_of(x, struct d71_pipeline, base)
extern const struct komeda_pipeline_funcs d71_pipeline_funcs;
int d71_probe_block(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg);
void d71_read_block_header(u32 __iomem *reg, struct block_header *blk);
void d71_dump(struct komeda_dev *mdev, struct seq_file *sf);
#endif /* !_D71_DEV_H_ */
linux-7.2.3/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
+541
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _D71_REG_H_
#define _D71_REG_H_
/* Common block registers offset */
#define BLK_BLOCK_INFO 0x000
#define BLK_PIPELINE_INFO 0x004
#define BLK_MAX_LINE_SIZE 0x008
#define BLK_VALID_INPUT_ID0 0x020
#define BLK_OUTPUT_ID0 0x060
#define BLK_INPUT_ID0 0x080
#define BLK_IRQ_RAW_STATUS 0x0A0
#define BLK_IRQ_CLEAR 0x0A4
#define BLK_IRQ_MASK 0x0A8
#define BLK_IRQ_STATUS 0x0AC
#define BLK_STATUS 0x0B0
#define BLK_INFO 0x0C0
#define BLK_CONTROL 0x0D0
#define BLK_SIZE 0x0D4
#define BLK_IN_SIZE 0x0E0
#define BLK_P0_PTR_LOW 0x100
#define BLK_P0_PTR_HIGH 0x104
#define BLK_P0_STRIDE 0x108
#define BLK_P1_PTR_LOW 0x110
#define BLK_P1_PTR_HIGH 0x114
#define BLK_P1_STRIDE 0x118
#define BLK_P2_PTR_LOW 0x120
#define BLK_P2_PTR_HIGH 0x124
#define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F)
#define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4)
#define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8)
#define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0)
#define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4)
#define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F)
#define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8)
/* Common block control register bits */
#define BLK_CTRL_EN BIT(0)
/* Common size macro */
#define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
#define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
#define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
/* AD_CONTROL register */
#define AD_CONTROL 0x160
/* AD_CONTROL register bits */
#define AD_AEN BIT(0)
#define AD_YT BIT(1)
#define AD_BS BIT(2)
#define AD_WB BIT(3)
#define AD_TH BIT(4)
/* Global Control Unit */
#define GLB_ARCH_ID 0x000
#define GLB_CORE_ID 0x004
#define GLB_CORE_INFO 0x008
#define GLB_IRQ_STATUS 0x010
#define GCU_CONFIG_VALID0 0x0D4
#define GCU_CONFIG_VALID1 0x0D8
/* GCU_CONTROL_BITS */
#define GCU_CONTROL_MODE(x) ((x) & 0x7)
#define GCU_CONTROL_SRST BIT(16)
/* GCU_CONFIGURATION registers */
#define GCU_CONFIGURATION_ID0 0x100
#define GCU_CONFIGURATION_ID1 0x104
/* GCU configuration */
#define GCU_MAX_LINE_SIZE(x) ((x) & 0xFFFF)
#define GCU_MAX_NUM_LINES(x) ((x) >> 16)
#define GCU_NUM_RICH_LAYERS(x) ((x) & 0x7)
#define GCU_NUM_PIPELINES(x) (((x) >> 3) & 0x7)
#define GCU_NUM_SCALERS(x) (((x) >> 6) & 0x7)
#define GCU_DISPLAY_SPLIT_EN(x) (((x) >> 16) & 0x1)
#define GCU_DISPLAY_TBU_EN(x) (((x) >> 17) & 0x1)
/* GCU opmode */
#define INACTIVE_MODE 0
#define TBU_CONNECT_MODE 1
#define TBU_DISCONNECT_MODE 2
#define DO0_ACTIVE_MODE 3
#define DO1_ACTIVE_MODE 4
#define DO01_ACTIVE_MODE 5
/* GLB_IRQ_STATUS bits */
#define GLB_IRQ_STATUS_GCU BIT(0)
#define GLB_IRQ_STATUS_LPU0 BIT(8)
#define GLB_IRQ_STATUS_LPU1 BIT(9)
#define GLB_IRQ_STATUS_ATU0 BIT(10)
#define GLB_IRQ_STATUS_ATU1 BIT(11)
#define GLB_IRQ_STATUS_ATU2 BIT(12)
#define GLB_IRQ_STATUS_ATU3 BIT(13)
#define GLB_IRQ_STATUS_CU0 BIT(16)
#define GLB_IRQ_STATUS_CU1 BIT(17)
#define GLB_IRQ_STATUS_DOU0 BIT(24)
#define GLB_IRQ_STATUS_DOU1 BIT(25)
#define GLB_IRQ_STATUS_PIPE0 (GLB_IRQ_STATUS_LPU0 |\
GLB_IRQ_STATUS_ATU0 |\
GLB_IRQ_STATUS_ATU1 |\
GLB_IRQ_STATUS_CU0 |\
GLB_IRQ_STATUS_DOU0)
#define GLB_IRQ_STATUS_PIPE1 (GLB_IRQ_STATUS_LPU1 |\
GLB_IRQ_STATUS_ATU2 |\
GLB_IRQ_STATUS_ATU3 |\
GLB_IRQ_STATUS_CU1 |\
GLB_IRQ_STATUS_DOU1)
#define GLB_IRQ_STATUS_ATU (GLB_IRQ_STATUS_ATU0 |\
GLB_IRQ_STATUS_ATU1 |\
GLB_IRQ_STATUS_ATU2 |\
GLB_IRQ_STATUS_ATU3)
/* GCU_IRQ_BITS */
#define GCU_IRQ_CVAL0 BIT(0)
#define GCU_IRQ_CVAL1 BIT(1)
#define GCU_IRQ_MODE BIT(4)
#define GCU_IRQ_ERR BIT(11)
/* GCU_STATUS_BITS */
#define GCU_STATUS_MODE(x) ((x) & 0x7)
#define GCU_STATUS_MERR BIT(4)
#define GCU_STATUS_TCS0 BIT(8)
#define GCU_STATUS_TCS1 BIT(9)
#define GCU_STATUS_ACTIVE BIT(31)
/* GCU_CONFIG_VALIDx BITS */
#define GCU_CONFIG_CVAL BIT(0)
/* PERIPHERAL registers */
#define PERIPH_MAX_LINE_SIZE BIT(0)
#define PERIPH_NUM_RICH_LAYERS BIT(4)
#define PERIPH_SPLIT_EN BIT(8)
#define PERIPH_TBU_EN BIT(12)
#define PERIPH_AFBC_DMA_EN BIT(16)
#define PERIPH_CONFIGURATION_ID 0x1D4
/* LPU register */
#define LPU_TBU_STATUS 0x0B4
#define LPU_RAXI_CONTROL 0x0D0
#define LPU_WAXI_CONTROL 0x0D4
#define LPU_TBU_CONTROL 0x0D8
/* LPU_xAXI_CONTROL_BITS */
#define TO_RAXI_AOUTSTDCAPB(x) (x)
#define TO_RAXI_BOUTSTDCAPB(x) ((x) << 8)
#define TO_RAXI_BEN(x) ((x) << 15)
#define TO_xAXI_BURSTLEN(x) ((x) << 16)
#define TO_xAXI_AxQOS(x) ((x) << 24)
#define TO_xAXI_ORD(x) ((x) << 31)
#define TO_WAXI_OUTSTDCAPB(x) (x)
#define RAXI_AOUTSTDCAPB_MASK 0x7F
#define RAXI_BOUTSTDCAPB_MASK 0x7F00
#define RAXI_BEN_MASK BIT(15)
#define xAXI_BURSTLEN_MASK 0x3F0000
#define xAXI_AxQOS_MASK 0xF000000
#define xAXI_ORD_MASK BIT(31)
#define WAXI_OUTSTDCAPB_MASK 0x3F
/* LPU_TBU_CONTROL BITS */
#define TO_TBU_DOUTSTDCAPB(x) (x)
#define TBU_DOUTSTDCAPB_MASK 0x3F
/* LPU_IRQ_BITS */
#define LPU_IRQ_OVR BIT(9)
#define LPU_IRQ_IBSY BIT(10)
#define LPU_IRQ_ERR BIT(11)
#define LPU_IRQ_EOW BIT(12)
#define LPU_IRQ_PL0 BIT(13)
/* LPU_STATUS_BITS */
#define LPU_STATUS_AXIED(x) ((x) & 0xF)
#define LPU_STATUS_AXIE BIT(4)
#define LPU_STATUS_AXIRP BIT(5)
#define LPU_STATUS_AXIWP BIT(6)
#define LPU_STATUS_FEMPTY BIT(11)
#define LPU_STATUS_FFULL BIT(14)
#define LPU_STATUS_ACE0 BIT(16)
#define LPU_STATUS_ACE1 BIT(17)
#define LPU_STATUS_ACE2 BIT(18)
#define LPU_STATUS_ACE3 BIT(19)
#define LPU_STATUS_ACTIVE BIT(31)
#define AXIEID_MASK 0xF
#define AXIE_MASK LPU_STATUS_AXIE
#define AXIRP_MASK LPU_STATUS_AXIRP
#define AXIWP_MASK LPU_STATUS_AXIWP
#define FROM_AXIEID(reg) ((reg) & AXIEID_MASK)
#define TO_AXIE(x) ((x) << 4)
#define FROM_AXIRP(reg) (((reg) & AXIRP_MASK) >> 5)
#define FROM_AXIWP(reg) (((reg) & AXIWP_MASK) >> 6)
/* LPU_TBU_STATUS_BITS */
#define LPU_TBU_STATUS_TCF BIT(1)
#define LPU_TBU_STATUS_TTNG BIT(2)
#define LPU_TBU_STATUS_TITR BIT(8)
#define LPU_TBU_STATUS_TEMR BIT(16)
#define LPU_TBU_STATUS_TTF BIT(31)
/* LPU_TBU_CONTROL BITS */
#define LPU_TBU_CTRL_TLBPEN BIT(16)
/* CROSSBAR CONTROL BITS */
#define CBU_INPUT_CTRL_EN BIT(0)
#define CBU_NUM_INPUT_IDS 5
#define CBU_NUM_OUTPUT_IDS 5
/* CU register */
#define CU_BG_COLOR 0x0DC
#define CU_INPUT0_SIZE 0x0E0
#define CU_INPUT0_OFFSET 0x0E4
#define CU_INPUT0_CONTROL 0x0E8
#define CU_INPUT1_SIZE 0x0F0
#define CU_INPUT1_OFFSET 0x0F4
#define CU_INPUT1_CONTROL 0x0F8
#define CU_INPUT2_SIZE 0x100
#define CU_INPUT2_OFFSET 0x104
#define CU_INPUT2_CONTROL 0x108
#define CU_INPUT3_SIZE 0x110
#define CU_INPUT3_OFFSET 0x114
#define CU_INPUT3_CONTROL 0x118
#define CU_INPUT4_SIZE 0x120
#define CU_INPUT4_OFFSET 0x124
#define CU_INPUT4_CONTROL 0x128
#define CU_PER_INPUT_REGS 4
#define CU_NUM_INPUT_IDS 5
#define CU_NUM_OUTPUT_IDS 1
/* CU control register bits */
#define CU_CTRL_COPROC BIT(0)
/* CU_IRQ_BITS */
#define CU_IRQ_OVR BIT(9)
#define CU_IRQ_ERR BIT(11)
/* CU_STATUS_BITS */
#define CU_STATUS_CPE BIT(0)
#define CU_STATUS_ZME BIT(1)
#define CU_STATUS_CFGE BIT(2)
#define CU_STATUS_ACTIVE BIT(31)
/* CU input control register bits */
#define CU_INPUT_CTRL_EN BIT(0)
#define CU_INPUT_CTRL_PAD BIT(1)
#define CU_INPUT_CTRL_PMUL BIT(2)
#define CU_INPUT_CTRL_ALPHA(x) (((x) & 0xFF) << 8)
/* DOU register */
/* DOU_IRQ_BITS */
#define DOU_IRQ_UND BIT(8)
#define DOU_IRQ_ERR BIT(11)
#define DOU_IRQ_PL0 BIT(13)
#define DOU_IRQ_PL1 BIT(14)
/* DOU_STATUS_BITS */
#define DOU_STATUS_DRIFTTO BIT(0)
#define DOU_STATUS_FRAMETO BIT(1)
#define DOU_STATUS_TETO BIT(2)
#define DOU_STATUS_CSCE BIT(8)
#define DOU_STATUS_ACTIVE BIT(31)
/* Layer registers */
#define LAYER_INFO 0x0C0
#define LAYER_R_CONTROL 0x0D4
#define LAYER_FMT 0x0D8
#define LAYER_LT_COEFFTAB 0x0DC
#define LAYER_PALPHA 0x0E4
#define LAYER_YUV_RGB_COEFF0 0x130
#define LAYER_AD_H_CROP 0x164
#define LAYER_AD_V_CROP 0x168
#define LAYER_RGB_RGB_COEFF0 0x170
/* L_CONTROL_BITS */
#define L_EN BIT(0)
#define L_IT BIT(4)
#define L_R2R BIT(5)
#define L_FT BIT(6)
#define L_ROT(x) (((x) & 3) << 8)
#define L_HFLIP BIT(10)
#define L_VFLIP BIT(11)
#define L_TBU_EN BIT(16)
#define L_A_RCACHE(x) (((x) & 0xF) << 28)
#define L_ROT_R0 0
#define L_ROT_R90 1
#define L_ROT_R180 2
#define L_ROT_R270 3
/* LAYER_R_CONTROL BITS */
#define LR_CHI422_BILINEAR 0
#define LR_CHI422_REPLICATION 1
#define LR_CHI420_JPEG (0 << 2)
#define LR_CHI420_MPEG (1 << 2)
#define L_ITSEL(x) ((x) & 0xFFF)
#define L_FTSEL(x) (((x) & 0xFFF) << 16)
#define LAYER_PER_PLANE_REGS 4
/* Layer_WR registers */
#define LAYER_WR_PROG_LINE 0x0D4
#define LAYER_WR_FORMAT 0x0D8
/* Layer_WR control bits */
#define LW_OFM BIT(4)
#define LW_LALPHA(x) (((x) & 0xFF) << 8)
#define LW_A_WCACHE(x) (((x) & 0xF) << 28)
#define LW_TBU_EN BIT(16)
#define AxCACHE_MASK 0xF0000000
/* Layer AXI R/W cache setting */
#define AxCACHE_B BIT(0) /* Bufferable */
#define AxCACHE_M BIT(1) /* Modifiable */
#define AxCACHE_RA BIT(2) /* Read-Allocate */
#define AxCACHE_WA BIT(3) /* Write-Allocate */
/* Layer info bits */
#define L_INFO_RF BIT(0)
#define L_INFO_CM BIT(1)
#define L_INFO_ABUF_SIZE(x) (((x) >> 4) & 0x7)
#define L_INFO_YUV_MAX_LINESZ(x) (((x) >> 16) & 0xFFFF)
/* Scaler registers */
#define SC_COEFFTAB 0x0DC
#define SC_OUT_SIZE 0x0E4
#define SC_H_CROP 0x0E8
#define SC_V_CROP 0x0EC
#define SC_H_INIT_PH 0x0F0
#define SC_H_DELTA_PH 0x0F4
#define SC_V_INIT_PH 0x0F8
#define SC_V_DELTA_PH 0x0FC
#define SC_ENH_LIMITS 0x130
#define SC_ENH_COEFF0 0x134
#define SC_MAX_ENH_COEFF 9
/* SC_CTRL_BITS */
#define SC_CTRL_SCL BIT(0)
#define SC_CTRL_LS BIT(1)
#define SC_CTRL_AP BIT(4)
#define SC_CTRL_IENH BIT(8)
#define SC_CTRL_RGBSM BIT(16)
#define SC_CTRL_ASM BIT(17)
#define SC_VTSEL(vtal) ((vtal) << 16)
#define SC_NUM_INPUTS_IDS 1
#define SC_NUM_OUTPUTS_IDS 1
#define MG_NUM_INPUTS_IDS 2
#define MG_NUM_OUTPUTS_IDS 1
/* Merger registers */
#define MG_INPUT_ID0 BLK_INPUT_ID0
#define MG_INPUT_ID1 (MG_INPUT_ID0 + 4)
#define MG_SIZE BLK_SIZE
/* Splitter registers */
#define SP_OVERLAP_SIZE 0xD8
/* Backend registers */
#define BS_INFO 0x0C0
#define BS_PROG_LINE 0x0D4
#define BS_PREFETCH_LINE 0x0D8
#define BS_BG_COLOR 0x0DC
#define BS_ACTIVESIZE 0x0E0
#define BS_HINTERVALS 0x0E4
#define BS_VINTERVALS 0x0E8
#define BS_SYNC 0x0EC
#define BS_DRIFT_TO 0x100
#define BS_FRAME_TO 0x104
#define BS_TE_TO 0x108
#define BS_T0_INTERVAL 0x110
#define BS_T1_INTERVAL 0x114
#define BS_T2_INTERVAL 0x118
#define BS_CRC0_LOW 0x120
#define BS_CRC0_HIGH 0x124
#define BS_CRC1_LOW 0x128
#define BS_CRC1_HIGH 0x12C
#define BS_USER 0x130
/* BS control register bits */
#define BS_CTRL_EN BIT(0)
#define BS_CTRL_VM BIT(1)
#define BS_CTRL_BM BIT(2)
#define BS_CTRL_HMASK BIT(4)
#define BS_CTRL_VD BIT(5)
#define BS_CTRL_TE BIT(8)
#define BS_CTRL_TS BIT(9)
#define BS_CTRL_TM BIT(12)
#define BS_CTRL_DL BIT(16)
#define BS_CTRL_SBS BIT(17)
#define BS_CTRL_CRC BIT(18)
#define BS_CTRL_PM BIT(20)
/* BS active size/intervals */
#define BS_H_INTVALS(hfp, hbp) (((hfp) & 0xFFF) + (((hbp) & 0x3FF) << 16))
#define BS_V_INTVALS(vfp, vbp) (((vfp) & 0x3FFF) + (((vbp) & 0xFF) << 16))
/* BS_SYNC bits */
#define BS_SYNC_HSW(x) ((x) & 0x3FF)
#define BS_SYNC_HSP BIT(12)
#define BS_SYNC_VSW(x) (((x) & 0xFF) << 16)
#define BS_SYNC_VSP BIT(28)
#define BS_NUM_INPUT_IDS 0
#define BS_NUM_OUTPUT_IDS 0
/* Image process registers */
#define IPS_DEPTH 0x0D8
#define IPS_RGB_RGB_COEFF0 0x130
#define IPS_RGB_YUV_COEFF0 0x170
#define IPS_DEPTH_MARK 0xF
/* IPS control register bits */
#define IPS_CTRL_RGB BIT(0)
#define IPS_CTRL_FT BIT(4)
#define IPS_CTRL_YUV BIT(8)
#define IPS_CTRL_CHD422 BIT(9)
#define IPS_CTRL_CHD420 BIT(10)
#define IPS_CTRL_LPF BIT(11)
#define IPS_CTRL_DITH BIT(12)
#define IPS_CTRL_CLAMP BIT(16)
#define IPS_CTRL_SBS BIT(17)
/* IPS info register bits */
#define IPS_INFO_CHD420 BIT(10)
#define IPS_NUM_INPUT_IDS 2
#define IPS_NUM_OUTPUT_IDS 1
/* FT_COEFF block registers */
#define FT_COEFF0 0x80
#define GLB_IT_COEFF 0x80
/* GLB_SC_COEFF registers */
#define GLB_SC_COEFF_ADDR 0x0080
#define GLB_SC_COEFF_DATA 0x0084
#define GLB_LT_COEFF_DATA 0x0080
#define GLB_SC_COEFF_MAX_NUM 1024
#define GLB_LT_COEFF_NUM 65
/* GLB_SC_ADDR */
#define SC_COEFF_R_ADDR BIT(18)
#define SC_COEFF_G_ADDR BIT(17)
#define SC_COEFF_B_ADDR BIT(16)
#define SC_COEFF_DATA(x, y) (((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))
enum d71_blk_type {
D71_BLK_TYPE_GCU = 0x00,
D71_BLK_TYPE_LPU = 0x01,
D71_BLK_TYPE_CU = 0x02,
D71_BLK_TYPE_DOU = 0x03,
D71_BLK_TYPE_AEU = 0x04,
D71_BLK_TYPE_GLB_LT_COEFF = 0x05,
D71_BLK_TYPE_GLB_SCL_COEFF = 0x06, /* SH/SV scaler coeff */
D71_BLK_TYPE_GLB_SC_COEFF = 0x07,
D71_BLK_TYPE_PERIPH = 0x08,
D71_BLK_TYPE_LPU_TRUSTED = 0x09,
D71_BLK_TYPE_AEU_TRUSTED = 0x0A,
D71_BLK_TYPE_LPU_LAYER = 0x10,
D71_BLK_TYPE_LPU_WB_LAYER = 0x11,
D71_BLK_TYPE_CU_SPLITTER = 0x20,
D71_BLK_TYPE_CU_SCALER = 0x21,
D71_BLK_TYPE_CU_MERGER = 0x22,
D71_BLK_TYPE_DOU_IPS = 0x30,
D71_BLK_TYPE_DOU_BS = 0x31,
D71_BLK_TYPE_DOU_FT_COEFF = 0x32,
D71_BLK_TYPE_AEU_DS = 0x40,
D71_BLK_TYPE_AEU_AES = 0x41,
D71_BLK_TYPE_RESERVED = 0xFF
};
/* Constant of components */
#define D71_MAX_PIPELINE 2
#define D71_PIPELINE_MAX_SCALERS 2
#define D71_PIPELINE_MAX_LAYERS 4
#define D71_MAX_GLB_IT_COEFF 3
#define D71_MAX_GLB_SCL_COEFF 4
#define D71_MAX_LAYERS_PER_LPU 4
#define D71_BLOCK_MAX_INPUT 9
#define D71_BLOCK_MAX_OUTPUT 5
#define D71_MAX_SC_PER_CU 2
#define D71_BLOCK_OFFSET_PERIPH 0xFE00
#define D71_BLOCK_SIZE 0x0200
#define D71_DEFAULT_PREPRETCH_LINE 5
#define D71_BUS_WIDTH_16_BYTES 16
#define D71_SC_MAX_UPSCALING 64
#define D71_SC_MAX_DOWNSCALING 6
#define D71_SC_SPLIT_OVERLAP 8
#define D71_SC_ENH_SPLIT_OVERLAP 1
#define D71_MG_MIN_MERGED_SIZE 4
#define D71_MG_MAX_MERGED_HSIZE 4032
#define D71_MG_MAX_MERGED_VSIZE 4096
#define D71_PALPHA_DEF_MAP 0xFFAA5500
#define D71_LAYER_CONTROL_DEFAULT 0x30000000
#define D71_WB_LAYER_CONTROL_DEFAULT 0x3000FF00
#define D71_BS_CONTROL_DEFAULT 0x00000002
struct block_header {
u32 block_info;
u32 pipeline_info;
u32 input_ids[D71_BLOCK_MAX_INPUT];
u32 output_ids[D71_BLOCK_MAX_OUTPUT];
};
static inline u32 get_block_type(struct block_header *blk)
{
return BLOCK_INFO_BLK_TYPE(blk->block_info);
}
#endif /* !_D71_REG_H_ */