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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
config DRM_ATMEL_HLCDC
tristate "DRM Support for ATMEL HLCDC Display Controller"
depends on DRM && OF && COMMON_CLK && ((MFD_ATMEL_HLCDC && ARM) || COMPILE_TEST)
select DRM_CLIENT_SELECTION
select DRM_GEM_DMA_HELPER
select DRM_KMS_HELPER
select DRM_PANEL
help
Choose this option if you have an ATMEL SoC with an HLCDC display
controller (i.e. at91sam9n12, at91sam9x5 family or sama5d3 family).
linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/Makefile
+7
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# SPDX-License-Identifier: GPL-2.0
atmel-hlcdc-dc-y := atmel_hlcdc_crtc.o \
atmel_hlcdc_dc.o \
atmel_hlcdc_output.o \
atmel_hlcdc_plane.o
obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc-dc.o
linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+661
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Traphandler
* Copyright (C) 2014 Free Electrons
*
* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
*/
#include <linux/clk.h>
#include <linux/media-bus-format.h>
#include <linux/mfd/atmel-hlcdc.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <video/videomode.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_modeset_helper_vtables.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
#include "atmel_hlcdc_dc.h"
/**
* struct atmel_hlcdc_crtc_state - Atmel HLCDC CRTC state structure
*
* @base: base CRTC state
* @output_mode: RGBXXX output mode
* @dpi: output DPI mode
*/
struct atmel_hlcdc_crtc_state {
struct drm_crtc_state base;
unsigned int output_mode;
u8 dpi;
};
static inline struct atmel_hlcdc_crtc_state *
drm_crtc_state_to_atmel_hlcdc_crtc_state(struct drm_crtc_state *state)
{
return container_of(state, struct atmel_hlcdc_crtc_state, base);
}
/**
* struct atmel_hlcdc_crtc - Atmel HLCDC CRTC structure
*
* @base: base DRM CRTC structure
* @dc: pointer to the atmel_hlcdc structure provided by the MFD device
* @event: pointer to the current page flip event
* @id: CRTC id (returned by drm_crtc_index)
*/
struct atmel_hlcdc_crtc {
struct drm_crtc base;
struct atmel_hlcdc_dc *dc;
struct drm_pending_vblank_event *event;
int id;
};
static inline struct atmel_hlcdc_crtc *
drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
{
return container_of(crtc, struct atmel_hlcdc_crtc, base);
}
static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
{
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
struct regmap *regmap = crtc->dc->hlcdc->regmap;
struct drm_display_mode *adj = &c->state->adjusted_mode;
struct drm_encoder *encoder = NULL, *en_iter;
struct drm_connector *connector = NULL;
struct atmel_hlcdc_crtc_state *state;
struct drm_device *ddev = c->dev;
struct drm_connector_list_iter iter;
unsigned long mode_rate;
struct videomode vm;
unsigned long prate;
unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL;
unsigned int cfg = 0;
int div, ret;
/* get encoder from crtc */
drm_for_each_encoder(en_iter, ddev) {
if (en_iter->crtc == c) {
encoder = en_iter;
break;
}
}
if (encoder) {
/* Get the connector from encoder */
drm_connector_list_iter_begin(ddev, &iter);
drm_for_each_connector_iter(connector, &iter)
if (connector->encoder == encoder)
break;
drm_connector_list_iter_end(&iter);
}
ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
if (ret)
return;
vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;
regmap_write(regmap, ATMEL_HLCDC_CFG(1),
(vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16));
regmap_write(regmap, ATMEL_HLCDC_CFG(2),
(vm.vfront_porch - 1) | (vm.vback_porch << 16));
regmap_write(regmap, ATMEL_HLCDC_CFG(3),
(vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16));
regmap_write(regmap, ATMEL_HLCDC_CFG(4),
(adj->crtc_hdisplay - 1) |
((adj->crtc_vdisplay - 1) << 16));
prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
mode_rate = adj->crtc_clock * 1000;
if (!crtc->dc->desc->fixed_clksrc) {
prate *= 2;
cfg |= ATMEL_HLCDC_CLKSEL;
mask |= ATMEL_HLCDC_CLKSEL;
}
div = DIV_ROUND_UP(prate, mode_rate);
if (div < 2) {
div = 2;
} else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) {
/* The divider ended up too big, try a lower base rate. */
cfg &= ~ATMEL_HLCDC_CLKSEL;
prate /= 2;
div = DIV_ROUND_UP(prate, mode_rate);
if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK)
div = ATMEL_HLCDC_CLKDIV_MASK;
} else {
int div_low = prate / mode_rate;
if (div_low >= 2 &&
(10 * (prate / div_low - mode_rate) <
(mode_rate - prate / div)))
/*
* At least 10 times better when using a higher
* frequency than requested, instead of a lower.
* So, go with that.
*/
div = div_low;
}
cfg |= ATMEL_HLCDC_CLKDIV(div);
if (connector &&
connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
cfg |= ATMEL_HLCDC_CLKPOL;
regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg);
state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);
cfg = state->output_mode << 8;
if (!crtc->dc->desc->is_xlcdc) {
if (adj->flags & DRM_MODE_FLAG_NVSYNC)
cfg |= ATMEL_HLCDC_VSPOL;
if (adj->flags & DRM_MODE_FLAG_NHSYNC)
cfg |= ATMEL_HLCDC_HSPOL;
} else {
cfg |= state->dpi << 11;
}
regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
ATMEL_HLCDC_GUARDTIME_MASK |
(crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_MODE_MASK |
ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK),
cfg);
clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
}
static enum drm_mode_status
atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c,
const struct drm_display_mode *mode)
{
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
}
static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c,
struct drm_atomic_commit *state)
{
struct drm_device *dev = c->dev;
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
struct regmap *regmap = crtc->dc->hlcdc->regmap;
unsigned int status;
drm_crtc_vblank_off(c);
pm_runtime_get_sync(dev->dev);
if (crtc->dc->desc->is_xlcdc) {
regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
!(status & ATMEL_XLCDC_CM),
10, 1000))
drm_warn(dev, "Atmel LCDC status register CMSTS timeout\n");
regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
status & ATMEL_XLCDC_SD,
10, 1000))
drm_warn(dev, "Atmel LCDC status register SDSTS timeout\n");
}
regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
!(status & ATMEL_HLCDC_DISP),
10, 1000))
drm_warn(dev, "Atmel LCDC status register DISPSTS timeout\n");
regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
!(status & ATMEL_HLCDC_SYNC),
10, 1000))
drm_warn(dev, "Atmel LCDC status register LCDSTS timeout\n");
regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
!(status & ATMEL_HLCDC_PIXEL_CLK),
10, 1000))
drm_warn(dev, "Atmel LCDC status register CLKSTS timeout\n");
clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
pinctrl_pm_select_sleep_state(dev->dev);
pm_runtime_allow(dev->dev);
pm_runtime_put_sync(dev->dev);
}
static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,
struct drm_atomic_commit *state)
{
struct drm_device *dev = c->dev;
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
struct regmap *regmap = crtc->dc->hlcdc->regmap;
unsigned int status;
pm_runtime_get_sync(dev->dev);
pm_runtime_forbid(dev->dev);
pinctrl_pm_select_default_state(dev->dev);
clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
status & ATMEL_HLCDC_PIXEL_CLK,
10, 1000))
drm_warn(dev, "Atmel LCDC status register CLKSTS timeout\n");
regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
status & ATMEL_HLCDC_SYNC,
10, 1000))
drm_warn(dev, "Atmel LCDC status register LCDSTS timeout\n");
regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
status & ATMEL_HLCDC_DISP,
10, 1000))
drm_warn(dev, "Atmel LCDC status register DISPSTS timeout\n");
if (crtc->dc->desc->is_xlcdc) {
regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
status & ATMEL_XLCDC_CM,
10, 1000))
drm_warn(dev, "Atmel LCDC status register CMSTS timeout\n");
regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD);
if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
!(status & ATMEL_XLCDC_SD),
10, 1000))
drm_warn(dev, "Atmel LCDC status register SDSTS timeout\n");
}
pm_runtime_put_sync(dev->dev);
}
#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0)
#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1)
#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2)
#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3)
#define ATMEL_HLCDC_DPI_RGB565C1_OUTPUT BIT(4)
#define ATMEL_HLCDC_DPI_RGB565C2_OUTPUT BIT(5)
#define ATMEL_HLCDC_DPI_RGB565C3_OUTPUT BIT(6)
#define ATMEL_HLCDC_DPI_RGB666C1_OUTPUT BIT(7)
#define ATMEL_HLCDC_DPI_RGB666C2_OUTPUT BIT(8)
#define ATMEL_HLCDC_DPI_RGB888_OUTPUT BIT(9)
#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0)
#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0)
static int atmel_xlcdc_connector_output_dsi(struct drm_encoder *encoder,
struct drm_display_info *info)
{
int j;
unsigned int supported_fmts = 0;
switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {
case 0:
break;
case MEDIA_BUS_FMT_RGB565_1X16:
return ATMEL_HLCDC_DPI_RGB565C1_OUTPUT;
case MEDIA_BUS_FMT_RGB666_1X18:
return ATMEL_HLCDC_DPI_RGB666C1_OUTPUT;
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
return ATMEL_HLCDC_DPI_RGB666C2_OUTPUT;
case MEDIA_BUS_FMT_RGB888_1X24:
return ATMEL_HLCDC_DPI_RGB888_OUTPUT;
default:
return -EINVAL;
}
for (j = 0; j < info->num_bus_formats; j++) {
switch (info->bus_formats[j]) {
case MEDIA_BUS_FMT_RGB565_1X16:
supported_fmts |= ATMEL_HLCDC_DPI_RGB565C1_OUTPUT;
break;
case MEDIA_BUS_FMT_RGB666_1X18:
supported_fmts |= ATMEL_HLCDC_DPI_RGB666C1_OUTPUT;
break;
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
supported_fmts |= ATMEL_HLCDC_DPI_RGB666C2_OUTPUT;
break;
case MEDIA_BUS_FMT_RGB888_1X24:
supported_fmts |= ATMEL_HLCDC_DPI_RGB888_OUTPUT;
break;
default:
break;
}
}
return supported_fmts;
}
static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state)
{
struct drm_connector *connector = state->connector;
struct drm_display_info *info = &connector->display_info;
struct drm_encoder *encoder;
unsigned int supported_fmts = 0;
int j;
encoder = state->best_encoder;
if (!encoder)
encoder = connector->encoder;
/*
* atmel-hlcdc to support DSI formats with DSI video pipeline
* when DRM_MODE_ENCODER_DSI type is set by
* connector driver component.
*/
if (encoder->encoder_type == DRM_MODE_ENCODER_DSI)
return atmel_xlcdc_connector_output_dsi(encoder, info);
switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {
case 0:
break;
case MEDIA_BUS_FMT_RGB444_1X12:
return ATMEL_HLCDC_RGB444_OUTPUT;
case MEDIA_BUS_FMT_RGB565_1X16:
return ATMEL_HLCDC_RGB565_OUTPUT;
case MEDIA_BUS_FMT_RGB666_1X18:
return ATMEL_HLCDC_RGB666_OUTPUT;
case MEDIA_BUS_FMT_RGB888_1X24:
return ATMEL_HLCDC_RGB888_OUTPUT;
default:
return -EINVAL;
}
for (j = 0; j < info->num_bus_formats; j++) {
switch (info->bus_formats[j]) {
case MEDIA_BUS_FMT_RGB444_1X12:
supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT;
break;
case MEDIA_BUS_FMT_RGB565_1X16:
supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT;
break;
case MEDIA_BUS_FMT_RGB666_1X18:
supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT;
break;
case MEDIA_BUS_FMT_RGB888_1X24:
supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT;
break;
default:
break;
}
}
return supported_fmts;
}
static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state)
{
unsigned int output_fmts;
struct atmel_hlcdc_crtc_state *hstate;
struct drm_connector_state *cstate;
struct drm_connector *connector;
struct atmel_hlcdc_crtc *crtc;
int i;
crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc);
output_fmts = crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK :
ATMEL_HLCDC_OUTPUT_MODE_MASK;
for_each_new_connector_in_state(state->state, connector, cstate, i) {
unsigned int supported_fmts = 0;
if (!cstate->crtc)
continue;
supported_fmts = atmel_hlcdc_connector_output_mode(cstate);
if (crtc->dc->desc->conflicting_output_formats)
output_fmts &= supported_fmts;
else
output_fmts |= supported_fmts;
}
if (!output_fmts)
return -EINVAL;
hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state);
hstate->output_mode = fls(output_fmts) - 1;
if (crtc->dc->desc->is_xlcdc) {
/* check if MIPI DPI bit needs to be set */
if (fls(output_fmts) > 3) {
hstate->output_mode -= 4;
hstate->dpi = 1;
} else {
hstate->dpi = 0;
}
}
return 0;
}
static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
struct drm_atomic_commit *state)
{
struct drm_crtc_state *s = drm_atomic_get_new_crtc_state(state, c);
int ret;
ret = atmel_hlcdc_crtc_select_output_mode(s);
if (ret)
return ret;
ret = atmel_hlcdc_plane_prepare_disc_area(s);
if (ret)
return ret;
return atmel_hlcdc_plane_prepare_ahb_routing(s);
}
static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c,
struct drm_atomic_commit *state)
{
drm_crtc_vblank_on(c);
}
static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *c,
struct drm_atomic_commit *state)
{
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
unsigned long flags;
spin_lock_irqsave(&c->dev->event_lock, flags);
if (c->state->event) {
c->state->event->pipe = drm_crtc_index(c);
WARN_ON(drm_crtc_vblank_get(c) != 0);
crtc->event = c->state->event;
c->state->event = NULL;
}
spin_unlock_irqrestore(&c->dev->event_lock, flags);
}
static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
.mode_valid = atmel_hlcdc_crtc_mode_valid,
.mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
.atomic_check = atmel_hlcdc_crtc_atomic_check,
.atomic_begin = atmel_hlcdc_crtc_atomic_begin,
.atomic_flush = atmel_hlcdc_crtc_atomic_flush,
.atomic_enable = atmel_hlcdc_crtc_atomic_enable,
.atomic_disable = atmel_hlcdc_crtc_atomic_disable,
};
static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
if (crtc->event) {
drm_crtc_send_vblank_event(&crtc->base, crtc->event);
drm_crtc_vblank_put(&crtc->base);
crtc->event = NULL;
}
spin_unlock_irqrestore(&dev->event_lock, flags);
}
void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
{
drm_crtc_handle_vblank(c);
atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
}
static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
{
struct atmel_hlcdc_crtc_state *state;
if (crtc->state) {
__drm_atomic_helper_crtc_destroy_state(crtc->state);
state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
kfree(state);
crtc->state = NULL;
}
state = kzalloc_obj(*state);
if (state)
__drm_atomic_helper_crtc_reset(crtc, &state->base);
}
static struct drm_crtc_state *
atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
{
struct atmel_hlcdc_crtc_state *state, *cur;
struct atmel_hlcdc_crtc *c = drm_crtc_to_atmel_hlcdc_crtc(crtc);
if (WARN_ON(!crtc->state))
return NULL;
state = kmalloc_obj(*state);
if (!state)
return NULL;
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
state->output_mode = cur->output_mode;
if (c->dc->desc->is_xlcdc)
state->dpi = cur->dpi;
return &state->base;
}
static void atmel_hlcdc_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *s)
{
struct atmel_hlcdc_crtc_state *state;
state = drm_crtc_state_to_atmel_hlcdc_crtc_state(s);
__drm_atomic_helper_crtc_destroy_state(s);
kfree(state);
}
static int atmel_hlcdc_crtc_enable_vblank(struct drm_crtc *c)
{
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
struct regmap *regmap = crtc->dc->hlcdc->regmap;
/* Enable SOF (Start Of Frame) interrupt for vblank counting */
regmap_write(regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
return 0;
}
static void atmel_hlcdc_crtc_disable_vblank(struct drm_crtc *c)
{
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
struct regmap *regmap = crtc->dc->hlcdc->regmap;
regmap_write(regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
}
static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
.page_flip = drm_atomic_helper_page_flip,
.set_config = drm_atomic_helper_set_config,
.reset = atmel_hlcdc_crtc_reset,
.atomic_duplicate_state = atmel_hlcdc_crtc_duplicate_state,
.atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,
.enable_vblank = atmel_hlcdc_crtc_enable_vblank,
.disable_vblank = atmel_hlcdc_crtc_disable_vblank,
};
int atmel_hlcdc_crtc_create(struct drm_device *dev)
{
struct atmel_hlcdc_plane *primary = NULL, *cursor = NULL;
struct atmel_hlcdc_dc *dc = dev->dev_private;
struct atmel_hlcdc_crtc *crtc;
int i;
for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
if (!dc->layers[i])
continue;
switch (dc->layers[i]->desc->type) {
case ATMEL_HLCDC_BASE_LAYER:
primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);
break;
case ATMEL_HLCDC_CURSOR_LAYER:
cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);
break;
default:
break;
}
}
crtc = drmm_crtc_alloc_with_planes(dev, struct atmel_hlcdc_crtc, base,
&primary->base, &cursor->base, &atmel_hlcdc_crtc_funcs,
NULL);
if (IS_ERR(crtc))
return PTR_ERR(crtc);
crtc->dc = dc;
crtc->id = drm_crtc_index(&crtc->base);
for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
struct atmel_hlcdc_plane *overlay;
if (dc->layers[i] &&
dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {
overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);
overlay->base.possible_crtcs = 1 << crtc->id;
}
}
drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE);
drm_crtc_enable_color_mgmt(&crtc->base, 0, false,
ATMEL_HLCDC_CLUT_SIZE);
dc->crtc = &crtc->base;
return 0;
}
linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+1037
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
+502
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@@ -0,0 +1,502 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 Traphandler
* Copyright (C) 2014 Free Electrons
* Copyright (C) 2014 Atmel
*
* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
*/
#ifndef DRM_ATMEL_HLCDC_H
#define DRM_ATMEL_HLCDC_H
#include <linux/regmap.h>
#include <drm/drm_plane.h>
/* LCD controller common registers */
#define ATMEL_HLCDC_LAYER_CHER 0x0
#define ATMEL_HLCDC_LAYER_CHDR 0x4
#define ATMEL_HLCDC_LAYER_CHSR 0x8
#define ATMEL_HLCDC_LAYER_EN BIT(0)
#define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
#define ATMEL_HLCDC_LAYER_A2Q BIT(2)
#define ATMEL_HLCDC_LAYER_RST BIT(8)
#define ATMEL_HLCDC_LAYER_IER 0xc
#define ATMEL_HLCDC_LAYER_IDR 0x10
#define ATMEL_HLCDC_LAYER_IMR 0x14
#define ATMEL_HLCDC_LAYER_ISR 0x18
#define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
#define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
#define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p)))
#define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c)
#define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20)
#define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24)
#define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28)
#define ATMEL_HLCDC_LAYER_DMA_CFG 0
#define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4)
#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4)
#define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8)
#define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12)
#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13)
#define ATMEL_HLCDC_LAYER_FORMAT_CFG 1
#define ATMEL_HLCDC_LAYER_RGB (0 << 0)
#define ATMEL_HLCDC_LAYER_CLUT (1 << 0)
#define ATMEL_HLCDC_LAYER_YUV (2 << 0)
#define ATMEL_HLCDC_RGB_MODE(m) \
(ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))
#define ATMEL_HLCDC_CLUT_MODE(m) \
(ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))
#define ATMEL_HLCDC_YUV_MODE(m) \
(ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))
#define ATMEL_HLCDC_YUV422ROT BIT(16)
#define ATMEL_HLCDC_YUV422SWP BIT(17)
#define ATMEL_HLCDC_DSCALEOPT BIT(20)
#define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0)
#define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1)
#define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2)
#define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3)
#define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0)
#define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1)
#define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2)
#define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3)
#define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4)
#define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9)
#define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10)
#define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12)
#define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13)
#define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0)
#define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1)
#define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2)
#define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3)
#define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4)
#define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5)
#define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6)
#define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7)
#define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8)
#define ATMEL_HLCDC_LAYER_POS(x, y) ((x) | ((y) << 16))
#define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
#define ATMEL_HLCDC_LAYER_CRKEY BIT(0)
#define ATMEL_HLCDC_LAYER_INV BIT(1)
#define ATMEL_HLCDC_LAYER_ITER2BL BIT(2)
#define ATMEL_HLCDC_LAYER_ITER BIT(3)
#define ATMEL_HLCDC_LAYER_REVALPHA BIT(4)
#define ATMEL_HLCDC_LAYER_GAEN BIT(5)
#define ATMEL_HLCDC_LAYER_LAEN BIT(6)
#define ATMEL_HLCDC_LAYER_OVR BIT(7)
#define ATMEL_HLCDC_LAYER_DMA BIT(8)
#define ATMEL_HLCDC_LAYER_REP BIT(9)
#define ATMEL_HLCDC_LAYER_DSTKEY BIT(10)
#define ATMEL_HLCDC_LAYER_DISCEN BIT(11)
#define ATMEL_HLCDC_LAYER_GA_SHIFT 16
#define ATMEL_HLCDC_LAYER_GA_MASK \
GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
#define ATMEL_HLCDC_LAYER_GA(x) \
((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
#define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16))
#define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
#define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) | ((y) << 16))
#define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31)
#define ATMEL_HLCDC_LAYER_MAX_PLANES 3
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0)
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2)
#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3)
#define ATMEL_HLCDC_CLUT_SIZE 256
#define ATMEL_HLCDC_MAX_LAYERS 6
/* XLCDC controller specific registers */
#define ATMEL_XLCDC_LAYER_ENR 0x10
#define ATMEL_XLCDC_LAYER_EN BIT(0)
#define ATMEL_XLCDC_LAYER_IER 0x0
#define ATMEL_XLCDC_LAYER_IDR 0x4
#define ATMEL_XLCDC_LAYER_ISR 0xc
#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p)))
#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18)
#define ATMEL_XLCDC_LAYER_DMA_CFG 0
#define ATMEL_XLCDC_LAYER_DMA BIT(0)
#define ATMEL_XLCDC_LAYER_REP BIT(1)
#define ATMEL_XLCDC_LAYER_DISCEN BIT(4)
#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6)
#define ATMEL_XLCDC_LAYER_SFACTA_ONE BIT(9)
#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11)
#define ATMEL_XLCDC_LAYER_DFACTA_ONE BIT(14)
#define ATMEL_XLCDC_LAYER_A0_SHIFT 16
#define ATMEL_XLCDC_LAYER_A0(x) \
((x) << ATMEL_XLCDC_LAYER_A0_SHIFT)
#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0)
#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1)
#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4)
#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5)
#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE BIT(0)
#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4)
#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE BIT(16)
#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20)
#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE BIT(0)
#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4)
#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE BIT(16)
#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20)
/**
* Atmel HLCDC Layer registers layout structure
*
* Each HLCDC layer has its own register organization and a given register
* can be placed differently on 2 different layers depending on its
* capabilities.
* This structure stores common registers layout for a given layer and is
* used by HLCDC layer code to choose the appropriate register to write to
* or to read from.
*
* For all fields, a value of zero means "unsupported".
*
* See Atmel's datasheet for a detailled description of these registers.
*
* @xstride: xstride registers
* @pstride: pstride registers
* @pos: position register
* @size: displayed size register
* @memsize: memory size register
* @default_color: default color register
* @chroma_key: chroma key register
* @chroma_key_mask: chroma key mask register
* @general_config: general layer config register
* @sacler_config: scaler factors register
* @phicoeffs: X/Y PHI coefficient registers
* @disc_pos: discard area position register
* @disc_size: discard area size register
* @csc: color space conversion register
* @vxs_config: vertical scalar filter taps control register
* @hxs_config: horizontal scalar filter taps control register
*/
struct atmel_hlcdc_layer_cfg_layout {
int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
int pos;
int size;
int memsize;
int default_color;
int chroma_key;
int chroma_key_mask;
int general_config;
int scaler_config;
struct {
int x;
int y;
} phicoeffs;
int disc_pos;
int disc_size;
int csc;
int vxs_config;
int hxs_config;
};
/**
* Atmel HLCDC DMA descriptor structure
*
* This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
*
* The structure fields must remain in this specific order, because they're
* used by the HLCDC DMA engine, which expect them in this order.
* HLCDC DMA descriptors must be aligned on 64 bits.
*
* @addr: buffer DMA address
* @ctrl: DMA transfer options
* @next: next DMA descriptor to fetch
* @self: descriptor DMA address
*/
struct atmel_hlcdc_dma_channel_dscr {
dma_addr_t addr;
u32 ctrl;
dma_addr_t next;
dma_addr_t self;
} __aligned(sizeof(u64));
/**
* Atmel HLCDC layer types
*/
enum atmel_hlcdc_layer_type {
ATMEL_HLCDC_NO_LAYER,
ATMEL_HLCDC_BASE_LAYER,
ATMEL_HLCDC_OVERLAY_LAYER,
ATMEL_HLCDC_CURSOR_LAYER,
ATMEL_HLCDC_PP_LAYER,
};
/**
* Atmel HLCDC Supported formats structure
*
* This structure list all the formats supported by a given layer.
*
* @nformats: number of supported formats
* @formats: supported formats
*/
struct atmel_hlcdc_formats {
int nformats;
u32 *formats;
};
/**
* Atmel HLCDC Layer description structure
*
* This structure describes the capabilities provided by a given layer.
*
* @name: layer name
* @type: layer type
* @id: layer id
* @regs_offset: offset of the layer registers from the HLCDC registers base
* @cfgs_offset: CFGX registers offset from the layer registers base
* @formats: supported formats
* @layout: config registers layout
* @max_width: maximum width supported by this layer (0 means unlimited)
* @max_height: maximum height supported by this layer (0 means unlimited)
*/
struct atmel_hlcdc_layer_desc {
const char *name;
enum atmel_hlcdc_layer_type type;
int id;
int regs_offset;
int cfgs_offset;
int clut_offset;
struct atmel_hlcdc_formats *formats;
struct atmel_hlcdc_layer_cfg_layout layout;
int max_width;
int max_height;
};
/**
* Atmel HLCDC Layer.
*
* A layer can be a DRM plane of a post processing layer used to render
* HLCDC composition into memory.
*
* @desc: layer description
* @regmap: pointer to the HLCDC regmap
*/
struct atmel_hlcdc_layer {
const struct atmel_hlcdc_layer_desc *desc;
struct regmap *regmap;
};
/**
* Atmel HLCDC Plane.
*
* @base: base DRM plane structure
* @layer: HLCDC layer structure
* @properties: pointer to the property definitions structure
*/
struct atmel_hlcdc_plane {
struct drm_plane base;
struct atmel_hlcdc_layer layer;
};
static inline struct atmel_hlcdc_plane *
drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
{
return container_of(p, struct atmel_hlcdc_plane, base);
}
static inline struct atmel_hlcdc_plane *
atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
{
return container_of(layer, struct atmel_hlcdc_plane, layer);
}
/**
* struct atmel_hlcdc_dc - Atmel HLCDC Display Controller.
* @desc: HLCDC Display Controller description
* @dscrpool: DMA coherent pool used to allocate DMA descriptors
* @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
* @crtc: CRTC provided by the display controller
* @layers: active HLCDC layers
* @suspend: used to store the HLCDC state when entering suspend
* @suspend.imr: used to read/write LCDC Interrupt Mask Register
* @suspend.state: Atomic commit structure
*/
struct atmel_hlcdc_dc {
const struct atmel_hlcdc_dc_desc *desc;
struct dma_pool *dscrpool;
struct atmel_hlcdc *hlcdc;
struct drm_crtc *crtc;
struct drm_device dev;
struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
struct {
u32 imr;
struct drm_atomic_commit *state;
} suspend;
};
struct atmel_hlcdc_plane_state;
/**
* struct atmel_lcdc_dc_ops - describes atmel_lcdc ops group
* to differentiate HLCDC and XLCDC IP code support
* @plane_setup_scaler: update the vertical and horizontal scaling factors
* @update_lcdc_buffers: update the each LCDC layers DMA registers
* @lcdc_atomic_disable: disable LCDC interrupts and layers
* @lcdc_update_general_settings: update each LCDC layers general
* configuration register
* @lcdc_atomic_update: enable the LCDC layers and interrupts
* @lcdc_csc_init: update the color space conversion co-efficient of
* High-end overlay register
* @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC layer
*/
struct atmel_lcdc_dc_ops {
void (*plane_setup_scaler)(struct atmel_hlcdc_plane *plane,
struct atmel_hlcdc_plane_state *state);
void (*lcdc_update_buffers)(struct atmel_hlcdc_plane *plane,
struct atmel_hlcdc_plane_state *state,
u32 sr, int i);
void (*lcdc_atomic_disable)(struct atmel_hlcdc_plane *plane,
struct atmel_hlcdc_dc *dc);
void (*lcdc_update_general_settings)(struct atmel_hlcdc_plane *plane,
struct atmel_hlcdc_plane_state *state);
void (*lcdc_atomic_update)(struct atmel_hlcdc_plane *plane,
struct atmel_hlcdc_dc *dc);
void (*lcdc_csc_init)(struct atmel_hlcdc_plane *plane,
const struct atmel_hlcdc_layer_desc *desc);
void (*lcdc_irq_dbg)(struct atmel_hlcdc_plane *plane,
const struct atmel_hlcdc_layer_desc *desc);
};
extern const struct atmel_lcdc_dc_ops atmel_hlcdc_ops;
extern const struct atmel_lcdc_dc_ops atmel_xlcdc_ops;
/**
* Atmel HLCDC Display Controller description structure.
*
* This structure describes the HLCDC IP capabilities and depends on the
* HLCDC IP version (or Atmel SoC family).
*
* @min_width: minimum width supported by the Display Controller
* @min_height: minimum height supported by the Display Controller
* @max_width: maximum width supported by the Display Controller
* @max_height: maximum height supported by the Display Controller
* @max_spw: maximum vertical/horizontal pulse width
* @max_vpw: maximum vertical back/front porch width
* @max_hpw: maximum horizontal back/front porch width
* @conflicting_output_formats: true if RGBXXX output formats conflict with
* each other.
* @fixed_clksrc: true if clock source is fixed
* @is_xlcdc: true if XLCDC IP is supported
* @layers: a layer description table describing available layers
* @nlayers: layer description table size
* @ops: atmel lcdc dc ops
*/
struct atmel_hlcdc_dc_desc {
int min_width;
int min_height;
int max_width;
int max_height;
int max_spw;
int max_vpw;
int max_hpw;
bool conflicting_output_formats;
bool fixed_clksrc;
bool is_xlcdc;
const struct atmel_hlcdc_layer_desc *layers;
int nlayers;
const struct atmel_lcdc_dc_ops *ops;
};
extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
unsigned int reg, u32 val)
{
regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
}
static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
unsigned int reg)
{
u32 val;
regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);
return val;
}
static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
unsigned int cfgid, u32 val)
{
atmel_hlcdc_layer_write_reg(layer,
layer->desc->cfgs_offset +
(cfgid * sizeof(u32)), val);
}
static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
unsigned int cfgid)
{
return atmel_hlcdc_layer_read_reg(layer,
layer->desc->cfgs_offset +
(cfgid * sizeof(u32)));
}
static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer,
unsigned int c, u32 val)
{
regmap_write(layer->regmap,
layer->desc->clut_offset + c * sizeof(u32),
val);
}
static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
const struct atmel_hlcdc_layer_desc *desc,
struct regmap *regmap)
{
layer->desc = desc;
layer->regmap = regmap;
}
enum drm_mode_status
atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
const struct drm_display_mode *mode);
int atmel_hlcdc_create_planes(struct drm_device *dev);
void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
int atmel_hlcdc_crtc_create(struct drm_device *dev);
int atmel_hlcdc_create_outputs(struct drm_device *dev);
int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder);
#endif /* DRM_ATMEL_HLCDC_H */
linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
+129
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@@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Traphandler
* Copyright (C) 2014 Free Electrons
* Copyright (C) 2014 Atmel
*
* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
*/
#include <linux/media-bus-format.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <drm/drm_bridge.h>
#include <drm/drm_encoder.h>
#include <drm/drm_of.h>
#include <drm/drm_print.h>
#include <drm/drm_simple_kms_helper.h>
#include "atmel_hlcdc_dc.h"
struct atmel_hlcdc_rgb_output {
struct drm_encoder encoder;
int bus_fmt;
};
static struct atmel_hlcdc_rgb_output *
atmel_hlcdc_encoder_to_rgb_output(struct drm_encoder *encoder)
{
return container_of(encoder, struct atmel_hlcdc_rgb_output, encoder);
}
int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder)
{
struct atmel_hlcdc_rgb_output *output;
output = atmel_hlcdc_encoder_to_rgb_output(encoder);
return output->bus_fmt;
}
static int atmel_hlcdc_of_bus_fmt(const struct device_node *ep)
{
u32 bus_width;
int ret;
ret = of_property_read_u32(ep, "bus-width", &bus_width);
if (ret == -EINVAL)
return 0;
if (ret)
return ret;
switch (bus_width) {
case 12:
return MEDIA_BUS_FMT_RGB444_1X12;
case 16:
return MEDIA_BUS_FMT_RGB565_1X16;
case 18:
return MEDIA_BUS_FMT_RGB666_1X18;
case 24:
return MEDIA_BUS_FMT_RGB888_1X24;
default:
return -EINVAL;
}
}
static int atmel_hlcdc_attach_endpoint(struct drm_device *dev, int endpoint)
{
struct atmel_hlcdc_rgb_output *output;
struct device_node *ep;
struct drm_bridge *bridge;
struct atmel_hlcdc_dc *dc = dev->dev_private;
struct drm_crtc *crtc = dc->crtc;
int ret = 0;
bridge = devm_drm_of_get_bridge(dev->dev, dev->dev->of_node, 0, endpoint);
if (IS_ERR(bridge))
return PTR_ERR(bridge);
output = drmm_simple_encoder_alloc(dev, struct atmel_hlcdc_rgb_output,
encoder, DRM_MODE_ENCODER_NONE);
if (IS_ERR(output))
return PTR_ERR(output);
ep = of_graph_get_endpoint_by_regs(dev->dev->of_node, 0, endpoint);
if (!ep)
return -ENODEV;
output->bus_fmt = atmel_hlcdc_of_bus_fmt(ep);
of_node_put(ep);
if (output->bus_fmt < 0) {
drm_err(dev, "endpoint %d: invalid bus width\n", endpoint);
return -EINVAL;
}
output->encoder.possible_crtcs = drm_crtc_mask(crtc);
if (bridge)
ret = drm_bridge_attach(&output->encoder, bridge, NULL, 0);
return ret;
}
int atmel_hlcdc_create_outputs(struct drm_device *dev)
{
int endpoint, ret = 0;
int attached = 0;
/*
* Always scan the first few endpoints even if we get -ENODEV,
* but keep going after that as long as we keep getting hits.
*/
for (endpoint = 0; !ret || endpoint < 4; endpoint++) {
ret = atmel_hlcdc_attach_endpoint(dev, endpoint);
if (ret == -ENODEV)
continue;
if (ret)
break;
attached++;
}
/* At least one device was successfully attached.*/
if (ret == -ENODEV && attached)
return 0;
return ret;
}
linux-7.2.3/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
+1281
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