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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/nouveau/include/dispnv04/i2c/ch7006.h
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/*
* Copyright (C) 2009 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __NOUVEAU_I2C_CH7006_H__
#define __NOUVEAU_I2C_CH7006_H__
/**
* struct ch7006_encoder_params
*
* Describes how the ch7006 is wired up with the GPU. It should be
* used as the @params parameter of its @set_config method.
*
* See "http://www.chrontel.com/pdf/7006.pdf" for their precise
* meaning.
*/
struct ch7006_encoder_params {
/* private: FIXME: document the members */
enum {
CH7006_FORMAT_RGB16 = 0,
CH7006_FORMAT_YCrCb24m16,
CH7006_FORMAT_RGB24m16,
CH7006_FORMAT_RGB15,
CH7006_FORMAT_RGB24m12C,
CH7006_FORMAT_RGB24m12I,
CH7006_FORMAT_RGB24m8,
CH7006_FORMAT_RGB16m8,
CH7006_FORMAT_RGB15m8,
CH7006_FORMAT_YCrCb24m8,
} input_format;
enum {
CH7006_CLOCK_SLAVE = 0,
CH7006_CLOCK_MASTER,
} clock_mode;
enum {
CH7006_CLOCK_EDGE_NEG = 0,
CH7006_CLOCK_EDGE_POS,
} clock_edge;
int xcm, pcm;
enum {
CH7006_SYNC_SLAVE = 0,
CH7006_SYNC_MASTER,
} sync_direction;
enum {
CH7006_SYNC_SEPARATED = 0,
CH7006_SYNC_EMBEDDED,
} sync_encoding;
enum {
CH7006_POUT_1_8V = 0,
CH7006_POUT_3_3V,
} pout_level;
enum {
CH7006_ACTIVE_HSYNC = 0,
CH7006_ACTIVE_DSTART,
} active_detect;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/dispnv04/i2c/encoder_i2c.h
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/*
* Copyright (C) 2009 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __NOUVEAU_ENCODER_I2C_H__
#define __NOUVEAU_ENCODER_I2C_H__
#include <linux/i2c.h>
#include <drm/drm_crtc.h>
#include <drm/drm_encoder.h>
/**
* struct nouveau_i2c_encoder_funcs - Entry points exposed by a I2C encoder driver
*
* Most of its members are analogous to the function pointers in
* &drm_encoder_helper_funcs and they can optionally be used to
* initialize the latter. Connector-like methods (e.g. @get_modes and
* @set_property) will typically be wrapped around and only be called
* if the encoder is the currently selected one for the connector.
*/
struct nouveau_i2c_encoder_funcs {
/**
* @set_config: Initialize any encoder-specific modesetting parameters.
* The meaning of the @params parameter is implementation dependent. It
* will usually be a structure with DVO port data format settings or
* timings. It's not required for the new parameters to take effect
* until the next mode is set.
*/
void (*set_config)(struct drm_encoder *encoder,
void *params);
/**
* @destroy: Analogous to &drm_encoder_funcs @destroy callback.
*/
void (*destroy)(struct drm_encoder *encoder);
/**
* @dpms: Analogous to &drm_encoder_helper_funcs @dpms callback.
*/
void (*dpms)(struct drm_encoder *encoder, int mode);
/**
* @save: Save state. Wrapped by nouveau_i2c_encoder_save().
*/
void (*save)(struct drm_encoder *encoder);
/**
* @restore: Restore state. Wrapped by nouveau_i2c_encoder_restore().
*/
void (*restore)(struct drm_encoder *encoder);
/**
* @mode_fixup: Analogous to &drm_encoder_helper_funcs @mode_fixup
* callback. Wrapped by nouveau_i2c_encoder_mode_fixup().
*/
bool (*mode_fixup)(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
/**
* @mode_valid: Analogous to &drm_encoder_helper_funcs @mode_valid.
*/
int (*mode_valid)(struct drm_encoder *encoder,
const struct drm_display_mode *mode);
/**
* @mode_set: Analogous to &drm_encoder_helper_funcs @mode_set
* callback.
*/
void (*mode_set)(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
/**
* @detect: Analogous to &drm_encoder_helper_funcs @detect
* callback. Wrapped by nouveau_i2c_encoder_detect().
*/
enum drm_connector_status (*detect)(struct drm_encoder *encoder,
struct drm_connector *connector);
/**
* @get_modes: Get modes.
*/
int (*get_modes)(struct drm_encoder *encoder,
struct drm_connector *connector);
/**
* @create_resources: Create resources.
*/
int (*create_resources)(struct drm_encoder *encoder,
struct drm_connector *connector);
/**
* @set_property: Set property.
*/
int (*set_property)(struct drm_encoder *encoder,
struct drm_connector *connector,
struct drm_property *property,
uint64_t val);
};
/**
* struct nouveau_i2c_encoder - I2C encoder struct
*
* A &nouveau_i2c_encoder has two sets of callbacks, @encoder_i2c_funcs and the
* ones in @base. The former are never actually called by the common
* CRTC code, it's just a convenience for splitting the encoder
* functions in an upper, GPU-specific layer and a (hopefully)
* GPU-agnostic lower layer: It's the GPU driver responsibility to
* call the nouveau_i2c_encoder methods when appropriate.
*
* nouveau_i2c_encoder_init() provides a way to get an implementation of
* this.
*/
struct nouveau_i2c_encoder {
/**
* @base: DRM encoder object.
*/
struct drm_encoder base;
/**
* @encoder_i2c_funcs: I2C encoder callbacks.
*/
const struct nouveau_i2c_encoder_funcs *encoder_i2c_funcs;
/**
* @encoder_i2c_priv: I2C encoder private data.
*/
void *encoder_i2c_priv;
/**
* @i2c_client: corresponding I2C client structure
*/
struct i2c_client *i2c_client;
};
#define to_encoder_i2c(x) container_of((x), struct nouveau_i2c_encoder, base)
int nouveau_i2c_encoder_init(struct drm_device *dev,
struct nouveau_i2c_encoder *encoder,
struct i2c_adapter *adap,
const struct i2c_board_info *info);
static inline const struct nouveau_i2c_encoder_funcs *
get_encoder_i2c_funcs(struct drm_encoder *enc)
{
return to_encoder_i2c(enc)->encoder_i2c_funcs;
}
/**
* struct nouveau_i2c_encoder_driver
*
* Describes a device driver for an encoder connected to the GPU through an I2C
* bus.
*/
struct nouveau_i2c_encoder_driver {
/**
* @i2c_driver: I2C device driver description.
*/
struct i2c_driver i2c_driver;
/**
* @encoder_init: Callback to allocate any per-encoder data structures
* and to initialize the @encoder_i2c_funcs and (optionally) @encoder_i2c_priv
* members of @encoder.
*/
int (*encoder_init)(struct i2c_client *client,
struct drm_device *dev,
struct nouveau_i2c_encoder *encoder);
};
#define to_nouveau_i2c_encoder_driver(x) container_of((x), \
struct nouveau_i2c_encoder_driver, \
i2c_driver)
/**
* nouveau_i2c_encoder_get_client - Get the I2C client corresponding to an encoder
* @encoder: The encoder
*/
static inline struct i2c_client *nouveau_i2c_encoder_get_client(struct drm_encoder *encoder)
{
return to_encoder_i2c(encoder)->i2c_client;
}
/**
* nouveau_i2c_encoder_destroy - Unregister the I2C device backing an encoder
* @drm_encoder: Encoder to be unregistered.
*
* This should be called from the @destroy method of an I2C slave
* encoder driver once I2C access is no longer needed.
*/
static __always_inline void nouveau_i2c_encoder_destroy(struct drm_encoder *drm_encoder)
{
struct nouveau_i2c_encoder *encoder = to_encoder_i2c(drm_encoder);
struct i2c_client *client = nouveau_i2c_encoder_get_client(drm_encoder);
struct module *module = client->dev.driver->owner;
i2c_unregister_device(client);
encoder->i2c_client = NULL;
module_put(module);
}
/*
* Wrapper fxns which can be plugged in to drm_encoder_helper_funcs:
*/
bool nouveau_i2c_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
enum drm_connector_status nouveau_i2c_encoder_detect(struct drm_encoder *encoder,
struct drm_connector *connector);
void nouveau_i2c_encoder_save(struct drm_encoder *encoder);
void nouveau_i2c_encoder_restore(struct drm_encoder *encoder);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/dispnv04/i2c/sil164.h
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __NOUVEAU_I2C_SIL164_H__
#define __NOUVEAU_I2C_SIL164_H__
/**
* struct sil164_encoder_params
*
* Describes how the sil164 is connected to the GPU. It should be used
* as the @params parameter of its @set_config method.
*
* See "http://www.siliconimage.com/docs/SiI-DS-0021-E-164.pdf".
*/
struct sil164_encoder_params {
/* private: FIXME: document the members */
enum {
SIL164_INPUT_EDGE_FALLING = 0,
SIL164_INPUT_EDGE_RISING
} input_edge;
enum {
SIL164_INPUT_WIDTH_12BIT = 0,
SIL164_INPUT_WIDTH_24BIT
} input_width;
enum {
SIL164_INPUT_SINGLE_EDGE = 0,
SIL164_INPUT_DUAL_EDGE
} input_dual;
enum {
SIL164_PLL_FILTER_ON = 0,
SIL164_PLL_FILTER_OFF,
} pll_filter;
int input_skew; /** < Allowed range [-4, 3], use 0 for no de-skew. */
int duallink_skew; /** < Allowed range [-4, 3]. */
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/acr.h
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#ifndef __NVFW_ACR_H__
#define __NVFW_ACR_H__
struct wpr_header {
#define WPR_HEADER_V0_FALCON_ID_INVALID 0xffffffff
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
u32 lazy_bootstrap;
#define WPR_HEADER_V0_STATUS_NONE 0
#define WPR_HEADER_V0_STATUS_COPY 1
#define WPR_HEADER_V0_STATUS_VALIDATION_CODE_FAILED 2
#define WPR_HEADER_V0_STATUS_VALIDATION_DATA_FAILED 3
#define WPR_HEADER_V0_STATUS_VALIDATION_DONE 4
#define WPR_HEADER_V0_STATUS_VALIDATION_SKIPPED 5
#define WPR_HEADER_V0_STATUS_BOOTSTRAP_READY 6
u32 status;
};
void wpr_header_dump(struct nvkm_subdev *, const struct wpr_header *);
struct wpr_header_v1 {
#define WPR_HEADER_V1_FALCON_ID_INVALID 0xffffffff
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
u32 lazy_bootstrap;
u32 bin_version;
#define WPR_HEADER_V1_STATUS_NONE 0
#define WPR_HEADER_V1_STATUS_COPY 1
#define WPR_HEADER_V1_STATUS_VALIDATION_CODE_FAILED 2
#define WPR_HEADER_V1_STATUS_VALIDATION_DATA_FAILED 3
#define WPR_HEADER_V1_STATUS_VALIDATION_DONE 4
#define WPR_HEADER_V1_STATUS_VALIDATION_SKIPPED 5
#define WPR_HEADER_V1_STATUS_BOOTSTRAP_READY 6
#define WPR_HEADER_V1_STATUS_REVOCATION_CHECK_FAILED 7
u32 status;
};
void wpr_header_v1_dump(struct nvkm_subdev *, const struct wpr_header_v1 *);
struct wpr_generic_header {
#define WPR_GENERIC_HEADER_ID_LSF_UCODE_DESC 1
#define WPR_GENERIC_HEADER_ID_LSF_WPR_HEADER 2
#define WPR_GENERIC_HEADER_ID_LSF_SHARED_SUB_WPR 3
#define WPR_GENERIC_HEADER_ID_LSF_LSB_HEADER 4
u16 identifier;
u16 version;
u32 size;
};
struct wpr_header_v2 {
struct wpr_generic_header hdr;
struct wpr_header_v1 wpr;
};
void wpr_header_v2_dump(struct nvkm_subdev *, const struct wpr_header_v2 *);
struct lsf_signature {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
u32 b_dbg_present;
u32 falcon_id;
};
struct lsf_signature_v1 {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
u32 b_dbg_present;
u32 falcon_id;
u32 supports_versioning;
u32 version;
u32 depmap_count;
u8 depmap[11/*LSF_LSB_DEPMAP_SIZE*/ * 2 * 4];
u8 kdf[16];
};
struct lsb_header_tail {
u32 ucode_off;
u32 ucode_size;
u32 data_size;
u32 bl_code_size;
u32 bl_imem_off;
u32 bl_data_off;
u32 bl_data_size;
u32 app_code_off;
u32 app_code_size;
u32 app_data_off;
u32 app_data_size;
u32 flags;
};
struct lsb_header {
struct lsf_signature signature;
struct lsb_header_tail tail;
};
void lsb_header_dump(struct nvkm_subdev *, struct lsb_header *);
struct lsb_header_v1 {
struct lsf_signature_v1 signature;
struct lsb_header_tail tail;
};
void lsb_header_v1_dump(struct nvkm_subdev *, struct lsb_header_v1 *);
struct lsb_header_v2 {
struct wpr_generic_header hdr;
struct lsf_signature_v2 {
struct wpr_generic_header hdr;
u32 falcon_id;
u8 prd_present;
u8 dbg_present;
u16 reserved;
u32 sig_size;
u8 prod_sig[2][384 + 128];
u8 debug_sig[2][384 + 128];
u16 sig_algo_ver;
u16 sig_algo;
u16 hash_algo_ver;
u16 hash_algo;
u32 sig_algo_padding_type;
u8 depmap[11 * 2 * 4];
u32 depmap_count;
u8 supports_versioning;
u8 pad[3];
u32 ls_ucode_version;
u32 ls_ucode_id;
u32 ucode_ls_encrypted;
u32 ls_eng_algo_type;
u32 ls_eng_algo_ver;
u8 ls_enc_iv[16];
u8 rsvd[36];
} signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
u32 bl_code_size;
u32 bl_imem_off;
u32 bl_data_off;
u32 bl_data_size;
u32 rsvd0;
u32 app_code_off;
u32 app_code_size;
u32 app_data_off;
u32 app_data_size;
u32 app_imem_offset;
u32 app_dmem_offset;
u32 flags;
u32 monitor_code_offset;
u32 monitor_data_offset;
u32 manifest_offset;
struct hs_fmc_params {
u8 hs_fmc;
u8 padding[3];
u16 pkc_algo;
u16 pkc_algo_version;
u32 engid_mask;
u32 ucode_id;
u32 fuse_ver;
u8 pkc_signature[384 + 128];
u8 pkc_key[2048];
u8 rsvd[4];
} hs_fmc_params;
struct hs_ovl_sig_blob_params {
u8 hs_ovl_sig_blob_present;
u32 hs_ovl_sig_blob_offset;
u32 hs_ovl_sig_blob_size;
} hs_ovl_sig_blob_params;
u8 rsvd[20];
};
void lsb_header_v2_dump(struct nvkm_subdev *, struct lsb_header_v2 *);
struct flcn_acr_desc {
union {
u8 reserved_dmem[0x200];
u32 signatures[4];
} ucode_reserved_space;
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct {
u32 no_regions;
struct {
u32 start_addr;
u32 end_addr;
u32 region_id;
u32 read_mask;
u32 write_mask;
u32 client_mask;
} region_props[2];
} regions;
u32 ucode_blob_size;
u64 ucode_blob_base __aligned(8);
struct {
u32 vpr_enabled;
u32 vpr_start;
u32 vpr_end;
u32 hdcp_policies;
} vpr_desc;
};
void flcn_acr_desc_dump(struct nvkm_subdev *, struct flcn_acr_desc *);
struct flcn_acr_desc_v1 {
u8 reserved_dmem[0x200];
u32 signatures[4];
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_memory_range;
struct {
u32 no_regions;
struct {
u32 start_addr;
u32 end_addr;
u32 region_id;
u32 read_mask;
u32 write_mask;
u32 client_mask;
u32 shadow_mem_start_addr;
} region_props[2];
} regions;
u32 ucode_blob_size;
u64 ucode_blob_base __aligned(8);
struct {
u32 vpr_enabled;
u32 vpr_start;
u32 vpr_end;
u32 hdcp_policies;
} vpr_desc;
};
void flcn_acr_desc_v1_dump(struct nvkm_subdev *, struct flcn_acr_desc_v1 *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/flcn.h
+97
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/* SPDX-License-Identifier: MIT */
#ifndef __NVFW_FLCN_H__
#define __NVFW_FLCN_H__
#include <core/os.h>
struct nvkm_subdev;
struct loader_config {
u32 dma_idx;
u32 code_dma_base;
u32 code_size_total;
u32 code_size_to_load;
u32 code_entry_point;
u32 data_dma_base;
u32 data_size;
u32 overlay_dma_base;
u32 argc;
u32 argv;
u32 code_dma_base1;
u32 data_dma_base1;
u32 overlay_dma_base1;
};
void
loader_config_dump(struct nvkm_subdev *, const struct loader_config *);
struct loader_config_v1 {
u32 reserved;
u32 dma_idx;
u64 code_dma_base;
u32 code_size_total;
u32 code_size_to_load;
u32 code_entry_point;
u64 data_dma_base;
u32 data_size;
u64 overlay_dma_base;
u32 argc;
u32 argv;
} __packed;
void
loader_config_v1_dump(struct nvkm_subdev *, const struct loader_config_v1 *);
struct flcn_bl_dmem_desc {
u32 reserved[4];
u32 signature[4];
u32 ctx_dma;
u32 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
u32 data_dma_base;
u32 data_size;
u32 code_dma_base1;
u32 data_dma_base1;
};
void
flcn_bl_dmem_desc_dump(struct nvkm_subdev *, const struct flcn_bl_dmem_desc *);
struct flcn_bl_dmem_desc_v1 {
u32 reserved[4];
u32 signature[4];
u32 ctx_dma;
u64 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
u64 data_dma_base;
u32 data_size;
} __packed;
void flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *,
const struct flcn_bl_dmem_desc_v1 *);
struct flcn_bl_dmem_desc_v2 {
u32 reserved[4];
u32 signature[4];
u32 ctx_dma;
u64 code_dma_base;
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 sec_code_off;
u32 sec_code_size;
u32 code_entry_point;
u64 data_dma_base;
u32 data_size;
u32 argc;
u32 argv;
} __packed;
void flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *,
const struct flcn_bl_dmem_desc_v2 *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/fw.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVFW_FW_H__
#define __NVFW_FW_H__
#include <core/os.h>
struct nvkm_subdev;
struct nvfw_bin_hdr {
u32 bin_magic;
u32 bin_ver;
u32 bin_size;
u32 header_offset;
u32 data_offset;
u32 data_size;
};
const struct nvfw_bin_hdr *nvfw_bin_hdr(struct nvkm_subdev *, const void *);
struct nvfw_bl_desc {
u32 start_tag;
u32 dmem_load_off;
u32 code_off;
u32 code_size;
u32 data_off;
u32 data_size;
};
const struct nvfw_bl_desc *nvfw_bl_desc(struct nvkm_subdev *, const void *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/hs.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVFW_HS_H__
#define __NVFW_HS_H__
#include <core/os.h>
struct nvkm_subdev;
struct nvfw_hs_header {
u32 sig_dbg_offset;
u32 sig_dbg_size;
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 hdr_offset;
u32 hdr_size;
};
const struct nvfw_hs_header *nvfw_hs_header(struct nvkm_subdev *, const void *);
struct nvfw_hs_header_v2 {
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 meta_data_offset;
u32 meta_data_size;
u32 num_sig;
u32 header_offset;
u32 header_size;
};
const struct nvfw_hs_header_v2 *nvfw_hs_header_v2(struct nvkm_subdev *, const void *);
struct nvfw_hs_load_header {
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 data_dma_base;
u32 data_size;
u32 num_apps;
u32 apps[];
};
const struct nvfw_hs_load_header *
nvfw_hs_load_header(struct nvkm_subdev *, const void *);
struct nvfw_hs_load_header_v2 {
u32 os_code_offset;
u32 os_code_size;
u32 os_data_offset;
u32 os_data_size;
u32 num_apps;
struct {
u32 offset;
u32 size;
u32 data_offset;
u32 data_size;
} app[] __counted_by(num_apps);
};
const struct nvfw_hs_load_header_v2 *nvfw_hs_load_header_v2(struct nvkm_subdev *, const void *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/ls.h
+104
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@@ -0,0 +1,104 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVFW_LS_H__
#define __NVFW_LS_H__
#include <core/os.h>
struct nvkm_subdev;
struct nvfw_ls_desc_head {
u32 descriptor_size;
u32 image_size;
u32 tools_version;
u32 app_version;
char date[64];
u32 bootloader_start_offset;
u32 bootloader_size;
u32 bootloader_imem_offset;
u32 bootloader_entry_point;
u32 app_start_offset;
u32 app_size;
u32 app_imem_offset;
u32 app_imem_entry;
u32 app_dmem_offset;
u32 app_resident_code_offset;
u32 app_resident_code_size;
u32 app_resident_data_offset;
u32 app_resident_data_size;
};
struct nvfw_ls_desc {
struct nvfw_ls_desc_head head;
u32 nb_overlays;
struct {
u32 start;
u32 size;
} load_ovl[64];
u32 compressed;
};
const struct nvfw_ls_desc *nvfw_ls_desc(struct nvkm_subdev *, const void *);
struct nvfw_ls_desc_v1 {
struct nvfw_ls_desc_head head;
u32 nb_imem_overlays;
u32 nb_dmem_overlays;
struct {
u32 start;
u32 size;
} load_ovl[64];
u32 compressed;
};
const struct nvfw_ls_desc_v1 *
nvfw_ls_desc_v1(struct nvkm_subdev *, const void *);
struct nvfw_ls_desc_v2 {
u32 descriptor_size;
u32 image_size;
u32 tools_version;
u32 app_version;
char date[64];
u32 secure_bootloader;
u32 bootloader_start_offset;
u32 bootloader_size;
u32 bootloader_imem_offset;
u32 bootloader_entry_point;
u32 app_start_offset;
u32 app_size;
u32 app_imem_offset;
u32 app_imem_entry;
u32 app_dmem_offset;
u32 app_resident_code_offset;
u32 app_resident_code_size;
u32 app_resident_data_offset;
u32 app_resident_data_size;
u32 nb_imem_overlays;
u32 nb_dmem_overlays;
struct {
u32 start;
u32 size;
} load_ovl[64];
};
const struct nvfw_ls_desc_v2 *nvfw_ls_desc_v2(struct nvkm_subdev *, const void *);
struct nvfw_ls_hsbl_bin_hdr {
u32 bin_magic;
u32 bin_ver;
u32 bin_size;
u32 header_offset;
};
const struct nvfw_ls_hsbl_bin_hdr *nvfw_ls_hsbl_bin_hdr(struct nvkm_subdev *, const void *);
struct nvfw_ls_hsbl_hdr {
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 meta_data_offset;
u32 meta_data_size;
u32 num_sig;
};
const struct nvfw_ls_hsbl_hdr *nvfw_ls_hsbl_hdr(struct nvkm_subdev *, const void *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/pmu.h
+98
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@@ -0,0 +1,98 @@
#ifndef __NVFW_PMU_H__
#define __NVFW_PMU_H__
struct nv_pmu_args {
u32 reserved;
u32 freq_hz;
u32 trace_size;
u32 trace_dma_base;
u16 trace_dma_base1;
u8 trace_dma_offset;
u32 trace_dma_idx;
bool secure_mode;
bool raise_priv_sec;
struct {
u32 dma_base;
u16 dma_base1;
u8 dma_offset;
u16 fb_size;
u8 dma_idx;
} gc6_ctx;
u8 pad;
};
#define NV_PMU_UNIT_INIT 0x07
#define NV_PMU_UNIT_ACR 0x0a
struct nv_pmu_init_msg {
struct nvfw_falcon_msg hdr;
#define NV_PMU_INIT_MSG_INIT 0x00
u8 msg_type;
u8 pad;
u16 os_debug_entry_point;
struct {
u16 size;
u16 offset;
u8 index;
u8 pad;
} queue_info[5];
u16 sw_managed_area_offset;
u16 sw_managed_area_size;
};
struct nv_pmu_acr_cmd {
struct nvfw_falcon_cmd hdr;
#define NV_PMU_ACR_CMD_INIT_WPR_REGION 0x00
#define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON 0x01
#define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS 0x03
u8 cmd_type;
};
struct nv_pmu_acr_msg {
struct nvfw_falcon_cmd hdr;
u8 msg_type;
};
struct nv_pmu_acr_init_wpr_region_cmd {
struct nv_pmu_acr_cmd cmd;
u32 region_id;
u32 wpr_offset;
};
struct nv_pmu_acr_init_wpr_region_msg {
struct nv_pmu_acr_msg msg;
u32 error_code;
};
struct nv_pmu_acr_bootstrap_falcon_cmd {
struct nv_pmu_acr_cmd cmd;
#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
u32 flags;
u32 falcon_id;
};
struct nv_pmu_acr_bootstrap_falcon_msg {
struct nv_pmu_acr_msg msg;
u32 falcon_id;
};
struct nv_pmu_acr_bootstrap_multiple_falcons_cmd {
struct nv_pmu_acr_cmd cmd;
#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES 0x00000000
#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_NO 0x00000001
u32 flags;
u32 falcon_mask;
u32 use_va_mask;
u32 wpr_lo;
u32 wpr_hi;
};
struct nv_pmu_acr_bootstrap_multiple_falcons_msg {
struct nv_pmu_acr_msg msg;
u32 falcon_mask;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvfw/sec2.h
+105
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@@ -0,0 +1,105 @@
#ifndef __NVFW_SEC2_H__
#define __NVFW_SEC2_H__
struct nv_sec2_args {
u32 freq_hz;
u32 falc_trace_size;
u32 falc_trace_dma_base;
u32 falc_trace_dma_idx;
bool secure_mode;
};
#define NV_SEC2_UNIT_INIT 0x01
#define NV_SEC2_UNIT_UNLOAD 0x06
#define NV_SEC2_UNIT_ACR 0x08
struct nv_sec2_init_msg {
struct nvfw_falcon_msg hdr;
#define NV_SEC2_INIT_MSG_INIT 0x00
u8 msg_type;
u8 num_queues;
u16 os_debug_entry_point;
struct {
u32 offset;
u16 size;
u8 index;
#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
u8 id;
} queue_info[2];
u32 sw_managed_area_offset;
u16 sw_managed_area_size;
};
struct nv_sec2_init_msg_v1 {
struct nvfw_falcon_msg hdr;
#define NV_SEC2_INIT_MSG_INIT 0x00
u8 msg_type;
u8 num_queues;
u16 os_debug_entry_point;
struct {
u32 offset;
u16 size;
u8 index;
#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
u8 id;
} queue_info[2];
u32 sw_managed_area_offset;
u16 sw_managed_area_size;
u32 unkn[8];
};
struct nv_sec2_acr_cmd {
struct nvfw_falcon_cmd hdr;
#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00
u8 cmd_type;
};
struct nv_sec2_acr_msg {
struct nvfw_falcon_cmd hdr;
u8 msg_type;
};
struct nv_sec2_acr_bootstrap_falcon_cmd {
struct nv_sec2_acr_cmd cmd;
#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
u32 flags;
u32 falcon_id;
};
struct nv_sec2_acr_bootstrap_falcon_msg {
struct nv_sec2_acr_msg msg;
u32 error_code;
u32 falcon_id;
};
#define NV_SEC2_UNIT_V2_INIT 0x01
#define NV_SEC2_UNIT_V2_UNLOAD 0x05
#define NV_SEC2_UNIT_V2_ACR 0x07
struct nv_sec2_acr_bootstrap_falcon_cmd_v1 {
struct nv_sec2_acr_cmd cmd;
#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
u32 flags;
u32 falcon_id;
u32 unkn08;
u32 unkn0c;
};
struct nv_sec2_acr_bootstrap_falcon_msg_v1 {
struct nv_sec2_acr_msg msg;
u32 error_code;
u32 falcon_id;
u32 unkn08;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h
+45
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@@ -0,0 +1,45 @@
/*
* Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0039_h_
#define _cl0039_h_
/* dma method offsets, fields, and values */
#define NV039_SET_OBJECT (0x00000000)
#define NV039_NO_OPERATION (0x00000100)
#define NV039_SET_CONTEXT_DMA_NOTIFIES (0x00000180)
#define NV039_SET_CONTEXT_DMA_BUFFER_IN (0x00000184)
#define NV039_SET_CONTEXT_DMA_BUFFER_OUT (0x00000188)
#define NV039_OFFSET_IN (0x0000030C)
#define NV039_OFFSET_OUT (0x00000310)
#define NV039_PITCH_IN (0x00000314)
#define NV039_PITCH_OUT (0x00000318)
#define NV039_LINE_LENGTH_IN (0x0000031C)
#define NV039_LINE_COUNT (0x00000320)
#define NV039_FORMAT (0x00000324)
#define NV039_FORMAT_IN 7:0
#define NV039_FORMAT_OUT 31:8
#define NV039_BUFFER_NOTIFY (0x00000328)
#define NV039_BUFFER_NOTIFY_WRITE_ONLY (0x00000000)
#define NV039_BUFFER_NOTIFY_WRITE_THEN_AWAKEN (0x00000001)
#endif /* _cl0039_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h
+46
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@@ -0,0 +1,46 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef _cl006c_h_
#define _cl006c_h_
/* fields and values */
#define NV06C_PUT (0x00000040)
#define NV06C_PUT_PTR 31:2
#define NV06C_GET (0x00000044)
#define NV06C_GET_PTR 31:2
/* dma method descriptor format */
#define NV06C_METHOD_ADDRESS 12:2
#define NV06C_METHOD_SUBCHANNEL 15:13
#define NV06C_METHOD_COUNT 28:18
#define NV06C_OPCODE 31:29
#define NV06C_OPCODE_METHOD (0x00000000)
#define NV06C_OPCODE_NONINC_METHOD (0x00000002)
/* dma data format */
#define NV06C_DATA 31:0
/* dma jump format */
#define NV06C_OPCODE_JUMP (0x00000001)
#define NV06C_JUMP_OFFSET 28:2
#endif /* _cl006c_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h
+30
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@@ -0,0 +1,30 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef _cl006e_h_
#define _cl006e_h_
/* fields and values */
#define NV06E_SET_OBJECT (0x00000000)
#define NV06E_REFERENCE (0x00000048)
#define NV06E_SET_REFERENCE (0x00000050)
#endif /* _cl006e_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h
+10
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@@ -0,0 +1,10 @@
/* SPDX-License-Identifier: MIT */
#ifndef _cl176e_h_
#define _cl176e_h_
#define NV176E_SET_OBJECT (0x00000000)
#define NV176E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
#define NV176E_SEMAPHORE_OFFSET (0x00000064)
#define NV176E_SEMAPHORE_ACQUIRE (0x00000068)
#define NV176E_SEMAPHORE_RELEASE (0x0000006c)
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h
+35
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@@ -0,0 +1,35 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef _cl206e_h_
#define _cl206e_h_
/* dma opcode2 format */
#define NV206E_DMA_OPCODE2 1:0
#define NV206E_DMA_OPCODE2_NONE (0x00000000)
/* dma jump_long format */
#define NV206E_DMA_OPCODE2_JUMP_LONG (0x00000001)
#define NV206E_DMA_JUMP_LONG_OFFSET 31:2
/* dma call format */
#define NV206E_DMA_OPCODE2_CALL (0x00000002)
#define NV206E_DMA_CALL_OFFSET 31:2
#endif /* _cl206e_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h
+337
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@@ -0,0 +1,337 @@
/*
* Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl_nv50_twod_h_
#define _cl_nv50_twod_h_
#define NV502D_SET_OBJECT 0x0000
#define NV502D_SET_OBJECT_POINTER 15:0
#define NV502D_WAIT_FOR_IDLE 0x0110
#define NV502D_WAIT_FOR_IDLE_V 31:0
#define NV502D_SET_DST_CONTEXT_DMA 0x0184
#define NV502D_SET_DST_CONTEXT_DMA_HANDLE 31:0
#define NV502D_SET_SRC_CONTEXT_DMA 0x0188
#define NV502D_SET_SRC_CONTEXT_DMA_HANDLE 31:0
#define NV502D_SET_SEMAPHORE_CONTEXT_DMA 0x018c
#define NV502D_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
#define NV502D_SET_DST_FORMAT 0x0200
#define NV502D_SET_DST_FORMAT_V 7:0
#define NV502D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
#define NV502D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
#define NV502D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
#define NV502D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
#define NV502D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6
#define NV502D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1
#define NV502D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6
#define NV502D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7
#define NV502D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9
#define NV502D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA
#define NV502D_SET_DST_FORMAT_V_R5G6B5 0x000000E8
#define NV502D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9
#define NV502D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8
#define NV502D_SET_DST_FORMAT_V_Y8 0x000000F3
#define NV502D_SET_DST_FORMAT_V_Y16 0x000000EE
#define NV502D_SET_DST_FORMAT_V_Y32 0x000000FF
#define NV502D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV502D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC
#define NV502D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV502D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE
#define NV502D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C
#define NV502D_SET_DST_FORMAT_V_RF16 0x000000F2
#define NV502D_SET_DST_FORMAT_V_RF32 0x000000E5
#define NV502D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB
#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
#define NV502D_SET_DST_MEMORY_LAYOUT 0x0204
#define NV502D_SET_DST_MEMORY_LAYOUT_V 0:0
#define NV502D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV502D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV502D_SET_DST_PITCH 0x0214
#define NV502D_SET_DST_PITCH_V 31:0
#define NV502D_SET_DST_WIDTH 0x0218
#define NV502D_SET_DST_WIDTH_V 31:0
#define NV502D_SET_DST_HEIGHT 0x021c
#define NV502D_SET_DST_HEIGHT_V 31:0
#define NV502D_SET_DST_OFFSET_UPPER 0x0220
#define NV502D_SET_DST_OFFSET_UPPER_V 7:0
#define NV502D_SET_DST_OFFSET_LOWER 0x0224
#define NV502D_SET_DST_OFFSET_LOWER_V 31:0
#define NV502D_SET_SRC_FORMAT 0x0230
#define NV502D_SET_SRC_FORMAT_V 7:0
#define NV502D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF
#define NV502D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0
#define NV502D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF
#define NV502D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5
#define NV502D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6
#define NV502D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1
#define NV502D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6
#define NV502D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7
#define NV502D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9
#define NV502D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA
#define NV502D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8
#define NV502D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9
#define NV502D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8
#define NV502D_SET_SRC_FORMAT_V_Y8 0x000000F3
#define NV502D_SET_SRC_FORMAT_V_AY8 0x0000001D
#define NV502D_SET_SRC_FORMAT_V_Y16 0x000000EE
#define NV502D_SET_SRC_FORMAT_V_Y32 0x000000FF
#define NV502D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV502D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC
#define NV502D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV502D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE
#define NV502D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C
#define NV502D_SET_SRC_FORMAT_V_RF16 0x000000F2
#define NV502D_SET_SRC_FORMAT_V_RF32 0x000000E5
#define NV502D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB
#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
#define NV502D_SET_SRC_MEMORY_LAYOUT 0x0234
#define NV502D_SET_SRC_MEMORY_LAYOUT_V 0:0
#define NV502D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV502D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV502D_SET_SRC_PITCH 0x0244
#define NV502D_SET_SRC_PITCH_V 31:0
#define NV502D_SET_SRC_WIDTH 0x0248
#define NV502D_SET_SRC_WIDTH_V 31:0
#define NV502D_SET_SRC_HEIGHT 0x024c
#define NV502D_SET_SRC_HEIGHT_V 31:0
#define NV502D_SET_SRC_OFFSET_UPPER 0x0250
#define NV502D_SET_SRC_OFFSET_UPPER_V 7:0
#define NV502D_SET_SRC_OFFSET_LOWER 0x0254
#define NV502D_SET_SRC_OFFSET_LOWER_V 31:0
#define NV502D_SET_CLIP_ENABLE 0x0290
#define NV502D_SET_CLIP_ENABLE_V 0:0
#define NV502D_SET_CLIP_ENABLE_V_FALSE 0x00000000
#define NV502D_SET_CLIP_ENABLE_V_TRUE 0x00000001
#define NV502D_SET_ROP 0x02a0
#define NV502D_SET_ROP_V 7:0
#define NV502D_SET_OPERATION 0x02ac
#define NV502D_SET_OPERATION_V 2:0
#define NV502D_SET_OPERATION_V_SRCCOPY_AND 0x00000000
#define NV502D_SET_OPERATION_V_ROP_AND 0x00000001
#define NV502D_SET_OPERATION_V_BLEND_AND 0x00000002
#define NV502D_SET_OPERATION_V_SRCCOPY 0x00000003
#define NV502D_SET_OPERATION_V_ROP 0x00000004
#define NV502D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005
#define NV502D_SET_OPERATION_V_BLEND_PREMULT 0x00000006
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004
#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005
#define NV502D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec
#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0
#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000
#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001
#define NV502D_RENDER_SOLID_PRIM_MODE 0x0580
#define NV502D_RENDER_SOLID_PRIM_MODE_V 2:0
#define NV502D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000
#define NV502D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001
#define NV502D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002
#define NV502D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003
#define NV502D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR 0x0588
#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0
#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8)
#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0
#define NV502D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8)
#define NV502D_RENDER_SOLID_PRIM_POINT_Y_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800
#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0
#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000
#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808
#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0
#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000
#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001
#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002
#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c
#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0
#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000
#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001
#define NV502D_SET_PIXELS_FROM_CPU_WRAP 0x0810
#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V 1:0
#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000
#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001
#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002
#define NV502D_SET_PIXELS_FROM_CPU_COLOR0 0x0814
#define NV502D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_COLOR1 0x0818
#define NV502D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c
#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0
#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000
#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001
#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838
#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c
#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840
#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844
#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848
#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c
#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850
#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854
#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858
#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c
#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0
#define NV502D_PIXELS_FROM_CPU_DATA 0x0860
#define NV502D_PIXELS_FROM_CPU_DATA_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888
#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0
#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000
#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc
#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0
#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4
#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8
#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc
#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0
#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4
#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0
#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8
#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0
#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc
#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0
#endif /* _cl_nv50_twod_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h
+153
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@@ -0,0 +1,153 @@
/*
* Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl_nv50_memory_to_memory_format_h_
#define _cl_nv50_memory_to_memory_format_h_
#define NV5039_SET_OBJECT 0x0000
#define NV5039_SET_OBJECT_POINTER 15:0
#define NV5039_NO_OPERATION 0x0100
#define NV5039_NO_OPERATION_V 31:0
#define NV5039_SET_CONTEXT_DMA_NOTIFY 0x0180
#define NV5039_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
#define NV5039_SET_CONTEXT_DMA_BUFFER_IN 0x0184
#define NV5039_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
#define NV5039_SET_SRC_MEMORY_LAYOUT 0x0200
#define NV5039_SET_SRC_MEMORY_LAYOUT_V 0:0
#define NV5039_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV5039_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV5039_SET_SRC_BLOCK_SIZE 0x0204
#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH 3:0
#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT 7:4
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004
#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH 11:8
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004
#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005
#define NV5039_SET_SRC_WIDTH 0x0208
#define NV5039_SET_SRC_WIDTH_V 31:0
#define NV5039_SET_SRC_HEIGHT 0x020c
#define NV5039_SET_SRC_HEIGHT_V 31:0
#define NV5039_SET_SRC_DEPTH 0x0210
#define NV5039_SET_SRC_DEPTH_V 31:0
#define NV5039_SET_SRC_LAYER 0x0214
#define NV5039_SET_SRC_LAYER_V 31:0
#define NV5039_SET_SRC_ORIGIN 0x0218
#define NV5039_SET_SRC_ORIGIN_X 15:0
#define NV5039_SET_SRC_ORIGIN_Y 31:16
#define NV5039_SET_DST_MEMORY_LAYOUT 0x021c
#define NV5039_SET_DST_MEMORY_LAYOUT_V 0:0
#define NV5039_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV5039_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV5039_SET_DST_BLOCK_SIZE 0x0220
#define NV5039_SET_DST_BLOCK_SIZE_WIDTH 3:0
#define NV5039_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT 7:4
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004
#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH 11:8
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004
#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005
#define NV5039_SET_DST_WIDTH 0x0224
#define NV5039_SET_DST_WIDTH_V 31:0
#define NV5039_SET_DST_HEIGHT 0x0228
#define NV5039_SET_DST_HEIGHT_V 31:0
#define NV5039_SET_DST_DEPTH 0x022c
#define NV5039_SET_DST_DEPTH_V 31:0
#define NV5039_SET_DST_LAYER 0x0230
#define NV5039_SET_DST_LAYER_V 31:0
#define NV5039_SET_DST_ORIGIN 0x0234
#define NV5039_SET_DST_ORIGIN_X 15:0
#define NV5039_SET_DST_ORIGIN_Y 31:16
#define NV5039_OFFSET_IN_UPPER 0x0238
#define NV5039_OFFSET_IN_UPPER_VALUE 7:0
#define NV5039_OFFSET_OUT_UPPER 0x023c
#define NV5039_OFFSET_OUT_UPPER_VALUE 7:0
#define NV5039_OFFSET_IN 0x030c
#define NV5039_OFFSET_IN_VALUE 31:0
#define NV5039_OFFSET_OUT 0x0310
#define NV5039_OFFSET_OUT_VALUE 31:0
#define NV5039_PITCH_IN 0x0314
#define NV5039_PITCH_IN_VALUE 31:0
#define NV5039_PITCH_OUT 0x0318
#define NV5039_PITCH_OUT_VALUE 31:0
#define NV5039_LINE_LENGTH_IN 0x031c
#define NV5039_LINE_LENGTH_IN_VALUE 31:0
#define NV5039_LINE_COUNT 0x0320
#define NV5039_LINE_COUNT_VALUE 31:0
#define NV5039_FORMAT 0x0324
#define NV5039_FORMAT_IN 7:0
#define NV5039_FORMAT_IN_ONE 0x00000001
#define NV5039_FORMAT_OUT 15:8
#define NV5039_FORMAT_OUT_ONE 0x00000001
#define NV5039_BUFFER_NOTIFY 0x0328
#define NV5039_BUFFER_NOTIFY_TYPE 31:0
#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_ONLY 0x00000000
#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001
#endif /* _cl_nv50_memory_to_memory_format_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl507a.h
+36
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@@ -0,0 +1,36 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl507a_h_
#define _cl507a_h_
#define NV507A_FREE (0x00000008)
#define NV507A_FREE_COUNT 5:0
#define NV507A_UPDATE (0x00000080)
#define NV507A_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV507A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV507A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT (0x00000084)
#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
#endif // _cl507a_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl507c.h
+165
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@@ -0,0 +1,165 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl507c_h_
#define _cl507c_h_
#define NV_DISP_BASE_NOTIFIER_1 0x00000000
#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004
#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000
#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0
#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002
// dma opcode instructions
#define NV507C_DMA 0x00000000
#define NV507C_DMA_OPCODE 31:29
#define NV507C_DMA_OPCODE_METHOD 0x00000000
#define NV507C_DMA_OPCODE_JUMP 0x00000001
#define NV507C_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV507C_DMA_OPCODE 31:29
#define NV507C_DMA_OPCODE_METHOD 0x00000000
#define NV507C_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV507C_DMA_METHOD_COUNT 27:18
#define NV507C_DMA_METHOD_OFFSET 11:2
#define NV507C_DMA_DATA 31:0
#define NV507C_DMA_NOP 0x00000000
#define NV507C_DMA_OPCODE 31:29
#define NV507C_DMA_OPCODE_JUMP 0x00000001
#define NV507C_DMA_JUMP_OFFSET 11:2
#define NV507C_DMA_OPCODE 31:29
#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV507C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NV507C_PUT (0x00000000)
#define NV507C_PUT_PTR 11:2
#define NV507C_GET (0x00000004)
#define NV507C_GET_PTR 11:2
#define NV507C_UPDATE (0x00000080)
#define NV507C_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV507C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV507C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV507C_SET_PRESENT_CONTROL (0x00000084)
#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8
#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
#define NV507C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV507C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16
#define NV507C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10
#define NV507C_SET_SEMAPHORE_CONTROL (0x00000088)
#define NV507C_SET_SEMAPHORE_CONTROL_OFFSET 11:2
#define NV507C_SET_SEMAPHORE_ACQUIRE (0x0000008C)
#define NV507C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NV507C_SET_SEMAPHORE_RELEASE (0x00000090)
#define NV507C_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NV507C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094)
#define NV507C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0
#define NV507C_SET_NOTIFIER_CONTROL (0x000000A0)
#define NV507C_SET_NOTIFIER_CONTROL_MODE 30:30
#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NV507C_SET_NOTIFIER_CONTROL_OFFSET 11:2
#define NV507C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4)
#define NV507C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NV507C_SET_CONTEXT_DMA_ISO (0x000000C0)
#define NV507C_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV507C_SET_BASE_LUT_LO (0x000000E0)
#define NV507C_SET_BASE_LUT_LO_ENABLE 31:30
#define NV507C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV507C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV507C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000003)
#define NV507C_SET_BASE_LUT_LO_MODE 29:29
#define NV507C_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV507C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV507C_SET_BASE_LUT_LO_ORIGIN 7:2
#define NV507C_SET_PROCESSING (0x00000110)
#define NV507C_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV507C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV507C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV507C_SET_CONVERSION (0x00000114)
#define NV507C_SET_CONVERSION_GAIN 15:0
#define NV507C_SET_CONVERSION_OFS 31:16
#define NV507C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
#define NV507C_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV507C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020)
#define NV507C_SURFACE_SET_SIZE_WIDTH 14:0
#define NV507C_SURFACE_SET_SIZE_HEIGHT 30:16
#define NV507C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020)
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV507C_SURFACE_SET_STORAGE_PITCH 17:8
#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV507C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020)
#define NV507C_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV507C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV507C_SURFACE_SET_PARAMS_GAMMA 2:2
#define NV507C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV507C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV507C_SURFACE_SET_PARAMS_LAYOUT 5:4
#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000)
#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001)
#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002)
#define NV507C_SURFACE_SET_PARAMS_KIND 22:16
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D)
#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E)
#define NV507C_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F)
#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE 24:24
#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000)
#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001)
#endif // _cl507c_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h
+375
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@@ -0,0 +1,375 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl507d_h_
#define _cl507d_h_
#define NV_DISP_CORE_NOTIFIER_1 0x00000000
#define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
// class methods
#define NV507D_UPDATE (0x00000080)
#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0
#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8
#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_BASE0 1:1
#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_BASE1 9:9
#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000)
#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001)
#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY 31:31
#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000)
#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001)
#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30
#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000)
#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001)
#define NV507D_UPDATE_INHIBIT_INTERRUPTS 29:29
#define NV507D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000)
#define NV507D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001)
#define NV507D_SET_NOTIFIER_CONTROL (0x00000084)
#define NV507D_SET_NOTIFIER_CONTROL_MODE 30:30
#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NV507D_SET_NOTIFIER_CONTROL_OFFSET 11:2
#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY 31:31
#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000)
#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001)
#define NV507D_SET_CONTEXT_DMA_NOTIFIER (0x00000088)
#define NV507D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NV507D_GET_CAPABILITIES (0x0000008C)
#define NV507D_GET_CAPABILITIES_DUMMY 31:0
#define NV507D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080)
#define NV507D_DAC_SET_CONTROL_OWNER 3:0
#define NV507D_DAC_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV507D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV507D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV507D_DAC_SET_CONTROL_SUB_OWNER 5:4
#define NV507D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV507D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV507D_DAC_SET_CONTROL_PROTOCOL 13:8
#define NV507D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012)
#define NV507D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F)
#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14
#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000)
#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001)
#define NV507D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080)
#define NV507D_DAC_SET_POLARITY_HSYNC 0:0
#define NV507D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000)
#define NV507D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001)
#define NV507D_DAC_SET_POLARITY_VSYNC 1:1
#define NV507D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000)
#define NV507D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001)
#define NV507D_DAC_SET_POLARITY_RESERVED 31:2
#define NV507D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040)
#define NV507D_SOR_SET_CONTROL_OWNER 3:0
#define NV507D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV507D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV507D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV507D_SOR_SET_CONTROL_SUB_OWNER 5:4
#define NV507D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV507D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV507D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007)
#define NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV507D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040)
#define NV507D_PIOR_SET_CONTROL_OWNER 3:0
#define NV507D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV507D_PIOR_SET_CONTROL_SUB_OWNER 5:4
#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV507D_PIOR_SET_CONTROL_PROTOCOL 11:8
#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000)
#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001)
#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV507D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400)
#define NV507D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0
#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE 23:22
#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000)
#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001)
#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002)
#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24
#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000)
#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001)
#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25
#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000)
#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001)
#define NV507D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400)
#define NV507D_HEAD_SET_CONTROL_STRUCTURE 2:1
#define NV507D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000)
#define NV507D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001)
#define NV507D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400)
#define NV507D_HEAD_SET_OVERSCAN_COLOR_RED 9:0
#define NV507D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10
#define NV507D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20
#define NV507D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400)
#define NV507D_HEAD_SET_RASTER_SIZE_WIDTH 14:0
#define NV507D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16
#define NV507D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400)
#define NV507D_HEAD_SET_RASTER_SYNC_END_X 14:0
#define NV507D_HEAD_SET_RASTER_SYNC_END_Y 30:16
#define NV507D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400)
#define NV507D_HEAD_SET_RASTER_BLANK_END_X 14:0
#define NV507D_HEAD_SET_RASTER_BLANK_END_Y 30:16
#define NV507D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400)
#define NV507D_HEAD_SET_RASTER_BLANK_START_X 14:0
#define NV507D_HEAD_SET_RASTER_BLANK_START_Y 30:16
#define NV507D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400)
#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0
#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16
#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400)
#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0
#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400)
#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0
#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10
#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20
#define NV507D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400)
#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31
#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV507D_HEAD_SET_BASE_LUT_LO_MODE 30:30
#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV507D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2
#define NV507D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400)
#define NV507D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV507D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
#define NV507D_HEAD_SET_OFFSET_ORIGIN 31:0
#define NV507D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400)
#define NV507D_HEAD_SET_SIZE_WIDTH 14:0
#define NV507D_HEAD_SET_SIZE_HEIGHT 30:16
#define NV507D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400)
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV507D_HEAD_SET_STORAGE_PITCH 17:8
#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV507D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400)
#define NV507D_HEAD_SET_PARAMS_FORMAT 15:8
#define NV507D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV507D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV507D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV507D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV507D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV507D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV507D_HEAD_SET_PARAMS_KIND 22:16
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH (0x00000000)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D)
#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E)
#define NV507D_HEAD_SET_PARAMS_KIND_FROM_PTE (0x0000007F)
#define NV507D_HEAD_SET_PARAMS_PART_STRIDE 24:24
#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000)
#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001)
#define NV507D_HEAD_SET_CONTEXT_DMA_ISO(a) (0x00000874 + (a)*0x00000400)
#define NV507D_HEAD_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV507D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400)
#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26
#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8
#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16
#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4
#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000)
#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003)
#define NV507D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400)
#define NV507D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV507D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400)
#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NV507D_HEAD_SET_DITHER_CONTROL_BITS 2:1
#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000)
#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001)
#define NV507D_HEAD_SET_DITHER_CONTROL_MODE 6:3
#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NV507D_HEAD_SET_DITHER_CONTROL_PHASE 8:7
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002)
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16
#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24
#define NV507D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400)
#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2
#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000)
#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001)
#define NV507D_HEAD_SET_PROCAMP_SAT_COS 19:8
#define NV507D_HEAD_SET_PROCAMP_SAT_SINE 31:20
#define NV507D_HEAD_SET_PROCAMP_TRANSITION 4:3
#define NV507D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000)
#define NV507D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001)
#define NV507D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002)
#define NV507D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0
#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16
#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400)
#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0
#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16
#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400)
#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0
#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16
#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400)
#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0
#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400)
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#endif // _cl507d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl507e.h
+93
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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl507e_h_
#define _cl507e_h_
// class methods
#define NV507E_SET_PRESENT_CONTROL (0x00000084)
#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
#define NV507E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV507E_SET_CONTEXT_DMA_ISO (0x000000C0)
#define NV507E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV507E_SET_POINT_IN (0x000000E0)
#define NV507E_SET_POINT_IN_X 14:0
#define NV507E_SET_POINT_IN_Y 30:16
#define NV507E_SET_SIZE_IN (0x000000E4)
#define NV507E_SET_SIZE_IN_WIDTH 14:0
#define NV507E_SET_SIZE_IN_HEIGHT 30:16
#define NV507E_SET_SIZE_OUT (0x000000E8)
#define NV507E_SET_SIZE_OUT_WIDTH 14:0
#define NV507E_SET_COMPOSITION_CONTROL (0x00000100)
#define NV507E_SET_COMPOSITION_CONTROL_MODE 3:0
#define NV507E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
#define NV507E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
#define NV507E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002)
#define NV507E_SURFACE_SET_OFFSET (0x00000800)
#define NV507E_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV507E_SURFACE_SET_SIZE (0x00000808)
#define NV507E_SURFACE_SET_SIZE_WIDTH 14:0
#define NV507E_SURFACE_SET_SIZE_HEIGHT 30:16
#define NV507E_SURFACE_SET_STORAGE (0x0000080C)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV507E_SURFACE_SET_STORAGE_PITCH 17:8
#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV507E_SURFACE_SET_PARAMS (0x00000810)
#define NV507E_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028)
#define NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029)
#define NV507E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV507E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#define NV507E_SURFACE_SET_PARAMS_KIND 22:16
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E)
#define NV507E_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F)
#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE 24:24
#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000)
#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001)
#endif // _cl507e_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h
+39
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/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef _cl826f_h_
#define _cl826f_h_
#define NV826F_SEMAPHOREA (0x00000010)
#define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0
#define NV826F_SEMAPHOREB (0x00000014)
#define NV826F_SEMAPHOREB_OFFSET_LOWER 31:00
#define NV826F_SEMAPHOREC (0x00000018)
#define NV826F_SEMAPHOREC_PAYLOAD 31:0
#define NV826F_SEMAPHORED (0x0000001C)
#define NV826F_SEMAPHORED_OPERATION 2:0
#define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
#define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002
#define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
#define NV826F_NON_STALLED_INTERRUPT (0x00000020)
#define NV826F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
#endif /* _cl826f_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl827c.h
+86
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@@ -0,0 +1,86 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl827c_h_
#define _cl827c_h_
// class methods
#define NV827C_SET_PRESENT_CONTROL (0x00000084)
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
#define NV827C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV827C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16
#define NV827C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10
#define NV827C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004)
#define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV827C_SET_PROCESSING (0x00000110)
#define NV827C_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV827C_SET_CONVERSION (0x00000114)
#define NV827C_SET_CONVERSION_GAIN 15:0
#define NV827C_SET_CONVERSION_OFS 31:16
#define NV827C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
#define NV827C_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV827C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020)
#define NV827C_SURFACE_SET_SIZE_WIDTH 14:0
#define NV827C_SURFACE_SET_SIZE_HEIGHT 30:16
#define NV827C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV827C_SURFACE_SET_STORAGE_PITCH 17:8
#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV827C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020)
#define NV827C_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV827C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV827C_SURFACE_SET_PARAMS_GAMMA 2:2
#define NV827C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV827C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV827C_SURFACE_SET_PARAMS_LAYOUT 5:4
#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000)
#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001)
#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002)
#define NV827C_SURFACE_SET_PARAMS_RESERVED0 22:16
#define NV827C_SURFACE_SET_PARAMS_RESERVED1 24:24
#endif // _cl827c_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl827d.h
+106
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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl827d_h_
#define _cl827d_h_
// class methods
#define NV827D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400)
#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31
#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV827D_HEAD_SET_BASE_LUT_LO_MODE 30:30
#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV827D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2
#define NV827D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400)
#define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400)
#define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV827D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
#define NV827D_HEAD_SET_OFFSET_ORIGIN 31:0
#define NV827D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400)
#define NV827D_HEAD_SET_SIZE_WIDTH 14:0
#define NV827D_HEAD_SET_SIZE_HEIGHT 30:16
#define NV827D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV827D_HEAD_SET_STORAGE_PITCH 17:8
#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV827D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400)
#define NV827D_HEAD_SET_PARAMS_FORMAT 15:8
#define NV827D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV827D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV827D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV827D_HEAD_SET_PARAMS_GAMMA 2:2
#define NV827D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV827D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV827D_HEAD_SET_PARAMS_RESERVED0 22:16
#define NV827D_HEAD_SET_PARAMS_RESERVED1 24:24
#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV827D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400)
#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26
#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8
#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003)
#define NV827D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400)
#define NV827D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400)
#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV827D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0
#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16
#endif // _cl827d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl827e.h
+88
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@@ -0,0 +1,88 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl827e_h_
#define _cl827e_h_
#define NV_DISP_NOTIFICATION_1 0x00000000
#define NV_DISP_NOTIFICATION_1_SIZEOF 0x00000010
#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0 0x00000000
#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0 31:0
#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1 0x00000001
#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1 31:0
#define NV_DISP_NOTIFICATION_1__2 0x00000002
#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP 31:0
#define NV_DISP_NOTIFICATION_1__3 0x00000003
#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_1__3_R0 15:8
#define NV_DISP_NOTIFICATION_1__3_STATUS 31:16
#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED 0x00000000
// class methods
#define NV827E_SET_PRESENT_CONTROL (0x00000084)
#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
#define NV827E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV827E_SET_CONTEXT_DMA_ISO (0x000000C0)
#define NV827E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV827E_SET_COMPOSITION_CONTROL (0x00000100)
#define NV827E_SET_COMPOSITION_CONTROL_MODE 3:0
#define NV827E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
#define NV827E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
#define NV827E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002)
#define NV827E_SURFACE_SET_OFFSET (0x00000800)
#define NV827E_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV827E_SURFACE_SET_SIZE (0x00000808)
#define NV827E_SURFACE_SET_SIZE_WIDTH 14:0
#define NV827E_SURFACE_SET_SIZE_HEIGHT 30:16
#define NV827E_SURFACE_SET_STORAGE (0x0000080C)
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV827E_SURFACE_SET_STORAGE_PITCH 17:8
#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV827E_SURFACE_SET_PARAMS (0x00000810)
#define NV827E_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV827E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028)
#define NV827E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029)
#define NV827E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV827E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV827E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0
#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#define NV827E_SURFACE_SET_PARAMS_RESERVED0 22:16
#define NV827E_SURFACE_SET_PARAMS_RESERVED1 24:24
#endif // _cl827e_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h
+101
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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl837d_h_
#define _cl837d_h_
// class methods
#define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040)
#define NV837D_SOR_SET_CONTROL_OWNER 3:0
#define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER 5:4
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV837D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#define NV837D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040)
#define NV837D_PIOR_SET_CONTROL_OWNER 3:0
#define NV837D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER 5:4
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV837D_PIOR_SET_CONTROL_PROTOCOL 11:8
#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000)
#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001)
#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#endif // _cl837d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h
+68
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@@ -0,0 +1,68 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl887d_h_
#define _cl887d_h_
#define NV887D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040)
#define NV887D_SOR_SET_CONTROL_OWNER 3:0
#define NV887D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER 5:4
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV887D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#endif // _cl887d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h
+357
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@@ -0,0 +1,357 @@
/*
* Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl_fermi_twod_a_h_
#define _cl_fermi_twod_a_h_
#define NV902D_SET_OBJECT 0x0000
#define NV902D_SET_OBJECT_CLASS_ID 15:0
#define NV902D_SET_OBJECT_ENGINE_ID 20:16
#define NV902D_WAIT_FOR_IDLE 0x0110
#define NV902D_WAIT_FOR_IDLE_V 31:0
#define NV902D_SET_DST_FORMAT 0x0200
#define NV902D_SET_DST_FORMAT_V 7:0
#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6
#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1
#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6
#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7
#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9
#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA
#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8
#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9
#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8
#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3
#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE
#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF
#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC
#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE
#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C
#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2
#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5
#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB
#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6
#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7
#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0
#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7
#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE
#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA
#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB
#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA
#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB
#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF
#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4
#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7
#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204
#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0
#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV902D_SET_DST_PITCH 0x0214
#define NV902D_SET_DST_PITCH_V 31:0
#define NV902D_SET_DST_WIDTH 0x0218
#define NV902D_SET_DST_WIDTH_V 31:0
#define NV902D_SET_DST_HEIGHT 0x021c
#define NV902D_SET_DST_HEIGHT_V 31:0
#define NV902D_SET_DST_OFFSET_UPPER 0x0220
#define NV902D_SET_DST_OFFSET_UPPER_V 7:0
#define NV902D_SET_DST_OFFSET_LOWER 0x0224
#define NV902D_SET_DST_OFFSET_LOWER_V 31:0
#define NV902D_SET_SRC_FORMAT 0x0230
#define NV902D_SET_SRC_FORMAT_V 7:0
#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF
#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0
#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF
#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5
#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6
#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1
#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6
#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7
#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9
#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA
#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8
#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9
#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8
#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3
#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D
#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE
#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF
#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC
#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE
#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C
#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2
#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5
#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB
#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6
#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7
#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0
#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7
#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE
#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA
#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB
#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA
#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB
#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF
#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4
#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7
#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234
#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0
#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001
#define NV902D_SET_SRC_PITCH 0x0244
#define NV902D_SET_SRC_PITCH_V 31:0
#define NV902D_SET_SRC_WIDTH 0x0248
#define NV902D_SET_SRC_WIDTH_V 31:0
#define NV902D_SET_SRC_HEIGHT 0x024c
#define NV902D_SET_SRC_HEIGHT_V 31:0
#define NV902D_SET_SRC_OFFSET_UPPER 0x0250
#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0
#define NV902D_SET_SRC_OFFSET_LOWER 0x0254
#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0
#define NV902D_SET_CLIP_ENABLE 0x0290
#define NV902D_SET_CLIP_ENABLE_V 0:0
#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000
#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001
#define NV902D_SET_ROP 0x02a0
#define NV902D_SET_ROP_V 7:0
#define NV902D_SET_OPERATION 0x02ac
#define NV902D_SET_OPERATION_V 2:0
#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000
#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001
#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002
#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003
#define NV902D_SET_OPERATION_V_ROP 0x00000004
#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005
#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005
#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006
#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec
#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0
#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000
#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001
#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580
#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0
#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000
#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001
#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002
#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003
#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588
#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0
#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8)
#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0
#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8)
#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800
#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0
#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000
#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808
#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0
#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000
#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001
#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002
#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c
#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0
#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000
#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001
#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810
#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0
#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000
#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001
#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002
#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814
#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818
#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c
#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0
#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000
#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001
#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838
#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c
#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840
#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844
#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848
#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c
#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850
#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854
#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858
#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c
#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0
#define NV902D_PIXELS_FROM_CPU_DATA 0x0860
#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888
#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0
#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000
#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc
#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0
#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4
#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8
#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc
#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0
#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4
#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0
#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8
#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0
#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc
#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0
#endif /* _cl_fermi_twod_a_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h
+74
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@@ -0,0 +1,74 @@
/*
* Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl_fermi_memory_to_memory_format_a_h_
#define _cl_fermi_memory_to_memory_format_a_h_
#define NV9039_SET_OBJECT 0x0000
#define NV9039_SET_OBJECT_CLASS_ID 15:0
#define NV9039_SET_OBJECT_ENGINE_ID 20:16
#define NV9039_OFFSET_OUT_UPPER 0x0238
#define NV9039_OFFSET_OUT_UPPER_VALUE 7:0
#define NV9039_OFFSET_OUT 0x023c
#define NV9039_OFFSET_OUT_VALUE 31:0
#define NV9039_LAUNCH_DMA 0x0300
#define NV9039_LAUNCH_DMA_SRC_INLINE 0:0
#define NV9039_LAUNCH_DMA_SRC_INLINE_FALSE 0x00000000
#define NV9039_LAUNCH_DMA_SRC_INLINE_TRUE 0x00000001
#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT 4:4
#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000
#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH 0x00000001
#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000
#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001
#define NV9039_LAUNCH_DMA_COMPLETION_TYPE 13:12
#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000
#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001
#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002
#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE 17:16
#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000
#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001
#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 20:20
#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000
#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001
#define NV9039_OFFSET_IN_UPPER 0x030c
#define NV9039_OFFSET_IN_UPPER_VALUE 7:0
#define NV9039_OFFSET_IN 0x0310
#define NV9039_OFFSET_IN_VALUE 31:0
#define NV9039_PITCH_IN 0x0314
#define NV9039_PITCH_IN_VALUE 31:0
#define NV9039_PITCH_OUT 0x0318
#define NV9039_PITCH_OUT_VALUE 31:0
#define NV9039_LINE_LENGTH_IN 0x031c
#define NV9039_LINE_LENGTH_IN_VALUE 31:0
#define NV9039_LINE_COUNT 0x0320
#define NV9039_LINE_COUNT_VALUE 31:0
#endif /* _cl_fermi_memory_to_memory_format_a_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h
+74
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@@ -0,0 +1,74 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef _cl906f_h_
#define _cl906f_h_
/* fields and values */
#define NV906F_SEMAPHOREA (0x00000010)
#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0
#define NV906F_SEMAPHOREB (0x00000014)
#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2
#define NV906F_SEMAPHOREC (0x00000018)
#define NV906F_SEMAPHOREC_PAYLOAD 31:0
#define NV906F_SEMAPHORED (0x0000001C)
#define NV906F_SEMAPHORED_OPERATION 3:0
#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002
#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12
#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
#define NV906F_SEMAPHORED_RELEASE_WFI 20:20
#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24
#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
#define NV906F_NON_STALL_INTERRUPT (0x00000020)
#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0
#define NV906F_SET_REFERENCE (0x00000050)
#define NV906F_SET_REFERENCE_COUNT 31:0
/* dma method formats */
#define NV906F_DMA_METHOD_ADDRESS 11:0
#define NV906F_DMA_SUBDEVICE_MASK 15:4
#define NV906F_DMA_METHOD_SUBCHANNEL 15:13
#define NV906F_DMA_TERT_OP 17:16
#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
#define NV906F_DMA_METHOD_COUNT 28:16
#define NV906F_DMA_IMMD_DATA 28:16
#define NV906F_DMA_SEC_OP 31:29
#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001)
#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005)
#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006)
#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
#endif /* _cl906f_h_ */
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl907c.h
+143
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@@ -0,0 +1,143 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl907c_h_
#define _cl907c_h_
// class methods
#define NV907C_SET_PRESENT_CONTROL (0x00000084)
#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8
#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME (0x00000003)
#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2
#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NV907C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV907C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16
#define NV907C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10
#define NV907C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004)
#define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV907C_SET_BASE_LUT_LO (0x000000E0)
#define NV907C_SET_BASE_LUT_LO_ENABLE 31:30
#define NV907C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV907C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002)
#define NV907C_SET_BASE_LUT_LO_MODE 27:24
#define NV907C_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV907C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV907C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV907C_SET_BASE_LUT_HI (0x000000E4)
#define NV907C_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV907C_SET_OUTPUT_LUT_LO (0x000000E8)
#define NV907C_SET_OUTPUT_LUT_LO_ENABLE 31:30
#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002)
#define NV907C_SET_OUTPUT_LUT_LO_MODE 27:24
#define NV907C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV907C_SET_CONTEXT_DMA_LUT (0x000000FC)
#define NV907C_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV907C_SET_CSC_RED2RED (0x00000140)
#define NV907C_SET_CSC_RED2RED_OWNER 31:31
#define NV907C_SET_CSC_RED2RED_OWNER_CORE (0x00000000)
#define NV907C_SET_CSC_RED2RED_OWNER_BASE (0x00000001)
#define NV907C_SET_CSC_RED2RED_COEFF 18:0
#define NV907C_SET_CSC_GRN2RED (0x00000144)
#define NV907C_SET_CSC_GRN2RED_COEFF 18:0
#define NV907C_SET_CSC_BLU2RED (0x00000148)
#define NV907C_SET_CSC_BLU2RED_COEFF 18:0
#define NV907C_SET_CSC_CONSTANT2RED (0x0000014C)
#define NV907C_SET_CSC_CONSTANT2RED_COEFF 18:0
#define NV907C_SET_CSC_RED2GRN (0x00000150)
#define NV907C_SET_CSC_RED2GRN_COEFF 18:0
#define NV907C_SET_CSC_GRN2GRN (0x00000154)
#define NV907C_SET_CSC_GRN2GRN_COEFF 18:0
#define NV907C_SET_CSC_BLU2GRN (0x00000158)
#define NV907C_SET_CSC_BLU2GRN_COEFF 18:0
#define NV907C_SET_CSC_CONSTANT2GRN (0x0000015C)
#define NV907C_SET_CSC_CONSTANT2GRN_COEFF 18:0
#define NV907C_SET_CSC_RED2BLU (0x00000160)
#define NV907C_SET_CSC_RED2BLU_COEFF 18:0
#define NV907C_SET_CSC_GRN2BLU (0x00000164)
#define NV907C_SET_CSC_GRN2BLU_COEFF 18:0
#define NV907C_SET_CSC_BLU2BLU (0x00000168)
#define NV907C_SET_CSC_BLU2BLU_COEFF 18:0
#define NV907C_SET_CSC_CONSTANT2BLU (0x0000016C)
#define NV907C_SET_CSC_CONSTANT2BLU_COEFF 18:0
#define NV907C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
#define NV907C_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV907C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020)
#define NV907C_SURFACE_SET_SIZE_WIDTH 15:0
#define NV907C_SURFACE_SET_SIZE_HEIGHT 31:16
#define NV907C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020)
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV907C_SURFACE_SET_STORAGE_PITCH 20:8
#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV907C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020)
#define NV907C_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV907C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV907C_SURFACE_SET_PARAMS_GAMMA 2:2
#define NV907C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV907C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV907C_SURFACE_SET_PARAMS_LAYOUT 5:4
#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000)
#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001)
#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002)
#endif // _cl907c_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h
+436
View File
@@ -0,0 +1,436 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl907d_h_
#define _cl907d_h_
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27
// class methods
#define NV907D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020)
#define NV907D_DAC_SET_CONTROL_OWNER_MASK 3:0
#define NV907D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NV907D_DAC_SET_CONTROL_PROTOCOL 12:8
#define NV907D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000)
#define NV907D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013)
#define NV907D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020)
#define NV907D_SOR_SET_CONTROL_OWNER_MASK 3:0
#define NV907D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NV907D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV907D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV907D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV907D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#define NV907D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTROL_STRUCTURE 0:0
#define NV907D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000)
#define NV907D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001)
#define NV907D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300)
#define NV907D_HEAD_SET_OVERSCAN_COLOR_RED 9:0
#define NV907D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10
#define NV907D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20
#define NV907D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300)
#define NV907D_HEAD_SET_RASTER_SIZE_WIDTH 14:0
#define NV907D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16
#define NV907D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300)
#define NV907D_HEAD_SET_RASTER_SYNC_END_X 14:0
#define NV907D_HEAD_SET_RASTER_SYNC_END_Y 30:16
#define NV907D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300)
#define NV907D_HEAD_SET_RASTER_BLANK_END_X 14:0
#define NV907D_HEAD_SET_RASTER_BLANK_END_Y 30:16
#define NV907D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300)
#define NV907D_HEAD_SET_RASTER_BLANK_START_X 14:0
#define NV907D_HEAD_SET_RASTER_BLANK_START_Y 30:16
#define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300)
#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0
#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16
#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300)
#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0
#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10
#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20
#define NV907D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300)
#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0
#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000)
#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001)
#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002)
#define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2
#define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000)
#define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001)
#define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3
#define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000)
#define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i))
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i))
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF)
#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i))
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i))
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF)
#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF)
#define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5
#define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000)
#define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001)
#define NV907D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC 6:6
#define NV907D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_DISABLE (0x00000000)
#define NV907D_HEAD_SET_CRC_CONTROL_WIDE_PIPE_CRC_ENABLE (0x00000001)
#define NV907D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0
#define NV907D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000)
#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001)
#define NV907D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300)
#define NV907D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300)
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000)
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000)
#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001)
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300)
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000)
#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001)
#define NV907D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV907D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300)
#define NV907D_HEAD_SET_OFFSET_ORIGIN 31:0
#define NV907D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300)
#define NV907D_HEAD_SET_SIZE_WIDTH 15:0
#define NV907D_HEAD_SET_SIZE_HEIGHT 31:16
#define NV907D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300)
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV907D_HEAD_SET_STORAGE_PITCH 20:8
#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV907D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300)
#define NV907D_HEAD_SET_PARAMS_FORMAT 15:8
#define NV907D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV907D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV907D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV907D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV907D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV907D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV907D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV907D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV907D_HEAD_SET_PARAMS_GAMMA 2:2
#define NV907D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV907D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV907D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26
#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8
#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16
#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV907D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300)
#define NV907D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV907D_HEAD_SET_DITHER_CONTROL(a) (0x00000490 + (a)*0x00000300)
#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NV907D_HEAD_SET_DITHER_CONTROL_BITS 2:1
#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000)
#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001)
#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002)
#define NV907D_HEAD_SET_DITHER_CONTROL_MODE 6:3
#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
#define NV907D_HEAD_SET_DITHER_CONTROL_PHASE 8:7
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002)
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16
#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24
#define NV907D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300)
#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2
#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000)
#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001)
#define NV907D_HEAD_SET_PROCAMP_SAT_COS 19:8
#define NV907D_HEAD_SET_PROCAMP_SAT_SINE 31:20
#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5
#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000)
#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001)
#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6
#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000)
#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001)
#define NV907D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300)
#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0
#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16
#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300)
#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0
#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300)
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300)
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300)
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0
#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300)
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#endif // _cl907d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl907e.h
+73
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@@ -0,0 +1,73 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl907e_h_
#define _cl907e_h_
// class methods
#define NV907E_SET_PRESENT_CONTROL (0x00000084)
#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
#define NV907E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV907E_SET_CONTEXT_DMA_ISO (0x000000C0)
#define NV907E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV907E_SET_COMPOSITION_CONTROL (0x00000100)
#define NV907E_SET_COMPOSITION_CONTROL_MODE 3:0
#define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
#define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
#define NV907E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002)
#define NV907E_SURFACE_SET_OFFSET (0x00000400)
#define NV907E_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV907E_SURFACE_SET_SIZE (0x00000408)
#define NV907E_SURFACE_SET_SIZE_WIDTH 15:0
#define NV907E_SURFACE_SET_SIZE_HEIGHT 31:16
#define NV907E_SURFACE_SET_STORAGE (0x0000040C)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV907E_SURFACE_SET_STORAGE_PITCH 20:8
#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV907E_SURFACE_SET_PARAMS (0x00000410)
#define NV907E_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV907E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#endif // _cl907e_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h
+108
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@@ -0,0 +1,108 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917d_h_
#define _cl917d_h_
// class methods
#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300)
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003)
#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8
#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV917D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300)
#define NV917D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV917D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300)
#define NV917D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002)
#endif // _cl917d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h
+162
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@@ -0,0 +1,162 @@
/*******************************************************************************
Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef _cla0b5_h_
#define _cla0b5_h_
#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
#define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
#define NVA0B5_LAUNCH_DMA (0x00000300)
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002)
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000)
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001)
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002)
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001)
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11
#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000)
#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001)
#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12
#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000)
#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
#define NVA0B5_OFFSET_IN_UPPER (0x00000400)
#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0
#define NVA0B5_OFFSET_IN_LOWER (0x00000404)
#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0
#define NVA0B5_OFFSET_OUT_UPPER (0x00000408)
#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0
#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C)
#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0
#define NVA0B5_PITCH_IN (0x00000410)
#define NVA0B5_PITCH_IN_VALUE 31:0
#define NVA0B5_PITCH_OUT (0x00000414)
#define NVA0B5_PITCH_OUT_VALUE 31:0
#define NVA0B5_LINE_LENGTH_IN (0x00000418)
#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0
#define NVA0B5_LINE_COUNT (0x0000041C)
#define NVA0B5_LINE_COUNT_VALUE 31:0
#define NVA0B5_SET_REMAP_CONST_A (0x00000700)
#define NVA0B5_SET_REMAP_CONST_A_V 31:0
#define NVA0B5_SET_REMAP_CONST_B (0x00000704)
#define NVA0B5_SET_REMAP_CONST_B_V 31:0
#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003)
#endif // _cla0b5_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h
+137
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@@ -0,0 +1,137 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _clc36f_h_
#define _clc36f_h_
#define NVC36F_NON_STALL_INTERRUPT (0x00000020)
#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
// specifying the page address for a targeted TLB invalidate and the uTLB for
// a targeted REPLAY_CANCEL for UVM.
// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
// rearranged fields.
#define NVC36F_MEM_OP_A (0x00000028)
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
#define NVC36F_MEM_OP_B (0x0000002c)
#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
#define NVC36F_MEM_OP_C (0x00000030)
#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0
#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
// MEM_OP_D MUST be preceded by MEM_OPs A-C.
#define NVC36F_MEM_OP_D (0x00000034)
#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
#define NVC36F_MEM_OP_D_OPERATION 31:27
#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
// CLEAN_LINES is an alias for Tegra/GPU IP usage
#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
#define NVC36F_SEM_ADDR_LO (0x0000005c)
#define NVC36F_SEM_ADDR_LO_OFFSET 31:2
#define NVC36F_SEM_ADDR_HI (0x00000060)
#define NVC36F_SEM_ADDR_HI_OFFSET 7:0
#define NVC36F_SEM_PAYLOAD_LO (0x00000064)
#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0
#define NVC36F_SEM_PAYLOAD_HI (0x00000068)
#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0
#define NVC36F_SEM_EXECUTE (0x0000006c)
#define NVC36F_SEM_EXECUTE_OPERATION 2:0
#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
#define NVC36F_SEM_EXECUTE_REDUCTION 30:27
#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006
#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc37a.h
+31
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@@ -0,0 +1,31 @@
/*
* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc37a__h_
#define _clc37a__h_
#define NVC37A_UPDATE (0x00000200)
#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
#endif // _clc37a_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc37b.h
+49
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@@ -0,0 +1,49 @@
/*
* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC37b_h_
#define _clC37b_h_
// dma opcode instructions
#define NVC37B_DMA
#define NVC37B_DMA_OPCODE 31:29
#define NVC37B_DMA_OPCODE_METHOD 0x00000000
#define NVC37B_DMA_OPCODE_JUMP 0x00000001
#define NVC37B_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVC37B_DMA_METHOD_COUNT 27:18
#define NVC37B_DMA_METHOD_OFFSET 13:2
#define NVC37B_DMA_DATA 31:0
#define NVC37B_DMA_DATA_NOP 0x00000000
#define NVC37B_DMA_JUMP_OFFSET 11:2
#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVC37B_UPDATE (0x00000200)
#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVC37B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVC37B_SET_POINT_OUT_X 15:0
#define NVC37B_SET_POINT_OUT_Y 31:16
#endif // _clC37b_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc37d.h
+567
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@@ -0,0 +1,567 @@
/*
* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC37d_h_
#define _clC37d_h_
#define NV_DISP_NOTIFIER 0x00000000
#define NV_DISP_NOTIFIER_SIZEOF 0x00000010
#define NV_DISP_NOTIFIER__0 0x00000000
#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFIER__0_FIELD 8:8
#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9
#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
#define NV_DISP_NOTIFIER__0_R1 15:10
#define NV_DISP_NOTIFIER__0_R2 23:16
#define NV_DISP_NOTIFIER__0_R3 29:24
#define NV_DISP_NOTIFIER__0_STATUS 31:30
#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
#define NV_DISP_NOTIFIER__1 0x00000001
#define NV_DISP_NOTIFIER__1_R4 31:0
#define NV_DISP_NOTIFIER__2 0x00000002
#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0
#define NV_DISP_NOTIFIER__3 0x00000003
#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0
// class methods
#define NVC37D_UPDATE (0x00000200)
#define NVC37D_UPDATE_SPECIAL_HANDLING 21:20
#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000)
#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001)
#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002)
#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON 19:12
#define NVC37D_UPDATE_INHIBIT_INTERRUPTS 24:24
#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000)
#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001)
#define NVC37D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NVC37D_SET_NOTIFIER_CONTROL (0x0000020C)
#define NVC37D_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET 11:4
#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY 12:12
#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000)
#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS (0x00000218)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVC37D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK 7:0
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040)
#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A)
#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16
#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NVC37D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080)
#define NVC37D_WINDOW_SET_CONTROL_OWNER 3:0
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i))
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007)
#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT 17:16
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257 (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025 (0x00000002)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
#define NVC37D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400)
#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003)
#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3
#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001)
#define NVC37D_HEAD_SET_PROCAMP_SAT_COS 15:4
#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE 27:16
#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28
#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000)
#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001)
#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 29:29
#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001)
#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL 31:30
#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO (0x00000000)
#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO (0x00000001)
#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400)
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000)
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001)
#define NVC37D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400)
#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS 5:4
#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000)
#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001)
#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002)
#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003)
#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2
#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001)
#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE 10:8
#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE 13:12
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400)
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000)
#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT 5:4
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400)
#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0
#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16
#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400)
#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0
#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16
#define NVC37D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400)
#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH 14:0
#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16
#define NVC37D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400)
#define NVC37D_HEAD_SET_RASTER_SYNC_END_X 14:0
#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y 30:16
#define NVC37D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400)
#define NVC37D_HEAD_SET_RASTER_BLANK_END_X 14:0
#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y 30:16
#define NVC37D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400)
#define NVC37D_HEAD_SET_RASTER_BLANK_START_X 14:0
#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y 30:16
#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004)
#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004)
#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NVC37D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0
#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8
#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12
#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20
#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA 29:28
#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10 (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12 (0x00000003)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a) (0x000020A4 + (a)*0x00000400)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE 1:0
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257 (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE 5:4
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS (0x00000001)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC (0x00000002)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE 9:8
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX (0x00000000)
#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001)
#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a) (0x000020A8 + (a)*0x00000400)
#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN 31:0
#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a) (0x000020AC + (a)*0x00000400)
#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE 31:0
#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400)
#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0
#define NVC37D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400)
#define NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 4:0
#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8
#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000)
#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i))
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR(i) (0x00000060 +(i))
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR__SIZE_1 4
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR0 (0x00000060)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR1 (0x00000061)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR2 (0x00000062)
#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR3 (0x00000063)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i))
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR(i) (0x00000060 +(i))
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR__SIZE_1 4
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR0 (0x00000060)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR1 (0x00000061)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR2 (0x00000062)
#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR3 (0x00000063)
#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9
#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000)
#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001)
#endif // _clC37d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc37e.h
+394
View File
@@ -0,0 +1,394 @@
/*
* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC37e_h_
#define _clC37e_h_
// class methods
#define NVC37E_UPDATE (0x00000200)
#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
#define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C)
#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0
#define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210)
#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214)
#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218)
#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0
#define NVC37E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C)
#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NVC37E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVC37E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET 11:4
#define NVC37E_SET_SIZE (0x00000224)
#define NVC37E_SET_SIZE_WIDTH 15:0
#define NVC37E_SET_SIZE_HEIGHT 31:16
#define NVC37E_SET_STORAGE (0x00000228)
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVC37E_SET_STORAGE_MEMORY_LAYOUT 4:4
#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVC37E_SET_PARAMS (0x0000022C)
#define NVC37E_SET_PARAMS_FORMAT 7:0
#define NVC37E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVC37E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024)
#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R (0x00000037)
#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R (0x00000057)
#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444 (0x0000005A)
#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420 (0x0000005B)
#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R (0x00000077)
#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444 (0x0000007A)
#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420 (0x0000007B)
#define NVC37E_SET_PARAMS_COLOR_SPACE 9:8
#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020 (0x00000003)
#define NVC37E_SET_PARAMS_INPUT_RANGE 13:12
#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS (0x00000000)
#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED (0x00000001)
#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL (0x00000002)
#define NVC37E_SET_PARAMS_UNDERREPLICATE 16:16
#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE (0x00000000)
#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE (0x00000001)
#define NVC37E_SET_PARAMS_DE_GAMMA 21:20
#define NVC37E_SET_PARAMS_DE_GAMMA_NONE (0x00000000)
#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB (0x00000001)
#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10 (0x00000002)
#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12 (0x00000003)
#define NVC37E_SET_PARAMS_CSC 17:17
#define NVC37E_SET_PARAMS_CSC_DISABLE (0x00000000)
#define NVC37E_SET_PARAMS_CSC_ENABLE (0x00000001)
#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVC37E_SET_PARAMS_SWAP_UV 19:19
#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVC37E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVC37E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVC37E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004)
#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NVC37E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004)
#define NVC37E_SET_OFFSET_ORIGIN 31:0
#define NVC37E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVC37E_SET_POINT_IN_X 15:0
#define NVC37E_SET_POINT_IN_Y 31:16
#define NVC37E_SET_SIZE_IN (0x00000298)
#define NVC37E_SET_SIZE_IN_WIDTH 14:0
#define NVC37E_SET_SIZE_IN_HEIGHT 30:16
#define NVC37E_SET_SIZE_OUT (0x000002A4)
#define NVC37E_SET_SIZE_OUT_WIDTH 14:0
#define NVC37E_SET_SIZE_OUT_HEIGHT 30:16
#define NVC37E_SET_CONTROL_INPUT_LUT (0x000002B0)
#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE 1:0
#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257 (0x00000000)
#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 (0x00000002)
#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE 5:4
#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY (0x00000000)
#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS (0x00000001)
#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC (0x00000002)
#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE 9:8
#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX (0x00000000)
#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001)
#define NVC37E_SET_OFFSET_INPUT_LUT (0x000002B4)
#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN 31:0
#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT (0x000002B8)
#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE 31:0
#define NVC37E_SET_CSC_RED2RED (0x000002BC)
#define NVC37E_SET_CSC_RED2RED_COEFF 18:0
#define NVC37E_SET_CSC_GREEN2RED (0x000002C0)
#define NVC37E_SET_CSC_GREEN2RED_COEFF 18:0
#define NVC37E_SET_CSC_BLUE2RED (0x000002C4)
#define NVC37E_SET_CSC_BLUE2RED_COEFF 18:0
#define NVC37E_SET_CSC_CONSTANT2RED (0x000002C8)
#define NVC37E_SET_CSC_CONSTANT2RED_COEFF 18:0
#define NVC37E_SET_CSC_RED2GREEN (0x000002CC)
#define NVC37E_SET_CSC_RED2GREEN_COEFF 18:0
#define NVC37E_SET_CSC_GREEN2GREEN (0x000002D0)
#define NVC37E_SET_CSC_GREEN2GREEN_COEFF 18:0
#define NVC37E_SET_CSC_BLUE2GREEN (0x000002D4)
#define NVC37E_SET_CSC_BLUE2GREEN_COEFF 18:0
#define NVC37E_SET_CSC_CONSTANT2GREEN (0x000002D8)
#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF 18:0
#define NVC37E_SET_CSC_RED2BLUE (0x000002DC)
#define NVC37E_SET_CSC_RED2BLUE_COEFF 18:0
#define NVC37E_SET_CSC_GREEN2BLUE (0x000002E0)
#define NVC37E_SET_CSC_GREEN2BLUE_COEFF 18:0
#define NVC37E_SET_CSC_BLUE2BLUE (0x000002E4)
#define NVC37E_SET_CSC_BLUE2BLUE_COEFF 18:0
#define NVC37E_SET_CSC_CONSTANT2BLUE (0x000002E8)
#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF 18:0
#define NVC37E_SET_COMPOSITION_CONTROL (0x000002EC)
#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH 11:4
#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVC37E_SET_KEY_ALPHA (0x000002F8)
#define NVC37E_SET_KEY_ALPHA_MIN 15:0
#define NVC37E_SET_KEY_ALPHA_MAX 31:16
#define NVC37E_SET_KEY_RED_CR (0x000002FC)
#define NVC37E_SET_KEY_RED_CR_MIN 15:0
#define NVC37E_SET_KEY_RED_CR_MAX 31:16
#define NVC37E_SET_KEY_GREEN_Y (0x00000300)
#define NVC37E_SET_KEY_GREEN_Y_MIN 15:0
#define NVC37E_SET_KEY_GREEN_Y_MAX 31:16
#define NVC37E_SET_KEY_BLUE_CB (0x00000304)
#define NVC37E_SET_KEY_BLUE_CB_MIN 15:0
#define NVC37E_SET_KEY_BLUE_CB_MAX 31:16
#define NVC37E_SET_PRESENT_CONTROL (0x00000308)
#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS (0x00000370)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#endif // _clC37e_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h
+355
View File
@@ -0,0 +1,355 @@
/*
* Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC57d_h_
#define _clC57d_h_
// class methods
#define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
#define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
#define NVC57D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400)
#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003)
#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3
#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000)
#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001)
#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28
#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000)
#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F)
#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000)
#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
#define NVC57D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400)
#define NVC57D_HEAD_SET_RASTER_SIZE_WIDTH 14:0
#define NVC57D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16
#define NVC57D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400)
#define NVC57D_HEAD_SET_RASTER_SYNC_END_X 14:0
#define NVC57D_HEAD_SET_RASTER_SYNC_END_Y 30:16
#define NVC57D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400)
#define NVC57D_HEAD_SET_RASTER_BLANK_END_X 14:0
#define NVC57D_HEAD_SET_RASTER_BLANK_END_Y 30:16
#define NVC57D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400)
#define NVC57D_HEAD_SET_RASTER_BLANK_START_X 14:0
#define NVC57D_HEAD_SET_RASTER_BLANK_START_Y 30:16
#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400)
#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0
#define NVC57D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F)
#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020)
#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8
#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000)
#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i))
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056)
#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i))
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056)
#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057)
#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9
#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000)
#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001)
#define NVC57D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400)
#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0
#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1
#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE 3:2
#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVC57D_HEAD_SET_OLUT_CONTROL_SIZE 18:8
#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400)
#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0
#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400)
#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0
#define NVC57D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400)
#define NVC57D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0
#endif // _clC57d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc57e.h
+142
View File
@@ -0,0 +1,142 @@
/*
* Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC57e_h_
#define _clC57e_h_
// class methods
#define NVC57E_SET_SIZE (0x00000224)
#define NVC57E_SET_SIZE_WIDTH 15:0
#define NVC57E_SET_SIZE_HEIGHT 31:16
#define NVC57E_SET_STORAGE (0x00000228)
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVC57E_SET_STORAGE_MEMORY_LAYOUT 4:4
#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVC57E_SET_PARAMS (0x0000022C)
#define NVC57E_SET_PARAMS_FORMAT 7:0
#define NVC57E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVC57E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVC57E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVC57E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVC57E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVC57E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVC57E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVC57E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVC57E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVC57E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVC57E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024)
#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVC57E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVC57E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVC57E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVC57E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVC57E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVC57E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVC57E_SET_PARAMS_SWAP_UV 19:19
#define NVC57E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVC57E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVC57E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVC57E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVC57E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004)
#define NVC57E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NVC57E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004)
#define NVC57E_SET_OFFSET_ORIGIN 31:0
#define NVC57E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVC57E_SET_POINT_IN_X 15:0
#define NVC57E_SET_POINT_IN_Y 31:16
#define NVC57E_SET_SIZE_IN (0x00000298)
#define NVC57E_SET_SIZE_IN_WIDTH 15:0
#define NVC57E_SET_SIZE_IN_HEIGHT 31:16
#define NVC57E_SET_SIZE_OUT (0x000002A4)
#define NVC57E_SET_SIZE_OUT_WIDTH 15:0
#define NVC57E_SET_SIZE_OUT_HEIGHT 31:16
#define NVC57E_SET_PRESENT_CONTROL (0x00000308)
#define NVC57E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVC57E_SET_FMT_COEFFICIENT_C00 (0x00000400)
#define NVC57E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C01 (0x00000404)
#define NVC57E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C02 (0x00000408)
#define NVC57E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
#define NVC57E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C10 (0x00000410)
#define NVC57E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C11 (0x00000414)
#define NVC57E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C12 (0x00000418)
#define NVC57E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
#define NVC57E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C20 (0x00000420)
#define NVC57E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C21 (0x00000424)
#define NVC57E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C22 (0x00000428)
#define NVC57E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
#define NVC57E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
#define NVC57E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
#define NVC57E_SET_ILUT_CONTROL (0x00000440)
#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVC57E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVC57E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVC57E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVC57E_SET_ILUT_CONTROL_MODE 3:2
#define NVC57E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVC57E_SET_ILUT_CONTROL_SIZE 18:8
#define NVC57E_SET_CONTEXT_DMA_ILUT (0x00000444)
#define NVC57E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0
#define NVC57E_SET_OFFSET_ILUT (0x00000448)
#define NVC57E_SET_OFFSET_ILUT_ORIGIN 31:0
#endif // _clC57e_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clc97b.h
+22
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@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _clc97b_h_
#define _clc97b_h_
// dma opcode instructions
#define NVC97B_DMA
#define NVC97B_DMA_OPCODE 31:29
#define NVC97B_DMA_OPCODE_METHOD 0x00000000
#define NVC97B_DMA_OPCODE_JUMP 0x00000001
#define NVC97B_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVC97B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVC97B_DMA_METHOD_COUNT 27:18
#define NVC97B_DMA_METHOD_OFFSET 15:2
#define NVC97B_DMA_DATA 31:0
#define NVC97B_DMA_DATA_NOP 0x00000000
#define NVC97B_DMA_JUMP_OFFSET 15:2
#define NVC97B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
#endif // _clc97b_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h
+868
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@@ -0,0 +1,868 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _clca7d_h_
#define _clca7d_h_
// class methods
#define NVCA7D_UPDATE (0x00000200)
#define NVCA7D_UPDATE_SPECIAL_HANDLING 21:20
#define NVCA7D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000)
#define NVCA7D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001)
#define NVCA7D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002)
#define NVCA7D_UPDATE_SPECIAL_HANDLING_REASON 19:12
#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS 24:24
#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000)
#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001)
#define NVCA7D_UPDATE_RELEASE_ELV 0:0
#define NVCA7D_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCA7D_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCA7D_UPDATE_FORCE_FULLSCREEN 28:28
#define NVCA7D_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCA7D_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCA7D_SET_NOTIFIER_CONTROL (0x0000020C)
#define NVCA7D_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVCA7D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVCA7D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY 12:12
#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000)
#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS (0x00000218)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVCA7D_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000260)
#define NVCA7D_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000264)
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
#define NVCA7D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK 7:0
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040)
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C)
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16
#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NVCA7D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER 3:0
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i))
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007)
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F)
#define NVCA7D_WINDOW_SET_CONTROL_HIDE 8:8
#define NVCA7D_WINDOW_SET_CONTROL_HIDE_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_CONTROL_HIDE_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS 9:9
#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME 10:10
#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT 26:25
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH_BLOCKLINEAR (0x00000000)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH (0x00000001)
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_BLOCKLINEAR (0x00000002)
#define NVCA7D_WINDOW_SET_PHYSICAL(a) (0x00001014 + (a)*0x00000080)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW 31:0
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_NONE (0x00000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW0 (0x00000001)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW1 (0x00000002)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW2 (0x00000004)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW3 (0x00000008)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW4 (0x00000010)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW5 (0x00000020)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW6 (0x00000040)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW7 (0x00000080)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW8 (0x00000100)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW9 (0x00000200)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW10 (0x00000400)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW11 (0x00000800)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW12 (0x00001000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW13 (0x00002000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW14 (0x00004000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW15 (0x00008000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW16 (0x00010000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW17 (0x00020000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW18 (0x00040000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW19 (0x00080000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW20 (0x00100000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW21 (0x00200000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW22 (0x00400000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW23 (0x00800000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW24 (0x01000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW25 (0x02000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW26 (0x04000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW27 (0x08000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW28 (0x10000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW29 (0x20000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW30 (0x40000000)
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW31 (0x80000000)
#define NVCA7D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003)
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28
#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000)
#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F)
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F)
#define NVCA7D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_CONTROL_STRUCTURE 1:0
#define NVCA7D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2
#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER 3:3
#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE 11:10
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_NO_LOCK (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_FRAME_LOCK (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_RASTER_LOCK (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN 8:4
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCKOUT_WINDOW 15:12
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE 23:22
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_NO_LOCK (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_FRAME_LOCK (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_RASTER_LOCK (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN 20:16
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN 28:24
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE 30:30
#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE 31:31
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000800)
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS 5:4
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2
#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE 10:8
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005)
#define NVCA7D_HEAD_SET_DITHER_CONTROL_PHASE 13:12
#define NVCA7D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000800 + (b)*0x00000004)
#define NVCA7D_HEAD_SET_DISPLAY_ID_CODE 31:0
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED 5:5
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_ELV_START 31:17
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000800)
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16
#define NVCA7D_HEAD_SET_TILE_MASK(a) (0x00002060 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE 7:0
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_NONE (0x00000000)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE0 (0x00000001)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE1 (0x00000002)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE2 (0x00000004)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE3 (0x00000008)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE4 (0x00000010)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE5 (0x00000020)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE6 (0x00000040)
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE7 (0x00000080)
#define NVCA7D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_RASTER_SIZE_WIDTH 15:0
#define NVCA7D_HEAD_SET_RASTER_SIZE_HEIGHT 31:16
#define NVCA7D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_RASTER_SYNC_END_X 14:0
#define NVCA7D_HEAD_SET_RASTER_SYNC_END_Y 30:16
#define NVCA7D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000800)
#define NVCA7D_HEAD_SET_RASTER_BLANK_END_X 14:0
#define NVCA7D_HEAD_SET_RASTER_BLANK_END_Y 30:16
#define NVCA7D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_RASTER_BLANK_START_X 14:0
#define NVCA7D_HEAD_SET_RASTER_BLANK_START_Y 30:16
#define NVCA7D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000800)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a) (0x00002150 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI 31:0
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a) (0x00002154 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ADDRESS_LO 31:4
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET 3:2
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_IOVA (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE 0:0
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT(a) (0x00002158 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT_ADDRESS_HI 31:0
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT(a) (0x0000215C + (a)*0x00000800)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ADDRESS_LO 31:4
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET 3:2
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_IOVA (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE 0:0
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(a,b) (0x00002170 + (a)*0x00000800 + (b)*0x00000004)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR_ADDRESS_HI 31:0
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(a,b) (0x00002178 + (a)*0x00000800 + (b)*0x00000004)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ADDRESS_LO 31:4
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET 3:2
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_IOVA (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND 1:1
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_PITCH (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_BLOCKLINEAR (0x00000001)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE 0:0
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020)
#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8
#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000)
#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i))
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056)
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i))
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056)
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057)
#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9
#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0
#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE 3:2
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SIZE 18:8
#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND 4:4
#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_DISABLE (0x00000000)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_ENABLE (0x00000001)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_LEVEL 25:20
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS 5:5
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_3BITS (0x00000000)
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_4BITS (0x00000001)
#define NVCA7D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000800)
#define NVCA7D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0
#define NVCA7D_TILE_SET_TILE_SIZE(a) (0x00006000 + (a)*0x00000200)
#define NVCA7D_TILE_SET_TILE_SIZE_START 14:0
#define NVCA7D_TILE_SET_TILE_SIZE_WIDTH 30:16
#endif // _clca7d_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/class/clca7e.h
+137
View File
@@ -0,0 +1,137 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _clca7e_h_
#define _clca7e_h_
// class methods
#define NVCA7E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCA7E_SET_SIZE (0x00000224)
#define NVCA7E_SET_SIZE_WIDTH 15:0
#define NVCA7E_SET_SIZE_HEIGHT 31:16
#define NVCA7E_SET_STORAGE (0x00000228)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVCA7E_SET_PARAMS (0x0000022C)
#define NVCA7E_SET_PARAMS_FORMAT 7:0
#define NVCA7E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVCA7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVCA7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVCA7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVCA7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVCA7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVCA7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVCA7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVCA7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVCA7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVCA7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVCA7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVCA7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVCA7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVCA7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVCA7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVCA7E_SET_PARAMS_SWAP_UV 19:19
#define NVCA7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVCA7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVCA7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVCA7E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVCA7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVCA7E_SET_POINT_IN_X 15:0
#define NVCA7E_SET_POINT_IN_Y 31:16
#define NVCA7E_SET_SIZE_IN (0x00000298)
#define NVCA7E_SET_SIZE_IN_WIDTH 15:0
#define NVCA7E_SET_SIZE_IN_HEIGHT 31:16
#define NVCA7E_SET_SIZE_OUT (0x000002A4)
#define NVCA7E_SET_SIZE_OUT_WIDTH 15:0
#define NVCA7E_SET_SIZE_OUT_HEIGHT 31:16
#define NVCA7E_SET_PRESENT_CONTROL (0x00000308)
#define NVCA7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
#define NVCA7E_SET_ILUT_CONTROL (0x00000440)
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCA7E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVCA7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCA7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCA7E_SET_ILUT_CONTROL_MODE 3:2
#define NVCA7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVCA7E_SET_ILUT_CONTROL_SIZE 18:8
#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
#endif // _clca7e_h
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/drf.h
+208
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@@ -0,0 +1,208 @@
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NVHW_DRF_H__
#define __NVHW_DRF_H__
/* Helpers common to all DRF accessors. */
#define DRF_LO(drf) (0 ? drf)
#define DRF_HI(drf) (1 ? drf)
#define DRF_BITS(drf) (DRF_HI(drf) - DRF_LO(drf) + 1)
#define DRF_MASK(drf) (~0ULL >> (64 - DRF_BITS(drf)))
#define DRF_SMASK(drf) (DRF_MASK(drf) << DRF_LO(drf))
/* Helpers for DRF-MW accessors. */
#define DRF_MX_MW(drf) drf
#define DRF_MX(drf) DRF_MX_##drf
#define DRF_MW(drf) DRF_MX(drf)
#define DRF_MW_SPANS(o,drf) (DRF_LW_IDX((o),drf) != DRF_HW_IDX((o),drf))
#define DRF_MW_SIZE(o) (sizeof((o)[0]) * 8)
#define DRF_LW_IDX(o,drf) (DRF_LO(DRF_MW(drf)) / DRF_MW_SIZE(o))
#define DRF_LW_LO(o,drf) (DRF_LO(DRF_MW(drf)) % DRF_MW_SIZE(o))
#define DRF_LW_HI(o,drf) (DRF_MW_SPANS((o),drf) ? (DRF_MW_SIZE(o) - 1) : DRF_HW_HI((o),drf))
#define DRF_LW_BITS(o,drf) (DRF_LW_HI((o),drf) - DRF_LW_LO((o),drf) + 1)
#define DRF_LW_MASK(o,drf) (~0ULL >> (64 - DRF_LW_BITS((o),drf)))
#define DRF_LW_SMASK(o,drf) (DRF_LW_MASK((o),drf) << DRF_LW_LO((o),drf))
#define DRF_LW_GET(o,drf) (((o)[DRF_LW_IDX((o),drf)] >> DRF_LW_LO((o),drf)) & DRF_LW_MASK((o),drf))
#define DRF_LW_VAL(o,drf,v) (((v) & DRF_LW_MASK((o),drf)) << DRF_LW_LO((o),drf))
#define DRF_LW_CLR(o,drf) ((o)[DRF_LW_IDX((o),drf)] & ~DRF_LW_SMASK((o),drf))
#define DRF_LW_SET(o,drf,v) (DRF_LW_CLR((o),drf) | DRF_LW_VAL((o),drf,(v)))
#define DRF_HW_IDX(o,drf) (DRF_HI(DRF_MW(drf)) / DRF_MW_SIZE(o))
#define DRF_HW_LO(o,drf) 0
#define DRF_HW_HI(o,drf) (DRF_HI(DRF_MW(drf)) % DRF_MW_SIZE(o))
#define DRF_HW_BITS(o,drf) (DRF_HW_HI((o),drf) - DRF_HW_LO((o),drf) + 1)
#define DRF_HW_MASK(o,drf) (~0ULL >> (64 - DRF_HW_BITS((o),drf)))
#define DRF_HW_SMASK(o,drf) (DRF_HW_MASK((o),drf) << DRF_HW_LO((o),drf))
#define DRF_HW_GET(o,drf) ((o)[DRF_HW_IDX(o,drf)] & DRF_HW_SMASK((o),drf))
#define DRF_HW_VAL(o,drf,v) (((long long)(v) >> DRF_LW_BITS((o),drf)) & DRF_HW_SMASK((o),drf))
#define DRF_HW_CLR(o,drf) ((o)[DRF_HW_IDX((o),drf)] & ~DRF_HW_SMASK((o),drf))
#define DRF_HW_SET(o,drf,v) (DRF_HW_CLR((o),drf) | DRF_HW_VAL((o),drf,(v)))
/* DRF accessors. */
#define NVVAL_X(drf,v) (((v) & DRF_MASK(drf)) << DRF_LO(drf))
#define NVVAL_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, (v))
#define NVVAL_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), (v))
#define NVVAL_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
#define NVVAL(A...) NVVAL_(X, ##A, NVVAL_I, NVVAL_N)(X, ##A)
#define NVDEF_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)
#define NVDEF_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), d##_##r##_##f##_##v)
#define NVDEF_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
#define NVDEF(A...) NVDEF_(X, ##A, NVDEF_I, NVDEF_N)(X, ##A)
#define NVVAL_GET_X(o,drf) (((o) >> DRF_LO(drf)) & DRF_MASK(drf))
#define NVVAL_GET_N(X,o,d,r,f ) NVVAL_GET_X(o, d##_##r##_##f)
#define NVVAL_GET_I(X,o,d,r,f,i) NVVAL_GET_X(o, d##_##r##_##f(i))
#define NVVAL_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
#define NVVAL_GET(A...) NVVAL_GET_(X, ##A, NVVAL_GET_I, NVVAL_GET_N)(X, ##A)
#define NVVAL_TEST_X(o,drf,cmp,drfv) (NVVAL_GET_X((o), drf) cmp drfv)
#define NVVAL_TEST_N(X,o,d,r,f, cmp,v) NVVAL_TEST_X(o, d##_##r##_##f , cmp, (v))
#define NVVAL_TEST_I(X,o,d,r,f,i,cmp,v) NVVAL_TEST_X(o, d##_##r##_##f(i), cmp, (v))
#define NVVAL_TEST_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL
#define NVVAL_TEST(A...) NVVAL_TEST_(X, ##A, NVVAL_TEST_I, NVVAL_TEST_N)(X, ##A)
#define NVDEF_TEST_N(X,o,d,r,f, cmp,v) NVVAL_TEST_X(o, d##_##r##_##f , cmp, d##_##r##_##f##_##v)
#define NVDEF_TEST_I(X,o,d,r,f,i,cmp,v) NVVAL_TEST_X(o, d##_##r##_##f(i), cmp, d##_##r##_##f##_##v)
#define NVDEF_TEST_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL
#define NVDEF_TEST(A...) NVDEF_TEST_(X, ##A, NVDEF_TEST_I, NVDEF_TEST_N)(X, ##A)
#define NVVAL_SET_X(o,drf,v) (((o) & ~DRF_SMASK(drf)) | NVVAL_X(drf, (v)))
#define NVVAL_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, (v))
#define NVVAL_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), (v))
#define NVVAL_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define NVVAL_SET(A...) NVVAL_SET_(X, ##A, NVVAL_SET_I, NVVAL_SET_N)(X, ##A)
#define NVDEF_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v)
#define NVDEF_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v)
#define NVDEF_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define NVDEF_SET(A...) NVDEF_SET_(X, ##A, NVDEF_SET_I, NVDEF_SET_N)(X, ##A)
/* DRF-MW accessors. */
#define NVVAL_MW_GET_X(o,drf) \
((DRF_MW_SPANS((o),drf) ? \
(DRF_HW_GET((o),drf) << DRF_LW_BITS((o),drf)) : 0) | DRF_LW_GET((o),drf))
#define NVVAL_MW_GET_N(X,o,d,r,f ) NVVAL_MW_GET_X((o), d##_##r##_##f)
#define NVVAL_MW_GET_I(X,o,d,r,f,i) NVVAL_MW_GET_X((o), d##_##r##_##f(i))
#define NVVAL_MW_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
#define NVVAL_MW_GET(A...) NVVAL_MW_GET_(X, ##A, NVVAL_MW_GET_I, NVVAL_MW_GET_N)(X, ##A)
#define NVVAL_MW_SET_X(o,drf,v) do { \
(o)[DRF_LW_IDX((o),drf)] = DRF_LW_SET((o),drf,(v)); \
if (DRF_MW_SPANS((o),drf)) \
(o)[DRF_HW_IDX((o),drf)] = DRF_HW_SET((o),drf,(v)); \
} while(0)
#define NVVAL_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X((o), d##_##r##_##f, (v))
#define NVVAL_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X((o), d##_##r##_##f(i), (v))
#define NVVAL_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define NVVAL_MW_SET(A...) NVVAL_MW_SET_(X, ##A, NVVAL_MW_SET_I, NVVAL_MW_SET_N)(X, ##A)
#define NVDEF_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v)
#define NVDEF_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v)
#define NVDEF_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define NVDEF_MW_SET(A...) NVDEF_MW_SET_(X, ##A, NVDEF_MW_SET_I, NVDEF_MW_SET_N)(X, ##A)
/* Helper for reading an arbitrary object. */
#define DRF_RD_X(e,p,o,dr) e((p), (o), dr)
#define DRF_RD_N(X,e,p,o,d,r ) DRF_RD_X(e, (p), (o), d##_##r)
#define DRF_RD_I(X,e,p,o,d,r,i) DRF_RD_X(e, (p), (o), d##_##r(i))
#define DRF_RD_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define DRF_RD(A...) DRF_RD_(X, ##A, DRF_RD_I, DRF_RD_N)(X, ##A)
/* Helper for writing an arbitrary object. */
#define DRF_WR_X(e,p,o,dr,v) e((p), (o), dr, (v))
#define DRF_WR_N(X,e,p,o,d,r, v) DRF_WR_X(e, (p), (o), d##_##r , (v))
#define DRF_WR_I(X,e,p,o,d,r,i,v) DRF_WR_X(e, (p), (o), d##_##r(i), (v))
#define DRF_WR_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL
#define DRF_WR(A...) DRF_WR_(X, ##A, DRF_WR_I, DRF_WR_N)(X, ##A)
/* Helper for modifying an arbitrary object. */
#define DRF_MR_X(er,ew,ty,p,o,dr,m,v) ({ \
ty _t = DRF_RD_X(er, (p), (o), dr); \
DRF_WR_X(ew, (p), (o), dr, (_t & ~(m)) | (v)); \
_t; \
})
#define DRF_MR_N(X,er,ew,ty,p,o,d,r ,m,v) DRF_MR_X(er, ew, ty, (p), (o), d##_##r , (m), (v))
#define DRF_MR_I(X,er,ew,ty,p,o,d,r,i,m,v) DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), (m), (v))
#define DRF_MR_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,IMPL,...) IMPL
#define DRF_MR(A...) DRF_MR_(X, ##A, DRF_MR_I, DRF_MR_N)(X, ##A)
/* Helper for extracting a field value from arbitrary object. */
#define DRF_RV_X(e,p,o,dr,drf) NVVAL_GET_X(DRF_RD_X(e, (p), (o), dr), drf)
#define DRF_RV_N(X,e,p,o,d,r, f) DRF_RV_X(e, (p), (o), d##_##r , d##_##r##_##f)
#define DRF_RV_I(X,e,p,o,d,r,i,f) DRF_RV_X(e, (p), (o), d##_##r(i), d##_##r##_##f)
#define DRF_RV_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL
#define DRF_RV(A...) DRF_RV_(X, ##A, DRF_RV_I, DRF_RV_N)(X, ##A)
/* Helper for writing field value to arbitrary object (all other bits cleared). */
#define DRF_WV_N(X,e,p,o,d,r, f,v) \
DRF_WR_X(e, (p), (o), d##_##r , NVVAL_X(d##_##r##_##f, (v)))
#define DRF_WV_I(X,e,p,o,d,r,i,f,v) \
DRF_WR_X(e, (p), (o), d##_##r(i), NVVAL_X(d##_##r##_##f, (v)))
#define DRF_WV_(X,_1,_2,_3,_4,_5,_6,_7,_8,IMPL,...) IMPL
#define DRF_WV(A...) DRF_WV_(X, ##A, DRF_WV_I, DRF_WV_N)(X, ##A)
/* Helper for writing field definition to arbitrary object (all other bits cleared). */
#define DRF_WD_N(X,e,p,o,d,r, f,v) \
DRF_WR_X(e, (p), (o), d##_##r , NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v))
#define DRF_WD_I(X,e,p,o,d,r,i,f,v) \
DRF_WR_X(e, (p), (o), d##_##r(i), NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v))
#define DRF_WD_(X,_1,_2,_3,_4,_5,_6,_7,_8,IMPL,...) IMPL
#define DRF_WD(A...) DRF_WD_(X, ##A, DRF_WD_I, DRF_WD_N)(X, ##A)
/* Helper for modifying field value in arbitrary object. */
#define DRF_MV_N(X,er,ew,ty,p,o,d,r, f,v) \
NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r , DRF_SMASK(d##_##r##_##f), \
NVVAL_X(d##_##r##_##f, (v))), d##_##r##_##f)
#define DRF_MV_I(X,er,ew,ty,p,o,d,r,i,f,v) \
NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), DRF_SMASK(d##_##r##_##f), \
NVVAL_X(d##_##r##_##f, (v))), d##_##r##_##f)
#define DRF_MV_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,IMPL,...) IMPL
#define DRF_MV(A...) DRF_MV_(X, ##A, DRF_MV_I, DRF_MV_N)(X, ##A)
/* Helper for modifying field definition in arbitrary object. */
#define DRF_MD_N(X,er,ew,ty,p,o,d,r, f,v) \
NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r , DRF_SMASK(d##_##r##_##f), \
NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)), d##_##r##_##f)
#define DRF_MD_I(X,er,ew,ty,p,o,d,r,i,f,v) \
NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), DRF_SMASK(d##_##r##_##f), \
NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)), d##_##r##_##f)
#define DRF_MD_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,IMPL,...) IMPL
#define DRF_MD(A...) DRF_MD_(X, ##A, DRF_MD_I, DRF_MD_N)(X, ##A)
/* Helper for testing against field value in arbitrary object */
#define DRF_TV_N(X,e,p,o,d,r, f,cmp,v) \
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r ), d##_##r##_##f, cmp, (v))
#define DRF_TV_I(X,e,p,o,d,r,i,f,cmp,v) \
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r(i)), d##_##r##_##f, cmp, (v))
#define DRF_TV_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,IMPL,...) IMPL
#define DRF_TV(A...) DRF_TV_(X, ##A, DRF_TV_I, DRF_TV_N)(X, ##A)
/* Helper for testing against field definition in arbitrary object */
#define DRF_TD_N(X,e,p,o,d,r, f,cmp,v) \
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r ), d##_##r##_##f, cmp, d##_##r##_##f##_##v)
#define DRF_TD_I(X,e,p,o,d,r,i,f,cmp,v) \
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r(i)), d##_##r##_##f, cmp, d##_##r##_##f##_##v)
#define DRF_TD_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,IMPL,...) IMPL
#define DRF_TD(A...) DRF_TD_(X, ##A, DRF_TD_I, DRF_TD_N)(X, ##A)
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gb100/dev_hshub_base.h
+28
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@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb100_dev_hshub_base_h__
#define __gb100_dev_hshub_base_h__
#define NV_PFB_HSHUB0 0x00870fff:0x00870000
#define NV_PFB_HSHUB 0x00000FFF:0x00000000 /* RW--D */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00000E50 /* RW-4R */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00000E54 /* RW-4R */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO 0x000006C0 /* RW-4R */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI 0x000006C4 /* RW-4R */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gb100_dev_hshub_base_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h
+18
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb10b_dev_fb_h__
#define __gb10b_dev_fb_h__
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */
#endif // __gb10b_dev_fb_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h
+12
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb202_dev_ce_h__
#define __gb202_dev_ce_h__
#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
#endif // __gb202_dev_ce_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h
+17
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb202_dev_therm_h__
#define __gb202_dev_therm_h__
#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
#endif // __gb202_dev_therm_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_falcon_v4.h
+20
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_falcon_v4_h__
#define __gh100_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */
#endif // __gh100_dev_falcon_v4_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_fb.h
+15
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_fb_h_
#define __gh100_dev_fb_h_
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gh100_dev_fb_h_
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_fsp_pri.h
+28
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_fsp_pri_h__
#define __gh100_dev_fsp_pri_h__
#define NV_PFSP 0x8F3FFF:0x8F0000 /* RW--D */
#define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */
#define NV_PFSP_MSGQ_HEAD__SIZE_1 8 /* */
#define NV_PFSP_MSGQ_HEAD_VAL 31:0 /* RWIUF */
#define NV_PFSP_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */
#define NV_PFSP_MSGQ_TAIL__SIZE_1 8 /* */
#define NV_PFSP_MSGQ_TAIL_VAL 31:0 /* RWIUF */
#define NV_PFSP_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */
#define NV_PFSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PFSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PFSP_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */
#define NV_PFSP_QUEUE_TAIL__SIZE_1 8 /* */
#define NV_PFSP_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
#define NV_PFSP_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
#endif // __gh100_dev_fsp_pri_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_mmu.h
+173
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_mmu_h__
#define __gh100_dev_mmu_h__
#define NV_MMU_PTE /* ----G */
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PTE_KIND (1*32+7):(1*32+4) /* RWXVF */
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */
#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */
#define NV_MMU_VER3_PDE /* ----G */
#define NV_MMU_VER3_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_VER3_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER3_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_VER3_PDE_APERTURE_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_PCF 5:3 /* RWXVF */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_ADDRESS 51:12 /* RWXVF */
#define NV_MMU_VER3_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER3_PDE__SIZE 8
#define NV_MMU_VER3_DUAL_PDE /* ----G */
#define NV_MMU_VER3_DUAL_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG 5:3 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG 51:8 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL 69:67 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL 115:76 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */
#define NV_MMU_VER3_DUAL_PDE__SIZE 16
#define NV_MMU_VER3_PTE /* ----G */
#define NV_MMU_VER3_PTE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER3_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PCF 7:3 /* RWXVF */
#define NV_MMU_VER3_PTE_PCF_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_SPARSE 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE 0x00000004 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE 0x00000005 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE 0x00000006 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE 0x00000007 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE 0x00000008 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE 0x00000009 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE 0x0000000A /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE 0x0000000B /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE 0x0000000C /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000D /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE 0x0000000E /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000F /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD 0x00000010 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD 0x00000011 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD 0x00000012 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD 0x00000013 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD 0x00000014 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD 0x00000015 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD 0x00000016 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD 0x00000017 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD 0x00000018 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD 0x00000019 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD 0x0000001A /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD 0x0000001B /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD 0x0000001C /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001D /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD 0x0000001E /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */
#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_2 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_3 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_4 0x00000004 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_5 0x00000005 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_6 0x00000006 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_7 0x00000007 /* RW--V */
#define NV_MMU_VER3_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER3_PTE__SIZE 8
#endif // __gh100_dev_mmu_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_riscv_pri.h
+14
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_riscv_pri_h__
#define __gh100_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */
#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */
#define NV_PRISCV_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#endif // __gh100_dev_riscv_pri_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_therm.h
+17
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_therm_h__
#define __gh100_dev_therm_h__
#define NV_THERM_I2CS_SCRATCH 0x000200bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
#endif // __gh100_dev_therm_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_xtl_ep_pri.h
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_dev_xtl_ep_pri_h__
#define __gh100_dev_xtl_ep_pri_h__
#define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */
#endif // __gh100_dev_xtl_ep_pri_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/pri_nv_xal_ep.h
+13
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gh100_pri_nv_xal_ep_h__
#define __gh100_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x000010
#define NV_XAL_EP_BAR0_WINDOW_BASE 21:0
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40
#endif // __gh100_pri_nv_xal_ep_h__
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/chan.h
+76
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/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __NVIF_CHAN_H__
#define __NVIF_CHAN_H__
#include "push.h"
struct nvif_chan {
const struct nvif_chan_func {
struct {
u32 (*read_get)(struct nvif_chan *);
} push;
struct {
u32 (*read_get)(struct nvif_chan *);
void (*push)(struct nvif_chan *, bool main, u64 addr, u32 size,
bool no_prefetch);
void (*kick)(struct nvif_chan *);
int (*post)(struct nvif_chan *, u32 gpptr, u32 pbptr);
u32 post_size;
} gpfifo;
struct {
int (*release)(struct nvif_chan *, u64 addr, u32 data);
} sem;
} *func;
struct {
struct nvif_map map;
} userd;
struct {
struct nvif_map map;
u32 cur;
u32 max;
int free;
} gpfifo;
struct {
struct nvif_map map;
u64 addr;
} sema;
struct nvif_push push;
struct nvif_user *usermode;
u32 doorbell_token;
};
int nvif_chan_dma_wait(struct nvif_chan *, u32 push_nr);
void nvif_chan_gpfifo_ctor(const struct nvif_chan_func *, void *userd, void *gpfifo, u32 gpfifo_size,
void *push, u64 push_addr, u32 push_size, struct nvif_chan *);
int nvif_chan_gpfifo_wait(struct nvif_chan *, u32 gpfifo_nr, u32 push_nr);
void nvif_chan_gpfifo_push(struct nvif_chan *, u64 addr, u32 size, bool no_prefetch);
int nvif_chan_gpfifo_post(struct nvif_chan *);
void nvif_chan506f_gpfifo_push(struct nvif_chan *, bool main, u64 addr, u32 size, bool no_prefetch);
void nvif_chan506f_gpfifo_kick(struct nvif_chan *);
int nvif_chan906f_ctor_(const struct nvif_chan_func *, void *userd, void *gpfifo, u32 gpfifo_size,
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
struct nvif_chan *);
u32 nvif_chan906f_read_get(struct nvif_chan *);
u32 nvif_chan906f_gpfifo_read_get(struct nvif_chan *);
int nvif_chan906f_gpfifo_post(struct nvif_chan *, u32 gpptr, u32 pbptr);
int nvif_chan506f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size,
void *push, u64 push_addr, u32 push_size);
int nvif_chan906f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size,
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr);
int nvif_chanc36f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size,
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
struct nvif_user *usermode, u32 doorbell_token);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/cl0002.h
+67
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL0002_H__
#define __NVIF_CL0002_H__
struct nv_dma_v0 {
__u8 version;
#define NV_DMA_V0_TARGET_VM 0x00
#define NV_DMA_V0_TARGET_VRAM 0x01
#define NV_DMA_V0_TARGET_PCI 0x02
#define NV_DMA_V0_TARGET_PCI_US 0x03
#define NV_DMA_V0_TARGET_AGP 0x04
__u8 target;
#define NV_DMA_V0_ACCESS_VM 0x00
#define NV_DMA_V0_ACCESS_RD 0x01
#define NV_DMA_V0_ACCESS_WR 0x02
#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
__u8 access;
__u8 pad03[5];
__u64 start;
__u64 limit;
/* ... chipset-specific class data */
};
struct nv50_dma_v0 {
__u8 version;
#define NV50_DMA_V0_PRIV_VM 0x00
#define NV50_DMA_V0_PRIV_US 0x01
#define NV50_DMA_V0_PRIV__S 0x02
__u8 priv;
#define NV50_DMA_V0_PART_VM 0x00
#define NV50_DMA_V0_PART_256 0x01
#define NV50_DMA_V0_PART_1KB 0x02
__u8 part;
#define NV50_DMA_V0_COMP_NONE 0x00
#define NV50_DMA_V0_COMP_1 0x01
#define NV50_DMA_V0_COMP_2 0x02
#define NV50_DMA_V0_COMP_VM 0x03
__u8 comp;
#define NV50_DMA_V0_KIND_PITCH 0x00
#define NV50_DMA_V0_KIND_VM 0x7f
__u8 kind;
__u8 pad05[3];
};
struct gf100_dma_v0 {
__u8 version;
#define GF100_DMA_V0_PRIV_VM 0x00
#define GF100_DMA_V0_PRIV_US 0x01
#define GF100_DMA_V0_PRIV__S 0x02
__u8 priv;
#define GF100_DMA_V0_KIND_PITCH 0x00
#define GF100_DMA_V0_KIND_VM 0xff
__u8 kind;
__u8 pad03[5];
};
struct gf119_dma_v0 {
__u8 version;
#define GF119_DMA_V0_PAGE_LP 0x00
#define GF119_DMA_V0_PAGE_SP 0x01
__u8 page;
#define GF119_DMA_V0_KIND_PITCH 0x00
#define GF119_DMA_V0_KIND_VM 0xff
__u8 kind;
__u8 pad03[5];
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/cl0046.h
+6
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL0046_H__
#define __NVIF_CL0046_H__
#define NV04_DISP_NTFY_CONN 0x01
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
+93
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL0080_H__
#define __NVIF_CL0080_H__
#define NV_DEVICE_V0_INFO 0x00
#define NV_DEVICE_V0_TIME 0x01
struct nv_device_info_v0 {
__u8 version;
#define NV_DEVICE_INFO_V0_IGP 0x00
#define NV_DEVICE_INFO_V0_PCI 0x01
#define NV_DEVICE_INFO_V0_AGP 0x02
#define NV_DEVICE_INFO_V0_PCIE 0x03
#define NV_DEVICE_INFO_V0_SOC 0x04
__u8 platform;
__u16 chipset; /* from NV_PMC_BOOT_0 */
__u8 revision; /* from NV_PMC_BOOT_0 */
#define NV_DEVICE_INFO_V0_TNT 0x01
#define NV_DEVICE_INFO_V0_CELSIUS 0x02
#define NV_DEVICE_INFO_V0_KELVIN 0x03
#define NV_DEVICE_INFO_V0_RANKINE 0x04
#define NV_DEVICE_INFO_V0_CURIE 0x05
#define NV_DEVICE_INFO_V0_TESLA 0x06
#define NV_DEVICE_INFO_V0_FERMI 0x07
#define NV_DEVICE_INFO_V0_KEPLER 0x08
#define NV_DEVICE_INFO_V0_MAXWELL 0x09
#define NV_DEVICE_INFO_V0_PASCAL 0x0a
#define NV_DEVICE_INFO_V0_VOLTA 0x0b
#define NV_DEVICE_INFO_V0_TURING 0x0c
#define NV_DEVICE_INFO_V0_AMPERE 0x0d
#define NV_DEVICE_INFO_V0_ADA 0x0e
#define NV_DEVICE_INFO_V0_HOPPER 0x0f
#define NV_DEVICE_INFO_V0_BLACKWELL 0x10
__u8 family;
__u8 pad06[2];
__u64 ram_size;
__u64 ram_user;
char chip[16];
char name[64];
};
struct nv_device_info_v1 {
__u8 version;
__u8 count;
__u8 pad02[6];
struct nv_device_info_v1_data {
__u64 mthd; /* NV_DEVICE_INFO_* (see below). */
__u64 data;
} data[];
};
struct nv_device_time_v0 {
__u8 version;
__u8 pad01[7];
__u64 time;
};
#define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32)
#define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32))
#define NV_DEVICE_HOST(n) ((n) | (0x00000001ULL << 32))
/* This will be returned in the mthd field for unsupported queries. */
#define NV_DEVICE_INFO_INVALID ~0ULL
/* Returns the number of available runlists. */
#define NV_DEVICE_HOST_RUNLISTS NV_DEVICE_HOST(0x00000000)
/* Returns the number of available channels (0 if per-runlist). */
#define NV_DEVICE_HOST_CHANNELS NV_DEVICE_HOST(0x00000001)
/* Returns a mask of available engine types on runlist(data). */
#define NV_DEVICE_HOST_RUNLIST_ENGINES NV_DEVICE_HOST(0x00000100)
#define NV_DEVICE_HOST_RUNLIST_ENGINES_SW 0x00000001
#define NV_DEVICE_HOST_RUNLIST_ENGINES_GR 0x00000002
#define NV_DEVICE_HOST_RUNLIST_ENGINES_MPEG 0x00000004
#define NV_DEVICE_HOST_RUNLIST_ENGINES_ME 0x00000008
#define NV_DEVICE_HOST_RUNLIST_ENGINES_CIPHER 0x00000010
#define NV_DEVICE_HOST_RUNLIST_ENGINES_BSP 0x00000020
#define NV_DEVICE_HOST_RUNLIST_ENGINES_VP 0x00000040
#define NV_DEVICE_HOST_RUNLIST_ENGINES_CE 0x00000080
#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC 0x00000100
#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD 0x00000200
#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC 0x00000400
#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP 0x00000800
#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSENC 0x00001000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_VIC 0x00002000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_OFA 0x00040000
/* Returns the number of available channels on runlist(data). */
#define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101)
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/cl9097.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL9097_H__
#define __NVIF_CL9097_H__
#define FERMI_A_ZBC_COLOR 0x00
#define FERMI_A_ZBC_DEPTH 0x01
struct fermi_a_zbc_color_v0 {
__u8 version;
#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
__u8 format;
__u8 index;
__u8 pad03[5];
__u32 ds[4];
__u32 l2[4];
};
struct fermi_a_zbc_depth_v0 {
__u8 version;
#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
__u8 format;
__u8 index;
__u8 pad03[5];
__u32 ds;
__u32 l2;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/class.h
+295
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLASS_H__
#define __NVIF_CLASS_H__
/* these class numbers are made up by us, and not nvidia-assigned */
#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
#define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
#define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
#define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
#define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
#define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a
#define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b
#define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b
#define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b
#define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
#define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
#define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
#define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
#define NVIF_CLASS_EVENT /* if000e.h */ 0x8000000e
#define NVIF_CLASS_DISP /* if0010.h */ 0x80000010
#define NVIF_CLASS_CONN /* if0011.h */ 0x80000011
#define NVIF_CLASS_OUTP /* if0012.h */ 0x80000012
#define NVIF_CLASS_HEAD /* if0013.h */ 0x80000013
#define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014
#define NVIF_CLASS_CHAN /* if0020.h */ 0x80000020
#define NVIF_CLASS_CGRP /* if0021.h */ 0x80000021
/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_NULL_CLASS 0x00000030
#define NV_DEVICE /* cl0080.h */ 0x00000080
#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
#define NV50_TWOD 0x0000502d
#define FERMI_TWOD_A 0x0000902d
#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
#define BLACKWELL_INLINE_TO_MEMORY_A 0x0000cd40
#define NV04_DISP /* cl0046.h */ 0x00000046
#define VOLTA_USERMODE_A 0x0000c361
#define TURING_USERMODE_A 0x0000c461
#define AMPERE_USERMODE_A 0x0000c561
#define HOPPER_USERMODE_A 0x0000c661
#define BLACKWELL_USERMODE_A 0x0000c761
#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
#define NV03_CHANNEL_DMA /* if0020.h */ 0x0000006b
#define NV10_CHANNEL_DMA /* if0020.h */ 0x0000006e
#define NV17_CHANNEL_DMA /* if0020.h */ 0x0000176e
#define NV40_CHANNEL_DMA /* if0020.h */ 0x0000406e
#define KEPLER_CHANNEL_GROUP_A /* if0021.h */ 0x0000a06c
#define NV50_CHANNEL_GPFIFO /* if0020.h */ 0x0000506f
#define G82_CHANNEL_GPFIFO /* if0020.h */ 0x0000826f
#define FERMI_CHANNEL_GPFIFO /* if0020.h */ 0x0000906f
#define KEPLER_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000a06f
#define KEPLER_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000a16f
#define MAXWELL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000b06f
#define PASCAL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c06f
#define VOLTA_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c36f
#define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f
#define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f
#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
#define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f
#define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f
#define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f
#define NV50_DISP /* if0010.h */ 0x00005070
#define G82_DISP /* if0010.h */ 0x00008270
#define GT200_DISP /* if0010.h */ 0x00008370
#define GT214_DISP /* if0010.h */ 0x00008570
#define GT206_DISP /* if0010.h */ 0x00008870
#define GF110_DISP /* if0010.h */ 0x00009070
#define GK104_DISP /* if0010.h */ 0x00009170
#define GK110_DISP /* if0010.h */ 0x00009270
#define GM107_DISP /* if0010.h */ 0x00009470
#define GM200_DISP /* if0010.h */ 0x00009570
#define GP100_DISP /* if0010.h */ 0x00009770
#define GP102_DISP /* if0010.h */ 0x00009870
#define GV100_DISP /* if0010.h */ 0x0000c370
#define TU102_DISP /* if0010.h */ 0x0000c570
#define GA102_DISP /* if0010.h */ 0x0000c670
#define AD102_DISP /* if0010.h */ 0x0000c770
#define GB202_DISP 0x0000ca70
#define GV100_DISP_CAPS 0x0000c373
#define GB202_DISP_CAPS 0x0000ca73
#define NV31_MPEG 0x00003174
#define G82_MPEG 0x00008274
#define NV74_VP2 0x00007476
#define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a
#define G82_DISP_CURSOR /* if0014.h */ 0x0000827a
#define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a
#define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a
#define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a
#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
#define GB202_DISP_CURSOR 0x0000ca7a
#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
#define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b
#define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b
#define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
#define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b
#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
#define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c
#define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c
#define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c
#define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c
#define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c
#define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d
#define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d
#define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d
#define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d
#define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d
#define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d
#define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d
#define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d
#define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d
#define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d
#define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d
#define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d
#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d
#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
#define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
#define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e
#define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e
#define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e
#define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e
#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
#define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e
#define NV50_TESLA 0x00005097
#define G82_TESLA 0x00008297
#define GT200_TESLA 0x00008397
#define GT214_TESLA 0x00008597
#define GT21A_TESLA 0x00008697
#define FERMI_A /* cl9097.h */ 0x00009097
#define FERMI_B /* cl9097.h */ 0x00009197
#define FERMI_C /* cl9097.h */ 0x00009297
#define KEPLER_A /* cl9097.h */ 0x0000a097
#define KEPLER_B /* cl9097.h */ 0x0000a197
#define KEPLER_C /* cl9097.h */ 0x0000a297
#define MAXWELL_A /* cl9097.h */ 0x0000b097
#define MAXWELL_B /* cl9097.h */ 0x0000b197
#define PASCAL_A /* cl9097.h */ 0x0000c097
#define PASCAL_B /* cl9097.h */ 0x0000c197
#define VOLTA_A /* cl9097.h */ 0x0000c397
#define TURING_A /* cl9097.h */ 0x0000c597
#define AMPERE_A 0x0000c697
#define AMPERE_B /* cl9097.h */ 0x0000c797
#define ADA_A /* cl9097.h */ 0x0000c997
#define HOPPER_A 0x0000cb97
#define BLACKWELL_A 0x0000cd97
#define BLACKWELL_B 0x0000ce97
#define NV74_BSP 0x000074b0
#define NVB8B0_VIDEO_DECODER 0x0000b8b0
#define NVC4B0_VIDEO_DECODER 0x0000c4b0
#define NVC6B0_VIDEO_DECODER 0x0000c6b0
#define NVC7B0_VIDEO_DECODER 0x0000c7b0
#define NVC9B0_VIDEO_DECODER 0x0000c9b0
#define NVCDB0_VIDEO_DECODER 0x0000cdb0
#define NVCFB0_VIDEO_DECODER 0x0000cfb0
#define GT212_MSVLD 0x000085b1
#define IGT21A_MSVLD 0x000086b1
#define G98_MSVLD 0x000088b1
#define GF100_MSVLD 0x000090b1
#define GK104_MSVLD 0x000095b1
#define GT212_MSPDEC 0x000085b2
#define G98_MSPDEC 0x000088b2
#define GF100_MSPDEC 0x000090b2
#define GK104_MSPDEC 0x000095b2
#define GT212_MSPPP 0x000085b3
#define G98_MSPPP 0x000088b3
#define GF100_MSPPP 0x000090b3
#define G98_SEC 0x000088b4
#define GT212_DMA 0x000085b5
#define FERMI_DMA 0x000090b5
#define KEPLER_DMA_COPY_A 0x0000a0b5
#define MAXWELL_DMA_COPY_A 0x0000b0b5
#define PASCAL_DMA_COPY_A 0x0000c0b5
#define PASCAL_DMA_COPY_B 0x0000c1b5
#define VOLTA_DMA_COPY_A 0x0000c3b5
#define TURING_DMA_COPY_A 0x0000c5b5
#define AMPERE_DMA_COPY_A 0x0000c6b5
#define AMPERE_DMA_COPY_B 0x0000c7b5
#define HOPPER_DMA_COPY_A 0x0000c8b5
#define BLACKWELL_DMA_COPY_A 0x0000c9b5
#define BLACKWELL_DMA_COPY_B 0x0000cab5
#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
#define NVCFB7_VIDEO_ENCODER 0x0000cfb7
#define FERMI_DECOMPRESS 0x000090b8
#define NV50_COMPUTE 0x000050c0
#define GT214_COMPUTE 0x000085c0
#define FERMI_COMPUTE_A 0x000090c0
#define FERMI_COMPUTE_B 0x000091c0
#define KEPLER_COMPUTE_A 0x0000a0c0
#define KEPLER_COMPUTE_B 0x0000a1c0
#define MAXWELL_COMPUTE_A 0x0000b0c0
#define MAXWELL_COMPUTE_B 0x0000b1c0
#define PASCAL_COMPUTE_A 0x0000c0c0
#define PASCAL_COMPUTE_B 0x0000c1c0
#define VOLTA_COMPUTE_A 0x0000c3c0
#define TURING_COMPUTE_A 0x0000c5c0
#define AMPERE_COMPUTE_A 0x0000c6c0
#define AMPERE_COMPUTE_B 0x0000c7c0
#define ADA_COMPUTE_A 0x0000c9c0
#define HOPPER_COMPUTE_A 0x0000cbc0
#define BLACKWELL_COMPUTE_A 0x0000cdc0
#define BLACKWELL_COMPUTE_B 0x0000cec0
#define NV74_CIPHER 0x000074c1
#define NVB8D1_VIDEO_NVJPG 0x0000b8d1
#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
#define NVCDD1_VIDEO_NVJPG 0x0000cdd1
#define NVCFD1_VIDEO_NVJPG 0x0000cfd1
#define NVB8FA_VIDEO_OFA 0x0000b8fa
#define NVC6FA_VIDEO_OFA 0x0000c6fa
#define NVC7FA_VIDEO_OFA 0x0000c7fa
#define NVC9FA_VIDEO_OFA 0x0000c9fa
#define NVCDFA_VIDEO_OFA 0x0000cdfa
#define NVCFFA_VIDEO_OFA 0x0000cffa
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/clb069.h
+15
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#ifndef __NVIF_CLB069_H__
#define __NVIF_CLB069_H__
struct nvif_clb069_v0 {
__u8 version;
__u8 pad01[3];
__u32 entries;
__u32 get;
__u32 put;
};
union nvif_clb069_event_args {
struct nvif_clb069_event_vn {
} vn;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/client.h
+18
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLIENT_H__
#define __NVIF_CLIENT_H__
#include <nvif/object.h>
struct nvif_client {
struct nvif_object object;
const struct nvif_driver *driver;
};
int nvif_client_ctor(struct nvif_client *parent, const char *name, struct nvif_client *);
void nvif_client_dtor(struct nvif_client *);
int nvif_client_suspend(struct nvif_client *, bool);
int nvif_client_resume(struct nvif_client *);
/*XXX*/
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/conn.h
+38
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CONN_H__
#define __NVIF_CONN_H__
#include <nvif/object.h>
#include <nvif/event.h>
struct nvif_disp;
struct nvif_conn {
struct nvif_object object;
u32 id;
struct {
enum {
NVIF_CONN_VGA,
NVIF_CONN_TV,
NVIF_CONN_DVI_I,
NVIF_CONN_DVI_D,
NVIF_CONN_LVDS,
NVIF_CONN_LVDS_SPWG,
NVIF_CONN_HDMI,
NVIF_CONN_DP,
NVIF_CONN_EDP,
} type;
} info;
};
int nvif_conn_ctor(struct nvif_disp *, const char *name, int id, struct nvif_conn *);
void nvif_conn_dtor(struct nvif_conn *);
static inline int
nvif_conn_id(struct nvif_conn *conn)
{
return conn->object.handle;
}
int nvif_conn_event_ctor(struct nvif_conn *, const char *name, nvif_event_func, u8 types,
struct nvif_event *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/device.h
+25
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_DEVICE_H__
#define __NVIF_DEVICE_H__
#include <nvif/object.h>
#include <nvif/cl0080.h>
#include <nvif/user.h>
struct nvif_device {
struct nvif_object object;
struct nv_device_info_v0 info;
struct nvif_fifo_runlist {
u64 engines;
} *runlist;
int runlists;
struct nvif_user user;
};
int nvif_device_ctor(struct nvif_client *, const char *name, struct nvif_device *);
void nvif_device_dtor(struct nvif_device *);
int nvif_device_map(struct nvif_device *);
u64 nvif_device_time(struct nvif_device *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/disp.h
+16
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#ifndef __NVIF_DISP_H__
#define __NVIF_DISP_H__
#include <nvif/object.h>
struct nvif_device;
struct nvif_disp {
struct nvif_object object;
unsigned long conn_mask;
unsigned long outp_mask;
unsigned long head_mask;
};
int nvif_disp_ctor(struct nvif_device *, const char *name, s32 oclass,
struct nvif_disp *);
void nvif_disp_dtor(struct nvif_disp *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/driver.h
+22
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_DRIVER_H__
#define __NVIF_DRIVER_H__
#include <nvif/os.h>
struct nvif_client;
struct nvif_driver {
const char *name;
int (*init)(const char *name, u64 device, const char *cfg,
const char *dbg, void **priv);
int (*suspend)(void *priv, bool runtime);
int (*resume)(void *priv);
int (*ioctl)(void *priv, void *data, u32 size, void **hack);
void __iomem *(*map)(void *priv, u64 handle, u32 size);
void (*unmap)(void *priv, void __iomem *ptr, u32 size);
};
int nvif_driver_init(const char *drv, const char *cfg, const char *dbg,
const char *name, u64 device, struct nvif_client *);
extern const struct nvif_driver nvif_driver_nvkm;
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/event.h
+36
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_EVENT_H__
#define __NVIF_EVENT_H__
#include <nvif/object.h>
#include <nvif/if000e.h>
struct nvif_event;
#define NVIF_EVENT_KEEP 0
#define NVIF_EVENT_DROP 1
typedef int (*nvif_event_func)(struct nvif_event *, void *repv, u32 repc);
struct nvif_event {
struct nvif_object object;
nvif_event_func func;
};
static inline bool
nvif_event_constructed(struct nvif_event *event)
{
return nvif_object_constructed(&event->object);
}
int nvif_event_ctor_(struct nvif_object *, const char *, u32, nvif_event_func, bool,
struct nvif_event_v0 *, u32, bool, struct nvif_event *);
static inline int
nvif_event_ctor(struct nvif_object *parent, const char *name, u32 handle, nvif_event_func func,
bool wait, struct nvif_event_v0 *args, u32 argc, struct nvif_event *event)
{
return nvif_event_ctor_(parent, name, handle, func, wait, args, argc, true, event);
}
void nvif_event_dtor(struct nvif_event *);
int nvif_event_allow(struct nvif_event *);
int nvif_event_block(struct nvif_event *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/fifo.h
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#ifndef __NVIF_FIFO_H__
#define __NVIF_FIFO_H__
#include <nvif/device.h>
/* Returns mask of runlists that support a NV_DEVICE_INFO_RUNLIST_ENGINES_* type. */
u64 nvif_fifo_runlist(struct nvif_device *, u64 engine);
/* CE-supporting runlists (excluding GRCE, if others exist). */
static inline u64
nvif_fifo_runlist_ce(struct nvif_device *device)
{
u64 runmgr = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
u64 runmce = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_CE);
if (runmce && !(runmce &= ~runmgr))
runmce = runmgr;
return runmce;
}
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/head.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_HEAD_H__
#define __NVIF_HEAD_H__
#include <nvif/object.h>
#include <nvif/event.h>
struct nvif_disp;
struct nvif_head {
struct nvif_object object;
};
int nvif_head_ctor(struct nvif_disp *, const char *name, int id, struct nvif_head *);
void nvif_head_dtor(struct nvif_head *);
static inline int
nvif_head_id(struct nvif_head *head)
{
return head->object.handle;
}
int nvif_head_vblank_event_ctor(struct nvif_head *, const char *name, nvif_event_func, bool wait,
struct nvif_event *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0000.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0000_H__
#define __NVIF_IF0000_H__
struct nvif_client_v0 {
__u8 version;
__u8 pad01[7];
char name[32];
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0001.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0001_H__
#define __NVIF_IF0001_H__
#define NVIF_CONTROL_PSTATE_INFO 0x00
#define NVIF_CONTROL_PSTATE_ATTR 0x01
#define NVIF_CONTROL_PSTATE_USER 0x02
struct nvif_control_pstate_info_v0 {
__u8 version;
__u8 count; /* out: number of power states */
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
__s8 ustate_ac; /* out: target pstate index */
__s8 ustate_dc; /* out: target pstate index */
__s8 pwrsrc; /* out: current power source */
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
__s8 pstate; /* out: current pstate index */
__u8 pad06[2];
};
struct nvif_control_pstate_attr_v0 {
__u8 version;
#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
__s8 state; /* in: index of pstate to query
* out: pstate identifier
*/
__u8 index; /* in: index of attribute to query
* out: index of next attribute, or 0 if no more
*/
__u8 pad03[5];
__u32 min;
__u32 max;
char name[32];
char unit[16];
};
struct nvif_control_pstate_user_v0 {
__u8 version;
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
__s8 ustate; /* in: pstate identifier */
__s8 pwrsrc; /* in: target power source */
__u8 pad03[5];
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0004.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0004_H__
#define __NVIF_IF0004_H__
union nv04_nvsw_event_args {
struct nv04_nvsw_event_vn {
} vn;
};
#define NV04_NVSW_GET_REF 0x00
struct nv04_nvsw_get_ref_v0 {
__u8 version;
__u8 pad01[3];
__u32 ref;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0005.h
+5
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0005_H__
#define __NVIF_IF0005_H__
#define NV10_NVSW_NTFY_UEVENT 0x00
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0008.h
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#ifndef __NVIF_IF0008_H__
#define __NVIF_IF0008_H__
struct nvif_mmu_v0 {
__u8 version;
__u8 dmabits;
__u8 heap_nr;
__u8 type_nr;
__u16 kind_nr;
};
#define NVIF_MMU_V0_HEAP 0x00
#define NVIF_MMU_V0_TYPE 0x01
#define NVIF_MMU_V0_KIND 0x02
struct nvif_mmu_heap_v0 {
__u8 version;
__u8 index;
__u8 pad02[6];
__u64 size;
};
struct nvif_mmu_type_v0 {
__u8 version;
__u8 index;
__u8 heap;
__u8 vram;
__u8 host;
__u8 comp;
__u8 disp;
__u8 kind;
__u8 mappable;
__u8 coherent;
__u8 uncached;
};
struct nvif_mmu_kind_v0 {
__u8 version;
__u8 kind_inv;
__u16 count;
__u8 data[];
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if000a.h
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#ifndef __NVIF_IF000A_H__
#define __NVIF_IF000A_H__
struct nvif_mem_v0 {
__u8 version;
__u8 type;
__u8 page;
__u8 pad03[5];
__u64 size;
__u64 addr;
__u8 data[];
};
struct nvif_mem_ram_vn {
};
struct nvif_mem_ram_v0 {
__u8 version;
__u8 pad01[7];
dma_addr_t *dma;
struct scatterlist *sgl;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if000b.h
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#ifndef __NVIF_IF000B_H__
#define __NVIF_IF000B_H__
#include "if000a.h"
struct nv04_mem_vn {
/* nvkm_mem_vX ... */
};
struct nv04_mem_map_vn {
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if000c.h
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#ifndef __NVIF_IF000C_H__
#define __NVIF_IF000C_H__
struct nvif_vmm_v0 {
__u8 version;
__u8 page_nr;
#define NVIF_VMM_V0_TYPE_UNMANAGED 0x00
#define NVIF_VMM_V0_TYPE_MANAGED 0x01
#define NVIF_VMM_V0_TYPE_RAW 0x02
__u8 type;
__u8 pad03[5];
__u64 addr;
__u64 size;
__u8 data[];
};
#define NVIF_VMM_V0_PAGE 0x00
#define NVIF_VMM_V0_GET 0x01
#define NVIF_VMM_V0_PUT 0x02
#define NVIF_VMM_V0_MAP 0x03
#define NVIF_VMM_V0_UNMAP 0x04
#define NVIF_VMM_V0_PFNMAP 0x05
#define NVIF_VMM_V0_PFNCLR 0x06
#define NVIF_VMM_V0_RAW 0x07
#define NVIF_VMM_V0_MTHD(i) ((i) + 0x80)
struct nvif_vmm_page_v0 {
__u8 version;
__u8 index;
__u8 shift;
__u8 sparse;
__u8 vram;
__u8 host;
__u8 comp;
__u8 pad07[1];
};
struct nvif_vmm_get_v0 {
__u8 version;
#define NVIF_VMM_GET_V0_ADDR 0x00
#define NVIF_VMM_GET_V0_PTES 0x01
#define NVIF_VMM_GET_V0_LAZY 0x02
__u8 type;
__u8 sparse;
__u8 page;
__u8 align;
__u8 pad05[3];
__u64 size;
__u64 addr;
};
struct nvif_vmm_put_v0 {
__u8 version;
__u8 pad01[7];
__u64 addr;
};
struct nvif_vmm_map_v0 {
__u8 version;
__u8 pad01[7];
__u64 addr;
__u64 size;
__u64 memory;
__u64 offset;
__u8 data[];
};
struct nvif_vmm_unmap_v0 {
__u8 version;
__u8 pad01[7];
__u64 addr;
};
struct nvif_vmm_raw_v0 {
__u8 version;
#define NVIF_VMM_RAW_V0_GET 0x0
#define NVIF_VMM_RAW_V0_PUT 0x1
#define NVIF_VMM_RAW_V0_MAP 0x2
#define NVIF_VMM_RAW_V0_UNMAP 0x3
#define NVIF_VMM_RAW_V0_SPARSE 0x4
__u8 op;
__u8 sparse;
__u8 ref;
__u8 shift;
__u32 argc;
__u8 pad01[7];
__u64 addr;
__u64 size;
__u64 offset;
__u64 memory;
__u64 argv;
};
struct nvif_vmm_pfnmap_v0 {
__u8 version;
__u8 page;
__u8 pad02[6];
__u64 addr;
__u64 size;
#define NVIF_VMM_PFNMAP_V0_ADDR 0xfffffffffffff000ULL
#define NVIF_VMM_PFNMAP_V0_ADDR_SHIFT 12
#define NVIF_VMM_PFNMAP_V0_APER 0x00000000000000f0ULL
#define NVIF_VMM_PFNMAP_V0_HOST 0x0000000000000000ULL
#define NVIF_VMM_PFNMAP_V0_VRAM 0x0000000000000010ULL
#define NVIF_VMM_PFNMAP_V0_A 0x0000000000000004ULL
#define NVIF_VMM_PFNMAP_V0_W 0x0000000000000002ULL
#define NVIF_VMM_PFNMAP_V0_V 0x0000000000000001ULL
#define NVIF_VMM_PFNMAP_V0_NONE 0x0000000000000000ULL
__u64 phys[];
};
struct nvif_vmm_pfnclr_v0 {
__u8 version;
__u8 pad01[7];
__u64 addr;
__u64 size;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if000d.h
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#ifndef __NVIF_IF000D_H__
#define __NVIF_IF000D_H__
#include "if000c.h"
struct nv04_vmm_vn {
/* nvif_vmm_vX ... */
};
struct nv04_vmm_map_vn {
/* nvif_vmm_map_vX ... */
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if000e.h
+26
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF000E_H__
#define __NVIF_IF000E_H__
union nvif_event_args {
struct nvif_event_v0 {
__u8 version;
__u8 wait;
__u8 pad02[6];
__u8 data[];
} v0;
};
#define NVIF_EVENT_V0_ALLOW 0x00
#define NVIF_EVENT_V0_BLOCK 0x01
union nvif_event_allow_args {
struct nvif_event_allow_vn {
} vn;
};
union nvif_event_block_args {
struct nvif_event_block_vn {
} vn;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0010.h
+14
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@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0010_H__
#define __NVIF_IF0010_H__
union nvif_disp_args {
struct nvif_disp_v0 {
__u8 version;
__u8 pad01[3];
__u32 conn_mask;
__u32 outp_mask;
__u32 head_mask;
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0011.h
+33
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0011_H__
#define __NVIF_IF0011_H__
union nvif_conn_args {
struct nvif_conn_v0 {
__u8 version;
__u8 id; /* DCB connector table index. */
__u8 pad02[6];
#define NVIF_CONN_V0_VGA 0x00
#define NVIF_CONN_V0_TV 0x01
#define NVIF_CONN_V0_DVI_I 0x02
#define NVIF_CONN_V0_DVI_D 0x03
#define NVIF_CONN_V0_LVDS 0x04
#define NVIF_CONN_V0_LVDS_SPWG 0x05
#define NVIF_CONN_V0_HDMI 0x06
#define NVIF_CONN_V0_DP 0x07
#define NVIF_CONN_V0_EDP 0x08
__u8 type;
} v0;
};
union nvif_conn_event_args {
struct nvif_conn_event_v0 {
__u8 version;
#define NVIF_CONN_EVENT_V0_PLUG 0x01
#define NVIF_CONN_EVENT_V0_UNPLUG 0x02
#define NVIF_CONN_EVENT_V0_IRQ 0x04
__u8 types;
__u8 pad02[6];
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0012.h
+294
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0012_H__
#define __NVIF_IF0012_H__
#include <drm/display/drm_dp.h>
union nvif_outp_args {
struct nvif_outp_v0 {
__u8 version;
__u8 id; /* DCB device index. */
#define NVIF_OUTP_V0_TYPE_DAC 0x00
#define NVIF_OUTP_V0_TYPE_SOR 0x01
#define NVIF_OUTP_V0_TYPE_PIOR 0x02
__u8 type;
#define NVIF_OUTP_V0_PROTO_RGB_CRT 0x00
#define NVIF_OUTP_V0_PROTO_TMDS 0x01
#define NVIF_OUTP_V0_PROTO_LVDS 0x02
#define NVIF_OUTP_V0_PROTO_DP 0x03
__u8 proto;
__u8 heads;
__u8 ddc;
__u8 conn;
union {
struct {
__u32 freq_max;
} rgb_crt;
struct {
__u8 dual;
} tmds;
struct {
__u8 acpi_edid;
} lvds;
struct {
__u8 aux;
__u8 mst;
__u8 increased_wm;
__u8 link_nr;
__u32 link_bw;
} dp;
};
} v0;
};
#define NVIF_OUTP_V0_DETECT 0x00
#define NVIF_OUTP_V0_EDID_GET 0x01
#define NVIF_OUTP_V0_INHERIT 0x10
#define NVIF_OUTP_V0_ACQUIRE 0x11
#define NVIF_OUTP_V0_RELEASE 0x12
#define NVIF_OUTP_V0_LOAD_DETECT 0x20
#define NVIF_OUTP_V0_BL_GET 0x30
#define NVIF_OUTP_V0_BL_SET 0x31
#define NVIF_OUTP_V0_LVDS 0x40
#define NVIF_OUTP_V0_HDMI 0x50
#define NVIF_OUTP_V0_INFOFRAME 0x60
#define NVIF_OUTP_V0_HDA_ELD 0x61
#define NVIF_OUTP_V0_DP_AUX_PWR 0x70
#define NVIF_OUTP_V0_DP_AUX_XFER 0x71
#define NVIF_OUTP_V0_DP_RATES 0x72
#define NVIF_OUTP_V0_DP_TRAIN 0x73
#define NVIF_OUTP_V0_DP_DRIVE 0x74
#define NVIF_OUTP_V0_DP_SST 0x75
#define NVIF_OUTP_V0_DP_MST_ID_GET 0x76
#define NVIF_OUTP_V0_DP_MST_ID_PUT 0x77
#define NVIF_OUTP_V0_DP_MST_VCPI 0x78
union nvif_outp_detect_args {
struct nvif_outp_detect_v0 {
__u8 version;
#define NVIF_OUTP_DETECT_V0_NOT_PRESENT 0x00
#define NVIF_OUTP_DETECT_V0_PRESENT 0x01
#define NVIF_OUTP_DETECT_V0_UNKNOWN 0x02
__u8 status;
} v0;
};
union nvif_outp_edid_get_args {
struct nvif_outp_edid_get_v0 {
__u8 version;
__u8 pad01;
__u16 size;
__u8 data[2048];
} v0;
};
union nvif_outp_load_detect_args {
struct nvif_outp_load_detect_v0 {
__u8 version;
__u8 load;
__u8 pad02[2];
__u32 data; /*TODO: move vbios loadval parsing into nvkm */
} v0;
};
union nvif_outp_acquire_args {
struct nvif_outp_acquire_v0 {
__u8 version;
#define NVIF_OUTP_ACQUIRE_V0_DAC 0x00
#define NVIF_OUTP_ACQUIRE_V0_SOR 0x01
#define NVIF_OUTP_ACQUIRE_V0_PIOR 0x02
__u8 type;
__u8 or;
__u8 link;
__u8 pad04[4];
union {
struct {
__u8 hda;
} sor;
};
} v0;
};
union nvif_outp_inherit_args {
struct nvif_outp_inherit_v0 {
__u8 version;
#define NVIF_OUTP_INHERIT_V0_RGB_CRT 0x00
#define NVIF_OUTP_INHERIT_V0_TV 0x01
#define NVIF_OUTP_INHERIT_V0_TMDS 0x02
#define NVIF_OUTP_INHERIT_V0_LVDS 0x03
#define NVIF_OUTP_INHERIT_V0_DP 0x04
// In/out. Input is one of the above values, output is the actual hw protocol
__u8 proto;
__u8 or;
__u8 link;
__u8 head;
union {
struct {
// TODO: Figure out padding, and whether we even want this field
__u8 hda;
} tmds;
};
} v0;
};
union nvif_outp_release_args {
struct nvif_outp_release_vn {
} vn;
};
union nvif_outp_bl_get_args {
struct nvif_outp_bl_get_v0 {
__u8 version;
__u8 level;
} v0;
};
union nvif_outp_bl_set_args {
struct nvif_outp_bl_set_v0 {
__u8 version;
__u8 level;
} v0;
};
union nvif_outp_lvds_args {
struct nvif_outp_lvds_v0 {
__u8 version;
__u8 dual;
__u8 bpc8;
} v0;
};
union nvif_outp_hdmi_args {
struct nvif_outp_hdmi_v0 {
__u8 version;
__u8 head;
__u8 enable;
__u8 max_ac_packet;
__u8 rekey;
__u8 scdc;
__u8 scdc_scrambling;
__u8 scdc_low_rates;
__u32 khz;
} v0;
};
union nvif_outp_infoframe_args {
struct nvif_outp_infoframe_v0 {
__u8 version;
#define NVIF_OUTP_INFOFRAME_V0_AVI 0
#define NVIF_OUTP_INFOFRAME_V0_VSI 1
__u8 type;
__u8 head;
__u8 pad03[5];
__u8 data[];
} v0;
};
union nvif_outp_hda_eld_args {
struct nvif_outp_hda_eld_v0 {
__u8 version;
__u8 head;
__u8 pad02[6];
__u8 data[];
} v0;
};
union nvif_outp_dp_aux_pwr_args {
struct nvif_outp_dp_aux_pwr_v0 {
__u8 version;
__u8 state;
__u8 pad02[6];
} v0;
};
union nvif_outp_dp_aux_xfer_args {
struct nvif_outp_dp_aux_xfer_v0 {
__u8 version;
__u8 pad01;
__u8 type;
__u8 size;
__u32 addr;
__u8 data[16];
} v0;
};
union nvif_outp_dp_rates_args {
struct nvif_outp_dp_rates_v0 {
__u8 version;
__u8 pad01[6];
__u8 rates;
struct {
__s8 dpcd;
__u32 rate;
} rate[8];
} v0;
};
union nvif_outp_dp_train_args {
struct nvif_outp_dp_train_v0 {
__u8 version;
__u8 retrain;
__u8 mst;
__u8 lttprs;
__u8 post_lt_adj;
__u8 link_nr;
__u32 link_bw;
__u8 dpcd[DP_RECEIVER_CAP_SIZE];
} v0;
};
union nvif_outp_dp_drive_args {
struct nvif_outp_dp_drive_v0 {
__u8 version;
__u8 pad01[2];
__u8 lanes;
__u8 pe[4];
__u8 vs[4];
} v0;
};
union nvif_outp_dp_sst_args {
struct nvif_outp_dp_sst_v0 {
__u8 version;
__u8 head;
__u8 pad02[2];
__u32 watermark;
__u32 hblanksym;
__u32 vblanksym;
} v0;
};
union nvif_outp_dp_mst_id_put_args {
struct nvif_outp_dp_mst_id_put_v0 {
__u8 version;
__u8 pad01[3];
__u32 id;
} v0;
};
union nvif_outp_dp_mst_id_get_args {
struct nvif_outp_dp_mst_id_get_v0 {
__u8 version;
__u8 pad01[3];
__u32 id;
} v0;
};
union nvif_outp_dp_mst_vcpi_args {
struct nvif_outp_dp_mst_vcpi_v0 {
__u8 version;
__u8 head;
__u8 start_slot;
__u8 num_slots;
__u16 pbn;
__u16 aligned_pbn;
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0013.h
+35
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0013_H__
#define __NVIF_IF0013_H__
union nvif_head_args {
struct nvif_head_v0 {
__u8 version;
__u8 id;
__u8 pad02[6];
} v0;
};
union nvif_head_event_args {
struct nvif_head_event_vn {
} vn;
};
#define NVIF_HEAD_V0_SCANOUTPOS 0x00
union nvif_head_scanoutpos_args {
struct nvif_head_scanoutpos_v0 {
__u8 version;
__u8 pad01[7];
__s64 time[2];
__u16 vblanks;
__u16 vblanke;
__u16 vtotal;
__u16 vline;
__u16 hblanks;
__u16 hblanke;
__u16 htotal;
__u16 hline;
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0014.h
+13
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0014_H__
#define __NVIF_IF0014_H__
union nvif_disp_chan_args {
struct nvif_disp_chan_v0 {
__u8 version;
__u8 id;
__u8 pad02[6];
__u64 pushbuf;
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0020.h
+45
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0020_H__
#define __NVIF_IF0020_H__
union nvif_chan_args {
struct nvif_chan_v0 {
__u8 version;
__u8 namelen;
__u8 runlist;
__u8 runq;
__u8 priv;
__u8 pad05;
__u16 devm;
__u64 vmm;
__u64 ctxdma;
__u64 offset;
__u64 length;
__u64 huserd;
__u64 ouserd;
__u32 token;
__u16 chid;
__u8 pad3e;
#define NVIF_CHAN_V0_INST_APER_VRAM 0
#define NVIF_CHAN_V0_INST_APER_HOST 1
#define NVIF_CHAN_V0_INST_APER_NCOH 2
#define NVIF_CHAN_V0_INST_APER_INST 0xff
__u8 aper;
__u64 inst;
__u8 name[];
} v0;
};
union nvif_chan_event_args {
struct nvif_chan_event_v0 {
__u8 version;
#define NVIF_CHAN_EVENT_V0_NON_STALL_INTR 0x00
#define NVIF_CHAN_EVENT_V0_KILLED 0x01
__u8 type;
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if0021.h
+16
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@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0021_H__
#define __NVIF_IF0021_H__
union nvif_cgrp_args {
struct nvif_cgrp_v0 {
__u8 version;
__u8 namelen;
__u8 runlist;
__u8 pad03[3];
__u16 cgid;
__u64 vmm;
__u8 name[];
} v0;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if500b.h
+25
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@@ -0,0 +1,25 @@
#ifndef __NVIF_IF500B_H__
#define __NVIF_IF500B_H__
#include "if000a.h"
struct nv50_mem_vn {
/* nvif_mem_vX ... */
};
struct nv50_mem_v0 {
/* nvif_mem_vX ... */
__u8 version;
__u8 bankswz;
__u8 contig;
};
struct nv50_mem_map_vn {
};
struct nv50_mem_map_v0 {
__u8 version;
__u8 ro;
__u8 kind;
__u8 comp;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if500d.h
+21
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@@ -0,0 +1,21 @@
#ifndef __NVIF_IF500D_H__
#define __NVIF_IF500D_H__
#include "if000c.h"
struct nv50_vmm_vn {
/* nvif_vmm_vX ... */
};
struct nv50_vmm_map_vn {
/* nvif_vmm_map_vX ... */
};
struct nv50_vmm_map_v0 {
/* nvif_vmm_map_vX ... */
__u8 version;
__u8 ro;
__u8 priv;
__u8 kind;
__u8 comp;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if900b.h
+23
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@@ -0,0 +1,23 @@
#ifndef __NVIF_IF900B_H__
#define __NVIF_IF900B_H__
#include "if000a.h"
struct gf100_mem_vn {
/* nvif_mem_vX ... */
};
struct gf100_mem_v0 {
/* nvif_mem_vX ... */
__u8 version;
__u8 contig;
};
struct gf100_mem_map_vn {
};
struct gf100_mem_map_v0 {
__u8 version;
__u8 ro;
__u8 kind;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/if900d.h
+21
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@@ -0,0 +1,21 @@
#ifndef __NVIF_IF900D_H__
#define __NVIF_IF900D_H__
#include "if000c.h"
struct gf100_vmm_vn {
/* nvif_vmm_vX ... */
};
struct gf100_vmm_map_vn {
/* nvif_vmm_map_vX ... */
};
struct gf100_vmm_map_v0 {
/* nvif_vmm_map_vX ... */
__u8 version;
__u8 vol;
__u8 ro;
__u8 priv;
__u8 kind;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/ifb00d.h
+27
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@@ -0,0 +1,27 @@
#ifndef __NVIF_IFB00D_H__
#define __NVIF_IFB00D_H__
#include "if000c.h"
struct gm200_vmm_vn {
/* nvif_vmm_vX ... */
};
struct gm200_vmm_v0 {
/* nvif_vmm_vX ... */
__u8 version;
__u8 bigpage;
};
struct gm200_vmm_map_vn {
/* nvif_vmm_map_vX ... */
};
struct gm200_vmm_map_v0 {
/* nvif_vmm_map_vX ... */
__u8 version;
__u8 vol;
__u8 ro;
__u8 priv;
__u8 kind;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/ifc00d.h
+42
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@@ -0,0 +1,42 @@
#ifndef __NVIF_IFC00D_H__
#define __NVIF_IFC00D_H__
#include "if000c.h"
struct gp100_vmm_vn {
/* nvif_vmm_vX ... */
};
struct gp100_vmm_v0 {
/* nvif_vmm_vX ... */
__u8 version;
__u8 fault_replay;
};
struct gp100_vmm_map_vn {
/* nvif_vmm_map_vX ... */
};
struct gp100_vmm_map_v0 {
/* nvif_vmm_map_vX ... */
__u8 version;
__u8 vol;
__u8 ro;
__u8 priv;
__u8 kind;
};
#define GP100_VMM_VN_FAULT_REPLAY NVIF_VMM_V0_MTHD(0x00)
#define GP100_VMM_VN_FAULT_CANCEL NVIF_VMM_V0_MTHD(0x01)
struct gp100_vmm_fault_replay_vn {
};
struct gp100_vmm_fault_cancel_v0 {
__u8 version;
__u8 hub;
__u8 gpc;
__u8 client;
__u8 pad04[4];
__u64 inst;
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/ioctl.h
+85
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/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IOCTL_H__
#define __NVIF_IOCTL_H__
struct nvif_ioctl_v0 {
/* New members MUST be added within the struct_group() macro below. */
struct_group_tagged(nvif_ioctl_v0_hdr, __hdr,
__u8 version;
#define NVIF_IOCTL_V0_SCLASS 0x01
#define NVIF_IOCTL_V0_NEW 0x02
#define NVIF_IOCTL_V0_DEL 0x03
#define NVIF_IOCTL_V0_MTHD 0x04
#define NVIF_IOCTL_V0_MAP 0x07
#define NVIF_IOCTL_V0_UNMAP 0x08
__u8 type;
__u8 pad02[4];
#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
#define NVIF_IOCTL_V0_OWNER_ANY 0xff
__u8 owner;
#define NVIF_IOCTL_V0_ROUTE_NVIF 0x00
#define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff
__u8 route;
__u64 token;
__u64 object;
);
__u8 data[]; /* ioctl data (below) */
};
static_assert(offsetof(struct nvif_ioctl_v0, data) == sizeof(struct nvif_ioctl_v0_hdr),
"struct member likely outside of struct_group()");
struct nvif_ioctl_sclass_v0 {
/* nvif_ioctl ... */
__u8 version;
__u8 count;
__u8 pad02[6];
struct nvif_ioctl_sclass_oclass_v0 {
__s32 oclass;
__s16 minver;
__s16 maxver;
} oclass[];
};
struct nvif_ioctl_new_v0 {
/* nvif_ioctl ... */
__u8 version;
__u8 pad01[6];
__u8 route;
__u64 token;
__u64 object;
__u32 handle;
__s32 oclass;
__u8 data[]; /* class data (class.h) */
};
struct nvif_ioctl_del {
};
struct nvif_ioctl_mthd_v0 {
/* New members MUST be added within the struct_group() macro below. */
struct_group_tagged(nvif_ioctl_mthd_v0_hdr, __hdr,
/* nvif_ioctl ... */
__u8 version;
__u8 method;
__u8 pad02[6];
);
__u8 data[]; /* method data (class.h) */
};
static_assert(offsetof(struct nvif_ioctl_mthd_v0, data) == sizeof(struct nvif_ioctl_mthd_v0_hdr),
"struct member likely outside of struct_group()");
struct nvif_ioctl_map_v0 {
/* nvif_ioctl ... */
__u8 version;
#define NVIF_IOCTL_MAP_V0_IO 0x00
#define NVIF_IOCTL_MAP_V0_VA 0x01
__u8 type;
__u8 pad02[6];
__u64 handle;
__u64 length;
__u8 data[];
};
struct nvif_ioctl_unmap {
};
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/log.h
+51
View File
@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: MIT */
/* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. */
#ifndef __NVIF_LOG_H__
#define __NVIF_LOG_H__
#ifdef CONFIG_DEBUG_FS
/**
* nvif_log - structure for tracking logging buffers
* @entry: an entry in a list of struct nvif_logs
* @shutdown: pointer to function to call to clean up
*
* Structure used to track logging buffers so that they can be cleaned up
* when the module exits.
*
* The @shutdown function is called when the module exits. It should free all
* backing resources, such as logging buffers.
*/
struct nvif_log {
struct list_head entry;
void (*shutdown)(struct nvif_log *log);
};
/**
* nvif_logs - linked list of nvif_log objects
*/
struct nvif_logs {
struct list_head head;
};
#define NVIF_LOGS_DECLARE(logs) \
struct nvif_logs logs = { LIST_HEAD_INIT(logs.head) }
static inline void nvif_log_shutdown(struct nvif_logs *logs)
{
if (!list_empty(&logs->head)) {
struct nvif_log *log, *n;
list_for_each_entry_safe(log, n, &logs->head, entry) {
/* shutdown() should also delete the log entry */
log->shutdown(log);
}
}
}
extern struct nvif_logs gsp_logs;
#endif
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/mem.h
+22
View File
@@ -0,0 +1,22 @@
#ifndef __NVIF_MEM_H__
#define __NVIF_MEM_H__
#include "mmu.h"
struct nvif_mem {
struct nvif_object object;
u8 type;
u8 page;
u64 addr;
u64 size;
};
int nvif_mem_ctor_type(struct nvif_mmu *mmu, const char *name, s32 oclass,
int type, u8 page, u64 size, void *argv, u32 argc,
struct nvif_mem *);
int nvif_mem_ctor(struct nvif_mmu *mmu, const char *name, s32 oclass, u8 type,
u8 page, u64 size, void *argv, u32 argc, struct nvif_mem *);
void nvif_mem_dtor(struct nvif_mem *);
int nvif_mem_ctor_map(struct nvif_mmu *, const char *name, u8 type, u64 size,
struct nvif_mem *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvif/mmu.h
+58
View File
@@ -0,0 +1,58 @@
#ifndef __NVIF_MMU_H__
#define __NVIF_MMU_H__
#include <nvif/object.h>
struct nvif_mmu {
struct nvif_object object;
u8 dmabits;
u8 heap_nr;
u8 type_nr;
u8 kind_inv;
u16 kind_nr;
s32 mem;
struct {
u64 size;
} *heap;
struct {
#define NVIF_MEM_VRAM 0x01
#define NVIF_MEM_HOST 0x02
#define NVIF_MEM_COMP 0x04
#define NVIF_MEM_DISP 0x08
#define NVIF_MEM_KIND 0x10
#define NVIF_MEM_MAPPABLE 0x20
#define NVIF_MEM_COHERENT 0x40
#define NVIF_MEM_UNCACHED 0x80
u8 type;
u8 heap;
} *type;
u8 *kind;
};
int nvif_mmu_ctor(struct nvif_object *, const char *name, s32 oclass,
struct nvif_mmu *);
void nvif_mmu_dtor(struct nvif_mmu *);
static inline bool
nvif_mmu_kind_valid(struct nvif_mmu *mmu, u8 kind)
{
if (kind) {
if (kind >= mmu->kind_nr || mmu->kind[kind] == mmu->kind_inv)
return false;
}
return true;
}
static inline int
nvif_mmu_type(struct nvif_mmu *mmu, u8 mask)
{
int i;
for (i = 0; i < mmu->type_nr; i++) {
if ((mmu->type[i].type & mask) == mask)
return i;
}
return -EINVAL;
}
#endif

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