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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_M0203_H__
#define __NVBIOS_M0203_H__
struct nvbios_M0203T {
#define M0203T_TYPE_RAMCFG 0x00
u8 type;
u16 pointer;
};
u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_M0203T *);
struct nvbios_M0203E {
#define M0203E_TYPE_DDR2 0x0
#define M0203E_TYPE_DDR3 0x1
#define M0203E_TYPE_GDDR3 0x2
#define M0203E_TYPE_GDDR5 0x3
#define M0203E_TYPE_HBM2 0x6
#define M0203E_TYPE_GDDR5X 0x8
#define M0203E_TYPE_GDDR6 0x9
#define M0203E_TYPE_SKIP 0xf
u8 type;
u8 strap;
u8 group;
};
u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0203E *);
u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr,
struct nvbios_M0203E *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_M0205_H__
#define __NVBIOS_M0205_H__
struct nvbios_M0205T {
u16 freq;
};
u32 nvbios_M0205Te(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u32 nvbios_M0205Tp(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz,
struct nvbios_M0205T *);
struct nvbios_M0205E {
u8 type;
};
u32 nvbios_M0205Ee(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_M0205Ep(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0205E *);
struct nvbios_M0205S {
u8 data;
};
u32 nvbios_M0205Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr);
u32 nvbios_M0205Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0205S *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_M0209_H__
#define __NVBIOS_M0209_H__
u32 nvbios_M0209Te(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
struct nvbios_M0209E {
u8 v00_40;
u8 bits;
u8 modulo;
u8 v02_40;
u8 v02_07;
u8 v03;
};
u32 nvbios_M0209Ee(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_M0209Ep(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_M0209E *);
struct nvbios_M0209S {
u32 data[0x200];
};
u32 nvbios_M0209Se(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr);
u32 nvbios_M0209Sp(struct nvkm_bios *, int ent, int idx, u8 *ver, u8 *hdr,
struct nvbios_M0209S *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_P0260_H__
#define __NVBIOS_P0260_H__
u32 nvbios_P0260Te(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
struct nvbios_P0260E {
u32 data;
};
u32 nvbios_P0260Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
u32 nvbios_P0260Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_P0260E *);
struct nvbios_P0260X {
u32 data;
};
u32 nvbios_P0260Xe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
u32 nvbios_P0260Xp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_P0260X *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_BIT_H__
#define __NVBIOS_BIT_H__
struct bit_entry {
u8 id;
u8 version;
u16 length;
u16 offset;
};
int bit_entry(struct nvkm_bios *, u8 id, struct bit_entry *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_BMP_H__
#define __NVBIOS_BMP_H__
static inline u16
bmp_version(struct nvkm_bios *bios)
{
if (bios->bmp_offset) {
return nvbios_rd08(bios, bios->bmp_offset + 5) << 8 |
nvbios_rd08(bios, bios->bmp_offset + 6);
}
return 0x0000;
}
static inline u16
bmp_mem_init_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nvbios_rd16(bios, bios->bmp_offset + 24);
return 0x0000;
}
static inline u16
bmp_sdr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nvbios_rd16(bios, bios->bmp_offset + 26);
return 0x0000;
}
static inline u16
bmp_ddr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nvbios_rd16(bios, bios->bmp_offset + 28);
return 0x0000;
}
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_BOOST_H__
#define __NVBIOS_BOOST_H__
u32 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *);
struct nvbios_boostE {
u8 pstate;
u32 min;
u32 max;
};
u32 nvbios_boostEe(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *);
u32 nvbios_boostEp(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *,
struct nvbios_boostE *);
u32 nvbios_boostEm(struct nvkm_bios *, u8, u8 *, u8 *, u8 *, u8 *,
struct nvbios_boostE *);
struct nvbios_boostS {
u8 domain;
u8 percent;
u32 min;
u32 max;
};
u32 nvbios_boostSe(struct nvkm_bios *, int, u32, u8 *, u8 *, u8, u8);
u32 nvbios_boostSp(struct nvkm_bios *, int, u32, u8 *, u8 *, u8, u8,
struct nvbios_boostS *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_CONN_H__
#define __NVBIOS_CONN_H__
/*
* An enumerator representing all of the possible VBIOS connector types defined
* by Nvidia at
* https://nvidia.github.io/open-gpu-doc/DCB/DCB-4.x-Specification.html.
*
* [1] Nvidia's documentation actually claims DCB_CONNECTOR_HDMI_0 is a "3-Pin
* DIN Stereo Connector". This seems very likely to be a documentation typo
* or some sort of funny historical baggage, because we've treated this
* connector type as HDMI for years without issue.
* TODO: Check with Nvidia what's actually happening here.
*/
enum dcb_connector_type {
/* Analog outputs */
DCB_CONNECTOR_VGA = 0x00, // VGA 15-pin connector
DCB_CONNECTOR_DVI_A = 0x01, // DVI-A
DCB_CONNECTOR_POD_VGA = 0x02, // Pod - VGA 15-pin connector
DCB_CONNECTOR_TV_0 = 0x10, // TV - Composite Out
DCB_CONNECTOR_TV_1 = 0x11, // TV - S-Video Out
DCB_CONNECTOR_TV_2 = 0x12, // TV - S-Video Breakout - Composite
DCB_CONNECTOR_TV_3 = 0x13, // HDTV Component - YPrPb
DCB_CONNECTOR_TV_SCART = 0x14, // TV - SCART Connector
DCB_CONNECTOR_TV_SCART_D = 0x16, // TV - Composite SCART over D-connector
DCB_CONNECTOR_TV_DTERM = 0x17, // HDTV - D-connector (EIAJ4120)
DCB_CONNECTOR_POD_TV_3 = 0x18, // Pod - HDTV - YPrPb
DCB_CONNECTOR_POD_TV_1 = 0x19, // Pod - S-Video
DCB_CONNECTOR_POD_TV_0 = 0x1a, // Pod - Composite
/* DVI digital outputs */
DCB_CONNECTOR_DVI_I_TV_1 = 0x20, // DVI-I-TV-S-Video
DCB_CONNECTOR_DVI_I_TV_0 = 0x21, // DVI-I-TV-Composite
DCB_CONNECTOR_DVI_I_TV_2 = 0x22, // DVI-I-TV-S-Video Breakout-Composite
DCB_CONNECTOR_DVI_I = 0x30, // DVI-I
DCB_CONNECTOR_DVI_D = 0x31, // DVI-D
DCB_CONNECTOR_DVI_ADC = 0x32, // Apple Display Connector (ADC)
DCB_CONNECTOR_DMS59_0 = 0x38, // LFH-DVI-I-1
DCB_CONNECTOR_DMS59_1 = 0x39, // LFH-DVI-I-2
DCB_CONNECTOR_BNC = 0x3c, // BNC Connector [for SDI?]
/* LVDS / TMDS digital outputs */
DCB_CONNECTOR_LVDS = 0x40, // LVDS-SPWG-Attached [is this name correct?]
DCB_CONNECTOR_LVDS_SPWG = 0x41, // LVDS-OEM-Attached (non-removable)
DCB_CONNECTOR_LVDS_REM = 0x42, // LVDS-SPWG-Detached [following naming above]
DCB_CONNECTOR_LVDS_SPWG_REM = 0x43, // LVDS-OEM-Detached (removable)
DCB_CONNECTOR_TMDS = 0x45, // TMDS-OEM-Attached (non-removable)
/* DP digital outputs */
DCB_CONNECTOR_DP = 0x46, // DisplayPort External Connector
DCB_CONNECTOR_eDP = 0x47, // DisplayPort Internal Connector
DCB_CONNECTOR_mDP = 0x48, // DisplayPort (Mini) External Connector
/* Dock outputs (not used) */
DCB_CONNECTOR_DOCK_VGA_0 = 0x50, // VGA 15-pin if not docked
DCB_CONNECTOR_DOCK_VGA_1 = 0x51, // VGA 15-pin if docked
DCB_CONNECTOR_DOCK_DVI_I_0 = 0x52, // DVI-I if not docked
DCB_CONNECTOR_DOCK_DVI_I_1 = 0x53, // DVI-I if docked
DCB_CONNECTOR_DOCK_DVI_D_0 = 0x54, // DVI-D if not docked
DCB_CONNECTOR_DOCK_DVI_D_1 = 0x55, // DVI-D if docked
DCB_CONNECTOR_DOCK_DP_0 = 0x56, // DisplayPort if not docked
DCB_CONNECTOR_DOCK_DP_1 = 0x57, // DisplayPort if docked
DCB_CONNECTOR_DOCK_mDP_0 = 0x58, // DisplayPort (Mini) if not docked
DCB_CONNECTOR_DOCK_mDP_1 = 0x59, // DisplayPort (Mini) if docked
/* HDMI? digital outputs */
DCB_CONNECTOR_HDMI_0 = 0x60, // HDMI? See [1] in top-level enum comment above
DCB_CONNECTOR_HDMI_1 = 0x61, // HDMI-A connector
DCB_CONNECTOR_SPDIF = 0x62, // Audio S/PDIF connector
DCB_CONNECTOR_HDMI_C = 0x63, // HDMI-C (Mini) connector
/* Misc. digital outputs */
DCB_CONNECTOR_DMS59_DP0 = 0x64, // LFH-DP-1
DCB_CONNECTOR_DMS59_DP1 = 0x65, // LFH-DP-2
DCB_CONNECTOR_WFD = 0x70, // Virtual connector for Wifi Display (WFD)
DCB_CONNECTOR_USB_C = 0x71, // [DP over USB-C; not present in docs]
DCB_CONNECTOR_NONE = 0xff // Skip Entry
};
struct nvbios_connT {
};
u32 nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_connT *info);
struct nvbios_connE {
u8 type;
u8 location;
u8 hpd;
u8 dp;
u8 di;
u8 sr;
u8 lcdid;
};
u32 nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr);
u32 nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr,
struct nvbios_connE *info);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_CSTEP_H__
#define __NVBIOS_CSTEP_H__
u32 nvbios_cstepTe(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
struct nvbios_cstepE {
u8 pstate;
u8 index;
};
u32 nvbios_cstepEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
u32 nvbios_cstepEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepE *);
u32 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr,
struct nvbios_cstepE *);
struct nvbios_cstepX {
u32 freq;
u8 unkn[2];
u8 voltage;
};
u32 nvbios_cstepXe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
u32 nvbios_cstepXp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepX *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_DCB_H__
#define __NVBIOS_DCB_H__
enum dcb_output_type {
DCB_OUTPUT_ANALOG = 0x0,
DCB_OUTPUT_TV = 0x1,
DCB_OUTPUT_TMDS = 0x2,
DCB_OUTPUT_LVDS = 0x3,
DCB_OUTPUT_DP = 0x6,
DCB_OUTPUT_WFD = 0x8,
DCB_OUTPUT_EOL = 0xe,
DCB_OUTPUT_UNUSED = 0xf,
DCB_OUTPUT_ANY = -1,
};
struct dcb_output {
int index; /* may not be raw dcb index if merging has happened */
u16 hasht;
u16 hashm;
enum dcb_output_type type;
uint8_t i2c_index;
uint8_t heads;
uint8_t connector;
uint8_t bus;
uint8_t location;
uint8_t or;
uint8_t link;
bool duallink_possible;
uint8_t extdev;
union {
struct sor_conf {
int link;
} sorconf;
struct {
int maxfreq;
} crtconf;
struct {
struct sor_conf sor;
bool use_straps_for_mode;
bool use_acpi_for_edid;
bool use_power_scripts;
} lvdsconf;
struct {
bool has_component_output;
} tvconf;
struct {
struct sor_conf sor;
int link_nr;
int link_bw;
} dpconf;
struct {
struct sor_conf sor;
int slave_addr;
} tmdsconf;
};
bool i2c_upper_default;
int id;
};
u16 dcb_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len);
u16 dcb_outp(struct nvkm_bios *, u8 idx, u8 *ver, u8 *len);
u16 dcb_outp_parse(struct nvkm_bios *, u8 idx, u8 *, u8 *,
struct dcb_output *);
u16 dcb_outp_match(struct nvkm_bios *, u16 type, u16 mask, u8 *, u8 *,
struct dcb_output *);
int dcb_outp_foreach(struct nvkm_bios *, void *data, int (*exec)
(struct nvkm_bios *, void *, int index, u16 entry));
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_DISP_H__
#define __NVBIOS_DISP_H__
u16 nvbios_disp_table(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub);
struct nvbios_disp {
u16 data;
};
u16 nvbios_disp_entry(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub);
u16 nvbios_disp_parse(struct nvkm_bios *, u8 idx, u8 *ver, u8 *hdr, u8 *sub,
struct nvbios_disp *);
struct nvbios_outp {
u16 type;
u16 mask;
u16 script[3];
};
u16 nvbios_outp_entry(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_outp_parse(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *);
u16 nvbios_outp_match(struct nvkm_bios *, u16 type, u16 mask,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *);
struct nvbios_ocfg {
u8 proto;
u8 flags;
u16 clkcmp[2];
};
u16 nvbios_ocfg_entry(struct nvkm_bios *, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_ocfg_parse(struct nvkm_bios *, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *);
u16 nvbios_ocfg_match(struct nvkm_bios *, u16 outp, u8 proto, u8 flags,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ocfg *);
u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_DP_H__
#define __NVBIOS_DP_H__
u16
nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
struct nvbios_dpout {
u16 type;
u16 mask;
u8 flags;
u32 script[5];
u32 lnkcmp;
};
u16 nvbios_dpout_parse(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *);
u16 nvbios_dpout_match(struct nvkm_bios *, u16 type, u16 mask,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *);
struct nvbios_dpcfg {
u8 pc;
u8 dc;
u8 pe;
u8 tx_pu;
};
u16
nvbios_dpcfg_parse(struct nvkm_bios *, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *);
u16
nvbios_dpcfg_match(struct nvkm_bios *, u16 outp, u8 pc, u8 vs, u8 pe,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_dpcfg *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_EXTDEV_H__
#define __NVBIOS_EXTDEV_H__
enum nvbios_extdev_type {
NVBIOS_EXTDEV_LM89 = 0x02,
NVBIOS_EXTDEV_VT1103M = 0x40,
NVBIOS_EXTDEV_PX3540 = 0x41,
NVBIOS_EXTDEV_VT1105M = 0x42, /* or close enough... */
NVBIOS_EXTDEV_INA219 = 0x4c,
NVBIOS_EXTDEV_INA209 = 0x4d,
NVBIOS_EXTDEV_INA3221 = 0x4e,
NVBIOS_EXTDEV_ADT7473 = 0x70, /* can also be a LM64 */
NVBIOS_EXTDEV_HDCP_EEPROM = 0x90,
NVBIOS_EXTDEV_NONE = 0xff,
};
struct nvbios_extdev_func {
u8 type;
u8 addr;
u8 bus;
};
int
nvbios_extdev_parse(struct nvkm_bios *, int, struct nvbios_extdev_func *);
int
nvbios_extdev_find(struct nvkm_bios *, enum nvbios_extdev_type,
struct nvbios_extdev_func *);
bool nvbios_extdev_skip_probe(struct nvkm_bios *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_FAN_H__
#define __NVBIOS_FAN_H__
#include <subdev/bios/therm.h>
u32 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_GPIO_H__
#define __NVBIOS_GPIO_H__
enum dcb_gpio_func_name {
DCB_GPIO_PANEL_POWER = 0x01,
DCB_GPIO_FAN = 0x09,
DCB_GPIO_TVDAC0 = 0x0c,
DCB_GPIO_THERM_EXT_POWER_EVENT = 0x10,
DCB_GPIO_TVDAC1 = 0x2d,
DCB_GPIO_FAN_SENSE = 0x3d,
DCB_GPIO_POWER_ALERT = 0x4c,
DCB_GPIO_EXT_POWER_LOW = 0x79,
DCB_GPIO_LOGO_LED_PWM = 0x84,
DCB_GPIO_UNUSED = 0xff,
DCB_GPIO_VID0 = 0x04,
DCB_GPIO_VID1 = 0x05,
DCB_GPIO_VID2 = 0x06,
DCB_GPIO_VID3 = 0x1a,
DCB_GPIO_VID4 = 0x73,
DCB_GPIO_VID5 = 0x74,
DCB_GPIO_VID6 = 0x75,
DCB_GPIO_VID7 = 0x76,
DCB_GPIO_VID_PWM = 0x81,
};
#define DCB_GPIO_LOG_DIR 0x02
#define DCB_GPIO_LOG_DIR_OUT 0x00
#define DCB_GPIO_LOG_DIR_IN 0x02
#define DCB_GPIO_LOG_VAL 0x01
#define DCB_GPIO_LOG_VAL_LO 0x00
#define DCB_GPIO_LOG_VAL_HI 0x01
struct dcb_gpio_func {
u8 func;
u8 line;
u8 log[2];
/* so far, "param" seems to only have an influence on PWM-related
* GPIOs such as FAN_CONTROL and PANEL_BACKLIGHT_LEVEL.
* if param equals 1, hardware PWM is available
* if param equals 0, the host should toggle the GPIO itself
*/
u8 param;
};
u16 dcb_gpio_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 dcb_gpio_entry(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len);
u16 dcb_gpio_parse(struct nvkm_bios *, int idx, int ent, u8 *ver, u8 *len,
struct dcb_gpio_func *);
u16 dcb_gpio_match(struct nvkm_bios *, int idx, u8 func, u8 line,
u8 *ver, u8 *len, struct dcb_gpio_func *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_I2C_H__
#define __NVBIOS_I2C_H__
enum dcb_i2c_type {
/* matches bios type field prior to ccb 4.1 */
DCB_I2C_NV04_BIT = 0x00,
DCB_I2C_NV4E_BIT = 0x04,
DCB_I2C_NVIO_BIT = 0x05,
DCB_I2C_NVIO_AUX = 0x06,
/* made up - mostly */
DCB_I2C_PMGR = 0x80,
DCB_I2C_UNUSED = 0xff
};
struct dcb_i2c_entry {
enum dcb_i2c_type type;
u8 drive;
u8 sense;
u8 share;
u8 auxch;
};
u16 dcb_i2c_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 dcb_i2c_entry(struct nvkm_bios *, u8 index, u8 *ver, u8 *len);
int dcb_i2c_parse(struct nvkm_bios *, u8 index, struct dcb_i2c_entry *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_ICCSENSE_H__
#define __NVBIOS_ICCSENSE_H__
struct pwr_rail_resistor_t {
u8 mohm;
bool enabled;
};
struct pwr_rail_t {
u8 mode;
u8 extdev_id;
u8 resistor_count;
struct pwr_rail_resistor_t resistors[3];
u16 config;
};
struct nvbios_iccsense {
int nr_entry;
struct pwr_rail_t *rail;
};
int nvbios_iccsense_parse(struct nvkm_bios *, struct nvbios_iccsense *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_IMAGE_H__
#define __NVBIOS_IMAGE_H__
struct nvbios_image {
u32 base;
u32 size;
u8 type;
bool last;
};
bool nvbios_image(struct nvkm_bios *, int, struct nvbios_image *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_INIT_H__
#define __NVBIOS_INIT_H__
struct nvbios_init {
struct nvkm_subdev *subdev;
u32 offset;
struct dcb_output *outp;
int or;
int link;
int head;
/* internal state used during parsing */
u8 execute;
u32 nested;
u32 repeat;
u32 repend;
u32 ramcfg;
};
#define nvbios_init(s,o,ARGS...) ({ \
struct nvbios_init init = { \
.subdev = (s), \
.offset = (o), \
.or = -1, \
.link = 0, \
.head = -1, \
.execute = 1, \
}; \
ARGS \
nvbios_exec(&init); \
})
int nvbios_exec(struct nvbios_init *);
int nvbios_post(struct nvkm_subdev *, bool execute);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_MXM_H__
#define __NVBIOS_MXM_H__
u16 mxm_table(struct nvkm_bios *, u8 *ver, u8 *hdr);
u8 mxm_sor_map(struct nvkm_bios *, u8 conn);
u8 mxm_ddc_map(struct nvkm_bios *, u8 port);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
+11
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_NPDE_H__
#define __NVBIOS_NPDE_H__
struct nvbios_npdeT {
u32 image_size;
bool last;
};
u32 nvbios_npdeTe(struct nvkm_bios *, u32);
u32 nvbios_npdeTp(struct nvkm_bios *, u32, struct nvbios_npdeT *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
+17
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_PCIR_H__
#define __NVBIOS_PCIR_H__
struct nvbios_pcirT {
u16 vendor_id;
u16 device_id;
u8 class_code[3];
u32 image_size;
u16 image_rev;
u8 image_type;
bool last;
};
u32 nvbios_pcirTe(struct nvkm_bios *, u32, u8 *ver, u16 *hdr);
u32 nvbios_pcirTp(struct nvkm_bios *, u32, u8 *ver, u16 *hdr,
struct nvbios_pcirT *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_PERF_H__
#define __NVBIOS_PERF_H__
u32 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
struct nvbios_perfE {
u8 pstate;
u8 fanspeed;
u8 voltage;
u32 core;
u32 shader;
u32 memory;
u32 vdec;
u32 disp;
u32 script;
u8 pcie_speed;
u8 pcie_width;
};
u32 nvbios_perf_entry(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_perfEp(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *);
struct nvbios_perfS {
union {
struct {
u32 freq;
} v40;
};
};
u32 nvbios_perfSe(struct nvkm_bios *, u32 data, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len);
u32 nvbios_perfSp(struct nvkm_bios *, u32 data, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *);
struct nvbios_perf_fan {
u32 pwm_divisor;
};
int nvbios_perf_fan_parse(struct nvkm_bios *, struct nvbios_perf_fan *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_PLL_H__
#define __NVBIOS_PLL_H__
/*XXX: kill me */
struct nvkm_pll_vals {
union {
struct {
#ifdef __BIG_ENDIAN
uint8_t N1, M1, N2, M2;
#else
uint8_t M1, N1, M2, N2;
#endif
};
struct {
uint16_t NM1, NM2;
} __attribute__((packed));
};
int log2P;
int refclk;
};
/* these match types in pll limits table version 0x40,
* nvkm uses them on all chipsets internally where a
* specific pll needs to be referenced, but the exact
* register isn't known.
*/
enum nvbios_pll_type {
PLL_CORE = 0x01,
PLL_SHADER = 0x02,
PLL_UNK03 = 0x03,
PLL_MEMORY = 0x04,
PLL_VDEC = 0x05,
PLL_UNK40 = 0x40,
PLL_UNK41 = 0x41,
PLL_UNK42 = 0x42,
PLL_VPLL0 = 0x80,
PLL_VPLL1 = 0x81,
PLL_VPLL2 = 0x82,
PLL_VPLL3 = 0x83,
PLL_MAX = 0xff
};
struct nvbios_pll {
enum nvbios_pll_type type;
u32 reg;
u32 refclk;
u8 min_p;
u8 max_p;
u8 bias_p;
/*
* for most pre nv50 cards setting a log2P of 7 (the common max_log2p
* value) is no different to 6 (at least for vplls) so allowing the MNP
* calc to use 7 causes the generated clock to be out by a factor of 2.
* however, max_log2p cannot be fixed-up during parsing as the
* unmodified max_log2p value is still needed for setting mplls, hence
* an additional max_usable_log2p member
*/
u8 max_p_usable;
struct {
u32 min_freq;
u32 max_freq;
u32 min_inputfreq;
u32 max_inputfreq;
u8 min_m;
u8 max_m;
u8 min_n;
u8 max_n;
} vco1, vco2;
};
int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_PMU_H__
#define __NVBIOS_PMU_H__
struct nvbios_pmuT {
};
u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
struct nvbios_pmuE {
u8 type;
u32 data;
};
u32 nvbios_pmuEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr);
u32 nvbios_pmuEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_pmuE *);
struct nvbios_pmuR {
u32 boot_addr_pmu;
u32 boot_addr;
u32 boot_size;
u32 code_addr_pmu;
u32 code_addr;
u32 code_size;
u32 init_addr_pmu;
u32 data_addr_pmu;
u32 data_addr;
u32 data_size;
u32 args_addr_pmu;
};
bool nvbios_pmuRm(struct nvkm_bios *, u8 type, struct nvbios_pmuR *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h
+27
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_POWER_BUDGET_H__
#define __NVBIOS_POWER_BUDGET_H__
#include <nvkm/subdev/bios.h>
struct nvbios_power_budget_entry {
u32 min_w;
u32 avg_w;
u32 max_w;
};
struct nvbios_power_budget {
u32 offset;
u8 ver;
u8 hlen;
u8 elen;
u8 ecount;
u8 cap_entry;
};
int nvbios_power_budget_header(struct nvkm_bios *,
struct nvbios_power_budget *);
int nvbios_power_budget_entry(struct nvkm_bios *, struct nvbios_power_budget *,
u8 idx, struct nvbios_power_budget_entry *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
+164
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_RAMCFG_H__
#define __NVBIOS_RAMCFG_H__
struct nvbios_ramcfg {
unsigned rammap_ver;
unsigned rammap_hdr;
unsigned rammap_min;
unsigned rammap_max;
union {
struct {
unsigned rammap_00_16_20:1;
unsigned rammap_00_16_40:1;
unsigned rammap_00_17_02:1;
};
struct {
unsigned rammap_10_04_02:1;
unsigned rammap_10_04_08:1;
};
struct {
unsigned rammap_11_08_01:1;
unsigned rammap_11_08_0c:2;
unsigned rammap_11_08_10:1;
unsigned rammap_11_09_01ff:9;
unsigned rammap_11_0a_03fe:9;
unsigned rammap_11_0a_0400:1;
unsigned rammap_11_0a_0800:1;
unsigned rammap_11_0b_01f0:5;
unsigned rammap_11_0b_0200:1;
unsigned rammap_11_0b_0400:1;
unsigned rammap_11_0b_0800:1;
unsigned rammap_11_0d:8;
unsigned rammap_11_0e:8;
unsigned rammap_11_0f:8;
unsigned rammap_11_11_0c:2;
};
};
unsigned ramcfg_ver;
unsigned ramcfg_hdr;
unsigned ramcfg_timing;
unsigned ramcfg_DLLoff;
unsigned ramcfg_RON;
unsigned ramcfg_FBVDDQ;
union {
struct {
unsigned ramcfg_00_03_01:1;
unsigned ramcfg_00_03_02:1;
unsigned ramcfg_00_03_08:1;
unsigned ramcfg_00_03_10:1;
unsigned ramcfg_00_04_02:1;
unsigned ramcfg_00_04_04:1;
unsigned ramcfg_00_04_20:1;
unsigned ramcfg_00_05:8;
unsigned ramcfg_00_06:8;
unsigned ramcfg_00_07:8;
unsigned ramcfg_00_08:8;
unsigned ramcfg_00_09:8;
unsigned ramcfg_00_0a_0f:4;
unsigned ramcfg_00_0a_f0:4;
};
struct {
unsigned ramcfg_10_02_01:1;
unsigned ramcfg_10_02_02:1;
unsigned ramcfg_10_02_04:1;
unsigned ramcfg_10_02_08:1;
unsigned ramcfg_10_02_10:1;
unsigned ramcfg_10_02_20:1;
unsigned ramcfg_10_03_0f:4;
unsigned ramcfg_10_04_01:1;
unsigned ramcfg_10_05:8;
unsigned ramcfg_10_06:8;
unsigned ramcfg_10_07:8;
unsigned ramcfg_10_08:8;
unsigned ramcfg_10_09_0f:4;
unsigned ramcfg_10_09_f0:4;
};
struct {
unsigned ramcfg_11_01_01:1;
unsigned ramcfg_11_01_02:1;
unsigned ramcfg_11_01_04:1;
unsigned ramcfg_11_01_08:1;
unsigned ramcfg_11_01_10:1;
unsigned ramcfg_11_01_40:1;
unsigned ramcfg_11_01_80:1;
unsigned ramcfg_11_02_03:2;
unsigned ramcfg_11_02_04:1;
unsigned ramcfg_11_02_08:1;
unsigned ramcfg_11_02_10:1;
unsigned ramcfg_11_02_40:1;
unsigned ramcfg_11_02_80:1;
unsigned ramcfg_11_03_0f:4;
unsigned ramcfg_11_03_30:2;
unsigned ramcfg_11_03_c0:2;
unsigned ramcfg_11_03_f0:4;
unsigned ramcfg_11_04:8;
unsigned ramcfg_11_06:8;
unsigned ramcfg_11_07_02:1;
unsigned ramcfg_11_07_04:1;
unsigned ramcfg_11_07_08:1;
unsigned ramcfg_11_07_10:1;
unsigned ramcfg_11_07_40:1;
unsigned ramcfg_11_07_80:1;
unsigned ramcfg_11_08_01:1;
unsigned ramcfg_11_08_02:1;
unsigned ramcfg_11_08_04:1;
unsigned ramcfg_11_08_08:1;
unsigned ramcfg_11_08_10:1;
unsigned ramcfg_11_08_20:1;
unsigned ramcfg_11_09:8;
};
};
unsigned timing_ver;
unsigned timing_hdr;
unsigned timing[11];
union {
struct {
unsigned timing_10_WR:8;
unsigned timing_10_WTR:8;
unsigned timing_10_CL:8;
unsigned timing_10_RC:8;
/*empty: 4 */
unsigned timing_10_RFC:8; /* Byte 5 */
/*empty: 6 */
unsigned timing_10_RAS:8; /* Byte 7 */
/*empty: 8 */
unsigned timing_10_RP:8; /* Byte 9 */
unsigned timing_10_RCDRD:8;
unsigned timing_10_RCDWR:8;
unsigned timing_10_RRD:8;
unsigned timing_10_13:8;
unsigned timing_10_ODT:3;
/* empty: 15 */
unsigned timing_10_16:8;
/* empty: 17 */
unsigned timing_10_18:8;
unsigned timing_10_CWL:8;
unsigned timing_10_20:8;
unsigned timing_10_21:8;
/* empty: 22, 23 */
unsigned timing_10_24:8;
};
struct {
unsigned timing_20_2e_03:2;
unsigned timing_20_2e_30:2;
unsigned timing_20_2e_c0:2;
unsigned timing_20_2f_03:2;
unsigned timing_20_2c_003f:6;
unsigned timing_20_2c_1fc0:7;
unsigned timing_20_30_f8:5;
unsigned timing_20_30_07:3;
unsigned timing_20_31_0007:3;
unsigned timing_20_31_0078:4;
unsigned timing_20_31_0780:4;
unsigned timing_20_31_0800:1;
unsigned timing_20_31_7000:3;
unsigned timing_20_31_8000:1;
};
};
};
u8 nvbios_ramcfg_count(struct nvkm_bios *);
u8 nvbios_ramcfg_index(struct nvkm_subdev *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_RAMMAP_H__
#define __NVBIOS_RAMMAP_H__
#include <subdev/bios/ramcfg.h>
u32 nvbios_rammapTe(struct nvkm_bios *, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u32 nvbios_rammapEe(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_rammapEp_from_perf(struct nvkm_bios *bios, u32 data, u8 size,
struct nvbios_ramcfg *p);
u32 nvbios_rammapEp(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
u32 nvbios_rammapSe(struct nvkm_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr);
u32 nvbios_rammapSp_from_perf(struct nvkm_bios *bios, u32 data, u8 size, int idx,
struct nvbios_ramcfg *p);
u32 nvbios_rammapSp(struct nvkm_bios *, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr, struct nvbios_ramcfg *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_THERM_H__
#define __NVBIOS_THERM_H__
struct nvbios_therm_threshold {
u8 temp;
u8 hysteresis;
};
struct nvbios_therm_sensor {
/* diode */
s16 slope_mult;
s16 slope_div;
s16 offset_num;
s16 offset_den;
s8 offset_constant;
/* thresholds */
struct nvbios_therm_threshold thrs_fan_boost;
struct nvbios_therm_threshold thrs_down_clock;
struct nvbios_therm_threshold thrs_critical;
struct nvbios_therm_threshold thrs_shutdown;
};
enum nvbios_therm_fan_type {
NVBIOS_THERM_FAN_UNK = 0,
NVBIOS_THERM_FAN_TOGGLE = 1,
NVBIOS_THERM_FAN_PWM = 2,
};
/* no vbios have more than 6 */
#define NVKM_TEMP_FAN_TRIP_MAX 10
struct nvbios_therm_trip_point {
int fan_duty;
int temp;
int hysteresis;
};
enum nvbios_therm_fan_mode {
NVBIOS_THERM_FAN_TRIP = 0,
NVBIOS_THERM_FAN_LINEAR = 1,
NVBIOS_THERM_FAN_OTHER = 2,
};
struct nvbios_therm_fan {
enum nvbios_therm_fan_type type;
u32 pwm_freq;
u8 min_duty;
u8 max_duty;
u16 bump_period;
u16 slow_down_period;
enum nvbios_therm_fan_mode fan_mode;
struct nvbios_therm_trip_point trip[NVKM_TEMP_FAN_TRIP_MAX];
u8 nr_fan_trip;
u8 linear_min_temp;
u8 linear_max_temp;
};
enum nvbios_therm_domain {
NVBIOS_THERM_DOMAIN_CORE,
NVBIOS_THERM_DOMAIN_AMBIENT,
};
int
nvbios_therm_sensor_parse(struct nvkm_bios *, enum nvbios_therm_domain,
struct nvbios_therm_sensor *);
int
nvbios_therm_fan_parse(struct nvkm_bios *, struct nvbios_therm_fan *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_TIMING_H__
#define __NVBIOS_TIMING_H__
#include <subdev/bios/ramcfg.h>
u32 nvbios_timingTe(struct nvkm_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u32 nvbios_timingEe(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_timingEp(struct nvkm_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_VMAP_H__
#define __NVBIOS_VMAP_H__
struct nvbios_vmap {
u8 max0;
u8 max1;
u8 max2;
};
u32 nvbios_vmap_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_vmap_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_vmap *);
struct nvbios_vmap_entry {
u8 mode;
u8 link;
u32 min;
u32 max;
s32 arg[6];
};
u32 nvbios_vmap_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len);
u32 nvbios_vmap_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len,
struct nvbios_vmap_entry *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
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/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_VOLT_H__
#define __NVBIOS_VOLT_H__
enum nvbios_volt_type {
NVBIOS_VOLT_GPIO = 0,
NVBIOS_VOLT_PWM,
};
struct nvbios_volt {
enum nvbios_volt_type type;
u32 min;
u32 max;
u32 base;
/* GPIO mode */
bool ranged;
u8 vidmask;
s16 step;
/* PWM mode */
u32 pwm_freq;
u32 pwm_range;
};
u32 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u32 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_volt *);
struct nvbios_volt_entry {
u32 voltage;
u8 vid;
};
u32 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len);
u32 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len,
struct nvbios_volt_entry *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h
+25
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@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_VPSTATE_H__
#define __NVBIOS_VPSTATE_H__
struct nvbios_vpstate_header {
u32 offset;
u8 version;
u8 hlen;
u8 ecount;
u8 elen;
u8 scount;
u8 slen;
u8 base_id;
u8 boost_id;
u8 tdp_id;
};
struct nvbios_vpstate_entry {
u8 pstate;
u16 clock_mhz;
};
int nvbios_vpstate_parse(struct nvkm_bios *, struct nvbios_vpstate_header *);
int nvbios_vpstate_entry(struct nvkm_bios *, struct nvbios_vpstate_header *,
u8 idx, struct nvbios_vpstate_entry *);
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
+19
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@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVBIOS_XPIO_H__
#define __NVBIOS_XPIO_H__
#define NVBIOS_XPIO_FLAG_AUX 0x10
#define NVBIOS_XPIO_FLAG_AUX0 0x00
#define NVBIOS_XPIO_FLAG_AUX1 0x10
struct nvbios_xpio {
u8 type;
u8 addr;
u8 flags;
};
u16 dcb_xpio_table(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 dcb_xpio_parse(struct nvkm_bios *, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *);
#endif