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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
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linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
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/* fuc microcode util functions for gf100 PGRAPH
*
* Copyright 2011 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_CODE
// queue_put - add request to queue
//
// In : $r13 queue pointer
// $r14 command
// $r15 data
//
queue_put:
// make sure we have space..
ld b32 $r8 D[$r13 + 0x0] // GET
ld b32 $r9 D[$r13 + 0x4] // PUT
xor $r8 8
cmpu b32 $r8 $r9
bra ne #queue_put_next
mov $r15 E_CMD_OVERFLOW
call(error)
ret
// store cmd/data on queue
queue_put_next:
and $r8 $r9 7
shl b32 $r8 3
add b32 $r8 $r13
add b32 $r8 8
st b32 D[$r8 + 0x0] $r14
st b32 D[$r8 + 0x4] $r15
// update PUT
add b32 $r9 1
and $r9 0xf
st b32 D[$r13 + 0x4] $r9
ret
// queue_get - fetch request from queue
//
// In : $r13 queue pointer
//
// Out: $p1 clear on success (data available)
// $r14 command
// $r15 data
//
queue_get:
bset $flags $p1
ld b32 $r8 D[$r13 + 0x0] // GET
ld b32 $r9 D[$r13 + 0x4] // PUT
cmpu b32 $r8 $r9
bra e #queue_get_done
// fetch first cmd/data pair
and $r9 $r8 7
shl b32 $r9 3
add b32 $r9 $r13
add b32 $r9 8
ld b32 $r14 D[$r9 + 0x0]
ld b32 $r15 D[$r9 + 0x4]
// update GET
add b32 $r8 1
and $r8 0xf
st b32 D[$r13 + 0x0] $r8
bclr $flags $p1
queue_get_done:
ret
// nv_rd32 - read 32-bit value from nv register
//
// In : $r14 register
// Out: $r15 value
//
nv_rd32:
mov b32 $r12 $r14
bset $r12 31 // MMIO_CTRL_PENDING
nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
nv_rd32_wait:
nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
xbit $r12 $r12 31
bra ne #nv_rd32_wait
mov $r10 6 // DONE_MMIO_RD
call(wait_doneo)
nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0)
ret
// nv_wr32 - write 32-bit value to nv register
//
// In : $r14 register
// $r15 value
//
nv_wr32:
nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15)
mov b32 $r12 $r14
bset $r12 31 // MMIO_CTRL_PENDING
bset $r12 30 // MMIO_CTRL_WRITE
nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
nv_wr32_wait:
nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
xbit $r12 $r12 31
bra ne #nv_wr32_wait
ret
// wait_donez - wait on FUC_DONE bit to become clear
//
// In : $r10 bit to wait on
//
wait_donez:
trace_set(T_WAIT);
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
wait_donez_ne:
nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
xbit $r8 $r8 $r10
bra ne #wait_donez_ne
trace_clr(T_WAIT)
ret
// wait_doneo - wait on FUC_DONE bit to become set
//
// In : $r10 bit to wait on
//
wait_doneo:
trace_set(T_WAIT);
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
wait_doneo_e:
nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
xbit $r8 $r8 $r10
bra e #wait_doneo_e
trace_clr(T_WAIT)
ret
// mmctx_size - determine size of a mmio list transfer
//
// In : $r14 mmio list head
// $r15 mmio list tail
// Out: $r15 transfer size (in bytes)
//
mmctx_size:
clear b32 $r9
nv_mmctx_size_loop:
ld b32 $r8 D[$r14]
shr b32 $r8 26
add b32 $r8 1
shl b32 $r8 2
add b32 $r9 $r8
add b32 $r14 4
cmpu b32 $r14 $r15
bra ne #nv_mmctx_size_loop
mov b32 $r15 $r9
ret
// mmctx_xfer - execute a list of mmio transfers
//
// In : $r10 flags
// bit 0: direction (0 = save, 1 = load)
// bit 1: set if first transfer
// bit 2: set if last transfer
// $r11 base
// $r12 mmio list head
// $r13 mmio list tail
// $r14 multi_stride
// $r15 multi_mask
//
mmctx_xfer:
trace_set(T_MMCTX)
clear b32 $r9
or $r11 $r11
bra e #mmctx_base_disabled
nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11)
bset $r9 0 // BASE_EN
mmctx_base_disabled:
or $r14 $r14
bra e #mmctx_multi_disabled
nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14)
nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15)
bset $r9 1 // MULTI_EN
mmctx_multi_disabled:
xbit $r11 $r10 0
shl b32 $r11 16 // DIR
bset $r11 12 // QLIMIT = 0x10
xbit $r14 $r10 1
shl b32 $r14 17
or $r11 $r14 // START_TRIGGER
nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
// loop over the mmio list, and send requests to the hw
mmctx_exec_loop:
// wait for space in mmctx queue
mmctx_wait_free:
nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
and $r14 0x1f
bra e #mmctx_wait_free
// queue up an entry
ld b32 $r14 D[$r12]
or $r14 $r9
nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14)
add b32 $r12 4
cmpu b32 $r12 $r13
bra ne #mmctx_exec_loop
xbit $r11 $r10 2
bra ne #mmctx_stop
// wait for queue to empty
mmctx_fini_wait:
nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
and $r11 0x1f
cmpu b32 $r11 0x10
bra ne #mmctx_fini_wait
mov $r10 5 // DONE_MMCTX
call(wait_donez)
bra #mmctx_done
mmctx_stop:
xbit $r11 $r10 0
shl b32 $r11 16 // DIR
bset $r11 12 // QLIMIT = 0x10
bset $r11 18 // STOP_TRIGGER
nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
mmctx_stop_wait:
// wait for STOP_TRIGGER to clear
nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
xbit $r11 $r11 18
bra ne #mmctx_stop_wait
mmctx_done:
trace_clr(T_MMCTX)
ret
// Wait for DONE_STRAND
//
strand_wait:
push $r10
mov $r10 2
call(wait_donez)
pop $r10
ret
// unknown - call before issuing strand commands
//
strand_pre:
mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
call(strand_wait)
ret
// unknown - call after issuing strand commands
//
strand_post:
mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
call(strand_wait)
ret
// Selects strand set?!
//
// In: $r14 id
//
strand_set:
mov $r12 0xf
nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call(strand_wait)
ret
// Initialise strand context data
//
// In : $r15 context base
// Out: $r15 context size (in bytes)
//
// Strandset(?) 3 hardcoded currently
//
strand_ctx_init:
trace_set(T_STRINIT)
call(strand_pre)
mov $r14 3
call(strand_set)
clear b32 $r12
nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call(strand_wait)
sub b32 $r12 $r0 1
nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call(strand_wait)
call(strand_post)
// read the size of each strand, poke the context offset of
// each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
// about it later then.
nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00)
nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00)
shr b32 $r14 $r15 8
ctx_init_strand_loop:
iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE
iowr I[$r8 + 0x100] $r14 // STRAND_LOAD_SWBASE
iord $r10 I[$r8 + 0x200] // STRAND_SIZE
shr b32 $r10 6
add b32 $r10 1
add b32 $r14 $r10
add b32 $r8 4
sub b32 $r9 1
bra ne #ctx_init_strand_loop
shl b32 $r14 8
sub b32 $r15 $r14 $r15
trace_clr(T_STRINIT)
ret
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
+492
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/* fuc microcode for gf100 PGRAPH/GPC
*
* Copyright 2011 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
/* TODO
* - bracket certain functions with scratch writes, useful for debugging
* - watchdog timer around ctx operations
*/
#ifdef INCLUDE_DATA
gpc_mmio_list_head: .b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head: .b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head: .b32 #mmio_list_base
unk_mmio_list_tail: .b32 #mmio_list_base
gpc_id: .b32 0
tpc_count: .b32 0
tpc_mask: .b32 0
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count: .b32 0
unk_mask: .b32 0
#endif
cmd_queue: queue_init
mmio_list_base:
#endif
#ifdef INCLUDE_CODE
#define gpc_addr(reg,addr) /*
*/ imm32(reg,addr) /*
*/ or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
#define gpc_wr32(addr,reg) /*
*/ gpc_addr($r14,addr) /*
*/ mov b32 $r15 reg /*
*/ call(nv_wr32)
// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
push $r14
nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
mov $r15 1
nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
pop $r14
ret
#if CHIPSET >= GM107
tpc_strand_wait:
push $r9
trace_set(T_STRTPC)
tpc_strand_busy:
nv_iord($r9, NV_PGRAPH_GPCX_GPCCS_TPC_STATUS, 0)
bra b32 $r9 0x0 ne #tpc_strand_busy
trace_clr(T_STRTPC)
pop $r9
ret
#define tpc_strand_wait() call(tpc_strand_wait)
#define tpc_strand_enable() /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ tpc_strand_wait()
#define tpc_strand_disable() /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ tpc_strand_wait()
#define tpc_strand_seek(p) /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15) /*
*/ mov $r15 p /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_SELECT, $r15) /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK /*
*/ tpc_strand_wait()
#define tpc_strand_info(m) /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ mov $r15 m /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_DATA, $r15) /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ tpc_strand_wait()
#endif
// GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Input:
// CC_SCRATCH[1]: context base
//
// Output:
// CC_SCRATCH[0]:
// 31:31: set to signal completion
// CC_SCRATCH[1]:
// 31:0: GPC context size
//
init:
clear b32 $r0
// setup stack
nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
extr $r1 $r1 9:17
shl b32 $r1 8
mov $sp $r1
// enable fifo access
mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)
// setup i0 handler, and route all interrupts to it
mov $r1 #ih
mov $iv0 $r1
nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)
// enable fifo interrupt
mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)
// enable interrupts
bset $flags ie0
// how many TPCs do we have?
nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
mov $r3 1
and $r2 0x1f
shl b32 $r3 $r2
sub b32 $r3 1
st b32 D[$r0 + #tpc_count] $r2
st b32 D[$r0 + #tpc_mask] $r3
// determine which GPC we are, setup (optional) mmio access offset
nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
st b32 D[$r0 + #gpc_id] $r2
shl b32 $r2 15
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
// figure out which, and how many, UNKs are actually present
gpc_addr($r14, 0x500c30)
clear b32 $r2
clear b32 $r3
clear b32 $r4
init_unk_loop:
call(nv_rd32)
cmp b32 $r15 0
bra z #init_unk_next
mov $r15 1
shl b32 $r15 $r2
or $r4 $r15
add b32 $r3 1
init_unk_next:
add b32 $r2 1
add b32 $r14 4
cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
bra ne #init_unk_loop
init_unk_done:
st b32 D[$r0 + #unk_count] $r3
st b32 D[$r0 + #unk_mask] $r4
#endif
// initialise context base, and size tracking
nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
clear b32 $r3 // track GPC context size here
// set mmctx base addresses now so we don't have to do it later,
// they don't currently ever change
shr b32 $r5 $r2 8
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)
// calculate GPC mmio context size
ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
call(mmctx_size)
add b32 $r2 $r15
add b32 $r3 $r15
// calculate per-TPC mmio context size
ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
call(mmctx_size)
ld b32 $r14 D[$r0 + #tpc_count]
mulu $r14 $r15
add b32 $r2 $r14
add b32 $r3 $r14
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
// calculate per-UNK mmio context size
ld b32 $r14 D[$r0 + #unk_mmio_list_head]
ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
call(mmctx_size)
ld b32 $r14 D[$r0 + #unk_count]
mulu $r14 $r15
add b32 $r2 $r14
add b32 $r3 $r14
#endif
// round up base/size to 256 byte boundary (for strand SWBASE)
shr b32 $r3 2
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
shr b32 $r2 8
shr b32 $r3 6
add b32 $r2 1
add b32 $r3 1
shl b32 $r2 8
shl b32 $r3 8
// calculate size of strand context data
mov b32 $r15 $r2
call(strand_ctx_init)
add b32 $r2 $r15
add b32 $r3 $r15
#if CHIPSET >= GM107
// calculate size of tpc strand context data
mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
tpc_strand_enable();
tpc_strand_seek(0);
tpc_strand_info(-1);
ld b32 $r4 D[$r0 + #tpc_count]
gpc_addr($r5, NV_PGRAPH_GPC0_TPC0)
tpc_strand_init_tpc_loop:
add b32 $r14 $r5 NV_TPC_STRAND_CNT
call(nv_rd32)
mov b32 $r6 $r15
clear b32 $r7
tpc_strand_init_idx_loop:
add b32 $r14 $r5 NV_TPC_STRAND_INDEX
mov b32 $r15 $r7
call(nv_wr32)
add b32 $r14 $r5 NV_TPC_STRAND_SAVE_SWBASE
shr b32 $r15 $r2 8
call(nv_wr32)
add b32 $r14 $r5 NV_TPC_STRAND_LOAD_SWBASE
shr b32 $r15 $r2 8
call(nv_wr32)
add b32 $r14 $r5 NV_TPC_STRAND_WORDS
call(nv_rd32)
shr b32 $r15 6
add b32 $r15 1
shl b32 $r15 8
add b32 $r2 $r15
add b32 $r3 $r15
add b32 $r7 1
sub b32 $r6 1
bra nz #tpc_strand_init_idx_loop
add b32 $r5 NV_PGRAPH_GPC0_TPC0__SIZE
sub b32 $r4 1
bra nz #tpc_strand_init_tpc_loop
mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
tpc_strand_disable();
#endif
// save context size, and tell HUB we're done
nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
clear b32 $r2
bset $r2 31
nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
wait:
sleep $p0
bset $flags $p0
main:
mov $r13 #cmd_queue
call(queue_get)
bra $p1 #wait
// 0x0000-0x0003 are all context transfers
cmpu b32 $r14 0x04
bra nc #main_not_ctx_xfer
// fetch $flags and mask off $p1/$p2
mov $r1 $flags
mov $r2 0x0006
not b32 $r2
and $r1 $r2
// set $p1/$p2 according to transfer type
shl b32 $r14 1
or $r1 $r14
mov $flags $r1
// transfer context data
call(ctx_xfer)
bra #main
main_not_ctx_xfer:
shl b32 $r15 $r14 16
or $r15 E_BAD_COMMAND
call(error)
bra #main
// interrupt handler
ih:
push $r0
push $r8
mov $r8 $flags
push $r8
push $r9
push $r10
push $r11
push $r13
push $r14
push $r15
clear b32 $r0
// incoming fifo command?
nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
bra e #ih_no_fifo
// queue incoming fifo command for later processing
mov $r13 #cmd_queue
nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
call(queue_put)
mov $r14 1
nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)
// ack, and wake up main()
ih_no_fifo:
nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)
pop $r15
pop $r14
pop $r13
pop $r11
pop $r10
pop $r9
pop $r8
mov $flags $r8
pop $r8
pop $r0
bclr $flags $p0
iret
// Set this GPC's bit in HUB_BAR, used to signal completion of various
// activities to the HUB fuc
//
hub_barrier_done:
mov $r15 1
ld b32 $r14 D[$r0 + #gpc_id]
shl b32 $r15 $r14
nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET
ret
// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off? Anyways, without this,
// funny things happen.
//
ctx_redswitch:
mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
mov $r14 8
ctx_redswitch_delay:
sub b32 $r14 1
bra ne #ctx_redswitch_delay
or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
ret
// Transfer GPC context data between GPU and storage area
//
// In: $r15 context base address
// $p1 clear on save, set on load
// $p2 set if opposite direction done/will be done, so:
// on save it means: "a load will follow this save"
// on load it means: "a save preceeded this load"
//
ctx_xfer:
// set context base address
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
#if CHIPSET >= GM107
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE, $r15)
#endif
bra not $p1 #ctx_xfer_not_load
call(ctx_redswitch)
ctx_xfer_not_load:
// strands
call(strand_pre)
clear b32 $r2
nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
xbit $r2 $flags $p1 // SAVE/LOAD
add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)
#if CHIPSET >= GM107
tpc_strand_enable();
tpc_strand_seek(0);
xbit $r15 $flags $p1 // SAVE/LOAD
add b32 $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)
#endif
// mmio context
xbit $r10 $flags $p1 // direction
or $r10 2 // first
imm32($r11,0x500000)
ld b32 $r12 D[$r0 + #gpc_id]
shl b32 $r12 15
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
mov $r14 0 // not multi
call(mmctx_xfer)
// per-TPC mmio context
xbit $r10 $flags $p1 // direction
#if !NV_PGRAPH_GPCX_UNK__SIZE
or $r10 4 // last
#endif
imm32($r11, 0x504000)
ld b32 $r12 D[$r0 + #gpc_id]
shl b32 $r12 15
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
ld b32 $r15 D[$r0 + #tpc_mask]
mov $r14 0x800 // stride = 0x800
call(mmctx_xfer)
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
// per-UNK mmio context
xbit $r10 $flags $p1 // direction
or $r10 4 // last
imm32($r11, 0x503000)
ld b32 $r12 D[$r0 + #gpc_id]
shl b32 $r12 15
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
ld b32 $r12 D[$r0 + #unk_mmio_list_head]
ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
ld b32 $r15 D[$r0 + #unk_mask]
mov $r14 0x200 // stride = 0x200
call(mmctx_xfer)
#endif
// wait for strands to finish
call(strand_wait)
#if CHIPSET >= GM107
tpc_strand_wait()
#endif
// if load, or a save without a load following, do some
// unknown stuff that's done after finishing a block of
// strand commands
bra $p1 #ctx_xfer_post
bra not $p2 #ctx_xfer_done
ctx_xfer_post:
call(strand_post)
#if CHIPSET >= GM107
tpc_strand_disable()
#endif
// mark completion in HUB's barrier
ctx_xfer_done:
call(hub_barrier_done)
ret
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
+42
View File
@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000
#define CHIPSET GF100
#include "macros.fuc"
.section #gf100_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #gf100_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
+532
View File
@@ -0,0 +1,532 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gf100_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x00000064,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x00000064,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x00000064,
/* 0x000c: unk_mmio_list_tail */
0x00000064,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static uint32_t gf100_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0x0489b808,
0xf00c1bf4,
0x21f502f7,
0x00f8037e,
/* 0x001c: queue_put_next */
0xb60798c4,
0x8dbb0384,
0x0880b600,
0x80008e80,
0x90b6018f,
0x0f94f001,
0xf801d980,
/* 0x0039: queue_get */
0x0131f400,
0x9800d898,
0x89b801d9,
0x210bf404,
0xb60789c4,
0x9dbb0394,
0x0890b600,
0x98009e98,
0x80b6019f,
0x0f84f001,
0xf400d880,
/* 0x0066: queue_get_done */
0x00f80132,
/* 0x0068: nv_rd32 */
0xf002ecb9,
0x07f11fc9,
0x03f0ca00,
0x000cd001,
/* 0x007a: nv_rd32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0xa7f0f31b,
0x1021f506,
0x00f7f101,
0x01f3f0cb,
0xf800ffcf,
/* 0x009d: nv_wr32 */
0x0007f100,
0x0103f0cc,
0xbd000fd0,
0x02ecb904,
0xf01fc9f0,
0x07f11ec9,
0x03f0ca00,
0x000cd001,
/* 0x00be: nv_wr32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0x00f8f31b,
/* 0x00d0: wait_donez */
0x99f094bd,
0x0007f100,
0x0203f00f,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x00ed: wait_donez_ne */
0x0087f104,
0x0183f000,
0xff0088cf,
0x1bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0110: wait_doneo */
0x99f094bd,
0x0007f100,
0x0203f00f,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x012d: wait_doneo_e */
0x0087f104,
0x0183f000,
0xff0088cf,
0x0bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f405,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab,
0x0cb9f010,
0xf112b9f0,
0xf0c50007,
0x0bd00103,
/* 0x023b: mmctx_stop_wait */
0xf104bd00,
0xf0c500b7,
0xbbcf01b3,
0x12bbc800,
/* 0x024b: mmctx_done */
0xbdf31bf4,
0x0199f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x025e: strand_wait */
0xa0f900f8,
0xf402a7f0,
0xa0fcd021,
/* 0x026a: strand_pre */
0x97f000f8,
0xfc07f10c,
0x0203f04a,
0xbd0009d0,
0x5e21f504,
/* 0x027f: strand_post */
0xf000f802,
0x07f10d97,
0x03f04afc,
0x0009d002,
0x21f504bd,
0x00f8025e,
/* 0x0294: strand_set */
0xf10fc7f0,
0xf04ffc07,
0x0cd00203,
0xf004bd00,
0x07f10bc7,
0x03f04afc,
0x000cd002,
0x07f104bd,
0x03f04ffc,
0x000ed002,
0xc7f004bd,
0xfc07f10a,
0x0203f04a,
0xbd000cd0,
0x5e21f504,
/* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe,
0x408ed000,
0xb6808acf,
0xa0b606a5,
0x00eabb01,
0xb60480b6,
0x1bf40192,
0x08e4b6e8,
0xbdf2efbc,
0x0399f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x037e: error */
0xe0f900f8,
0xf102ffb9,
0xf09814e7,
0x21f440e3,
0x01f7f09d,
0xf102ffb9,
0xf09c1ce7,
0x21f440e3,
0xf8e0fc9d,
/* 0x03a1: init */
0xf104bd00,
0xf0420017,
0x11cf0013,
0x0911e700,
0x0814b601,
0xf00014fe,
0x07f10227,
0x03f01200,
0x0002d000,
0x17f104bd,
0x10fe04f8,
0x0007f100,
0x0003f007,
0xbd0000d0,
0x0427f004,
0x040007f1,
0xd00003f0,
0x04bd0002,
0xf11031f4,
0xf0820027,
0x22cf0123,
0x0137f000,
0xbb1f24f0,
0x32b60432,
0x05028001,
0xf1060380,
0xf0860027,
0x22cf0123,
0x04028000,
0xf10f24b6,
0xf0c90007,
0x02d00103,
0xf104bd00,
0xf0010027,
0x22cf0223,
0x9534bd00,
0x07f10825,
0x03f0c000,
0x0005d001,
0x07f104bd,
0x03f0c100,
0x0005d001,
0x0e9804bd,
0x010f9800,
0x015021f5,
0xbb002fbb,
0x0e98003f,
0x020f9801,
0x015021f5,
0xfd050e98,
0x2ebb00ef,
0x003ebb00,
0xf10235b6,
0xf0d30007,
0x03d00103,
0xb604bd00,
0x35b60825,
0x0120b606,
0xb60130b6,
0x34b60824,
0x022fb908,
0x02d321f5,
0xbb002fbb,
0x07f1003f,
0x03f00100,
0x0003d002,
0x24bd04bd,
0xf11f29f0,
0xf0080007,
0x02d00203,
/* 0x04bb: wait */
0xf404bd00,
0x31f40028,
/* 0x04c1: main */
0x1cd7f000,
0xf43921f4,
0xe4b0f401,
0x1e18f404,
0xf00181fe,
0x20bd0627,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x05b421f5,
/* 0x04eb: main_not_ctx_xfer */
0x94d90ef4,
0xf5f010ef,
0x7e21f501,
0xcc0ef403,
/* 0x04f8: ih */
0x80f900f9,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0xf104bdf0,
0xf00200a7,
0xaacf00a3,
0x04abc400,
0xf02c0bf4,
0xe7f11cd7,
0xe3f01a00,
0x00eecf00,
0x1900f7f1,
0xcf00f3f0,
0x21f400ff,
0x01e7f004,
0x1d0007f1,
0xd00003f0,
0x04bd000e,
/* 0x0548: ih_no_fifo */
0x010007f1,
0xd00003f0,
0x04bd000a,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xfc80fc00,
0x0032f400,
/* 0x056e: hub_barrier_done */
0xf7f001f8,
0x040e9801,
0xb904febb,
0xe7f102ff,
0xe3f09418,
0x9d21f440,
/* 0x0586: ctx_redswitch */
0xf7f000f8,
0x0007f120,
0x0103f085,
0xbd000fd0,
0x08e7f004,
/* 0x0598: ctx_redswitch_delay */
0xf401e2b6,
0xf5f1fd1b,
0xf5f10800,
0x07f10200,
0x03f08500,
0x000fd001,
0x00f804bd,
/* 0x05b4: ctx_xfer */
0x810007f1,
0xd00203f0,
0x04bd000f,
0xf50711f4,
/* 0x05c7: ctx_xfer_not_load */
0xf5058621,
0xbd026a21,
0xfc07f124,
0x0203f047,
0xbd0002d0,
0x012cf004,
0xf10320b6,
0xf04afc07,
0x02d00203,
0xf004bd00,
0xa5f001ac,
0x00b7f102,
0x50b3f000,
0xb6040c98,
0xbcbb0fc4,
0x000c9800,
0xf0010d98,
0x21f500e7,
0xacf0016f,
0x04a5f001,
0x4000b7f1,
0x9850b3f0,
0xc4b6040c,
0x00bcbb0f,
0x98010c98,
0x0f98020d,
0x00e7f106,
0x6f21f508,
0x5e21f501,
0x0601f402,
/* 0x063f: ctx_xfer_post */
0xf50712f4,
/* 0x0643: ctx_xfer_done */
0xf5027f21,
0xf8056e21,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
+42
View File
@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
#define CHIPSET GF117
#include "macros.fuc"
.section #gf117_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #gf117_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
+539
View File
@@ -0,0 +1,539 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gf117_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000000,
/* 0x0020: unk_mask */
0x00000000,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static uint32_t gf117_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0x0489b808,
0xf00c1bf4,
0x21f502f7,
0x00f8037e,
/* 0x001c: queue_put_next */
0xb60798c4,
0x8dbb0384,
0x0880b600,
0x80008e80,
0x90b6018f,
0x0f94f001,
0xf801d980,
/* 0x0039: queue_get */
0x0131f400,
0x9800d898,
0x89b801d9,
0x210bf404,
0xb60789c4,
0x9dbb0394,
0x0890b600,
0x98009e98,
0x80b6019f,
0x0f84f001,
0xf400d880,
/* 0x0066: queue_get_done */
0x00f80132,
/* 0x0068: nv_rd32 */
0xf002ecb9,
0x07f11fc9,
0x03f0ca00,
0x000cd001,
/* 0x007a: nv_rd32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0xa7f0f31b,
0x1021f506,
0x00f7f101,
0x01f3f0cb,
0xf800ffcf,
/* 0x009d: nv_wr32 */
0x0007f100,
0x0103f0cc,
0xbd000fd0,
0x02ecb904,
0xf01fc9f0,
0x07f11ec9,
0x03f0ca00,
0x000cd001,
/* 0x00be: nv_wr32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0x00f8f31b,
/* 0x00d0: wait_donez */
0x99f094bd,
0x0007f100,
0x0203f00f,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x00ed: wait_donez_ne */
0x0087f104,
0x0183f000,
0xff0088cf,
0x1bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0110: wait_doneo */
0x99f094bd,
0x0007f100,
0x0203f00f,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x012d: wait_doneo_e */
0x0087f104,
0x0183f000,
0xff0088cf,
0x0bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f405,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab,
0x0cb9f010,
0xf112b9f0,
0xf0c50007,
0x0bd00103,
/* 0x023b: mmctx_stop_wait */
0xf104bd00,
0xf0c500b7,
0xbbcf01b3,
0x12bbc800,
/* 0x024b: mmctx_done */
0xbdf31bf4,
0x0199f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x025e: strand_wait */
0xa0f900f8,
0xf402a7f0,
0xa0fcd021,
/* 0x026a: strand_pre */
0x97f000f8,
0xfc07f10c,
0x0203f04a,
0xbd0009d0,
0x5e21f504,
/* 0x027f: strand_post */
0xf000f802,
0x07f10d97,
0x03f04afc,
0x0009d002,
0x21f504bd,
0x00f8025e,
/* 0x0294: strand_set */
0xf10fc7f0,
0xf04ffc07,
0x0cd00203,
0xf004bd00,
0x07f10bc7,
0x03f04afc,
0x000cd002,
0x07f104bd,
0x03f04ffc,
0x000ed002,
0xc7f004bd,
0xfc07f10a,
0x0203f04a,
0xbd000cd0,
0x5e21f504,
/* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe,
0x408ed000,
0xb6808acf,
0xa0b606a5,
0x00eabb01,
0xb60480b6,
0x1bf40192,
0x08e4b6e8,
0xbdf2efbc,
0x0399f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x037e: error */
0xe0f900f8,
0xf102ffb9,
0xf09814e7,
0x21f440e3,
0x01f7f09d,
0xf102ffb9,
0xf09c1ce7,
0x21f440e3,
0xf8e0fc9d,
/* 0x03a1: init */
0xf104bd00,
0xf0420017,
0x11cf0013,
0x0911e700,
0x0814b601,
0xf00014fe,
0x07f10227,
0x03f01200,
0x0002d000,
0x17f104bd,
0x10fe0545,
0x0007f100,
0x0003f007,
0xbd0000d0,
0x0427f004,
0x040007f1,
0xd00003f0,
0x04bd0002,
0xf11031f4,
0xf0820027,
0x22cf0123,
0x0137f000,
0xbb1f24f0,
0x32b60432,
0x05028001,
0xf1060380,
0xf0860027,
0x22cf0123,
0x04028000,
0xf10f24b6,
0xf0c90007,
0x02d00103,
0xf104bd00,
0xf00c30e7,
0xe5f050e3,
0xbd24bd01,
/* 0x0433: init_unk_loop */
0xf444bd34,
0xf6b06821,
0x0f0bf400,
0xbb01f7f0,
0x4ffd04f2,
0x0130b605,
/* 0x0448: init_unk_next */
0xb60120b6,
0x26b004e0,
0xe21bf401,
/* 0x0454: init_unk_done */
0x80070380,
0x27f10804,
0x23f00100,
0x0022cf02,
0x259534bd,
0x0007f108,
0x0103f0c0,
0xbd0005d0,
0x0007f104,
0x0103f0c1,
0xbd0005d0,
0x000e9804,
0xf5010f98,
0xbb015021,
0x3fbb002f,
0x010e9800,
0xf5020f98,
0x98015021,
0xeffd050e,
0x002ebb00,
0x98003ebb,
0x0f98020e,
0x5021f503,
0x070e9801,
0xbb00effd,
0x3ebb002e,
0x0235b600,
0xd30007f1,
0xd00103f0,
0x04bd0003,
0xb60825b6,
0x20b60635,
0x0130b601,
0xb60824b6,
0x2fb90834,
0xd321f502,
0x002fbb02,
0xf1003fbb,
0xf0010007,
0x03d00203,
0xbd04bd00,
0x1f29f024,
0x080007f1,
0xd00203f0,
0x04bd0002,
/* 0x0508: wait */
0xf40028f4,
/* 0x050e: main */
0xd7f00031,
0x3921f424,
0xb0f401f4,
0x18f404e4,
0x0181fe1e,
0xbd0627f0,
0x0412fd20,
0xfd01e4b6,
0x18fe051e,
0x0121f500,
0xd90ef406,
/* 0x0538: main_not_ctx_xfer */
0xf010ef94,
0x21f501f5,
0x0ef4037e,
/* 0x0545: ih */
0xf900f9cc,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0x0200a7f1,
0xcf00a3f0,
0xabc400aa,
0x2c0bf404,
0xf124d7f0,
0xf01a00e7,
0xeecf00e3,
0x00f7f100,
0x00f3f019,
0xf400ffcf,
0xe7f00421,
0x0007f101,
0x0003f01d,
0xbd000ed0,
/* 0x0595: ih_no_fifo */
0x0007f104,
0x0003f001,
0xbd000ad0,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0x32f400fc,
/* 0x05bb: hub_barrier_done */
0xf001f800,
0x0e9801f7,
0x04febb04,
0xf102ffb9,
0xf09418e7,
0x21f440e3,
/* 0x05d3: ctx_redswitch */
0xf000f89d,
0x07f120f7,
0x03f08500,
0x000fd001,
0xe7f004bd,
/* 0x05e5: ctx_redswitch_delay */
0x01e2b608,
0xf1fd1bf4,
0xf10800f5,
0xf10200f5,
0xf0850007,
0x0fd00103,
0xf804bd00,
/* 0x0601: ctx_xfer */
0x0007f100,
0x0203f081,
0xbd000fd0,
0x0711f404,
0x05d321f5,
/* 0x0614: ctx_xfer_not_load */
0x026a21f5,
0x07f124bd,
0x03f047fc,
0x0002d002,
0x2cf004bd,
0x0320b601,
0x4afc07f1,
0xd00203f0,
0x04bd0002,
0xf001acf0,
0xb7f102a5,
0xb3f00000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x010d9800,
0xf500e7f0,
0xf0016f21,
0xb7f101ac,
0xb3f04000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x020d9801,
0xf1060f98,
0xf50800e7,
0xf0016f21,
0xa5f001ac,
0x00b7f104,
0x50b3f030,
0xb6040c98,
0xbcbb0fc4,
0x020c9800,
0x98030d98,
0xe7f1080f,
0x21f50200,
0x21f5016f,
0x01f4025e,
0x0712f406,
/* 0x06b0: ctx_xfer_post */
0x027f21f5,
/* 0x06b4: ctx_xfer_done */
0x05bb21f5,
0x000000f8,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
+42
View File
@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
#define CHIPSET GK100
#include "macros.fuc"
.section #gk104_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #gk104_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
+539
View File
@@ -0,0 +1,539 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gk104_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000000,
/* 0x0020: unk_mask */
0x00000000,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static uint32_t gk104_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0x0489b808,
0xf00c1bf4,
0x21f502f7,
0x00f8037e,
/* 0x001c: queue_put_next */
0xb60798c4,
0x8dbb0384,
0x0880b600,
0x80008e80,
0x90b6018f,
0x0f94f001,
0xf801d980,
/* 0x0039: queue_get */
0x0131f400,
0x9800d898,
0x89b801d9,
0x210bf404,
0xb60789c4,
0x9dbb0394,
0x0890b600,
0x98009e98,
0x80b6019f,
0x0f84f001,
0xf400d880,
/* 0x0066: queue_get_done */
0x00f80132,
/* 0x0068: nv_rd32 */
0xf002ecb9,
0x07f11fc9,
0x03f0ca00,
0x000cd001,
/* 0x007a: nv_rd32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0xa7f0f31b,
0x1021f506,
0x00f7f101,
0x01f3f0cb,
0xf800ffcf,
/* 0x009d: nv_wr32 */
0x0007f100,
0x0103f0cc,
0xbd000fd0,
0x02ecb904,
0xf01fc9f0,
0x07f11ec9,
0x03f0ca00,
0x000cd001,
/* 0x00be: nv_wr32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0x00f8f31b,
/* 0x00d0: wait_donez */
0x99f094bd,
0x0007f100,
0x0203f00f,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x00ed: wait_donez_ne */
0x0087f104,
0x0183f000,
0xff0088cf,
0x1bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0110: wait_doneo */
0x99f094bd,
0x0007f100,
0x0203f00f,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x012d: wait_doneo_e */
0x0087f104,
0x0183f000,
0xff0088cf,
0x0bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f405,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab,
0x0cb9f010,
0xf112b9f0,
0xf0c50007,
0x0bd00103,
/* 0x023b: mmctx_stop_wait */
0xf104bd00,
0xf0c500b7,
0xbbcf01b3,
0x12bbc800,
/* 0x024b: mmctx_done */
0xbdf31bf4,
0x0199f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x025e: strand_wait */
0xa0f900f8,
0xf402a7f0,
0xa0fcd021,
/* 0x026a: strand_pre */
0x97f000f8,
0xfc07f10c,
0x0203f04a,
0xbd0009d0,
0x5e21f504,
/* 0x027f: strand_post */
0xf000f802,
0x07f10d97,
0x03f04afc,
0x0009d002,
0x21f504bd,
0x00f8025e,
/* 0x0294: strand_set */
0xf10fc7f0,
0xf04ffc07,
0x0cd00203,
0xf004bd00,
0x07f10bc7,
0x03f04afc,
0x000cd002,
0x07f104bd,
0x03f04ffc,
0x000ed002,
0xc7f004bd,
0xfc07f10a,
0x0203f04a,
0xbd000cd0,
0x5e21f504,
/* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x0f0007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe,
0x408ed000,
0xb6808acf,
0xa0b606a5,
0x00eabb01,
0xb60480b6,
0x1bf40192,
0x08e4b6e8,
0xbdf2efbc,
0x0399f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x037e: error */
0xe0f900f8,
0xf102ffb9,
0xf09814e7,
0x21f440e3,
0x01f7f09d,
0xf102ffb9,
0xf09c1ce7,
0x21f440e3,
0xf8e0fc9d,
/* 0x03a1: init */
0xf104bd00,
0xf0420017,
0x11cf0013,
0x0911e700,
0x0814b601,
0xf00014fe,
0x07f10227,
0x03f01200,
0x0002d000,
0x17f104bd,
0x10fe0545,
0x0007f100,
0x0003f007,
0xbd0000d0,
0x0427f004,
0x040007f1,
0xd00003f0,
0x04bd0002,
0xf11031f4,
0xf0820027,
0x22cf0123,
0x0137f000,
0xbb1f24f0,
0x32b60432,
0x05028001,
0xf1060380,
0xf0860027,
0x22cf0123,
0x04028000,
0xf10f24b6,
0xf0c90007,
0x02d00103,
0xf104bd00,
0xf00c30e7,
0xe5f050e3,
0xbd24bd01,
/* 0x0433: init_unk_loop */
0xf444bd34,
0xf6b06821,
0x0f0bf400,
0xbb01f7f0,
0x4ffd04f2,
0x0130b605,
/* 0x0448: init_unk_next */
0xb60120b6,
0x26b004e0,
0xe21bf401,
/* 0x0454: init_unk_done */
0x80070380,
0x27f10804,
0x23f00100,
0x0022cf02,
0x259534bd,
0x0007f108,
0x0103f0c0,
0xbd0005d0,
0x0007f104,
0x0103f0c1,
0xbd0005d0,
0x000e9804,
0xf5010f98,
0xbb015021,
0x3fbb002f,
0x010e9800,
0xf5020f98,
0x98015021,
0xeffd050e,
0x002ebb00,
0x98003ebb,
0x0f98020e,
0x5021f503,
0x070e9801,
0xbb00effd,
0x3ebb002e,
0x0235b600,
0xd30007f1,
0xd00103f0,
0x04bd0003,
0xb60825b6,
0x20b60635,
0x0130b601,
0xb60824b6,
0x2fb90834,
0xd321f502,
0x002fbb02,
0xf1003fbb,
0xf0010007,
0x03d00203,
0xbd04bd00,
0x1f29f024,
0x080007f1,
0xd00203f0,
0x04bd0002,
/* 0x0508: wait */
0xf40028f4,
/* 0x050e: main */
0xd7f00031,
0x3921f424,
0xb0f401f4,
0x18f404e4,
0x0181fe1e,
0xbd0627f0,
0x0412fd20,
0xfd01e4b6,
0x18fe051e,
0x0121f500,
0xd90ef406,
/* 0x0538: main_not_ctx_xfer */
0xf010ef94,
0x21f501f5,
0x0ef4037e,
/* 0x0545: ih */
0xf900f9cc,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0x0200a7f1,
0xcf00a3f0,
0xabc400aa,
0x2c0bf404,
0xf124d7f0,
0xf01a00e7,
0xeecf00e3,
0x00f7f100,
0x00f3f019,
0xf400ffcf,
0xe7f00421,
0x0007f101,
0x0003f01d,
0xbd000ed0,
/* 0x0595: ih_no_fifo */
0x0007f104,
0x0003f001,
0xbd000ad0,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0x32f400fc,
/* 0x05bb: hub_barrier_done */
0xf001f800,
0x0e9801f7,
0x04febb04,
0xf102ffb9,
0xf09418e7,
0x21f440e3,
/* 0x05d3: ctx_redswitch */
0xf000f89d,
0x07f120f7,
0x03f08500,
0x000fd001,
0xe7f004bd,
/* 0x05e5: ctx_redswitch_delay */
0x01e2b608,
0xf1fd1bf4,
0xf10800f5,
0xf10200f5,
0xf0850007,
0x0fd00103,
0xf804bd00,
/* 0x0601: ctx_xfer */
0x0007f100,
0x0203f081,
0xbd000fd0,
0x0711f404,
0x05d321f5,
/* 0x0614: ctx_xfer_not_load */
0x026a21f5,
0x07f124bd,
0x03f047fc,
0x0002d002,
0x2cf004bd,
0x0320b601,
0x4afc07f1,
0xd00203f0,
0x04bd0002,
0xf001acf0,
0xb7f102a5,
0xb3f00000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x010d9800,
0xf500e7f0,
0xf0016f21,
0xb7f101ac,
0xb3f04000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x020d9801,
0xf1060f98,
0xf50800e7,
0xf0016f21,
0xa5f001ac,
0x00b7f104,
0x50b3f030,
0xb6040c98,
0xbcbb0fc4,
0x020c9800,
0x98030d98,
0xe7f1080f,
0x21f50200,
0x21f5016f,
0x01f4025e,
0x0712f406,
/* 0x06b0: ctx_xfer_post */
0x027f21f5,
/* 0x06b4: ctx_xfer_done */
0x05bb21f5,
0x000000f8,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
+42
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@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002
#define CHIPSET GK110
#include "macros.fuc"
.section #gk110_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #gk110_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
+539
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@@ -0,0 +1,539 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gk110_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000000,
/* 0x0020: unk_mask */
0x00000000,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static uint32_t gk110_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0x0489b808,
0xf00c1bf4,
0x21f502f7,
0x00f8037e,
/* 0x001c: queue_put_next */
0xb60798c4,
0x8dbb0384,
0x0880b600,
0x80008e80,
0x90b6018f,
0x0f94f001,
0xf801d980,
/* 0x0039: queue_get */
0x0131f400,
0x9800d898,
0x89b801d9,
0x210bf404,
0xb60789c4,
0x9dbb0394,
0x0890b600,
0x98009e98,
0x80b6019f,
0x0f84f001,
0xf400d880,
/* 0x0066: queue_get_done */
0x00f80132,
/* 0x0068: nv_rd32 */
0xf002ecb9,
0x07f11fc9,
0x03f0ca00,
0x000cd001,
/* 0x007a: nv_rd32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0xa7f0f31b,
0x1021f506,
0x00f7f101,
0x01f3f0cb,
0xf800ffcf,
/* 0x009d: nv_wr32 */
0x0007f100,
0x0103f0cc,
0xbd000fd0,
0x02ecb904,
0xf01fc9f0,
0x07f11ec9,
0x03f0ca00,
0x000cd001,
/* 0x00be: nv_wr32_wait */
0xc7f104bd,
0xc3f0ca00,
0x00cccf01,
0xf41fccc8,
0x00f8f31b,
/* 0x00d0: wait_donez */
0x99f094bd,
0x0007f100,
0x0203f037,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x00ed: wait_donez_ne */
0x0087f104,
0x0183f000,
0xff0088cf,
0x1bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0110: wait_doneo */
0x99f094bd,
0x0007f100,
0x0203f037,
0xbd0009d0,
0x0007f104,
0x0203f006,
0xbd000ad0,
/* 0x012d: wait_doneo_e */
0x0087f104,
0x0183f000,
0xff0088cf,
0x0bf4888a,
0xf094bdf3,
0x07f10099,
0x03f01700,
0x0009d002,
0x00f804bd,
/* 0x0150: mmctx_size */
/* 0x0152: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0xf404efb8,
0x9fb9eb1b,
/* 0x016f: mmctx_xfer */
0xbd00f802,
0x0199f094,
0x370007f1,
0xd00203f0,
0x04bd0009,
0xbbfd94bd,
0x120bf405,
0xc40007f1,
0xd00103f0,
0x04bd000b,
/* 0x0197: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0x0007f11e,
0x0103f0c6,
0xbd000ed0,
0x0007f104,
0x0103f0c7,
0xbd000fd0,
0x0199f004,
/* 0x01b8: mmctx_multi_disabled */
0xb600abc8,
0xb9f010b4,
0x01aec80c,
0xfd11e4b6,
0x07f105be,
0x03f0c500,
0x000bd001,
/* 0x01d6: mmctx_exec_loop */
/* 0x01d6: mmctx_wait_free */
0xe7f104bd,
0xe3f0c500,
0x00eecf01,
0xf41fe4f0,
0xce98f30b,
0x05e9fd00,
0xc80007f1,
0xd00103f0,
0x04bd000e,
0xb804c0b6,
0x1bf404cd,
0x02abc8d8,
/* 0x0207: mmctx_fini_wait */
0xf11f1bf4,
0xf0c500b7,
0xbbcf01b3,
0x1fb4f000,
0xf410b4b0,
0xa7f0f01b,
0xd021f405,
/* 0x0223: mmctx_stop */
0xc82b0ef4,
0xb4b600ab,
0x0cb9f010,
0xf112b9f0,
0xf0c50007,
0x0bd00103,
/* 0x023b: mmctx_stop_wait */
0xf104bd00,
0xf0c500b7,
0xbbcf01b3,
0x12bbc800,
/* 0x024b: mmctx_done */
0xbdf31bf4,
0x0199f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x025e: strand_wait */
0xa0f900f8,
0xf402a7f0,
0xa0fcd021,
/* 0x026a: strand_pre */
0x97f000f8,
0xfc07f10c,
0x0203f04a,
0xbd0009d0,
0x5e21f504,
/* 0x027f: strand_post */
0xf000f802,
0x07f10d97,
0x03f04afc,
0x0009d002,
0x21f504bd,
0x00f8025e,
/* 0x0294: strand_set */
0xf10fc7f0,
0xf04ffc07,
0x0cd00203,
0xf004bd00,
0x07f10bc7,
0x03f04afc,
0x000cd002,
0x07f104bd,
0x03f04ffc,
0x000ed002,
0xc7f004bd,
0xfc07f10a,
0x0203f04a,
0xbd000cd0,
0x5e21f504,
/* 0x02d3: strand_ctx_init */
0xbd00f802,
0x0399f094,
0x370007f1,
0xd00203f0,
0x04bd0009,
0x026a21f5,
0xf503e7f0,
0xbd029421,
0xfc07f1c4,
0x0203f047,
0xbd000cd0,
0x01c7f004,
0x4afc07f1,
0xd00203f0,
0x04bd000c,
0x025e21f5,
0xf1010c92,
0xf046fc07,
0x0cd00203,
0xf004bd00,
0x07f102c7,
0x03f04afc,
0x000cd002,
0x21f504bd,
0x21f5025e,
0x87f1027f,
0x83f04200,
0x0097f102,
0x0293f020,
0x950099cf,
/* 0x034a: ctx_init_strand_loop */
0x8ed008fe,
0x408ed000,
0xb6808acf,
0xa0b606a5,
0x00eabb01,
0xb60480b6,
0x1bf40192,
0x08e4b6e8,
0xbdf2efbc,
0x0399f094,
0x170007f1,
0xd00203f0,
0x04bd0009,
/* 0x037e: error */
0xe0f900f8,
0xf102ffb9,
0xf09814e7,
0x21f440e3,
0x01f7f09d,
0xf102ffb9,
0xf09c1ce7,
0x21f440e3,
0xf8e0fc9d,
/* 0x03a1: init */
0xf104bd00,
0xf0420017,
0x11cf0013,
0x0911e700,
0x0814b601,
0xf00014fe,
0x07f10227,
0x03f01200,
0x0002d000,
0x17f104bd,
0x10fe0545,
0x0007f100,
0x0003f007,
0xbd0000d0,
0x0427f004,
0x040007f1,
0xd00003f0,
0x04bd0002,
0xf11031f4,
0xf0820027,
0x22cf0123,
0x0137f000,
0xbb1f24f0,
0x32b60432,
0x05028001,
0xf1060380,
0xf0860027,
0x22cf0123,
0x04028000,
0xf10f24b6,
0xf0c90007,
0x02d00103,
0xf104bd00,
0xf00c30e7,
0xe5f050e3,
0xbd24bd01,
/* 0x0433: init_unk_loop */
0xf444bd34,
0xf6b06821,
0x0f0bf400,
0xbb01f7f0,
0x4ffd04f2,
0x0130b605,
/* 0x0448: init_unk_next */
0xb60120b6,
0x26b004e0,
0xe21bf402,
/* 0x0454: init_unk_done */
0x80070380,
0x27f10804,
0x23f00100,
0x0022cf02,
0x259534bd,
0x0007f108,
0x0103f0c0,
0xbd0005d0,
0x0007f104,
0x0103f0c1,
0xbd0005d0,
0x000e9804,
0xf5010f98,
0xbb015021,
0x3fbb002f,
0x010e9800,
0xf5020f98,
0x98015021,
0xeffd050e,
0x002ebb00,
0x98003ebb,
0x0f98020e,
0x5021f503,
0x070e9801,
0xbb00effd,
0x3ebb002e,
0x0235b600,
0xd30007f1,
0xd00103f0,
0x04bd0003,
0xb60825b6,
0x20b60635,
0x0130b601,
0xb60824b6,
0x2fb90834,
0xd321f502,
0x002fbb02,
0xf1003fbb,
0xf0010007,
0x03d00203,
0xbd04bd00,
0x1f29f024,
0x300007f1,
0xd00203f0,
0x04bd0002,
/* 0x0508: wait */
0xf40028f4,
/* 0x050e: main */
0xd7f00031,
0x3921f424,
0xb0f401f4,
0x18f404e4,
0x0181fe1e,
0xbd0627f0,
0x0412fd20,
0xfd01e4b6,
0x18fe051e,
0x0121f500,
0xd90ef406,
/* 0x0538: main_not_ctx_xfer */
0xf010ef94,
0x21f501f5,
0x0ef4037e,
/* 0x0545: ih */
0xf900f9cc,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0x0200a7f1,
0xcf00a3f0,
0xabc400aa,
0x2c0bf404,
0xf124d7f0,
0xf01a00e7,
0xeecf00e3,
0x00f7f100,
0x00f3f019,
0xf400ffcf,
0xe7f00421,
0x0007f101,
0x0003f01d,
0xbd000ed0,
/* 0x0595: ih_no_fifo */
0x0007f104,
0x0003f001,
0xbd000ad0,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0x32f400fc,
/* 0x05bb: hub_barrier_done */
0xf001f800,
0x0e9801f7,
0x04febb04,
0xf102ffb9,
0xf09418e7,
0x21f440e3,
/* 0x05d3: ctx_redswitch */
0xf000f89d,
0x07f120f7,
0x03f08500,
0x000fd001,
0xe7f004bd,
/* 0x05e5: ctx_redswitch_delay */
0x01e2b608,
0xf1fd1bf4,
0xf10800f5,
0xf10200f5,
0xf0850007,
0x0fd00103,
0xf804bd00,
/* 0x0601: ctx_xfer */
0x0007f100,
0x0203f081,
0xbd000fd0,
0x0711f404,
0x05d321f5,
/* 0x0614: ctx_xfer_not_load */
0x026a21f5,
0x07f124bd,
0x03f047fc,
0x0002d002,
0x2cf004bd,
0x0320b601,
0x4afc07f1,
0xd00203f0,
0x04bd0002,
0xf001acf0,
0xb7f102a5,
0xb3f00000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x010d9800,
0xf500e7f0,
0xf0016f21,
0xb7f101ac,
0xb3f04000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x020d9801,
0xf1060f98,
0xf50800e7,
0xf0016f21,
0xa5f001ac,
0x00b7f104,
0x50b3f030,
0xb6040c98,
0xbcbb0fc4,
0x020c9800,
0x98030d98,
0xe7f1080f,
0x21f50200,
0x21f5016f,
0x01f4025e,
0x0712f406,
/* 0x06b0: ctx_xfer_post */
0x027f21f5,
/* 0x06b4: ctx_xfer_done */
0x05bb21f5,
0x000000f8,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
+42
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@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
#define CHIPSET GK208
#include "macros.fuc"
.section #gk208_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #gk208_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
+475
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@@ -0,0 +1,475 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gk208_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000000,
/* 0x0020: unk_mask */
0x00000000,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static uint32_t gk208_grgpc_code[] = {
0x03140ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0xf489a408,
0x020f0b1b,
0x0002f87e,
/* 0x001a: queue_put_next */
0x98c400f8,
0x0384b607,
0xb6008dbb,
0x8eb50880,
0x018fb500,
0xf00190b6,
0xd9b50f94,
/* 0x0037: queue_get */
0xf400f801,
0xd8980131,
0x01d99800,
0x0bf489a4,
0x0789c421,
0xbb0394b6,
0x90b6009d,
0x009e9808,
0xb6019f98,
0x84f00180,
0x00d8b50f,
/* 0x0063: queue_get_done */
0xf80132f4,
/* 0x0065: nv_rd32 */
0xf0ecb200,
0x00801fc9,
0x0cf601ca,
/* 0x0073: nv_rd32_wait */
0x8c04bd00,
0xcf01ca00,
0xccc800cc,
0xf61bf41f,
0xec7e060a,
0x008f0000,
0xffcf01cb,
/* 0x008f: nv_wr32 */
0x8000f800,
0xf601cc00,
0x04bd000f,
0xc9f0ecb2,
0x1ec9f01f,
0x01ca0080,
0xbd000cf6,
/* 0x00a9: nv_wr32_wait */
0xca008c04,
0x00cccf01,
0xf41fccc8,
0x00f8f61b,
/* 0x00b8: wait_donez */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x00cf: wait_donez_ne */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf61bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x00ec: wait_doneo */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x0103: wait_doneo_e */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf60bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x0120: mmctx_size */
/* 0x0122: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0x1bf4efa4,
0xf89fb2ec,
/* 0x013d: mmctx_xfer */
0xf094bd00,
0x00800199,
0x09f60237,
0xbd04bd00,
0x05bbfd94,
0x800f0bf4,
0xf601c400,
0x04bd000b,
/* 0x015f: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0xc6008018,
0x000ef601,
0x008004bd,
0x0ff601c7,
0xf004bd00,
/* 0x017a: mmctx_multi_disabled */
0xabc80199,
0x10b4b600,
0xc80cb9f0,
0xe4b601ae,
0x05befd11,
0x01c50080,
0xbd000bf6,
/* 0x0195: mmctx_exec_loop */
/* 0x0195: mmctx_wait_free */
0xc5008e04,
0x00eecf01,
0xf41fe4f0,
0xce98f60b,
0x05e9fd00,
0x01c80080,
0xbd000ef6,
0x04c0b604,
0x1bf4cda4,
0x02abc8df,
/* 0x01bf: mmctx_fini_wait */
0x8b1c1bf4,
0xcf01c500,
0xb4f000bb,
0x10b4b01f,
0x0af31bf4,
0x00b87e05,
0x250ef400,
/* 0x01d8: mmctx_stop */
0xb600abc8,
0xb9f010b4,
0x12b9f00c,
0x01c50080,
0xbd000bf6,
/* 0x01ed: mmctx_stop_wait */
0xc5008b04,
0x00bbcf01,
0xf412bbc8,
/* 0x01fa: mmctx_done */
0x94bdf61b,
0x800199f0,
0xf6021700,
0x04bd0009,
/* 0x020a: strand_wait */
0xa0f900f8,
0xb87e020a,
0xa0fc0000,
/* 0x0216: strand_pre */
0x0c0900f8,
0x024afc80,
0xbd0009f6,
0x020a7e04,
/* 0x0227: strand_post */
0x0900f800,
0x4afc800d,
0x0009f602,
0x0a7e04bd,
0x00f80002,
/* 0x0238: strand_set */
0xfc800f0c,
0x0cf6024f,
0x0c04bd00,
0x4afc800b,
0x000cf602,
0xfc8004bd,
0x0ef6024f,
0x0c04bd00,
0x4afc800a,
0x000cf602,
0x0a7e04bd,
0x00f80002,
/* 0x0268: strand_ctx_init */
0x99f094bd,
0x37008003,
0x0009f602,
0x167e04bd,
0x030e0002,
0x0002387e,
0xfc80c4bd,
0x0cf60247,
0x0c04bd00,
0x4afc8001,
0x000cf602,
0x0a7e04bd,
0x0c920002,
0x46fc8001,
0x000cf602,
0x020c04bd,
0x024afc80,
0xbd000cf6,
0x020a7e04,
0x02277e00,
0x42008800,
0x20008902,
0x0099cf02,
/* 0x02c7: ctx_init_strand_loop */
0xf608fe95,
0x8ef6008e,
0x808acf40,
0xb606a5b6,
0xeabb01a0,
0x0480b600,
0xf40192b6,
0xe4b6e81b,
0xf2efbc08,
0x99f094bd,
0x17008003,
0x0009f602,
0x00f804bd,
/* 0x02f8: error */
0xffb2e0f9,
0x4098148e,
0x00008f7e,
0xffb2010f,
0x409c1c8e,
0x00008f7e,
0x00f8e0fc,
/* 0x0314: init */
0x004104bd,
0x0011cf42,
0x010911e7,
0xfe0814b6,
0x02020014,
0xf6120040,
0x04bd0002,
0xfe048441,
0x00400010,
0x0000f607,
0x040204bd,
0xf6040040,
0x04bd0002,
0x821031f4,
0xcf018200,
0x01030022,
0xbb1f24f0,
0x32b60432,
0x0502b501,
0x820603b5,
0xcf018600,
0x02b50022,
0x0f24b604,
0x01c90080,
0xbd0002f6,
0x0c308e04,
0x01e5f050,
0x34bd24bd,
/* 0x0386: init_unk_loop */
0x657e44bd,
0xf6b00000,
0x0e0bf400,
0xf2bb010f,
0x054ffd04,
/* 0x039b: init_unk_next */
0xb60130b6,
0xe0b60120,
0x0126b004,
/* 0x03a7: init_unk_done */
0xb5e21bf4,
0x04b50703,
0x01008208,
0x0022cf02,
0x259534bd,
0xc0008008,
0x0005f601,
0x008004bd,
0x05f601c1,
0x9804bd00,
0x0f98000e,
0x01207e01,
0x002fbb00,
0x98003fbb,
0x0f98010e,
0x01207e02,
0x050e9800,
0xbb00effd,
0x3ebb002e,
0x020e9800,
0x7e030f98,
0x98000120,
0xeffd070e,
0x002ebb00,
0xb6003ebb,
0x00800235,
0x03f601d3,
0xb604bd00,
0x35b60825,
0x0120b606,
0xb60130b6,
0x34b60824,
0x7e2fb208,
0xbb000268,
0x3fbb002f,
0x01008000,
0x0003f602,
0x24bd04bd,
0x801f29f0,
0xf6023000,
0x04bd0002,
/* 0x0448: wait */
0xf40028f4,
/* 0x044e: main */
0x240d0031,
0x0000377e,
0xb0f401f4,
0x18f404e4,
0x0181fe1d,
0x20bd0602,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x00051f7e,
/* 0x0477: main_not_ctx_xfer */
0x94da0ef4,
0xf5f010ef,
0x02f87e01,
0xcd0ef400,
/* 0x0484: ih */
0x80f900f9,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0x4a04bdf0,
0xaacf0200,
0x04abc400,
0x0d1f0bf4,
0x1a004e24,
0x4f00eecf,
0xffcf1900,
0x00047e00,
0x40010e00,
0x0ef61d00,
/* 0x04c3: ih_no_fifo */
0x4004bd00,
0x0af60100,
0xfc04bd00,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x00fc80fc,
0xf80032f4,
/* 0x04e5: hub_barrier_done */
0x98010f01,
0xfebb040e,
0x8effb204,
0x7e409418,
0xf800008f,
/* 0x04f9: ctx_redswitch */
0x80200f00,
0xf6018500,
0x04bd000f,
/* 0x0506: ctx_redswitch_delay */
0xe2b6080e,
0xfd1bf401,
0x0800f5f1,
0x0200f5f1,
0x01850080,
0xbd000ff6,
/* 0x051f: ctx_xfer */
0x8000f804,
0xf6028100,
0x04bd000f,
0x7e0711f4,
/* 0x052f: ctx_xfer_not_load */
0x7e0004f9,
0xbd000216,
0x47fc8024,
0x0002f602,
0x2cf004bd,
0x0320b601,
0x024afc80,
0xbd0002f6,
0x01acf004,
0x8b02a5f0,
0x98500000,
0xc4b6040c,
0x00bcbb0f,
0x98000c98,
0x000e010d,
0x00013d7e,
0x8b01acf0,
0x98504000,
0xc4b6040c,
0x00bcbb0f,
0x98010c98,
0x0f98020d,
0x08004e06,
0x00013d7e,
0xf001acf0,
0x008b04a5,
0x0c985030,
0x0fc4b604,
0x9800bcbb,
0x0d98020c,
0x080f9803,
0x7e02004e,
0x7e00013d,
0xf400020a,
0x12f40601,
/* 0x05b9: ctx_xfer_post */
0x02277e07,
/* 0x05bd: ctx_xfer_done */
0x04e57e00,
0x0000f800,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5
+42
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@@ -0,0 +1,42 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002
#define CHIPSET GM107
#include "macros.fuc"
.section #gm107_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
.section #gm107_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "gpc.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
+607
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@@ -0,0 +1,607 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gm107_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000000,
/* 0x0020: unk_mask */
0x00000000,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static uint32_t gm107_grgpc_code[] = {
0x03410ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0xf489a408,
0x020f0b1b,
0x0002f87e,
/* 0x001a: queue_put_next */
0x98c400f8,
0x0384b607,
0xb6008dbb,
0x8eb50880,
0x018fb500,
0xf00190b6,
0xd9b50f94,
/* 0x0037: queue_get */
0xf400f801,
0xd8980131,
0x01d99800,
0x0bf489a4,
0x0789c421,
0xbb0394b6,
0x90b6009d,
0x009e9808,
0xb6019f98,
0x84f00180,
0x00d8b50f,
/* 0x0063: queue_get_done */
0xf80132f4,
/* 0x0065: nv_rd32 */
0xf0ecb200,
0x00801fc9,
0x0cf601ca,
/* 0x0073: nv_rd32_wait */
0x8c04bd00,
0xcf01ca00,
0xccc800cc,
0xf61bf41f,
0xec7e060a,
0x008f0000,
0xffcf01cb,
/* 0x008f: nv_wr32 */
0x8000f800,
0xf601cc00,
0x04bd000f,
0xc9f0ecb2,
0x1ec9f01f,
0x01ca0080,
0xbd000cf6,
/* 0x00a9: nv_wr32_wait */
0xca008c04,
0x00cccf01,
0xf41fccc8,
0x00f8f61b,
/* 0x00b8: wait_donez */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x00cf: wait_donez_ne */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf61bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x00ec: wait_doneo */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x0103: wait_doneo_e */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf60bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x0120: mmctx_size */
/* 0x0122: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0x1bf4efa4,
0xf89fb2ec,
/* 0x013d: mmctx_xfer */
0xf094bd00,
0x00800199,
0x09f60237,
0xbd04bd00,
0x05bbfd94,
0x800f0bf4,
0xf601c400,
0x04bd000b,
/* 0x015f: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0xc6008018,
0x000ef601,
0x008004bd,
0x0ff601c7,
0xf004bd00,
/* 0x017a: mmctx_multi_disabled */
0xabc80199,
0x10b4b600,
0xc80cb9f0,
0xe4b601ae,
0x05befd11,
0x01c50080,
0xbd000bf6,
/* 0x0195: mmctx_exec_loop */
/* 0x0195: mmctx_wait_free */
0xc5008e04,
0x00eecf01,
0xf41fe4f0,
0xce98f60b,
0x05e9fd00,
0x01c80080,
0xbd000ef6,
0x04c0b604,
0x1bf4cda4,
0x02abc8df,
/* 0x01bf: mmctx_fini_wait */
0x8b1c1bf4,
0xcf01c500,
0xb4f000bb,
0x10b4b01f,
0x0af31bf4,
0x00b87e05,
0x250ef400,
/* 0x01d8: mmctx_stop */
0xb600abc8,
0xb9f010b4,
0x12b9f00c,
0x01c50080,
0xbd000bf6,
/* 0x01ed: mmctx_stop_wait */
0xc5008b04,
0x00bbcf01,
0xf412bbc8,
/* 0x01fa: mmctx_done */
0x94bdf61b,
0x800199f0,
0xf6021700,
0x04bd0009,
/* 0x020a: strand_wait */
0xa0f900f8,
0xb87e020a,
0xa0fc0000,
/* 0x0216: strand_pre */
0x0c0900f8,
0x024afc80,
0xbd0009f6,
0x020a7e04,
/* 0x0227: strand_post */
0x0900f800,
0x4afc800d,
0x0009f602,
0x0a7e04bd,
0x00f80002,
/* 0x0238: strand_set */
0xfc800f0c,
0x0cf6024f,
0x0c04bd00,
0x4afc800b,
0x000cf602,
0xfc8004bd,
0x0ef6024f,
0x0c04bd00,
0x4afc800a,
0x000cf602,
0x0a7e04bd,
0x00f80002,
/* 0x0268: strand_ctx_init */
0x99f094bd,
0x37008003,
0x0009f602,
0x167e04bd,
0x030e0002,
0x0002387e,
0xfc80c4bd,
0x0cf60247,
0x0c04bd00,
0x4afc8001,
0x000cf602,
0x0a7e04bd,
0x0c920002,
0x46fc8001,
0x000cf602,
0x020c04bd,
0x024afc80,
0xbd000cf6,
0x020a7e04,
0x02277e00,
0x42008800,
0x20008902,
0x0099cf02,
/* 0x02c7: ctx_init_strand_loop */
0xf608fe95,
0x8ef6008e,
0x808acf40,
0xb606a5b6,
0xeabb01a0,
0x0480b600,
0xf40192b6,
0xe4b6e81b,
0xf2efbc08,
0x99f094bd,
0x17008003,
0x0009f602,
0x00f804bd,
/* 0x02f8: error */
0xffb2e0f9,
0x4098148e,
0x00008f7e,
0xffb2010f,
0x409c1c8e,
0x00008f7e,
0x00f8e0fc,
/* 0x0314: tpc_strand_wait */
0x94bd90f9,
0x800a99f0,
0xf6023700,
0x04bd0009,
/* 0x0324: tpc_strand_busy */
0x033f0089,
0xb30099cf,
0xbdf90094,
0x0a99f094,
0x02170080,
0xbd0009f6,
0xf890fc04,
/* 0x0341: init */
0x4104bd00,
0x11cf4200,
0x0911e700,
0x0814b601,
0x020014fe,
0x12004002,
0xbd0002f6,
0x05ad4104,
0x400010fe,
0x00f60700,
0x0204bd00,
0x04004004,
0xbd0002f6,
0x1031f404,
0x01820082,
0x030022cf,
0x1f24f001,
0xb60432bb,
0x02b50132,
0x0603b505,
0x01860082,
0xb50022cf,
0x24b60402,
0xc900800f,
0x0002f601,
0x308e04bd,
0xe5f0500c,
0xbd24bd01,
/* 0x03b3: init_unk_loop */
0x7e44bd34,
0xb0000065,
0x0bf400f6,
0xbb010f0e,
0x4ffd04f2,
0x0130b605,
/* 0x03c8: init_unk_next */
0xb60120b6,
0x26b004e0,
0xe21bf402,
/* 0x03d4: init_unk_done */
0xb50703b5,
0x00820804,
0x22cf0201,
0x9534bd00,
0x00800825,
0x05f601c0,
0x8004bd00,
0xf601c100,
0x04bd0005,
0x98000e98,
0x207e010f,
0x2fbb0001,
0x003fbb00,
0x98010e98,
0x207e020f,
0x0e980001,
0x00effd05,
0xbb002ebb,
0x0e98003e,
0x030f9802,
0x0001207e,
0xfd070e98,
0x2ebb00ef,
0x003ebb00,
0x800235b6,
0xf601d300,
0x04bd0003,
0xb60825b6,
0x20b60635,
0x0130b601,
0xb60824b6,
0x2fb20834,
0x0002687e,
0xbb002fbb,
0x3f0f003f,
0x501d608e,
0xb201e5f0,
0x008f7eff,
0x8e0c0f00,
0xf0501da8,
0xffb201e5,
0x00008f7e,
0x0003147e,
0x608e3f0f,
0xe5f0501d,
0x7effb201,
0x0f00008f,
0x1d9c8e00,
0x01e5f050,
0x8f7effb2,
0x010f0000,
0x0003147e,
0x501da88e,
0xb201e5f0,
0x008f7eff,
0x8eff0f00,
0xf0501d98,
0xffb201e5,
0x00008f7e,
0xa88e020f,
0xe5f0501d,
0x7effb201,
0x7e00008f,
0x98000314,
0x00850504,
0x55f05040,
/* 0x04dd: tpc_strand_init_tpc_loop */
0x705eb801,
0x657e0005,
0xf6b20000,
/* 0x04ea: tpc_strand_init_idx_loop */
0x5eb874bd,
0xb2000560,
0x008f7e7f,
0x885eb800,
0x2f950005,
0x008f7e08,
0x8c5eb800,
0x2f950005,
0x008f7e08,
0x905eb800,
0x657e0005,
0xf5b60000,
0x01f0b606,
0xbb08f4b6,
0x3fbb002f,
0x0170b600,
0xf40162b6,
0x50b7bf1b,
0x42b60800,
0xa81bf401,
0x608e3f0f,
0xe5f0501d,
0x7effb201,
0x0f00008f,
0x1da88e0d,
0x01e5f050,
0x8f7effb2,
0x147e0000,
0x00800003,
0x03f60201,
0xbd04bd00,
0x1f29f024,
0x02300080,
0xbd0002f6,
/* 0x0571: wait */
0x0028f404,
/* 0x0577: main */
0x0d0031f4,
0x00377e24,
0xf401f400,
0xf404e4b0,
0x81fe1d18,
0xbd060201,
0x0412fd20,
0xfd01e4b6,
0x18fe051e,
0x06487e00,
0xda0ef400,
/* 0x05a0: main_not_ctx_xfer */
0xf010ef94,
0xf87e01f5,
0x0ef40002,
/* 0x05ad: ih */
0xf900f9cd,
0x0188fe80,
0x90f980f9,
0xb0f9a0f9,
0xe0f9d0f9,
0x04bdf0f9,
0xcf02004a,
0xabc400aa,
0x1f0bf404,
0x004e240d,
0x00eecf1a,
0xcf19004f,
0x047e00ff,
0x010e0000,
0xf61d0040,
0x04bd000e,
/* 0x05ec: ih_no_fifo */
0xf6010040,
0x04bd000a,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xfc80fc00,
0x0032f400,
/* 0x060e: hub_barrier_done */
0x010f01f8,
0xbb040e98,
0xffb204fe,
0x4094188e,
0x00008f7e,
/* 0x0622: ctx_redswitch */
0x200f00f8,
0x01850080,
0xbd000ff6,
/* 0x062f: ctx_redswitch_delay */
0xb6080e04,
0x1bf401e2,
0x00f5f1fd,
0x00f5f108,
0x85008002,
0x000ff601,
0x00f804bd,
/* 0x0648: ctx_xfer */
0x02810080,
0xbd000ff6,
0x1dc48e04,
0x01e5f050,
0x8f7effb2,
0x11f40000,
0x06227e07,
/* 0x0665: ctx_xfer_not_load */
0x02167e00,
0x8024bd00,
0xf60247fc,
0x04bd0002,
0xb6012cf0,
0xfc800320,
0x02f6024a,
0x0f04bd00,
0x1da88e0c,
0x01e5f050,
0x8f7effb2,
0x147e0000,
0x3f0f0003,
0x501d608e,
0xb201e5f0,
0x008f7eff,
0x8e000f00,
0xf0501d9c,
0xffb201e5,
0x00008f7e,
0x147e010f,
0xfcf00003,
0x03f0b601,
0x501da88e,
0xb201e5f0,
0x008f7eff,
0x01acf000,
0x8b02a5f0,
0x98500000,
0xc4b6040c,
0x00bcbb0f,
0x98000c98,
0x000e010d,
0x00013d7e,
0x8b01acf0,
0x98504000,
0xc4b6040c,
0x00bcbb0f,
0x98010c98,
0x0f98020d,
0x08004e06,
0x00013d7e,
0xf001acf0,
0x008b04a5,
0x0c985030,
0x0fc4b604,
0x9800bcbb,
0x0d98020c,
0x080f9803,
0x7e02004e,
0x7e00013d,
0x7e00020a,
0xf4000314,
0x12f40601,
/* 0x073d: ctx_xfer_post */
0x02277e1a,
0x8e0d0f00,
0xf0501da8,
0xffb201e5,
0x00008f7e,
0x0003147e,
/* 0x0754: ctx_xfer_done */
0x00060e7e,
0x000000f8,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
+699
View File
@@ -0,0 +1,699 @@
/* fuc microcode for gf100 PGRAPH/HUB
*
* Copyright 2011 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_DATA
hub_mmio_list_head: .b32 #hub_mmio_list_base
hub_mmio_list_tail: .b32 #hub_mmio_list_next
gpc_count: .b32 0
rop_count: .b32 0
cmd_queue: queue_init
ctx_current: .b32 0
.align 256
chan_data:
chan_mmio_count: .b32 0
chan_mmio_address: .b32 0
.align 256
xfer_data: .skip 256
hub_mmio_list_base:
.b32 0x0417e91c // 0x17e91c, 2
hub_mmio_list_next:
#endif
#ifdef INCLUDE_CODE
// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
mov $r15 1
nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
ret
// HUB fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Output:
// CC_SCRATCH[0]:
// 31:31: set to signal completion
// CC_SCRATCH[1]:
// 31:0: total PGRAPH context size
//
init:
clear b32 $r0
mov $xdbase $r0
// setup stack
nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0)
extr $r1 $r1 9:17
shl b32 $r1 8
mov $sp $r1
// enable fifo access
mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO
nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2)
// setup i0 handler, and route all interrupts to it
mov $r1 #ih
mov $iv0 $r1
clear b32 $r2
nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2)
// route HUB_CHSW_PULSE to fuc interrupt 8
mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8
nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2)
// not sure what these are, route them because NVIDIA does, and
// the IRQ handler will signal the host if we ever get one.. we
// may find out if/why we need to handle these if so..
//
mov $r2 0x2004 // { 0x04, ZERO } -> intr 9
nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2)
mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10
nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2)
mov $r2 0x200c // { 0x0c, ZERO } -> intr 15
nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2)
// enable all INTR_UP interrupts
sub b32 $r3 $r0 1
nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3)
// enable fifo, ctxsw, 9, fwmthd, 15 interrupts
imm32($r2, 0x8704)
nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2)
// fifo level triggered, rest edge
mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL
nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2)
// enable interrupts
bset $flags ie0
// fetch enabled GPC/ROP counts
nv_rd32($r14, 0x409604)
extr $r1 $r15 16:20
st b32 D[$r0 + #rop_count] $r1
and $r15 0x1f
st b32 D[$r0 + #gpc_count] $r15
// set BAR_REQMASK to GPC mask
mov $r1 1
shl b32 $r1 $r15
sub b32 $r1 1
nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1)
nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1)
// context size calculation, reserve first 256 bytes for use by fuc
mov $r1 256
//
mov $r15 2
call(ctx_4170s)
call(ctx_4170w)
mov $r15 0x10
call(ctx_86c)
// calculate size of mmio context data
ld b32 $r14 D[$r0 + #hub_mmio_list_head]
ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
call(mmctx_size)
// set mmctx base addresses now so we don't have to do it later,
// they don't (currently) ever change
shr b32 $r4 $r1 8
nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4)
nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4)
add b32 $r3 0x1300
add b32 $r1 $r15
shr b32 $r15 2
nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf??
// strands, base offset needs to be aligned to 256 bytes
shr b32 $r1 8
add b32 $r1 1
shl b32 $r1 8
mov b32 $r15 $r1
call(strand_ctx_init)
add b32 $r1 $r15
// initialise each GPC in sequence by passing in the offset of its
// context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
// has previously been uploaded by the host) running.
//
// the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
// when it has completed, and return the size of its context data
// in GPCn_CC_SCRATCH[1]
//
ld b32 $r3 D[$r0 + #gpc_count]
imm32($r4, 0x502000)
init_gpc:
// setup, and start GPC ucode running
add b32 $r14 $r4 0x804
mov b32 $r15 $r1
call(nv_wr32) // CC_SCRATCH[1] = ctx offset
add b32 $r14 $r4 0x10c
clear b32 $r15
call(nv_wr32)
add b32 $r14 $r4 0x104
call(nv_wr32) // ENTRY
add b32 $r14 $r4 0x100
mov $r15 2 // CTRL_START_TRIGGER
call(nv_wr32) // CTRL
// wait for it to complete, and adjust context size
add b32 $r14 $r4 0x800
init_gpc_wait:
call(nv_rd32)
xbit $r15 $r15 31
bra e #init_gpc_wait
add b32 $r14 $r4 0x804
call(nv_rd32)
add b32 $r1 $r15
// next!
add b32 $r4 0x8000
sub b32 $r3 1
bra ne #init_gpc
//
mov $r15 0
call(ctx_86c)
mov $r15 0
call(ctx_4170s)
// save context size, and tell host we're ready
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
clear b32 $r1
bset $r1 31
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1)
// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
wait:
// sleep until we have something to do
sleep $p0
bset $flags $p0
main:
mov $r13 #cmd_queue
call(queue_get)
bra $p1 #wait
// context switch, requested by GPU?
cmpu b32 $r14 0x4001
bra ne #main_not_ctx_switch
trace_set(T_AUTO)
nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0)
nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0)
xbit $r3 $r1 31
bra e #chsw_no_prev
xbit $r3 $r2 31
bra e #chsw_prev_no_next
push $r2
mov b32 $r2 $r1
trace_set(T_SAVE)
bclr $flags $p1
bset $flags $p2
call(ctx_xfer)
trace_clr(T_SAVE);
pop $r2
trace_set(T_LOAD);
bset $flags $p1
call(ctx_xfer)
trace_clr(T_LOAD);
bra #chsw_done
chsw_prev_no_next:
push $r2
mov b32 $r2 $r1
bclr $flags $p1
bclr $flags $p2
call(ctx_xfer)
pop $r2
nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
bra #chsw_done
chsw_no_prev:
xbit $r3 $r2 31
bra e #chsw_done
bset $flags $p1
bclr $flags $p2
call(ctx_xfer)
// ack the context switch request
chsw_done:
mov $r2 NV_PGRAPH_FECS_CHSW_ACK
nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2)
trace_clr(T_AUTO)
bra #main
// request to set current channel? (*not* a context switch)
main_not_ctx_switch:
cmpu b32 $r14 0x0001
bra ne #main_not_ctx_chan
mov b32 $r2 $r15
call(ctx_chan)
bra #main_done
// request to store current channel context?
main_not_ctx_chan:
cmpu b32 $r14 0x0002
bra ne #main_not_ctx_save
trace_set(T_SAVE)
bclr $flags $p1
bclr $flags $p2
call(ctx_xfer)
trace_clr(T_SAVE)
bra #main_done
main_not_ctx_save:
shl b32 $r15 $r14 16
or $r15 E_BAD_COMMAND
call(error)
bra #main
main_done:
clear b32 $r2
bset $r2 31
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2)
bra #main
// interrupt handler
ih:
push $r0
push $r8
mov $r8 $flags
push $r8
push $r9
push $r10
push $r11
push $r13
push $r14
push $r15
clear b32 $r0
// incoming fifo command?
nv_iord($r10, NV_PGRAPH_FECS_INTR, 0)
and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO
bra e #ih_no_fifo
// queue incoming fifo command for later processing
mov $r13 #cmd_queue
nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0)
nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0)
call(queue_put)
add b32 $r11 0x400
mov $r14 1
nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14)
// context switch request?
ih_no_fifo:
and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW
bra e #ih_no_ctxsw
// enqueue a context switch for later processing
mov $r13 #cmd_queue
mov $r14 0x4001
call(queue_put)
// firmware method?
ih_no_ctxsw:
and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
bra e #ih_no_fwmthd
// none we handle; report to host and ack
nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)
nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)
extr $r14 $r15 16:18
shl b32 $r14 $r14 2
imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))
add b32 $r14 $r15
call(nv_rd32)
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)
mov $r15 E_BAD_FWMTHD
call(error)
mov $r11 0x100
nv_wr32(0x400144, $r11)
// anything we didn't handle, bring it to the host's attention
ih_no_fwmthd:
mov $r11 0x504 // FIFO | CHSW | FWMTHD
not b32 $r11
and $r11 $r10 $r11
bra e #ih_no_other
nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11)
// ack, and wake up main()
ih_no_other:
nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10)
pop $r15
pop $r14
pop $r13
pop $r11
pop $r10
pop $r9
pop $r8
mov $flags $r8
pop $r8
pop $r0
bclr $flags $p0
iret
#if CHIPSET < GK100
// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
ctx_4160s:
mov $r15 1
nv_wr32(0x404160, $r15)
ctx_4160s_wait:
nv_rd32($r15, 0x404160)
xbit $r15 $r15 4
bra e #ctx_4160s_wait
ret
// Without clearing again at end of xfer, some things cause PGRAPH
// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
// still function with it set however...
ctx_4160c:
clear b32 $r15
nv_wr32(0x404160, $r15)
ret
#endif
// Again, not real sure
//
// In: $r15 value to set 0x404170 to
//
ctx_4170s:
or $r15 0x10
nv_wr32(0x404170, $r15)
ret
// Waits for a ctx_4170s() call to complete
//
ctx_4170w:
nv_rd32($r15, 0x404170)
and $r15 0x10
bra ne #ctx_4170w
ret
// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off? Anyways, without this,
// funny things happen.
//
ctx_redswitch:
mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC
or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP
or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC
or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN
nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
mov $r15 8
ctx_redswitch_delay:
sub b32 $r15 1
bra ne #ctx_redswitch_delay
or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP
or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN
nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
ret
// Not a clue what this is for, except that unless the value is 0x10, the
// strand context is saved (and presumably restored) incorrectly..
//
// In: $r15 value to set to (0x00/0x10 are used)
//
ctx_86c:
nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15)
nv_wr32(0x408a14, $r15)
nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15)
ret
// In: $r15 NV_PGRAPH_FECS_MEM_CMD_*
ctx_mem:
nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15)
ctx_mem_wait:
nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0)
or $r15 $r15
bra ne #ctx_mem_wait
ret
// ctx_load - load's a channel's ctxctl data, and selects its vm
//
// In: $r2 channel address
//
ctx_load:
trace_set(T_CHAN)
// switch to channel, somewhat magic in parts..
mov $r10 12 // DONE_UNK12
call(wait_donez)
clear b32 $r15
nv_iowr(0x409a24, 0, $r15)
nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2)
nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2)
mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN
call(ctx_mem)
nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
// load channel header, fetch PGRAPH context pointer
mov $xtargets $r0
bclr $r2 31
shl b32 $r2 4
add b32 $r2 2
trace_set(T_LCHAN)
nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2)
imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31)
or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM
nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
mov $r1 0x10 // chan + 0x0210
mov $r2 #xfer_data
sethi $r2 0x00020000 // 16 bytes
xdld $r1 $r2
xdwait
trace_clr(T_LCHAN)
// update current context
ld b32 $r1 D[$r0 + #xfer_data + 4]
shl b32 $r1 24
ld b32 $r2 D[$r0 + #xfer_data + 0]
shr b32 $r2 8
or $r1 $r2
st b32 D[$r0 + #ctx_current] $r1
// set transfer base to start of context, and fetch context header
trace_set(T_LCTXH)
nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1)
mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM
nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
mov $r1 #chan_data
sethi $r1 0x00060000 // 256 bytes
xdld $r0 $r1
xdwait
trace_clr(T_LCTXH)
trace_clr(T_CHAN)
ret
// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
// the active channel for ctxctl, but not actually transfer
// any context data. intended for use only during initial
// context construction.
//
// In: $r2 channel address
//
ctx_chan:
#if CHIPSET < GK100
call(ctx_4160s)
#endif
call(ctx_load)
mov $r10 12 // DONE_UNK12
call(wait_donez)
mov $r15 5 // MEM_CMD 5 ???
call(ctx_mem)
#if CHIPSET < GK100
call(ctx_4160c)
#endif
ret
// Execute per-context state overrides list
//
// Only executed on the first load of a channel. Might want to look into
// removing this and having the host directly modify the channel's context
// to change this state... The nouveau DRM already builds this list as
// it's definitely needed for NVIDIA's, so we may as well use it for now
//
// Input: $r1 mmio list length
//
ctx_mmio_exec:
// set transfer base to be the mmio list
ld b32 $r3 D[$r0 + #chan_mmio_address]
nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
clear b32 $r3
ctx_mmio_loop:
// fetch next 256 bytes of mmio list if necessary
and $r4 $r3 0xff
bra ne #ctx_mmio_pull
mov $r5 #xfer_data
sethi $r5 0x00060000 // 256 bytes
xdld $r3 $r5
xdwait
// execute a single list entry
ctx_mmio_pull:
ld b32 $r14 D[$r4 + #xfer_data + 0x00]
ld b32 $r15 D[$r4 + #xfer_data + 0x04]
call(nv_wr32)
// next!
add b32 $r3 8
sub b32 $r1 1
bra ne #ctx_mmio_loop
// set transfer base back to the current context
ctx_mmio_done:
ld b32 $r3 D[$r0 + #ctx_current]
nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
// disable the mmio list now, we don't need/want to execute it again
st b32 D[$r0 + #chan_mmio_count] $r0
mov $r1 #chan_data
sethi $r1 0x00060000 // 256 bytes
xdst $r0 $r1
xdwait
ret
// Transfer HUB context data between GPU and storage area
//
// In: $r2 channel address
// $p1 clear on save, set on load
// $p2 set if opposite direction done/will be done, so:
// on save it means: "a load will follow this save"
// on load it means: "a save preceeded this load"
//
ctx_xfer:
// according to mwk, some kind of wait for idle
mov $r14 4
nv_iowr(0x409c08, 0, $r14)
ctx_xfer_idle:
nv_iord($r14, 0x409c00, 0)
and $r14 0x2000
bra ne #ctx_xfer_idle
bra not $p1 #ctx_xfer_pre
bra $p2 #ctx_xfer_pre_load
ctx_xfer_pre:
mov $r15 0x10
call(ctx_86c)
#if CHIPSET < GK100
call(ctx_4160s)
#endif
bra not $p1 #ctx_xfer_exec
ctx_xfer_pre_load:
mov $r15 2
call(ctx_4170s)
call(ctx_4170w)
call(ctx_redswitch)
clear b32 $r15
call(ctx_4170s)
call(ctx_load)
// fetch context pointer, and initiate xfer on all GPCs
ctx_xfer_exec:
ld b32 $r1 D[$r0 + #ctx_current]
clear b32 $r2
nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2)
nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer
xbit $r15 $flags $p1
xbit $r2 $flags $p2
shl b32 $r2 1
or $r15 $r2
nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
// strands
call(strand_pre)
clear b32 $r2
nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2)
xbit $r2 $flags $p1 // SAVE/LOAD
add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2)
// mmio context
xbit $r10 $flags $p1 // direction
or $r10 6 // first, last
mov $r11 0 // base = 0
ld b32 $r12 D[$r0 + #hub_mmio_list_head]
ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
mov $r14 0 // not multi
call(mmctx_xfer)
// wait for GPCs to all complete
mov $r10 8 // DONE_BAR
call(wait_doneo)
// wait for strand xfer to complete
call(strand_wait)
// post-op
bra $p1 #ctx_xfer_post
mov $r10 12 // DONE_UNK12
call(wait_donez)
mov $r15 5 // MEM_CMD 5 ???
call(ctx_mem)
bra $p2 #ctx_xfer_done
ctx_xfer_post:
mov $r15 2
call(ctx_4170s)
clear b32 $r15
call(ctx_86c)
call(strand_post)
call(ctx_4170w)
clear b32 $r15
call(ctx_4170s)
bra not $p1 #ctx_xfer_no_post_mmio
ld b32 $r1 D[$r0 + #chan_mmio_count]
or $r1 $r1
bra e #ctx_xfer_no_post_mmio
call(ctx_mmio_exec)
ctx_xfer_no_post_mmio:
#if CHIPSET < GK100
call(ctx_4160c)
#endif
ctx_xfer_done:
ret
#endif
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
+40
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@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GF100
#include "macros.fuc"
.section #gf100_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #gf100_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
+1049
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linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
+40
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@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GF117
#include "macros.fuc"
.section #gf117_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #gf117_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
+1049
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linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
+40
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@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GK100
#include "macros.fuc"
.section #gk104_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #gk104_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
+1046
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linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
+40
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@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GK110
#include "macros.fuc"
.section #gk110_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #gk110_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
+1046
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linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
+40
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@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GK208
#include "macros.fuc"
.section #gk208_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #gk208_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
+918
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@@ -0,0 +1,918 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gk208_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
0x00000304,
/* 0x0008: gpc_count */
0x00000000,
/* 0x000c: rop_count */
0x00000000,
/* 0x0010: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0058: ctx_current */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0100: chan_data */
/* 0x0100: chan_mmio_count */
0x00000000,
/* 0x0104: chan_mmio_address */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0200: xfer_data */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0300: hub_mmio_list_base */
0x0417e91c,
};
static uint32_t gk208_grhub_code[] = {
0x030e0ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0xf489a408,
0x020f0b1b,
0x0002f87e,
/* 0x001a: queue_put_next */
0x98c400f8,
0x0384b607,
0xb6008dbb,
0x8eb50880,
0x018fb500,
0xf00190b6,
0xd9b50f94,
/* 0x0037: queue_get */
0xf400f801,
0xd8980131,
0x01d99800,
0x0bf489a4,
0x0789c421,
0xbb0394b6,
0x90b6009d,
0x009e9808,
0xb6019f98,
0x84f00180,
0x00d8b50f,
/* 0x0063: queue_get_done */
0xf80132f4,
/* 0x0065: nv_rd32 */
0xf0ecb200,
0x00801fc9,
0x0cf601ca,
/* 0x0073: nv_rd32_wait */
0x8c04bd00,
0xcf01ca00,
0xccc800cc,
0xf61bf41f,
0xec7e060a,
0x008f0000,
0xffcf01cb,
/* 0x008f: nv_wr32 */
0x8000f800,
0xf601cc00,
0x04bd000f,
0xc9f0ecb2,
0x1ec9f01f,
0x01ca0080,
0xbd000cf6,
/* 0x00a9: nv_wr32_wait */
0xca008c04,
0x00cccf01,
0xf41fccc8,
0x00f8f61b,
/* 0x00b8: wait_donez */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x00cf: wait_donez_ne */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf61bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x00ec: wait_doneo */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x0103: wait_doneo_e */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf60bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x0120: mmctx_size */
/* 0x0122: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0x1bf4efa4,
0xf89fb2ec,
/* 0x013d: mmctx_xfer */
0xf094bd00,
0x00800199,
0x09f60237,
0xbd04bd00,
0x05bbfd94,
0x800f0bf4,
0xf601c400,
0x04bd000b,
/* 0x015f: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0xc6008018,
0x000ef601,
0x008004bd,
0x0ff601c7,
0xf004bd00,
/* 0x017a: mmctx_multi_disabled */
0xabc80199,
0x10b4b600,
0xc80cb9f0,
0xe4b601ae,
0x05befd11,
0x01c50080,
0xbd000bf6,
/* 0x0195: mmctx_exec_loop */
/* 0x0195: mmctx_wait_free */
0xc5008e04,
0x00eecf01,
0xf41fe4f0,
0xce98f60b,
0x05e9fd00,
0x01c80080,
0xbd000ef6,
0x04c0b604,
0x1bf4cda4,
0x02abc8df,
/* 0x01bf: mmctx_fini_wait */
0x8b1c1bf4,
0xcf01c500,
0xb4f000bb,
0x10b4b01f,
0x0af31bf4,
0x00b87e05,
0x250ef400,
/* 0x01d8: mmctx_stop */
0xb600abc8,
0xb9f010b4,
0x12b9f00c,
0x01c50080,
0xbd000bf6,
/* 0x01ed: mmctx_stop_wait */
0xc5008b04,
0x00bbcf01,
0xf412bbc8,
/* 0x01fa: mmctx_done */
0x94bdf61b,
0x800199f0,
0xf6021700,
0x04bd0009,
/* 0x020a: strand_wait */
0xa0f900f8,
0xb87e020a,
0xa0fc0000,
/* 0x0216: strand_pre */
0x0c0900f8,
0x024afc80,
0xbd0009f6,
0x020a7e04,
/* 0x0227: strand_post */
0x0900f800,
0x4afc800d,
0x0009f602,
0x0a7e04bd,
0x00f80002,
/* 0x0238: strand_set */
0xfc800f0c,
0x0cf6024f,
0x0c04bd00,
0x4afc800b,
0x000cf602,
0xfc8004bd,
0x0ef6024f,
0x0c04bd00,
0x4afc800a,
0x000cf602,
0x0a7e04bd,
0x00f80002,
/* 0x0268: strand_ctx_init */
0x99f094bd,
0x37008003,
0x0009f602,
0x167e04bd,
0x030e0002,
0x0002387e,
0xfc80c4bd,
0x0cf60247,
0x0c04bd00,
0x4afc8001,
0x000cf602,
0x0a7e04bd,
0x0c920002,
0x46fc8001,
0x000cf602,
0x020c04bd,
0x024afc80,
0xbd000cf6,
0x020a7e04,
0x02277e00,
0x42008800,
0x20008902,
0x0099cf02,
/* 0x02c7: ctx_init_strand_loop */
0xf608fe95,
0x8ef6008e,
0x808acf40,
0xb606a5b6,
0xeabb01a0,
0x0480b600,
0xf40192b6,
0xe4b6e81b,
0xf2efbc08,
0x99f094bd,
0x17008003,
0x0009f602,
0x00f804bd,
/* 0x02f8: error */
0x02050080,
0xbd000ff6,
0x80010f04,
0xf6030700,
0x04bd000f,
/* 0x030e: init */
0x04bd00f8,
0x410007fe,
0x11cf4200,
0x0911e700,
0x0814b601,
0x020014fe,
0x12004002,
0xbd0002f6,
0x05ca4104,
0xbd0010fe,
0x07004024,
0xbd0002f6,
0x20034204,
0x01010080,
0xbd0002f6,
0x20044204,
0x01010480,
0xbd0002f6,
0x200b4204,
0x01010880,
0xbd0002f6,
0x200c4204,
0x01011c80,
0xbd0002f6,
0x01039204,
0x03090080,
0xbd0003f6,
0x87048204,
0x04004000,
0xbd0002f6,
0x40040204,
0x02f60300,
0xf404bd00,
0x048e1031,
0x657e4096,
0xfeb20000,
0xb590f1c7,
0xf4f00301,
0x020fb51f,
0x1fbb0101,
0x0112b604,
0x01030080,
0xbd0001f6,
0x04008004,
0x0001f601,
0x004104bd,
0x7e020f01,
0x7e0006ad,
0x0f0006bc,
0x06fe7e10,
0x000e9800,
0x7e010f98,
0x95000120,
0x00800814,
0x04f601c0,
0x8004bd00,
0xf601c100,
0x04bd0004,
0x130030b7,
0xb6001fbb,
0x008002f5,
0x0ff601d3,
0xb604bd00,
0x10b60815,
0x0814b601,
0x687e1fb2,
0x1fbb0002,
0x02039800,
0x50200084,
/* 0x0420: init_gpc */
0x08044eb8,
0x7e1fb200,
0xb800008f,
0x00010c4e,
0x8f7ef4bd,
0x4eb80000,
0x7e000104,
0xb800008f,
0x0001004e,
0x8f7e020f,
0x4eb80000,
/* 0x044f: init_gpc_wait */
0x7e000800,
0xc8000065,
0x0bf41fff,
0x044eb8f9,
0x657e0008,
0x1fbb0000,
0x0040b700,
0x0132b680,
0x0fb41bf4,
0x06fe7e00,
0x7e000f00,
0x800006ad,
0xf6020100,
0x04bd0001,
0x19f014bd,
0x3000801f,
0x0001f602,
/* 0x0492: wait */
0x28f404bd,
0x0031f400,
/* 0x0498: main */
0x377e100d,
0x01f40000,
0x01e4b1f4,
0xc71bf540,
0xf094bd00,
0x00800499,
0x09f60237,
0x8104bd00,
0xcf02c000,
0x00820011,
0x22cf02c1,
0x1f13c800,
0xc8770bf4,
0x0bf41f23,
0xb220f955,
0xf094bd12,
0x00800799,
0x09f60237,
0xf404bd00,
0x31f40132,
0x08817e02,
0xf094bd00,
0x00800799,
0x09f60217,
0xfc04bd00,
0xf094bd20,
0x00800699,
0x09f60237,
0xf404bd00,
0x817e0131,
0x94bd0008,
0x800699f0,
0xf6021700,
0x04bd0009,
/* 0x0523: chsw_prev_no_next */
0xf92f0ef4,
0xf412b220,
0x32f40132,
0x08817e02,
0x8020fc00,
0xf602c000,
0x04bd0002,
/* 0x053f: chsw_no_prev */
0xc8130ef4,
0x0bf41f23,
0x0131f40d,
0x7e0232f4,
/* 0x054f: chsw_done */
0x02000881,
0xc3008001,
0x0002f602,
0x94bd04bd,
0x800499f0,
0xf6021700,
0x04bd0009,
0xff300ef5,
/* 0x056c: main_not_ctx_switch */
0xf401e4b0,
0xf2b20c1b,
0x0008217e,
/* 0x057b: main_not_ctx_chan */
0xb0400ef4,
0x1bf402e4,
0xf094bd2c,
0x00800799,
0x09f60237,
0xf404bd00,
0x32f40132,
0x08817e02,
0xf094bd00,
0x00800799,
0x09f60217,
0xf404bd00,
/* 0x05aa: main_not_ctx_save */
0xef94110e,
0x01f5f010,
0x0002f87e,
0xfee40ef5,
/* 0x05b8: main_done */
0x29f024bd,
0x3000801f,
0x0002f602,
0x0ef504bd,
/* 0x05ca: ih */
0x00f9fed2,
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x02004a04,
0xc400aacf,
0x0bf404ab,
0x4e100d23,
0xeecf1a00,
0x19004f00,
0x7e00ffcf,
0xb7000004,
0x0e0400b0,
0x1d004001,
0xbd000ef6,
/* 0x060d: ih_no_fifo */
0x00abe404,
0x0c0bf401,
0x014e100d,
0x00047e40,
/* 0x061d: ih_no_ctxsw */
0x00abe400,
0x560bf404,
0x4007088e,
0x0000657e,
0x0080ffb2,
0x0ff60204,
0x8e04bd00,
0x7e400704,
0xb2000065,
0x030080ff,
0x000ff602,
0xfec704bd,
0x02ee9450,
0x4007008f,
0x7e00efbb,
0x80000065,
0xf6020200,
0x04bd000f,
0xf87e030f,
0x004b0002,
0x8ebfb201,
0x7e400144,
/* 0x0677: ih_no_fwmthd */
0x4b00008f,
0xb0bd0504,
0xf4b4abff,
0x00800c0b,
0x0bf60307,
/* 0x068b: ih_no_other */
0x4004bd00,
0x0af60100,
0xfc04bd00,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x00fc80fc,
0xf80032f4,
/* 0x06ad: ctx_4170s */
0x10f5f001,
0x708effb2,
0x8f7e4041,
0x00f80000,
/* 0x06bc: ctx_4170w */
0x4041708e,
0x0000657e,
0xf4f0ffb2,
0xf31bf410,
/* 0x06ce: ctx_redswitch */
0x004e00f8,
0x40e5f002,
0xf020e5f0,
0x008010e5,
0x0ef60185,
0x0f04bd00,
/* 0x06e5: ctx_redswitch_delay */
0x01f2b608,
0xf1fd1bf4,
0xf10400e5,
0x800100e5,
0xf6018500,
0x04bd000e,
/* 0x06fe: ctx_86c */
0x008000f8,
0x0ff60223,
0xb204bd00,
0x8a148eff,
0x008f7e40,
0x8effb200,
0x7e41a88c,
0xf800008f,
/* 0x071d: ctx_mem */
0x84008000,
0x000ff602,
/* 0x0726: ctx_mem_wait */
0x008f04bd,
0xffcf0284,
0x05fffd00,
0xf8f61bf4,
/* 0x0735: ctx_load */
0xf094bd00,
0x00800599,
0x09f60237,
0x0a04bd00,
0x00b87e0c,
0x80f4bd00,
0xf6028900,
0x04bd000f,
0x02c10080,
0xbd0002f6,
0x83008004,
0x0002f602,
0x070f04bd,
0x00071d7e,
0x02c00080,
0xbd0002f6,
0x000bfe04,
0xb61f2af0,
0x20b60424,
0xf094bd02,
0x00800899,
0x09f60237,
0x8004bd00,
0xf6028100,
0x04bd0002,
0x000000d2,
0x0225f080,
0x02880080,
0xbd0002f6,
0x42100104,
0x23f00200,
0x0512fa02,
0x94bd03f8,
0x800899f0,
0xf6021700,
0x04bd0009,
0xb6810198,
0x02981814,
0x0825b680,
0xb50512fd,
0x94bd1601,
0x800999f0,
0xf6023700,
0x04bd0009,
0x02810080,
0xbd0001f6,
0x80010204,
0xf6028800,
0x04bd0002,
0xf0010041,
0x01fa0613,
0xbd03f805,
0x0999f094,
0x02170080,
0xbd0009f6,
0xf094bd04,
0x00800599,
0x09f60217,
0xf804bd00,
/* 0x0821: ctx_chan */
0x07357e00,
0x7e0c0a00,
0x0f0000b8,
0x071d7e05,
/* 0x0833: ctx_mmio_exec */
0x9800f800,
0x00804103,
0x03f60281,
0xbd04bd00,
/* 0x0841: ctx_mmio_loop */
0xff34c434,
0x450e1bf4,
0x53f00200,
0x0535fa06,
/* 0x0852: ctx_mmio_pull */
0x4e9803f8,
0x814f9880,
0x00008f7e,
0xb60830b6,
0x1bf40112,
/* 0x0865: ctx_mmio_done */
0x160398df,
0x02810080,
0xbd0003f6,
0x4000b504,
0xf0010041,
0x01fa0613,
0xf803f806,
/* 0x0881: ctx_xfer */
0x80040e00,
0xf6030200,
0x04bd000e,
/* 0x088c: ctx_xfer_idle */
0x0300008e,
0xf100eecf,
0xf42000e4,
0x11f4f51b,
0x0c02f406,
/* 0x08a0: ctx_xfer_pre */
0xfe7e100f,
0x11f40006,
/* 0x08a9: ctx_xfer_pre_load */
0x7e020f1b,
0x7e0006ad,
0x7e0006bc,
0xbd0006ce,
0x06ad7ef4,
0x07357e00,
/* 0x08c1: ctx_xfer_exec */
0x16019800,
0x008024bd,
0x02f60105,
0xb204bd00,
0xa5008e1f,
0x008f7e41,
0x01fcf000,
0xb6022cf0,
0xf2fd0124,
0x8effb205,
0x7e41a504,
0x7e00008f,
0xbd000216,
0x47fc8024,
0x0002f602,
0x2cf004bd,
0x0320b601,
0x024afc80,
0xbd0002f6,
0x01acf004,
0x0b06a5f0,
0x000c9800,
0x0e010d98,
0x013d7e00,
0x7e080a00,
0x7e0000ec,
0xf400020a,
0x0c0a1201,
0x0000b87e,
0x1d7e050f,
0x02f40007,
/* 0x093d: ctx_xfer_post */
0x7e020f2d,
0xbd0006ad,
0x06fe7ef4,
0x02277e00,
0x06bc7e00,
0x7ef4bd00,
0xf40006ad,
0x01981011,
0x0511fd40,
0x7e070bf4,
/* 0x0967: ctx_xfer_no_post_mmio */
/* 0x0967: ctx_xfer_done */
0xf8000833,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5
+40
View File
@@ -0,0 +1,40 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#define CHIPSET GK208
#include "macros.fuc"
.section #gm107_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
.section #gm107_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
#include "hub.fuc"
.align 256
#undef INCLUDE_CODE
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h
+918
View File
@@ -0,0 +1,918 @@
/* SPDX-License-Identifier: MIT */
static uint32_t gm107_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
0x00000304,
/* 0x0008: gpc_count */
0x00000000,
/* 0x000c: rop_count */
0x00000000,
/* 0x0010: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0058: ctx_current */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0100: chan_data */
/* 0x0100: chan_mmio_count */
0x00000000,
/* 0x0104: chan_mmio_address */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0200: xfer_data */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0300: hub_mmio_list_base */
0x0417e91c,
};
static uint32_t gm107_grhub_code[] = {
0x030e0ef5,
/* 0x0004: queue_put */
0x9800d898,
0x86f001d9,
0xf489a408,
0x020f0b1b,
0x0002f87e,
/* 0x001a: queue_put_next */
0x98c400f8,
0x0384b607,
0xb6008dbb,
0x8eb50880,
0x018fb500,
0xf00190b6,
0xd9b50f94,
/* 0x0037: queue_get */
0xf400f801,
0xd8980131,
0x01d99800,
0x0bf489a4,
0x0789c421,
0xbb0394b6,
0x90b6009d,
0x009e9808,
0xb6019f98,
0x84f00180,
0x00d8b50f,
/* 0x0063: queue_get_done */
0xf80132f4,
/* 0x0065: nv_rd32 */
0xf0ecb200,
0x00801fc9,
0x0cf601ca,
/* 0x0073: nv_rd32_wait */
0x8c04bd00,
0xcf01ca00,
0xccc800cc,
0xf61bf41f,
0xec7e060a,
0x008f0000,
0xffcf01cb,
/* 0x008f: nv_wr32 */
0x8000f800,
0xf601cc00,
0x04bd000f,
0xc9f0ecb2,
0x1ec9f01f,
0x01ca0080,
0xbd000cf6,
/* 0x00a9: nv_wr32_wait */
0xca008c04,
0x00cccf01,
0xf41fccc8,
0x00f8f61b,
/* 0x00b8: wait_donez */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x00cf: wait_donez_ne */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf61bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x00ec: wait_doneo */
0x99f094bd,
0x37008000,
0x0009f602,
0x008004bd,
0x0af60206,
/* 0x0103: wait_doneo_e */
0x8804bd00,
0xcf010000,
0x8aff0088,
0xf60bf488,
0x99f094bd,
0x17008000,
0x0009f602,
0x00f804bd,
/* 0x0120: mmctx_size */
/* 0x0122: nv_mmctx_size_loop */
0xe89894bd,
0x1a85b600,
0xb60180b6,
0x98bb0284,
0x04e0b600,
0x1bf4efa4,
0xf89fb2ec,
/* 0x013d: mmctx_xfer */
0xf094bd00,
0x00800199,
0x09f60237,
0xbd04bd00,
0x05bbfd94,
0x800f0bf4,
0xf601c400,
0x04bd000b,
/* 0x015f: mmctx_base_disabled */
0xfd0099f0,
0x0bf405ee,
0xc6008018,
0x000ef601,
0x008004bd,
0x0ff601c7,
0xf004bd00,
/* 0x017a: mmctx_multi_disabled */
0xabc80199,
0x10b4b600,
0xc80cb9f0,
0xe4b601ae,
0x05befd11,
0x01c50080,
0xbd000bf6,
/* 0x0195: mmctx_exec_loop */
/* 0x0195: mmctx_wait_free */
0xc5008e04,
0x00eecf01,
0xf41fe4f0,
0xce98f60b,
0x05e9fd00,
0x01c80080,
0xbd000ef6,
0x04c0b604,
0x1bf4cda4,
0x02abc8df,
/* 0x01bf: mmctx_fini_wait */
0x8b1c1bf4,
0xcf01c500,
0xb4f000bb,
0x10b4b01f,
0x0af31bf4,
0x00b87e05,
0x250ef400,
/* 0x01d8: mmctx_stop */
0xb600abc8,
0xb9f010b4,
0x12b9f00c,
0x01c50080,
0xbd000bf6,
/* 0x01ed: mmctx_stop_wait */
0xc5008b04,
0x00bbcf01,
0xf412bbc8,
/* 0x01fa: mmctx_done */
0x94bdf61b,
0x800199f0,
0xf6021700,
0x04bd0009,
/* 0x020a: strand_wait */
0xa0f900f8,
0xb87e020a,
0xa0fc0000,
/* 0x0216: strand_pre */
0x0c0900f8,
0x024afc80,
0xbd0009f6,
0x020a7e04,
/* 0x0227: strand_post */
0x0900f800,
0x4afc800d,
0x0009f602,
0x0a7e04bd,
0x00f80002,
/* 0x0238: strand_set */
0xfc800f0c,
0x0cf6024f,
0x0c04bd00,
0x4afc800b,
0x000cf602,
0xfc8004bd,
0x0ef6024f,
0x0c04bd00,
0x4afc800a,
0x000cf602,
0x0a7e04bd,
0x00f80002,
/* 0x0268: strand_ctx_init */
0x99f094bd,
0x37008003,
0x0009f602,
0x167e04bd,
0x030e0002,
0x0002387e,
0xfc80c4bd,
0x0cf60247,
0x0c04bd00,
0x4afc8001,
0x000cf602,
0x0a7e04bd,
0x0c920002,
0x46fc8001,
0x000cf602,
0x020c04bd,
0x024afc80,
0xbd000cf6,
0x020a7e04,
0x02277e00,
0x42008800,
0x20008902,
0x0099cf02,
/* 0x02c7: ctx_init_strand_loop */
0xf608fe95,
0x8ef6008e,
0x808acf40,
0xb606a5b6,
0xeabb01a0,
0x0480b600,
0xf40192b6,
0xe4b6e81b,
0xf2efbc08,
0x99f094bd,
0x17008003,
0x0009f602,
0x00f804bd,
/* 0x02f8: error */
0x02050080,
0xbd000ff6,
0x80010f04,
0xf6030700,
0x04bd000f,
/* 0x030e: init */
0x04bd00f8,
0x410007fe,
0x11cf4200,
0x0911e700,
0x0814b601,
0x020014fe,
0x12004002,
0xbd0002f6,
0x05ca4104,
0xbd0010fe,
0x07004024,
0xbd0002f6,
0x20034204,
0x01010080,
0xbd0002f6,
0x20044204,
0x01010480,
0xbd0002f6,
0x200b4204,
0x01010880,
0xbd0002f6,
0x200c4204,
0x01011c80,
0xbd0002f6,
0x01039204,
0x03090080,
0xbd0003f6,
0x87048204,
0x04004000,
0xbd0002f6,
0x40040204,
0x02f60300,
0xf404bd00,
0x048e1031,
0x657e4096,
0xfeb20000,
0xb590f1c7,
0xf4f00301,
0x020fb51f,
0x1fbb0101,
0x0112b604,
0x01030080,
0xbd0001f6,
0x04008004,
0x0001f601,
0x004104bd,
0x7e020f01,
0x7e0006ad,
0x0f0006bc,
0x06fe7e10,
0x000e9800,
0x7e010f98,
0x95000120,
0x00800814,
0x04f601c0,
0x8004bd00,
0xf601c100,
0x04bd0004,
0x130030b7,
0xb6001fbb,
0x008002f5,
0x0ff601d3,
0xb604bd00,
0x10b60815,
0x0814b601,
0x687e1fb2,
0x1fbb0002,
0x02039800,
0x50200084,
/* 0x0420: init_gpc */
0x08044eb8,
0x7e1fb200,
0xb800008f,
0x00010c4e,
0x8f7ef4bd,
0x4eb80000,
0x7e000104,
0xb800008f,
0x0001004e,
0x8f7e020f,
0x4eb80000,
/* 0x044f: init_gpc_wait */
0x7e000800,
0xc8000065,
0x0bf41fff,
0x044eb8f9,
0x657e0008,
0x1fbb0000,
0x0040b700,
0x0132b680,
0x0fb41bf4,
0x06fe7e00,
0x7e000f00,
0x800006ad,
0xf6020100,
0x04bd0001,
0x19f014bd,
0x3000801f,
0x0001f602,
/* 0x0492: wait */
0x28f404bd,
0x0031f400,
/* 0x0498: main */
0x377e100d,
0x01f40000,
0x01e4b1f4,
0xc71bf540,
0xf094bd00,
0x00800499,
0x09f60237,
0x8104bd00,
0xcf02c000,
0x00820011,
0x22cf02c1,
0x1f13c800,
0xc8770bf4,
0x0bf41f23,
0xb220f955,
0xf094bd12,
0x00800799,
0x09f60237,
0xf404bd00,
0x31f40132,
0x08817e02,
0xf094bd00,
0x00800799,
0x09f60217,
0xfc04bd00,
0xf094bd20,
0x00800699,
0x09f60237,
0xf404bd00,
0x817e0131,
0x94bd0008,
0x800699f0,
0xf6021700,
0x04bd0009,
/* 0x0523: chsw_prev_no_next */
0xf92f0ef4,
0xf412b220,
0x32f40132,
0x08817e02,
0x8020fc00,
0xf602c000,
0x04bd0002,
/* 0x053f: chsw_no_prev */
0xc8130ef4,
0x0bf41f23,
0x0131f40d,
0x7e0232f4,
/* 0x054f: chsw_done */
0x02000881,
0xc3008001,
0x0002f602,
0x94bd04bd,
0x800499f0,
0xf6021700,
0x04bd0009,
0xff300ef5,
/* 0x056c: main_not_ctx_switch */
0xf401e4b0,
0xf2b20c1b,
0x0008217e,
/* 0x057b: main_not_ctx_chan */
0xb0400ef4,
0x1bf402e4,
0xf094bd2c,
0x00800799,
0x09f60237,
0xf404bd00,
0x32f40132,
0x08817e02,
0xf094bd00,
0x00800799,
0x09f60217,
0xf404bd00,
/* 0x05aa: main_not_ctx_save */
0xef94110e,
0x01f5f010,
0x0002f87e,
0xfee40ef5,
/* 0x05b8: main_done */
0x29f024bd,
0x3000801f,
0x0002f602,
0x0ef504bd,
/* 0x05ca: ih */
0x00f9fed2,
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x02004a04,
0xc400aacf,
0x0bf404ab,
0x4e100d23,
0xeecf1a00,
0x19004f00,
0x7e00ffcf,
0xb7000004,
0x0e0400b0,
0x1d004001,
0xbd000ef6,
/* 0x060d: ih_no_fifo */
0x00abe404,
0x0c0bf401,
0x014e100d,
0x00047e40,
/* 0x061d: ih_no_ctxsw */
0x00abe400,
0x560bf404,
0x4007088e,
0x0000657e,
0x0080ffb2,
0x0ff60204,
0x8e04bd00,
0x7e400704,
0xb2000065,
0x030080ff,
0x000ff602,
0xfec704bd,
0x02ee9450,
0x4007008f,
0x7e00efbb,
0x80000065,
0xf6020200,
0x04bd000f,
0xf87e030f,
0x004b0002,
0x8ebfb201,
0x7e400144,
/* 0x0677: ih_no_fwmthd */
0x4b00008f,
0xb0bd0504,
0xf4b4abff,
0x00800c0b,
0x0bf60307,
/* 0x068b: ih_no_other */
0x4004bd00,
0x0af60100,
0xfc04bd00,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x00fc80fc,
0xf80032f4,
/* 0x06ad: ctx_4170s */
0x10f5f001,
0x708effb2,
0x8f7e4041,
0x00f80000,
/* 0x06bc: ctx_4170w */
0x4041708e,
0x0000657e,
0xf4f0ffb2,
0xf31bf410,
/* 0x06ce: ctx_redswitch */
0x004e00f8,
0x40e5f002,
0xf020e5f0,
0x008010e5,
0x0ef60185,
0x0f04bd00,
/* 0x06e5: ctx_redswitch_delay */
0x01f2b608,
0xf1fd1bf4,
0xf10400e5,
0x800100e5,
0xf6018500,
0x04bd000e,
/* 0x06fe: ctx_86c */
0x008000f8,
0x0ff60223,
0xb204bd00,
0x8a148eff,
0x008f7e40,
0x8effb200,
0x7e41a88c,
0xf800008f,
/* 0x071d: ctx_mem */
0x84008000,
0x000ff602,
/* 0x0726: ctx_mem_wait */
0x008f04bd,
0xffcf0284,
0x05fffd00,
0xf8f61bf4,
/* 0x0735: ctx_load */
0xf094bd00,
0x00800599,
0x09f60237,
0x0a04bd00,
0x00b87e0c,
0x80f4bd00,
0xf6028900,
0x04bd000f,
0x02c10080,
0xbd0002f6,
0x83008004,
0x0002f602,
0x070f04bd,
0x00071d7e,
0x02c00080,
0xbd0002f6,
0x000bfe04,
0xb61f2af0,
0x20b60424,
0xf094bd02,
0x00800899,
0x09f60237,
0x8004bd00,
0xf6028100,
0x04bd0002,
0x000000d2,
0x0225f080,
0x02880080,
0xbd0002f6,
0x42100104,
0x23f00200,
0x0512fa02,
0x94bd03f8,
0x800899f0,
0xf6021700,
0x04bd0009,
0xb6810198,
0x02981814,
0x0825b680,
0xb50512fd,
0x94bd1601,
0x800999f0,
0xf6023700,
0x04bd0009,
0x02810080,
0xbd0001f6,
0x80010204,
0xf6028800,
0x04bd0002,
0xf0010041,
0x01fa0613,
0xbd03f805,
0x0999f094,
0x02170080,
0xbd0009f6,
0xf094bd04,
0x00800599,
0x09f60217,
0xf804bd00,
/* 0x0821: ctx_chan */
0x07357e00,
0x7e0c0a00,
0x0f0000b8,
0x071d7e05,
/* 0x0833: ctx_mmio_exec */
0x9800f800,
0x00804103,
0x03f60281,
0xbd04bd00,
/* 0x0841: ctx_mmio_loop */
0xff34c434,
0x450e1bf4,
0x53f00200,
0x0535fa06,
/* 0x0852: ctx_mmio_pull */
0x4e9803f8,
0x814f9880,
0x00008f7e,
0xb60830b6,
0x1bf40112,
/* 0x0865: ctx_mmio_done */
0x160398df,
0x02810080,
0xbd0003f6,
0x4000b504,
0xf0010041,
0x01fa0613,
0xf803f806,
/* 0x0881: ctx_xfer */
0x80040e00,
0xf6030200,
0x04bd000e,
/* 0x088c: ctx_xfer_idle */
0x0300008e,
0xf100eecf,
0xf42000e4,
0x11f4f51b,
0x0c02f406,
/* 0x08a0: ctx_xfer_pre */
0xfe7e100f,
0x11f40006,
/* 0x08a9: ctx_xfer_pre_load */
0x7e020f1b,
0x7e0006ad,
0x7e0006bc,
0xbd0006ce,
0x06ad7ef4,
0x07357e00,
/* 0x08c1: ctx_xfer_exec */
0x16019800,
0x008024bd,
0x02f60105,
0xb204bd00,
0xa5008e1f,
0x008f7e41,
0x01fcf000,
0xb6022cf0,
0xf2fd0124,
0x8effb205,
0x7e41a504,
0x7e00008f,
0xbd000216,
0x47fc8024,
0x0002f602,
0x2cf004bd,
0x0320b601,
0x024afc80,
0xbd0002f6,
0x01acf004,
0x0b06a5f0,
0x000c9800,
0x0e010d98,
0x013d7e00,
0x7e080a00,
0x7e0000ec,
0xf400020a,
0x0c0a1201,
0x0000b87e,
0x1d7e050f,
0x02f40007,
/* 0x093d: ctx_xfer_post */
0x7e020f2d,
0xbd0006ad,
0x06fe7ef4,
0x02277e00,
0x06bc7e00,
0x7ef4bd00,
0xf40006ad,
0x01981011,
0x0511fd40,
0x7e070bf4,
/* 0x0967: ctx_xfer_no_post_mmio */
/* 0x0967: ctx_xfer_done */
0xf8000833,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc
+261
View File
@@ -0,0 +1,261 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "os.h"
#define GF100 0xc0
#define GF117 0xd7
#define GK100 0xe0
#define GK110 0xf0
#define GK208 0x108
#define GM107 0x117
#define NV_PGRAPH_TRAPPED_ADDR 0x400704
#define NV_PGRAPH_TRAPPED_DATA_LO 0x400708
#define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c
#define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700)
#define NV_PGRAPH_FECS_INTR_ACK 0x409004
#define NV_PGRAPH_FECS_INTR 0x409008
#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400
#define NV_PGRAPH_FECS_INTR_CHSW 0x00000100
#define NV_PGRAPH_FECS_INTR_FIFO 0x00000004
#define NV_PGRAPH_FECS_INTR_MODE 0x40900c
#define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004
#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004
#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000
#define NV_PGRAPH_FECS_INTR_EN_SET 0x409010
#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004
#define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c
#define NV_PGRAPH_FECS_ACCESS 0x409048
#define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002
#define NV_PGRAPH_FECS_FIFO_DATA 0x409064
#define NV_PGRAPH_FECS_FIFO_CMD 0x409068
#define NV_PGRAPH_FECS_FIFO_ACK 0x409074
#define NV_PGRAPH_FECS_CAPS 0x409108
#define NV_PGRAPH_FECS_SIGNAL 0x409400
#define NV_PGRAPH_FECS_IROUTE 0x409404
#define NV_PGRAPH_FECS_BAR_MASK0 0x40940c
#define NV_PGRAPH_FECS_BAR_MASK1 0x409410
#define NV_PGRAPH_FECS_BAR 0x409414
#define NV_PGRAPH_FECS_BAR_SET 0x409418
#define NV_PGRAPH_FECS_RED_SWITCH 0x409614
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200
#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020
#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010
#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002
#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001
#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700
#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700
#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704
#define NV_PGRAPH_FECS_MMCTX_BASE 0x409710
#define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714
#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718
#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c
#define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720
#define NV_PGRAPH_FECS_MMIO_BASE 0x409724
#define NV_PGRAPH_FECS_MMIO_CTRL 0x409728
#define NV_PGRAPH_FECS_MMIO_CTRL_BASE_ENABLE 0x00000001
#define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c
#define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
#if CHIPSET < GK110
#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820)
#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
#define NV_PGRAPH_FECS_UNK86C 0x40986c
#else
#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
#define NV_PGRAPH_FECS_UNK86C 0x40988c
#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0)
#endif
#define NV_PGRAPH_FECS_STRANDS_CNT 0x409880
#define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908
#define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c
#define NV_PGRAPH_FECS_STRAND_WORDS 0x409910
#define NV_PGRAPH_FECS_STRAND_DATA 0x409918
#define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c
#define NV_PGRAPH_FECS_STRAND_CMD 0x409928
#define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001
#define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002
#define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a
#define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b
#define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c
#define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d
#define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c
#define NV_PGRAPH_FECS_MEM_BASE 0x409a04
#define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c
#define NV_PGRAPH_FECS_MEM_CMD 0x409a10
#define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007
#define NV_PGRAPH_FECS_MEM_TARGET 0x409a20
#define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000
#define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f
#define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001
#define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002
#define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00
#define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04
#define NV_PGRAPH_FECS_CHSW 0x409b0c
#define NV_PGRAPH_FECS_CHSW_ACK 0x00000001
#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c
#define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24
#define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004
#define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008
#define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010
#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c
#define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048
#define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002
#define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064
#define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068
#define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074
#define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608
#define NV_PGRAPH_GPCX_GPCCS_CAPS 0x41a108
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020
#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002
#define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704
#define NV_PGRAPH_GPCX_GPCCS_MMIO_BASE 0x41a724
#define NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL 0x41a728
#define NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE 0x00000001
#define NV_PGRAPH_GPCX_GPCCS_MMIO_RDVAL 0x41a72c
#define NV_PGRAPH_GPCX_GPCCS_MMIO_WRVAL 0x41a730
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c
#if CHIPSET < GK110
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820)
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c
#else
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0)
#endif
#define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04
#define NV_PGRAPH_GPCX_GPCCS_TPC_STATUS 0x41acfc
#define NV_PGRAPH_GPC0_TPC0 0x504000
#define NV_PGRAPH_GPC0_TPC0__SIZE 0x000800
#define NV_PGRAPH_GPC0_TPCX_STRAND_INDEX 0x501d60
#define NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL 0x0000003f
#define NV_PGRAPH_GPC0_TPCX_STRAND_DATA 0x501d98
#define NV_PGRAPH_GPC0_TPCX_STRAND_SELECT 0x501d9c
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD 0x501da8
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK 0x00000001
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO 0x00000002
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE 0x0000000c
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE 0x0000000d
#define NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE 0x501dc4
#define NV_TPC_STRAND_INDEX 0x560
#define NV_TPC_STRAND_CNT 0x570
#define NV_TPC_STRAND_SAVE_SWBASE 0x588
#define NV_TPC_STRAND_LOAD_SWBASE 0x58c
#define NV_TPC_STRAND_WORDS 0x590
#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2)
#define T_WAIT 0
#define T_MMCTX 1
#define T_STRWAIT 2
#define T_STRINIT 3
#define T_AUTO 4
#define T_CHAN 5
#define T_LOAD 6
#define T_SAVE 7
#define T_LCHAN 8
#define T_LCTXH 9
#define T_STRTPC 10
#if CHIPSET < GK208
#define imm32(reg,val) /*
*/ movw reg ((val) & 0x0000ffff) /*
*/ sethi reg ((val) & 0xffff0000)
#else
#define imm32(reg,val) /*
*/ mov reg (val)
#endif
#define nv_mkio(rv,r,i) /*
*/ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2))
#define hash #
#define fn(a) a
#if CHIPSET < GK208
#define call(a) call fn(hash)a
#else
#define call(a) lcall fn(hash)a
#endif
#define nv_iord(rv,r,i) /*
*/ nv_mkio(rv,r,i) /*
*/ iord rv I[rv]
#define nv_iowr(r,i,rv) /*
*/ nv_mkio($r0,r,i) /*
*/ iowr I[$r0] rv /*
*/ clear b32 $r0
#define nv_rd32(reg,addr) /*
*/ imm32($r14, addr) /*
*/ call(nv_rd32) /*
*/ mov b32 reg $r15
#define nv_wr32(addr,reg) /*
*/ mov b32 $r15 reg /*
*/ imm32($r14, addr) /*
*/ call(nv_wr32)
#define trace_set(bit) /*
*/ clear b32 $r9 /*
*/ bset $r9 bit /*
*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9)
#define trace_clr(bit) /*
*/ clear b32 $r9 /*
*/ bset $r9 bit /*
*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9)
linux-7.2.3/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h
+9
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@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_GRAPH_OS_H__
#define __NVKM_GRAPH_OS_H__
#define E_BAD_COMMAND 0x00000001
#define E_CMD_OVERFLOW 0x00000002
#define E_BAD_FWMTHD 0x00000003
#endif