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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/gpu/drm/sprd/Kconfig
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config DRM_SPRD
tristate "DRM Support for Unisoc SoCs Platform"
depends on ARCH_SPRD || COMPILE_TEST
depends on DRM && OF
select DRM_GEM_DMA_HELPER
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
help
Choose this option if you have a Unisoc chipset.
If M is selected the module will be called sprd_drm.
linux-7.2.3/drivers/gpu/drm/sprd/Makefile
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# SPDX-License-Identifier: GPL-2.0
sprd-drm-y := sprd_drm.o \
sprd_dpu.o \
sprd_dsi.o \
megacores_pll.o
obj-$(CONFIG_DRM_SPRD) += sprd-drm.o
linux-7.2.3/drivers/gpu/drm/sprd/megacores_pll.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Unisoc Inc.
*/
#include <asm/div64.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/regmap.h>
#include <linux/string.h>
#include "sprd_dsi.h"
#define L 0
#define H 1
#define CLK 0
#define DATA 1
#define INFINITY 0xffffffff
#define MIN_OUTPUT_FREQ (100)
#define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
/* sharkle */
#define VCO_BAND_LOW 750
#define VCO_BAND_MID 1100
#define VCO_BAND_HIGH 1500
#define PHY_REF_CLK 26000
static int dphy_calc_pll_param(struct dphy_pll *pll)
{
const u32 khz = 1000;
const u32 mhz = 1000000;
const unsigned long long factor = 100;
unsigned long long tmp;
int i;
pll->potential_fvco = pll->freq / khz;
pll->ref_clk = PHY_REF_CLK / khz;
for (i = 0; i < 4; ++i) {
if (pll->potential_fvco >= VCO_BAND_LOW &&
pll->potential_fvco <= VCO_BAND_HIGH) {
pll->fvco = pll->potential_fvco;
pll->out_sel = BIT(i);
break;
}
pll->potential_fvco <<= 1;
}
if (pll->fvco == 0)
return -EINVAL;
if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
/* vco band control */
pll->vco_band = 0x0;
/* low pass filter control */
pll->lpf_sel = 1;
} else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
pll->vco_band = 0x1;
pll->lpf_sel = 0;
} else {
return -EINVAL;
}
pll->nint = pll->fvco / pll->ref_clk;
tmp = pll->fvco * factor * mhz;
do_div(tmp, pll->ref_clk);
tmp = tmp - pll->nint * factor * mhz;
tmp *= BIT(20);
do_div(tmp, 100000000);
pll->kint = (u32)tmp;
pll->refin = 3; /* pre-divider bypass */
pll->sdm_en = true; /* use fraction N PLL */
pll->fdk_s = 0x1; /* fraction */
pll->cp_s = 0x0;
pll->det_delay = 0x1;
return 0;
}
static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
{
u8 reg_val[9] = {0};
int i;
u8 reg_addr[] = {
0x03, 0x04, 0x06, 0x08, 0x09,
0x0a, 0x0b, 0x0e, 0x0f
};
reg_val[0] = 1 | (1 << 1) | (pll->lpf_sel << 2);
reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7);
reg_val[2] = pll->nint;
reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2);
reg_val[4] = pll->kint >> 12;
reg_val[5] = pll->kint >> 4;
reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
reg_val[7] = 1 << 4;
reg_val[8] = pll->det_delay;
for (i = 0; i < sizeof(reg_addr); ++i) {
regmap_write(regmap, reg_addr[i], reg_val[i]);
DRM_DEBUG("%02x: %02x\n", reg_addr[i], reg_val[i]);
}
}
int dphy_pll_config(struct dsi_context *ctx)
{
struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
struct regmap *regmap = ctx->regmap;
struct dphy_pll *pll = &ctx->pll;
int ret;
pll->freq = dsi->slave->hs_rate;
/* FREQ = 26M * (NINT + KINT / 2^20) / out_sel */
ret = dphy_calc_pll_param(pll);
if (ret) {
drm_err(dsi->drm, "failed to calculate dphy pll parameters\n");
return ret;
}
dphy_set_pll_reg(pll, regmap);
return 0;
}
static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
{
switch (type) {
case REQUEST_TIME:
regmap_write(regmap, 0x31, val[CLK]);
regmap_write(regmap, 0x41, val[DATA]);
regmap_write(regmap, 0x51, val[DATA]);
regmap_write(regmap, 0x61, val[DATA]);
regmap_write(regmap, 0x71, val[DATA]);
regmap_write(regmap, 0x90, val[CLK]);
regmap_write(regmap, 0xa0, val[DATA]);
regmap_write(regmap, 0xb0, val[DATA]);
regmap_write(regmap, 0xc0, val[DATA]);
regmap_write(regmap, 0xd0, val[DATA]);
break;
case PREPARE_TIME:
regmap_write(regmap, 0x32, val[CLK]);
regmap_write(regmap, 0x42, val[DATA]);
regmap_write(regmap, 0x52, val[DATA]);
regmap_write(regmap, 0x62, val[DATA]);
regmap_write(regmap, 0x72, val[DATA]);
regmap_write(regmap, 0x91, val[CLK]);
regmap_write(regmap, 0xa1, val[DATA]);
regmap_write(regmap, 0xb1, val[DATA]);
regmap_write(regmap, 0xc1, val[DATA]);
regmap_write(regmap, 0xd1, val[DATA]);
break;
case ZERO_TIME:
regmap_write(regmap, 0x33, val[CLK]);
regmap_write(regmap, 0x43, val[DATA]);
regmap_write(regmap, 0x53, val[DATA]);
regmap_write(regmap, 0x63, val[DATA]);
regmap_write(regmap, 0x73, val[DATA]);
regmap_write(regmap, 0x92, val[CLK]);
regmap_write(regmap, 0xa2, val[DATA]);
regmap_write(regmap, 0xb2, val[DATA]);
regmap_write(regmap, 0xc2, val[DATA]);
regmap_write(regmap, 0xd2, val[DATA]);
break;
case TRAIL_TIME:
regmap_write(regmap, 0x34, val[CLK]);
regmap_write(regmap, 0x44, val[DATA]);
regmap_write(regmap, 0x54, val[DATA]);
regmap_write(regmap, 0x64, val[DATA]);
regmap_write(regmap, 0x74, val[DATA]);
regmap_write(regmap, 0x93, val[CLK]);
regmap_write(regmap, 0xa3, val[DATA]);
regmap_write(regmap, 0xb3, val[DATA]);
regmap_write(regmap, 0xc3, val[DATA]);
regmap_write(regmap, 0xd3, val[DATA]);
break;
case EXIT_TIME:
regmap_write(regmap, 0x36, val[CLK]);
regmap_write(regmap, 0x46, val[DATA]);
regmap_write(regmap, 0x56, val[DATA]);
regmap_write(regmap, 0x66, val[DATA]);
regmap_write(regmap, 0x76, val[DATA]);
regmap_write(regmap, 0x95, val[CLK]);
regmap_write(regmap, 0xA5, val[DATA]);
regmap_write(regmap, 0xB5, val[DATA]);
regmap_write(regmap, 0xc5, val[DATA]);
regmap_write(regmap, 0xd5, val[DATA]);
break;
case CLKPOST_TIME:
regmap_write(regmap, 0x35, val[CLK]);
regmap_write(regmap, 0x94, val[CLK]);
break;
/* the following just use default value */
case SETTLE_TIME:
fallthrough;
case TA_GET:
fallthrough;
case TA_GO:
fallthrough;
case TA_SURE:
fallthrough;
default:
break;
}
}
void dphy_timing_config(struct dsi_context *ctx)
{
struct regmap *regmap = ctx->regmap;
struct dphy_pll *pll = &ctx->pll;
const u32 factor = 2;
const u32 scale = 100;
u32 t_ui, t_byteck, t_half_byteck;
u32 range[2], constant;
u8 val[2];
u32 tmp = 0;
/* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */
t_ui = 1000 * scale / (pll->freq / 1000);
t_byteck = t_ui << 3;
t_half_byteck = t_ui << 2;
constant = t_ui << 1;
/* REQUEST_TIME: HS T-LPX: LP-01
* For T-LPX, mipi spec defined min value is 50ns,
* but maybe it shouldn't be too small, because BTA,
* LP-10, LP-00, LP-01, all of this is related to T-LPX.
*/
range[L] = 50 * scale;
range[H] = INFINITY;
val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
val[DATA] = val[CLK];
dphy_set_timing_reg(regmap, REQUEST_TIME, val);
/* PREPARE_TIME: HS sequence: LP-00 */
range[L] = 38 * scale;
range[H] = 95 * scale;
tmp = AVERAGE(range[L], range[H]);
val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;
range[L] = 40 * scale + 4 * t_ui;
range[H] = 85 * scale + 6 * t_ui;
tmp |= AVERAGE(range[L], range[H]) << 16;
val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;
dphy_set_timing_reg(regmap, PREPARE_TIME, val);
/* ZERO_TIME: HS-ZERO */
range[L] = 300 * scale;
range[H] = INFINITY;
val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
- 525 * t_byteck / 100, t_byteck) - 2;
range[L] = 145 * scale + 10 * t_ui;
val[DATA] = DIV_ROUND_UP(range[L] * factor
+ ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100,
t_byteck) - 2;
dphy_set_timing_reg(regmap, ZERO_TIME, val);
/* TRAIL_TIME: HS-TRAIL */
range[L] = 60 * scale;
range[H] = INFINITY;
val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui);
val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;
dphy_set_timing_reg(regmap, TRAIL_TIME, val);
/* EXIT_TIME: */
range[L] = 100 * scale;
range[H] = INFINITY;
val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
val[DATA] = val[CLK];
dphy_set_timing_reg(regmap, EXIT_TIME, val);
/* CLKPOST_TIME: */
range[L] = 60 * scale + 52 * t_ui;
range[H] = INFINITY;
val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
val[DATA] = val[CLK];
dphy_set_timing_reg(regmap, CLKPOST_TIME, val);
/* SETTLE_TIME:
* This time is used for receiver. So for transmitter,
* it can be ignored.
*/
/* TA_GO:
* transmitter drives bridge state(LP-00) before releasing control,
* reg 0x1f default value: 0x04, which is good.
*/
/* TA_SURE:
* After LP-10 state and before bridge state(LP-00),
* reg 0x20 default value: 0x01, which is good.
*/
/* TA_GET:
* receiver drives Bridge state(LP-00) before releasing control
* reg 0x21 default value: 0x03, which is good.
*/
}
linux-7.2.3/drivers/gpu/drm/sprd/sprd_dpu.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Unisoc Inc.
*/
#include <linux/component.h>
#include <linux/delay.h>
#include <linux/dma-buf.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_blend.h>
#include <drm/drm_fb_dma_helper.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include "sprd_drm.h"
#include "sprd_dpu.h"
#include "sprd_dsi.h"
/* Global control registers */
#define REG_DPU_CTRL 0x04
#define REG_DPU_CFG0 0x08
#define REG_PANEL_SIZE 0x20
#define REG_BLEND_SIZE 0x24
#define REG_BG_COLOR 0x2C
/* Layer0 control registers */
#define REG_LAY_BASE_ADDR0 0x30
#define REG_LAY_BASE_ADDR1 0x34
#define REG_LAY_BASE_ADDR2 0x38
#define REG_LAY_CTRL 0x40
#define REG_LAY_SIZE 0x44
#define REG_LAY_PITCH 0x48
#define REG_LAY_POS 0x4C
#define REG_LAY_ALPHA 0x50
#define REG_LAY_CROP_START 0x5C
/* Interrupt control registers */
#define REG_DPU_INT_EN 0x1E0
#define REG_DPU_INT_CLR 0x1E4
#define REG_DPU_INT_STS 0x1E8
/* DPI control registers */
#define REG_DPI_CTRL 0x1F0
#define REG_DPI_H_TIMING 0x1F4
#define REG_DPI_V_TIMING 0x1F8
/* MMU control registers */
#define REG_MMU_EN 0x800
#define REG_MMU_VPN_RANGE 0x80C
#define REG_MMU_PPN1 0x83C
#define REG_MMU_RANGE1 0x840
#define REG_MMU_PPN2 0x844
#define REG_MMU_RANGE2 0x848
/* Global control bits */
#define BIT_DPU_RUN BIT(0)
#define BIT_DPU_STOP BIT(1)
#define BIT_DPU_REG_UPDATE BIT(2)
#define BIT_DPU_IF_EDPI BIT(0)
/* Layer control bits */
#define BIT_DPU_LAY_EN BIT(0)
#define BIT_DPU_LAY_LAYER_ALPHA (0x01 << 2)
#define BIT_DPU_LAY_COMBO_ALPHA (0x02 << 2)
#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE (0x00 << 4)
#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE (0x01 << 4)
#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE (0x02 << 4)
#define BIT_DPU_LAY_FORMAT_ARGB8888 (0x03 << 4)
#define BIT_DPU_LAY_FORMAT_RGB565 (0x04 << 4)
#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3 (0x00 << 8)
#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0 (0x01 << 8)
#define BIT_DPU_LAY_NO_SWITCH (0x00 << 10)
#define BIT_DPU_LAY_RB_OR_UV_SWITCH (0x01 << 10)
#define BIT_DPU_LAY_MODE_BLEND_NORMAL (0x00 << 16)
#define BIT_DPU_LAY_MODE_BLEND_PREMULT (0x01 << 16)
#define BIT_DPU_LAY_ROTATION_0 (0x00 << 20)
#define BIT_DPU_LAY_ROTATION_90 (0x01 << 20)
#define BIT_DPU_LAY_ROTATION_180 (0x02 << 20)
#define BIT_DPU_LAY_ROTATION_270 (0x03 << 20)
#define BIT_DPU_LAY_ROTATION_0_M (0x04 << 20)
#define BIT_DPU_LAY_ROTATION_90_M (0x05 << 20)
#define BIT_DPU_LAY_ROTATION_180_M (0x06 << 20)
#define BIT_DPU_LAY_ROTATION_270_M (0x07 << 20)
/* Interrupt control & status bits */
#define BIT_DPU_INT_DONE BIT(0)
#define BIT_DPU_INT_TE BIT(1)
#define BIT_DPU_INT_ERR BIT(2)
#define BIT_DPU_INT_UPDATE_DONE BIT(4)
#define BIT_DPU_INT_VSYNC BIT(5)
/* DPI control bits */
#define BIT_DPU_EDPI_TE_EN BIT(8)
#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD BIT(10)
#define BIT_DPU_DPI_HALT_EN BIT(16)
static const u32 layer_fmts[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_RGB565,
DRM_FORMAT_BGR565,
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_NV16,
DRM_FORMAT_NV61,
DRM_FORMAT_YUV420,
DRM_FORMAT_YVU420,
};
struct sprd_plane {
struct drm_plane base;
};
static int dpu_wait_stop_done(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
int rc;
if (ctx->stopped)
return 0;
rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
msecs_to_jiffies(500));
ctx->evt_stop = false;
ctx->stopped = true;
if (!rc) {
drm_err(dpu->drm, "dpu wait for stop done time out!\n");
return -ETIMEDOUT;
}
return 0;
}
static int dpu_wait_update_done(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
int rc;
ctx->evt_update = false;
rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
msecs_to_jiffies(500));
if (!rc) {
drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
return -ETIMEDOUT;
}
return 0;
}
static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
{
u32 format = 0;
switch (fb->format->format) {
case DRM_FORMAT_BGRA8888:
/* BGRA8888 -> ARGB8888 */
format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
format |= BIT_DPU_LAY_FORMAT_ARGB8888;
break;
case DRM_FORMAT_RGBX8888:
case DRM_FORMAT_RGBA8888:
/* RGBA8888 -> ABGR8888 */
format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
fallthrough;
case DRM_FORMAT_ABGR8888:
/* RB switch */
format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
fallthrough;
case DRM_FORMAT_ARGB8888:
format |= BIT_DPU_LAY_FORMAT_ARGB8888;
break;
case DRM_FORMAT_XBGR8888:
/* RB switch */
format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
fallthrough;
case DRM_FORMAT_XRGB8888:
format |= BIT_DPU_LAY_FORMAT_ARGB8888;
break;
case DRM_FORMAT_BGR565:
/* RB switch */
format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
fallthrough;
case DRM_FORMAT_RGB565:
format |= BIT_DPU_LAY_FORMAT_RGB565;
break;
case DRM_FORMAT_NV12:
/* 2-Lane: Yuv420 */
format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
/* Y endian */
format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
/* UV endian */
format |= BIT_DPU_LAY_NO_SWITCH;
break;
case DRM_FORMAT_NV21:
/* 2-Lane: Yuv420 */
format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
/* Y endian */
format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
/* UV endian */
format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
break;
case DRM_FORMAT_NV16:
/* 2-Lane: Yuv422 */
format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
/* Y endian */
format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
/* UV endian */
format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
break;
case DRM_FORMAT_NV61:
/* 2-Lane: Yuv422 */
format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
/* Y endian */
format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
/* UV endian */
format |= BIT_DPU_LAY_NO_SWITCH;
break;
case DRM_FORMAT_YUV420:
format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
/* Y endian */
format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
/* UV endian */
format |= BIT_DPU_LAY_NO_SWITCH;
break;
case DRM_FORMAT_YVU420:
format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
/* Y endian */
format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
/* UV endian */
format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
break;
default:
break;
}
return format;
}
static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
{
u32 rotation = 0;
switch (state->rotation) {
default:
case DRM_MODE_ROTATE_0:
rotation = BIT_DPU_LAY_ROTATION_0;
break;
case DRM_MODE_ROTATE_90:
rotation = BIT_DPU_LAY_ROTATION_90;
break;
case DRM_MODE_ROTATE_180:
rotation = BIT_DPU_LAY_ROTATION_180;
break;
case DRM_MODE_ROTATE_270:
rotation = BIT_DPU_LAY_ROTATION_270;
break;
case DRM_MODE_REFLECT_Y:
rotation = BIT_DPU_LAY_ROTATION_180_M;
break;
case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
rotation = BIT_DPU_LAY_ROTATION_90_M;
break;
case DRM_MODE_REFLECT_X:
rotation = BIT_DPU_LAY_ROTATION_0_M;
break;
case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
rotation = BIT_DPU_LAY_ROTATION_270_M;
break;
}
return rotation;
}
static u32 drm_blend_to_dpu(struct drm_plane_state *state)
{
u32 blend = 0;
switch (state->pixel_blend_mode) {
case DRM_MODE_BLEND_COVERAGE:
/* alpha mode select - combo alpha */
blend |= BIT_DPU_LAY_COMBO_ALPHA;
/* Normal mode */
blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
break;
case DRM_MODE_BLEND_PREMULTI:
/* alpha mode select - combo alpha */
blend |= BIT_DPU_LAY_COMBO_ALPHA;
/* Pre-mult mode */
blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
break;
case DRM_MODE_BLEND_PIXEL_NONE:
default:
/* don't do blending, maybe RGBX */
/* alpha mode select - layer alpha */
blend |= BIT_DPU_LAY_LAYER_ALPHA;
break;
}
return blend;
}
static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
{
struct dpu_context *ctx = &dpu->ctx;
struct drm_gem_dma_object *dma_obj;
struct drm_framebuffer *fb = state->fb;
u32 addr, size, offset, pitch, blend, format, rotation;
u32 src_x = state->src_x >> 16;
u32 src_y = state->src_y >> 16;
u32 src_w = state->src_w >> 16;
u32 src_h = state->src_h >> 16;
u32 dst_x = state->crtc_x;
u32 dst_y = state->crtc_y;
u32 alpha = state->alpha;
u32 index = state->zpos;
int i;
offset = (dst_x & 0xffff) | (dst_y << 16);
size = (src_w & 0xffff) | (src_h << 16);
for (i = 0; i < fb->format->num_planes; i++) {
dma_obj = drm_fb_dma_get_gem_obj(fb, i);
addr = dma_obj->dma_addr + fb->offsets[i];
if (i == 0)
layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
else if (i == 1)
layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
else
layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
}
if (fb->format->num_planes == 3) {
/* UV pitch is 1/2 of Y pitch */
pitch = (fb->pitches[0] / fb->format->cpp[0]) |
(fb->pitches[0] / fb->format->cpp[0] << 15);
} else {
pitch = fb->pitches[0] / fb->format->cpp[0];
}
layer_reg_wr(ctx, REG_LAY_POS, offset, index);
layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
layer_reg_wr(ctx, REG_LAY_CROP_START,
src_y << 16 | src_x, index);
layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
format = drm_format_to_dpu(fb);
blend = drm_blend_to_dpu(state);
rotation = drm_rotation_to_dpu(state);
layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
format |
blend |
rotation,
index);
}
static void sprd_dpu_flip(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
/*
* Make sure the dpu is in stop status. DPU has no shadow
* registers in EDPI mode. So the config registers can only be
* updated in the rising edge of DPU_RUN bit.
*/
if (ctx->if_type == SPRD_DPU_IF_EDPI)
dpu_wait_stop_done(dpu);
/* update trigger and wait */
if (ctx->if_type == SPRD_DPU_IF_DPI) {
if (!ctx->stopped) {
dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
dpu_wait_update_done(dpu);
}
dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
ctx->stopped = false;
}
}
static void sprd_dpu_init(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
u32 int_mask = 0;
writel(0x00, ctx->base + REG_BG_COLOR);
writel(0x00, ctx->base + REG_MMU_EN);
writel(0x00, ctx->base + REG_MMU_PPN1);
writel(0xffff, ctx->base + REG_MMU_RANGE1);
writel(0x00, ctx->base + REG_MMU_PPN2);
writel(0xffff, ctx->base + REG_MMU_RANGE2);
writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
if (ctx->if_type == SPRD_DPU_IF_DPI) {
/* use dpi as interface */
dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
/* disable Halt function for SPRD DSI */
dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
/* select te from external pad */
dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
/* enable dpu update done INT */
int_mask |= BIT_DPU_INT_UPDATE_DONE;
/* enable dpu done INT */
int_mask |= BIT_DPU_INT_DONE;
/* enable dpu dpi vsync */
int_mask |= BIT_DPU_INT_VSYNC;
/* enable dpu TE INT */
int_mask |= BIT_DPU_INT_TE;
/* enable underflow err INT */
int_mask |= BIT_DPU_INT_ERR;
} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
/* use edpi as interface */
dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
/* use external te */
dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
/* enable te */
dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
/* enable stop done INT */
int_mask |= BIT_DPU_INT_DONE;
/* enable TE INT */
int_mask |= BIT_DPU_INT_TE;
}
writel(int_mask, ctx->base + REG_DPU_INT_EN);
}
static void sprd_dpu_fini(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
writel(0x00, ctx->base + REG_DPU_INT_EN);
writel(0xff, ctx->base + REG_DPU_INT_CLR);
}
static void sprd_dpi_init(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
u32 reg_val;
u32 size;
size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
writel(size, ctx->base + REG_PANEL_SIZE);
writel(size, ctx->base + REG_BLEND_SIZE);
if (ctx->if_type == SPRD_DPU_IF_DPI) {
/* set dpi timing */
reg_val = ctx->vm.hsync_len << 0 |
ctx->vm.hback_porch << 8 |
ctx->vm.hfront_porch << 20;
writel(reg_val, ctx->base + REG_DPI_H_TIMING);
reg_val = ctx->vm.vsync_len << 0 |
ctx->vm.vback_porch << 8 |
ctx->vm.vfront_porch << 20;
writel(reg_val, ctx->base + REG_DPI_V_TIMING);
}
}
void sprd_dpu_run(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
ctx->stopped = false;
}
void sprd_dpu_stop(struct sprd_dpu *dpu)
{
struct dpu_context *ctx = &dpu->ctx;
if (ctx->if_type == SPRD_DPU_IF_DPI)
dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
dpu_wait_stop_done(dpu);
}
static int sprd_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_commit *state)
{
struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
plane);
struct drm_crtc_state *crtc_state;
u32 fmt;
if (!plane_state->fb || !plane_state->crtc)
return 0;
fmt = drm_format_to_dpu(plane_state->fb);
if (!fmt)
return -EINVAL;
crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
DRM_PLANE_NO_SCALING,
DRM_PLANE_NO_SCALING,
true, true);
}
static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
struct drm_atomic_commit *state)
{
struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
drm_plane);
struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
/* start configure dpu layers */
sprd_dpu_layer(dpu, new_state);
}
static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
struct drm_atomic_commit *state)
{
struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
drm_plane);
struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
}
static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
{
unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
BIT(DRM_MODE_BLEND_PREMULTI) |
BIT(DRM_MODE_BLEND_COVERAGE);
/* create rotation property */
drm_plane_create_rotation_property(&plane->base,
DRM_MODE_ROTATE_0,
DRM_MODE_ROTATE_MASK |
DRM_MODE_REFLECT_MASK);
/* create alpha property */
drm_plane_create_alpha_property(&plane->base);
/* create blend mode property */
drm_plane_create_blend_mode_property(&plane->base, supported_modes);
/* create zpos property */
drm_plane_create_zpos_immutable_property(&plane->base, index);
}
static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
.atomic_check = sprd_plane_atomic_check,
.atomic_update = sprd_plane_atomic_update,
.atomic_disable = sprd_plane_atomic_disable,
};
static const struct drm_plane_funcs sprd_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = drm_plane_cleanup,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
};
static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
{
struct sprd_plane *plane, *primary;
enum drm_plane_type plane_type;
int i;
for (i = 0; i < 6; i++) {
plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
1, &sprd_plane_funcs,
layer_fmts, ARRAY_SIZE(layer_fmts),
NULL, plane_type, NULL);
if (IS_ERR(plane)) {
drm_err(drm, "failed to init drm plane: %d\n", i);
return plane;
}
drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
sprd_plane_create_properties(plane, i);
if (i == 0)
primary = plane;
}
return primary;
}
static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct sprd_dpu *dpu = to_sprd_crtc(crtc);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
struct drm_encoder *encoder;
struct sprd_dsi *dsi;
drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
drm_for_each_encoder_mask(encoder, crtc->dev,
crtc->state->encoder_mask) {
dsi = encoder_to_dsi(encoder);
if (dsi->slave->mode_flags & MIPI_DSI_MODE_VIDEO)
dpu->ctx.if_type = SPRD_DPU_IF_DPI;
else
dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
}
sprd_dpi_init(dpu);
}
static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_atomic_commit *state)
{
struct sprd_dpu *dpu = to_sprd_crtc(crtc);
sprd_dpu_init(dpu);
drm_crtc_vblank_on(&dpu->base);
}
static void sprd_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_atomic_commit *state)
{
struct sprd_dpu *dpu = to_sprd_crtc(crtc);
struct drm_device *drm = dpu->base.dev;
drm_crtc_vblank_off(&dpu->base);
sprd_dpu_fini(dpu);
spin_lock_irq(&drm->event_lock);
if (crtc->state->event) {
drm_crtc_send_vblank_event(crtc, crtc->state->event);
crtc->state->event = NULL;
}
spin_unlock_irq(&drm->event_lock);
}
static void sprd_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_atomic_commit *state)
{
struct sprd_dpu *dpu = to_sprd_crtc(crtc);
struct drm_device *drm = dpu->base.dev;
sprd_dpu_flip(dpu);
spin_lock_irq(&drm->event_lock);
if (crtc->state->event) {
drm_crtc_send_vblank_event(crtc, crtc->state->event);
crtc->state->event = NULL;
}
spin_unlock_irq(&drm->event_lock);
}
static int sprd_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct sprd_dpu *dpu = to_sprd_crtc(crtc);
dpu_reg_set(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
return 0;
}
static void sprd_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct sprd_dpu *dpu = to_sprd_crtc(crtc);
dpu_reg_clr(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
}
static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs = {
.mode_set_nofb = sprd_crtc_mode_set_nofb,
.atomic_flush = sprd_crtc_atomic_flush,
.atomic_enable = sprd_crtc_atomic_enable,
.atomic_disable = sprd_crtc_atomic_disable,
};
static const struct drm_crtc_funcs sprd_crtc_funcs = {
.destroy = drm_crtc_cleanup,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
.enable_vblank = sprd_crtc_enable_vblank,
.disable_vblank = sprd_crtc_disable_vblank,
};
static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm,
struct drm_plane *primary, struct device *dev)
{
struct device_node *port;
struct sprd_dpu *dpu;
dpu = drmm_crtc_alloc_with_planes(drm, struct sprd_dpu, base,
primary, NULL,
&sprd_crtc_funcs, NULL);
if (IS_ERR(dpu)) {
drm_err(drm, "failed to init crtc\n");
return dpu;
}
drm_crtc_helper_add(&dpu->base, &sprd_crtc_helper_funcs);
/*
* set crtc port so that drm_of_find_possible_crtcs call works
*/
port = of_graph_get_port_by_id(dev->of_node, 0);
if (!port) {
drm_err(drm, "failed to found crtc output port for %s\n",
dev->of_node->full_name);
return ERR_PTR(-EINVAL);
}
dpu->base.port = port;
of_node_put(port);
return dpu;
}
static irqreturn_t sprd_dpu_isr(int irq, void *data)
{
struct sprd_dpu *dpu = data;
struct dpu_context *ctx = &dpu->ctx;
u32 reg_val, int_mask = 0;
reg_val = readl(ctx->base + REG_DPU_INT_STS);
/* disable err interrupt */
if (reg_val & BIT_DPU_INT_ERR) {
int_mask |= BIT_DPU_INT_ERR;
drm_warn(dpu->drm, "Warning: dpu underflow!\n");
}
/* dpu update done isr */
if (reg_val & BIT_DPU_INT_UPDATE_DONE) {
ctx->evt_update = true;
wake_up_interruptible_all(&ctx->wait_queue);
}
/* dpu stop done isr */
if (reg_val & BIT_DPU_INT_DONE) {
ctx->evt_stop = true;
wake_up_interruptible_all(&ctx->wait_queue);
}
if (reg_val & BIT_DPU_INT_VSYNC)
drm_crtc_handle_vblank(&dpu->base);
writel(reg_val, ctx->base + REG_DPU_INT_CLR);
dpu_reg_clr(ctx, REG_DPU_INT_EN, int_mask);
return IRQ_HANDLED;
}
static int sprd_dpu_context_init(struct sprd_dpu *dpu,
struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct dpu_context *ctx = &dpu->ctx;
int ret;
ctx->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctx->base)) {
dev_err(dev, "failed to map dpu registers\n");
return PTR_ERR(ctx->base);
}
ctx->irq = platform_get_irq(pdev, 0);
if (ctx->irq < 0)
return ctx->irq;
/* disable and clear interrupts before register dpu IRQ. */
writel(0x00, ctx->base + REG_DPU_INT_EN);
writel(0xff, ctx->base + REG_DPU_INT_CLR);
ret = devm_request_irq(dev, ctx->irq, sprd_dpu_isr,
IRQF_TRIGGER_NONE, "DPU", dpu);
if (ret) {
dev_err(dev, "failed to register dpu irq handler\n");
return ret;
}
init_waitqueue_head(&ctx->wait_queue);
return 0;
}
static int sprd_dpu_bind(struct device *dev, struct device *master, void *data)
{
struct drm_device *drm = data;
struct sprd_dpu *dpu;
struct sprd_plane *plane;
int ret;
plane = sprd_planes_init(drm);
if (IS_ERR(plane))
return PTR_ERR(plane);
dpu = sprd_crtc_init(drm, &plane->base, dev);
if (IS_ERR(dpu))
return PTR_ERR(dpu);
dpu->drm = drm;
dev_set_drvdata(dev, dpu);
ret = sprd_dpu_context_init(dpu, dev);
if (ret)
return ret;
return 0;
}
static const struct component_ops dpu_component_ops = {
.bind = sprd_dpu_bind,
};
static const struct of_device_id dpu_match_table[] = {
{ .compatible = "sprd,sharkl3-dpu" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, dpu_match_table);
static int sprd_dpu_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &dpu_component_ops);
}
static void sprd_dpu_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &dpu_component_ops);
}
struct platform_driver sprd_dpu_driver = {
.probe = sprd_dpu_probe,
.remove = sprd_dpu_remove,
.driver = {
.name = "sprd-dpu-drv",
.of_match_table = dpu_match_table,
},
};
MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
MODULE_DESCRIPTION("Unisoc Display Controller Driver");
MODULE_LICENSE("GPL v2");
linux-7.2.3/drivers/gpu/drm/sprd/sprd_dpu.h
+109
View File
@@ -0,0 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 Unisoc Inc.
*/
#ifndef __SPRD_DPU_H__
#define __SPRD_DPU_H__
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <video/videomode.h>
#include <drm/drm_crtc.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
#include <uapi/drm/drm_mode.h>
/* DPU Layer registers offset */
#define DPU_LAY_REG_OFFSET 0x30
enum {
SPRD_DPU_IF_DPI,
SPRD_DPU_IF_EDPI,
SPRD_DPU_IF_LIMIT
};
/**
* Sprd DPU context structure
*
* @base: DPU controller base address
* @irq: IRQ number to install the handler for
* @if_type: The type of DPI interface, default is DPI mode.
* @vm: videomode structure to use for DPU and DPI initialization
* @stopped: indicates whether DPU are stopped
* @wait_queue: wait queue, used to wait for DPU shadow register update done and
* DPU stop register done interrupt signal.
* @evt_update: wait queue condition for DPU shadow register
* @evt_stop: wait queue condition for DPU stop register
*/
struct dpu_context {
void __iomem *base;
int irq;
u8 if_type;
struct videomode vm;
bool stopped;
wait_queue_head_t wait_queue;
bool evt_update;
bool evt_stop;
};
/**
* Sprd DPU device structure
*
* @crtc: crtc object
* @drm: A point to drm device
* @ctx: DPU's implementation specific context object
*/
struct sprd_dpu {
struct drm_crtc base;
struct drm_device *drm;
struct dpu_context ctx;
};
static inline struct sprd_dpu *to_sprd_crtc(struct drm_crtc *crtc)
{
return container_of(crtc, struct sprd_dpu, base);
}
static inline void
dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits)
{
u32 bits = readl_relaxed(ctx->base + offset);
writel(bits | set_bits, ctx->base + offset);
}
static inline void
dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits)
{
u32 bits = readl_relaxed(ctx->base + offset);
writel(bits & ~clr_bits, ctx->base + offset);
}
static inline u32
layer_reg_rd(struct dpu_context *ctx, u32 offset, int index)
{
u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;
return readl(ctx->base + layer_offset);
}
static inline void
layer_reg_wr(struct dpu_context *ctx, u32 offset, u32 cfg_bits, int index)
{
u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;
writel(cfg_bits, ctx->base + layer_offset);
}
void sprd_dpu_run(struct sprd_dpu *dpu);
void sprd_dpu_stop(struct sprd_dpu *dpu);
#endif
linux-7.2.3/drivers/gpu/drm/sprd/sprd_drm.c
+198
View File
@@ -0,0 +1,198 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Unisoc Inc.
*/
#include <linux/component.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
#include "sprd_drm.h"
#define DRIVER_NAME "sprd"
#define DRIVER_DESC "Spreadtrum SoCs' DRM Driver"
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
static const struct drm_mode_config_helper_funcs sprd_drm_mode_config_helper = {
.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
};
static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
static void sprd_drm_mode_config_init(struct drm_device *drm)
{
drm->mode_config.min_width = 0;
drm->mode_config.min_height = 0;
drm->mode_config.max_width = 8192;
drm->mode_config.max_height = 8192;
drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
}
DEFINE_DRM_GEM_DMA_FOPS(sprd_drm_fops);
static struct drm_driver sprd_drm_drv = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
.fops = &sprd_drm_fops,
/* GEM Operations */
DRM_GEM_DMA_DRIVER_OPS,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.major = DRIVER_MAJOR,
.minor = DRIVER_MINOR,
};
static int sprd_drm_bind(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm;
struct sprd_drm *sprd;
int ret;
sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm, drm);
if (IS_ERR(sprd))
return PTR_ERR(sprd);
drm = &sprd->drm;
platform_set_drvdata(pdev, drm);
ret = drmm_mode_config_init(drm);
if (ret)
return ret;
sprd_drm_mode_config_init(drm);
/* bind and init sub drivers */
ret = component_bind_all(drm->dev, drm);
if (ret) {
drm_err(drm, "failed to bind all component.\n");
return ret;
}
/* vblank init */
ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
if (ret) {
drm_err(drm, "failed to initialize vblank.\n");
goto err_unbind_all;
}
/* reset all the states of crtc/plane/encoder/connector */
drm_mode_config_reset(drm);
/* init kms poll for handling hpd */
drm_kms_helper_poll_init(drm);
ret = drm_dev_register(drm, 0);
if (ret < 0)
goto err_kms_helper_poll_fini;
return 0;
err_kms_helper_poll_fini:
drm_kms_helper_poll_fini(drm);
err_unbind_all:
component_unbind_all(drm->dev, drm);
return ret;
}
static void sprd_drm_unbind(struct device *dev)
{
struct drm_device *drm = dev_get_drvdata(dev);
drm_dev_unregister(drm);
drm_kms_helper_poll_fini(drm);
component_unbind_all(drm->dev, drm);
}
static const struct component_master_ops drm_component_ops = {
.bind = sprd_drm_bind,
.unbind = sprd_drm_unbind,
};
static int sprd_drm_probe(struct platform_device *pdev)
{
return drm_of_component_probe(&pdev->dev, component_compare_of, &drm_component_ops);
}
static void sprd_drm_remove(struct platform_device *pdev)
{
component_master_del(&pdev->dev, &drm_component_ops);
}
static void sprd_drm_shutdown(struct platform_device *pdev)
{
struct drm_device *drm = platform_get_drvdata(pdev);
if (!drm) {
dev_warn(&pdev->dev, "drm device is not available, no shutdown\n");
return;
}
drm_atomic_helper_shutdown(drm);
}
static const struct of_device_id drm_match_table[] = {
{ .compatible = "sprd,display-subsystem", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, drm_match_table);
static struct platform_driver sprd_drm_driver = {
.probe = sprd_drm_probe,
.remove = sprd_drm_remove,
.shutdown = sprd_drm_shutdown,
.driver = {
.name = "sprd-drm-drv",
.of_match_table = drm_match_table,
},
};
static struct platform_driver *sprd_drm_drivers[] = {
&sprd_drm_driver,
&sprd_dpu_driver,
&sprd_dsi_driver,
};
static int __init sprd_drm_init(void)
{
if (drm_firmware_drivers_only())
return -ENODEV;
return platform_register_drivers(sprd_drm_drivers,
ARRAY_SIZE(sprd_drm_drivers));
}
static void __exit sprd_drm_exit(void)
{
platform_unregister_drivers(sprd_drm_drivers,
ARRAY_SIZE(sprd_drm_drivers));
}
module_init(sprd_drm_init);
module_exit(sprd_drm_exit);
MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
MODULE_LICENSE("GPL v2");
linux-7.2.3/drivers/gpu/drm/sprd/sprd_drm.h
+19
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@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 Unisoc Inc.
*/
#ifndef _SPRD_DRM_H_
#define _SPRD_DRM_H_
#include <drm/drm_atomic.h>
#include <drm/drm_print.h>
struct sprd_drm {
struct drm_device drm;
};
extern struct platform_driver sprd_dpu_driver;
extern struct platform_driver sprd_dsi_driver;
#endif /* _SPRD_DRM_H_ */
linux-7.2.3/drivers/gpu/drm/sprd/sprd_dsi.c
+1066
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/gpu/drm/sprd/sprd_dsi.h
+126
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@@ -0,0 +1,126 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 Unisoc Inc.
*/
#ifndef __SPRD_DSI_H__
#define __SPRD_DSI_H__
#include <linux/of.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <video/videomode.h>
#include <drm/drm_bridge.h>
#include <drm/drm_connector.h>
#include <drm/drm_encoder.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_print.h>
#include <drm/drm_panel.h>
#define encoder_to_dsi(encoder) \
container_of(encoder, struct sprd_dsi, encoder)
enum dsi_work_mode {
DSI_MODE_CMD = 0,
DSI_MODE_VIDEO
};
enum video_burst_mode {
VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
VIDEO_NON_BURST_WITH_SYNC_EVENTS,
VIDEO_BURST_WITH_SYNC_PULSES
};
enum dsi_color_coding {
COLOR_CODE_16BIT_CONFIG1 = 0,
COLOR_CODE_16BIT_CONFIG2,
COLOR_CODE_16BIT_CONFIG3,
COLOR_CODE_18BIT_CONFIG1,
COLOR_CODE_18BIT_CONFIG2,
COLOR_CODE_24BIT,
COLOR_CODE_20BIT_YCC422_LOOSELY,
COLOR_CODE_24BIT_YCC422,
COLOR_CODE_16BIT_YCC422,
COLOR_CODE_30BIT,
COLOR_CODE_36BIT,
COLOR_CODE_12BIT_YCC420,
COLOR_CODE_COMPRESSTION,
COLOR_CODE_MAX
};
enum pll_timing {
NONE,
REQUEST_TIME,
PREPARE_TIME,
SETTLE_TIME,
ZERO_TIME,
TRAIL_TIME,
EXIT_TIME,
CLKPOST_TIME,
TA_GET,
TA_GO,
TA_SURE,
TA_WAIT,
};
struct dphy_pll {
u8 refin; /* Pre-divider control signal */
u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */
u8 fdk_s; /* PLL mode control: integer or fraction */
u8 sdm_en;
u8 div;
u8 int_n; /* integer N PLL */
u32 ref_clk; /* dphy reference clock, unit: MHz */
u32 freq; /* panel config, unit: KHz */
u32 fvco;
u32 potential_fvco;
u32 nint; /* sigma delta modulator NINT control */
u32 kint; /* sigma delta modulator KINT control */
u8 lpf_sel; /* low pass filter control */
u8 out_sel; /* post divider control */
u8 vco_band; /* vco range */
u8 det_delay;
};
struct dsi_context {
void __iomem *base;
struct regmap *regmap;
struct dphy_pll pll;
struct videomode vm;
bool enabled;
u8 work_mode;
u8 burst_mode;
u32 int0_mask;
u32 int1_mask;
/* maximum time (ns) for data lanes from HS to LP */
u16 data_hs2lp;
/* maximum time (ns) for data lanes from LP to HS */
u16 data_lp2hs;
/* maximum time (ns) for clk lanes from HS to LP */
u16 clk_hs2lp;
/* maximum time (ns) for clk lanes from LP to HS */
u16 clk_lp2hs;
/* maximum time (ns) for BTA operation - REQUIRED */
u16 max_rd_time;
/* enable receiving frame ack packets - for video mode */
bool frame_ack_en;
/* enable receiving tear effect ack packets - for cmd mode */
bool te_ack_en;
};
struct sprd_dsi {
struct drm_device *drm;
struct mipi_dsi_host host;
struct mipi_dsi_device *slave;
struct drm_encoder encoder;
struct drm_bridge *panel_bridge;
struct dsi_context ctx;
};
int dphy_pll_config(struct dsi_context *ctx);
void dphy_timing_config(struct dsi_context *ctx);
#endif /* __SPRD_DSI_H__ */